Commit Graph

11 Commits (047be5c0c3b2f12c9321412518e17b7267fe14ea)

Author SHA1 Message Date
Anton Blanchard 00bf0af21c xics: Fix warning when comparing two std_ulogic_vectors
Use unsigned() to make it clear what we are doing.

Signed-off-by: Anton Blanchard <>
2 years ago
Paul Mackerras 0aa898c7a6 xics: Rework the irq_gen process
At present, the loop in the irq_gen process generates a chain of
comparators and other logic to work out the source number and priority
of the most-favoured (lowest priority number) pending interrupt.
This replaces that chain with (1) logic to generate an array of bits,
one per priority, indicating whether any interrupt is pending at that
priority, (2) a priority encoder to select the most favoured priority
with an interrupt pending, (3) logic to generate an array of bits, one
per source, indicating whether an interrupt is pending at the priority
calculated in step 2, and (4) a priority encoder to work out the
lowest numbered source that has an interrupt pending at the selected
priority.  This reduces LUT utilization.

The priority encoder function implemented here uses the optimized
count-leading-zeroes logic from helpers.vhdl.

Signed-off-by: Paul Mackerras <>
2 years ago
Paul Mackerras ca4eb46aea Make wishbone addresses be in units of doublewords or words
This makes the 64-bit wishbone buses have the address expressed in
units of doublewords (64 bits), and similarly for the 32-bit buses the
address is in units of words (32 bits).  This is to comply with the
wishbone spec.  Previously the addresses on the wishbone buses were in
units of bytes regardless of the bus data width, which is not correct
and caused problems with interfacing with externally-generated logic.

Signed-off-by: Paul Mackerras <>
3 years ago
Anton Blanchard 7994b98404 Fix some whitespace issues
Signed-off-by: Anton Blanchard <>
3 years ago
Benjamin Herrenschmidt bb54af59de xics: Add support for reduced priority field size
This makes the ICS support less than the 8 architected bits
and sets the soc to use 3 bits by default.

All the supported bits set translates to "masked" (and will read
back at 0xff), any small value is used as-is.

Linux doesn't use priorities above 5, so this is a way to save
silicon. The number of supported priority bits is exposed to the
OS via the config register.

Signed-off-by: Benjamin Herrenschmidt <>
4 years ago
Benjamin Herrenschmidt 5c2fc47e2c xics: Add simple ICS
Move the external interrupt generation to a separate module
"ICS" (source controller) which a register per source containing
currently only the priority control.

Signed-off-by: Benjamin Herrenschmidt <>
4 years ago
Benjamin Herrenschmidt 8080168327 xics/icp: MFRR starts at 0xff not 0x00
Signed-off-by: Benjamin Herrenschmidt <>
4 years ago
Benjamin Herrenschmidt 0fa14f6dec xics: ICP should be big endian !
That's how Linux expects it. This also simplifies the
register access implementation since the bit fields now
align properly regardless of the access size.

Signed-off-by: Benjamin Herrenschmidt <>
4 years ago
Benjamin Herrenschmidt f86fb74bfe irq: Simplify xics->core irq input
Use a simple wire. common.vhdl types are better kept for things
local to the core. We can add more wires later if we need to for
HV irqs etc...

Signed-off-by: Benjamin Herrenschmidt <>
4 years ago
Benjamin Herrenschmidt 573b6b4bc4 soc: Rework interconnect
This changes the SoC interconnect such that the main 64-bit wishbone out
of the processor is first split between only 3 slaves (BRAM, DRAM and a
general "IO" bus) instead of all the slaves in the SoC.

The IO bus leg is then latched and down-converted to 32 bits data width,
before going through a second address decoder for the various IO devices.

This significantly reduces routing and timing pressure on the main bus,
allowing to get rid of frequent timing violations when synthetizing on
small'ish FPGAs such as the Artix-7 35T found on the original Arty board.

Signed-off-by: Benjamin Herrenschmidt <>
4 years ago
Michael Neuling b4f20c20b9 XICS interrupt controller
New unified ICP and ICS XICS compliant interrupt controller.
Configurable number of hardware sources.

Fixed hardware source number based on hardware line taken. All
hardware interrupts are a fixed priority. Level interrupts supported

Hardwired to 0xc0004000 in SOC (UART is kept at 0xc0002000).

Signed-off-by: Michael Neuling <>
4 years ago