Commit Graph

977 Commits (remove-potato-uart)
 

Author SHA1 Message Date
Anton Blanchard 9867fb6149 Add a decode for the nop instruction
We want these to go out without any GPR dependencies, so add
a specific entry in decode for them.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard 85062793b1
Merge pull request from antonblanchard/fetch-fix
Add a default value for RESET_ADDRESS
Anton Blanchard d52046104f Add a default value for RESET_ADDRESS
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard 71e45a82ee
Merge pull request from antonblanchard/writeback-fix
Some writeback updates
Anton Blanchard e69e79d8af Reformat writeback.vhdl
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard 50a361a5dc Exit if we try to write more than one GPR or CR in a cycle
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard ab34c48392
Merge pull request from antonblanchard/decode1-opt
No need to gate nia or insn in decode1
Anton Blanchard acdb2ea157 No need to gate nia or insn in decode1
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard 0e6861e5db
Merge pull request from antonblanchard/icache-2
Add a simple direct mapped icache
Anton Blanchard 89849a6856 Add a simple direct mapped icache
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard 6cbf456388 SOC memory wishbone should clear ACK regardless of STB
The memory wishbone doesn't clear ACK and move the state machine on
until STB is de-asserted. This seems like it isn't compliant with
the spec and results in a maximum throughput of 1 transfer every
3 cycles.

Fixing this improves the situation to one transfer every 2 cycles.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard 67446709ca
Merge pull request from antonblanchard/clk_gen_bypass
Fix clk_gen_bypass
Anton Blanchard d89a9929fd Fix clk_gen_bypass
I broke clk_gen_bypass when updating the SOC reset code.

Fixes 03fd06deaf ("Rework SOC reset")
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard 80aa781454
Merge pull request from antonblanchard/if-fix
Explicitly check against '1' in if statements
Anton Blanchard ca6f84efd6
Merge pull request from antonblanchard/record-fix
Remove names from end record statements
Anton Blanchard b9e28598b4 Explicitly check against '1' in if statements
nvc doesn't like what I think is a VHDL 2008 construct. Lets just
check against '1' explicitly.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard 142a722ce4 Remove names from end record statements
These are optional, and vhdlpp from iverilog barfs on them.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard 43f81773b4
Merge pull request from antonblanchard/fixes
Fix a couple of issues in the recent pipelining merge
Anton Blanchard 7caf71ba71 Fix issue in loadstore1
We weren't using the register in this stage.

Fixes: 819f820090 ("Register outputs on loadstore1")
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard 95442cd62c Fix issue in execute2
We weren't using the register in this stage.

Fixes: c7aa683ba8 ("Register outputs on execute2")
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard 1ba84b56dd
Merge pull request from antonblanchard/nia-remove
Remove nia from loadstore and multiply
Anton Blanchard 1d00c75ecc Remove nia from loadstore and multiply
Neither unit needs the NIA, so remove it.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard 8b88e26ece
Merge pull request from mikey/trivial
Remove FIXME comment
Michael Neuling 1e1b799382 Remove FIXME comment
This was mistakenly left behind in 4d5abfb430 ("Remove dynamic
ranges from code")

Signed-off-by: Michael Neuling <mikey@neuling.org>
Anton Blanchard ff1455dea6
Merge pull request from mikey/travis
Allow a full make check on Travis
Anton Blanchard 2f3ca35a6e
Merge pull request from antonblanchard/fetch-rework-v2
Fetch rework
Anton Blanchard 4528ef2b43 Reformat core.vhdl
Anton Blanchard a2df2a10a2 Remove sim console
We can force all existing code to use the UART console
by passing 0 in bit zero of the sim config register.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard 68533c4cfb Reduce multiply to 2 cycles
We want all non load/store ops to take 2 cycles to make
tracking write back easier.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard 9fe8d211eb Register outputs on writeback
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard c7aa683ba8 Register outputs on execute2
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard 819f820090 Register outputs on loadstore1
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard a8f8c54b77 Move debug execute output into decode2
This covers all units, and we avoid double printing.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard 92a7152370 Rework pipeline, add stall and flush signals
This adds stall and flush signals to the pipeline.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Michael Neuling 6b06d5f67d Allow a full make check on Travis
Some Travis instances allow more CPU time. On these we can perform the
full 'make check'.

This patch allows this longer `make check`. To enable it you need to
go into your Travis configuration and add a TRAVIS_FULL_CHECK
environment variable.

If you don't add this environment, the shorter make check_light is
still run.

Signed-off-by: Michael Neuling <mikey@neuling.org>
Anton Blanchard 3b32abcb5d
Merge pull request from antonblanchard/makefile-dependencies
Update Makefile dependencies
Anton Blanchard b6b2c78163 Update Makefile dependencies
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Benjamin Herrenschmidt d3acb5cce9 Switch soc to use std_ulogic
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Benjamin Herrenschmidt 3ac1dbc737 Share soc.vhdl between FPGA and sim
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Benjamin Herrenschmidt d21ef5836d Pass wishbone record to bram memory module
(And rename it to mw_soc_memory).

This makes soc.vhdl simpler and provides the same interface as
the simulated memory, which will help when sharing soc.vhdl
with sim later

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Benjamin Herrenschmidt 1d66e1f981 Rework wishbone slave address decoding
Don't make it synchronous, no latches

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Benjamin Herrenschmidt c97b080d8c Move wishbone arbiter out of the core
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Benjamin Herrenschmidt 310a56c076 Re-indent and reformat soc.vhdl
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Benjamin Herrenschmidt a69a93b466 Split FPGA toplevel from soc
This will be useful when we start needing different toplevels for
different boards.

We keep the reset and clock generators in the toplevel as they will
eventually be taken over by litedram when we integrate it, and they
are more likely to change on different system types.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Anton Blanchard 5ee86e7621
Merge pull request from antonblanchard/no-x-state
Don't send out X state from the memory behavioural
Anton Blanchard dce2e06f4c Don't send out X state from the memory behavioural
Just send out all 1s.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Anton Blanchard c3a5782bf4
Merge pull request from mikey/gitignore
Add new files to git ignore
Anton Blanchard 419b95a447
Merge pull request from antonblanchard/multiply-warn
Quieten multiply warning
Anton Blanchard a22afbdb5b Quieten multiply warning
We no longer gate multiply with the valid signal, so it's complaining
a lot. Comment out the warning.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Michael Neuling 5ae92a721f Add new files to git ignore
Signed-off-by: Michael Neuling <mikey@neuling.org>