microwatt

Commit Graph

Author	SHA1	Message	Date
Benjamin Herrenschmidt	1441b2a859	litedram: l2: Latency improvements This implements in the L2 cache the feature already in the L1s allowing a request to be completed before the end of a refill using partial line valid bits, and starting a refill from the row of the first miss on that line instead of the beginning of the line. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>	5 years ago
Benjamin Herrenschmidt	6828e93113	litedram: Test bench The test bench test simple access forms for now, it's a starting point but it already helped find/fix a bug. Includes a litedram update to be able to operate the sim model without inits. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>	5 years ago

Author

SHA1

Message

Date

Benjamin Herrenschmidt

1441b2a859

litedram: l2: Latency improvements

This implements in the L2 cache the feature already in the L1s
allowing a request to be completed before the end of a refill
using partial line valid bits, and starting a refill from the
row of the first miss on that line instead of the beginning of
the line.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>

Benjamin Herrenschmidt

6828e93113

litedram: Test bench

The test bench test simple access forms for now, it's a starting point
but it already helped find/fix a bug.

Includes a litedram update to be able to operate the sim model without
inits.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>

2 Commits (core_debug-init)