antmicro-artix-dc-scm: Update DRAM properties

Most pins are set to SSTL15, but litex generates SSTL135.

This should silence a vivado warning.

Signed-off-by: Joel Stanley <joel@jms.id.au>

fpga/antmicro_artix_dc_scm.xdc

@@ -19,258 +19,262 @@ set_property -dict { PACKAGE_PIN W20 IOSTANDARD LVCMOS33 } [get_ports { d13_led
 # ddram:0.a
 set_property LOC M2 [get_ports {ddram_a[0]}]
 set_property SLEW FAST [get_ports {ddram_a[0]}]
-set_property IOSTANDARD SSTL15 [get_ports {ddram_a[0]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddram_a[0]}]
 
 # ddram:0.a
 set_property LOC M5 [get_ports {ddram_a[1]}]
 set_property SLEW FAST [get_ports {ddram_a[1]}]
-set_property IOSTANDARD SSTL15 [get_ports {ddram_a[1]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddram_a[1]}]
 
 # ddram:0.a
 set_property LOC M3 [get_ports {ddram_a[2]}]
 set_property SLEW FAST [get_ports {ddram_a[2]}]
-set_property IOSTANDARD SSTL15 [get_ports {ddram_a[2]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddram_a[2]}]
 
 # ddram:0.a
 set_property LOC M1 [get_ports {ddram_a[3]}]
 set_property SLEW FAST [get_ports {ddram_a[3]}]
-set_property IOSTANDARD SSTL15 [get_ports {ddram_a[3]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddram_a[3]}]
 
 # ddram:0.a
 set_property LOC L6 [get_ports {ddram_a[4]}]
 set_property SLEW FAST [get_ports {ddram_a[4]}]
-set_property IOSTANDARD SSTL15 [get_ports {ddram_a[4]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddram_a[4]}]
 
 # ddram:0.a
 set_property LOC P1 [get_ports {ddram_a[5]}]
 set_property SLEW FAST [get_ports {ddram_a[5]}]
-set_property IOSTANDARD SSTL15 [get_ports {ddram_a[5]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddram_a[5]}]
 
 # ddram:0.a
 set_property LOC N3 [get_ports {ddram_a[6]}]
 set_property SLEW FAST [get_ports {ddram_a[6]}]
-set_property IOSTANDARD SSTL15 [get_ports {ddram_a[6]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddram_a[6]}]
 
 # ddram:0.a
 set_property LOC N2 [get_ports {ddram_a[7]}]
 set_property SLEW FAST [get_ports {ddram_a[7]}]
-set_property IOSTANDARD SSTL15 [get_ports {ddram_a[7]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddram_a[7]}]
 
 # ddram:0.a
 set_property LOC M6 [get_ports {ddram_a[8]}]
 set_property SLEW FAST [get_ports {ddram_a[8]}]
-set_property IOSTANDARD SSTL15 [get_ports {ddram_a[8]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddram_a[8]}]
 
 # ddram:0.a
 set_property LOC R1 [get_ports {ddram_a[9]}]
 set_property SLEW FAST [get_ports {ddram_a[9]}]
-set_property IOSTANDARD SSTL15 [get_ports {ddram_a[9]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddram_a[9]}]
 
 # ddram:0.a
 set_property LOC L5 [get_ports {ddram_a[10]}]
 set_property SLEW FAST [get_ports {ddram_a[10]}]
-set_property IOSTANDARD SSTL15 [get_ports {ddram_a[10]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddram_a[10]}]
 
 # ddram:0.a
 set_property LOC N5 [get_ports {ddram_a[11]}]
 set_property SLEW FAST [get_ports {ddram_a[11]}]
-set_property IOSTANDARD SSTL15 [get_ports {ddram_a[11]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddram_a[11]}]
 
 # ddram:0.a
 set_property LOC N4 [get_ports {ddram_a[12]}]
 set_property SLEW FAST [get_ports {ddram_a[12]}]
-set_property IOSTANDARD SSTL15 [get_ports {ddram_a[12]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddram_a[12]}]
 
 # ddram:0.a
 set_property LOC P2 [get_ports {ddram_a[13]}]
 set_property SLEW FAST [get_ports {ddram_a[13]}]
-set_property IOSTANDARD SSTL15 [get_ports {ddram_a[13]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddram_a[13]}]
 
 # ddram:0.a
 set_property LOC P6 [get_ports {ddram_a[14]}]
 set_property SLEW FAST [get_ports {ddram_a[14]}]
-set_property IOSTANDARD SSTL15 [get_ports {ddram_a[14]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddram_a[14]}]
 
 # ddram:0.ba
 set_property LOC L3 [get_ports {ddram_ba[0]}]
 set_property SLEW FAST [get_ports {ddram_ba[0]}]
-set_property IOSTANDARD SSTL15 [get_ports {ddram_ba[0]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddram_ba[0]}]
 
 # ddram:0.ba
 set_property LOC K6 [get_ports {ddram_ba[1]}]
 set_property SLEW FAST [get_ports {ddram_ba[1]}]
-set_property IOSTANDARD SSTL15 [get_ports {ddram_ba[1]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddram_ba[1]}]
 
 # ddram:0.ba
 set_property LOC L4 [get_ports {ddram_ba[2]}]
 set_property SLEW FAST [get_ports {ddram_ba[2]}]
-set_property IOSTANDARD SSTL15 [get_ports {ddram_ba[2]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddram_ba[2]}]
 
 # ddram:0.ras_n
 set_property LOC J4 [get_ports {ddram_ras_n}]
 set_property SLEW FAST [get_ports {ddram_ras_n}]
-set_property IOSTANDARD SSTL15 [get_ports {ddram_ras_n}]
+set_property IOSTANDARD SSTL135 [get_ports {ddram_ras_n}]
 
 # ddram:0.cas_n
 set_property LOC K3 [get_ports {ddram_cas_n}]
 set_property SLEW FAST [get_ports {ddram_cas_n}]
-set_property IOSTANDARD SSTL15 [get_ports {ddram_cas_n}]
+set_property IOSTANDARD SSTL135 [get_ports {ddram_cas_n}]
 
 # ddram:0.we_n
 set_property LOC L1 [get_ports {ddram_we_n}]
 set_property SLEW FAST [get_ports {ddram_we_n}]
-set_property IOSTANDARD SSTL15 [get_ports {ddram_we_n}]
+set_property IOSTANDARD SSTL135 [get_ports {ddram_we_n}]
 
 # ddram:0.dm
 set_property LOC G3 [get_ports {ddram_dm[0]}]
 set_property SLEW FAST [get_ports {ddram_dm[0]}]
-set_property IOSTANDARD SSTL15 [get_ports {ddram_dm[0]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddram_dm[0]}]
 
 # ddram:0.dm
 set_property LOC F1 [get_ports {ddram_dm[1]}]
 set_property SLEW FAST [get_ports {ddram_dm[1]}]
-set_property IOSTANDARD SSTL15 [get_ports {ddram_dm[1]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddram_dm[1]}]
 
 # ddram:0.dq
 set_property LOC G2 [get_ports {ddram_dq[0]}]
 set_property SLEW FAST [get_ports {ddram_dq[0]}]
-set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[0]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[0]}]
-set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddram_dq[0]}]
+set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[0]}]
 
 # ddram:0.dq
 set_property LOC H4 [get_ports {ddram_dq[1]}]
 set_property SLEW FAST [get_ports {ddram_dq[1]}]
-set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[1]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[1]}]
-set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddram_dq[1]}]
+set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[1]}]
 
 # ddram:0.dq
 set_property LOC H5 [get_ports {ddram_dq[2]}]
 set_property SLEW FAST [get_ports {ddram_dq[2]}]
-set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[2]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[2]}]
-set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddram_dq[2]}]
+set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[2]}]
 
 # ddram:0.dq
 set_property LOC J1 [get_ports {ddram_dq[3]}]
 set_property SLEW FAST [get_ports {ddram_dq[3]}]
-set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[3]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[3]}]
-set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddram_dq[3]}]
+set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[3]}]
 
 # ddram:0.dq
 set_property LOC K1 [get_ports {ddram_dq[4]}]
 set_property SLEW FAST [get_ports {ddram_dq[4]}]
-set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[4]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[4]}]
-set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddram_dq[4]}]
+set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[4]}]
 
 # ddram:0.dq
 set_property LOC H3 [get_ports {ddram_dq[5]}]
 set_property SLEW FAST [get_ports {ddram_dq[5]}]
-set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[5]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[5]}]
-set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddram_dq[5]}]
+set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[5]}]
 
 # ddram:0.dq
 set_property LOC H2 [get_ports {ddram_dq[6]}]
 set_property SLEW FAST [get_ports {ddram_dq[6]}]
-set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[6]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[6]}]
-set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddram_dq[6]}]
+set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[6]}]
 
 # ddram:0.dq
 set_property LOC J5 [get_ports {ddram_dq[7]}]
 set_property SLEW FAST [get_ports {ddram_dq[7]}]
-set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[7]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[7]}]
-set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddram_dq[7]}]
+set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[7]}]
 
 # ddram:0.dq
 set_property LOC E3 [get_ports {ddram_dq[8]}]
 set_property SLEW FAST [get_ports {ddram_dq[8]}]
-set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[8]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[8]}]
-set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddram_dq[8]}]
+set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[8]}]
 
 # ddram:0.dq
 set_property LOC B2 [get_ports {ddram_dq[9]}]
 set_property SLEW FAST [get_ports {ddram_dq[9]}]
-set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[9]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[9]}]
-set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddram_dq[9]}]
+set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[9]}]
 
 # ddram:0.dq
 set_property LOC F3 [get_ports {ddram_dq[10]}]
 set_property SLEW FAST [get_ports {ddram_dq[10]}]
-set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[10]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[10]}]
-set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddram_dq[10]}]
+set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[10]}]
 
 # ddram:0.dq
 set_property LOC D2 [get_ports {ddram_dq[11]}]
 set_property SLEW FAST [get_ports {ddram_dq[11]}]
-set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[11]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[11]}]
-set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddram_dq[11]}]
+set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[11]}]
 
 # ddram:0.dq
 set_property LOC C2 [get_ports {ddram_dq[12]}]
 set_property SLEW FAST [get_ports {ddram_dq[12]}]
-set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[12]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[12]}]
-set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddram_dq[12]}]
+set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[12]}]
 
 # ddram:0.dq
 set_property LOC A1 [get_ports {ddram_dq[13]}]
 set_property SLEW FAST [get_ports {ddram_dq[13]}]
-set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[13]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[13]}]
-set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddram_dq[13]}]
+set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[13]}]
 
 # ddram:0.dq
 set_property LOC E2 [get_ports {ddram_dq[14]}]
 set_property SLEW FAST [get_ports {ddram_dq[14]}]
-set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[14]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[14]}]
-set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddram_dq[14]}]
+set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[14]}]
 
 # ddram:0.dq
 set_property LOC B1 [get_ports {ddram_dq[15]}]
 set_property SLEW FAST [get_ports {ddram_dq[15]}]
-set_property IOSTANDARD SSTL15 [get_ports {ddram_dq[15]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddram_dq[15]}]
-set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddram_dq[15]}]
+set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dq[15]}]
 
 # ddram:0.dqs_p
 set_property LOC K2 [get_ports {ddram_dqs_p[0]}]
 set_property SLEW FAST [get_ports {ddram_dqs_p[0]}]
-set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddram_dqs_p[0]}]
+set_property IOSTANDARD DIFF_SSTL135 [get_ports {ddram_dqs_p[0]}]
+set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dqs_p[0]}]
 
 # ddram:0.dqs_p
 set_property LOC E1 [get_ports {ddram_dqs_p[1]}]
 set_property SLEW FAST [get_ports {ddram_dqs_p[1]}]
-set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddram_dqs_p[1]}]
+set_property IOSTANDARD DIFF_SSTL135 [get_ports {ddram_dqs_p[1]}]
+set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dqs_p[1]}]
 
 # ddram:0.dqs_n
 set_property LOC J2 [get_ports {ddram_dqs_n[0]}]
 set_property SLEW FAST [get_ports {ddram_dqs_n[0]}]
-set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddram_dqs_n[0]}]
+set_property IOSTANDARD DIFF_SSTL135 [get_ports {ddram_dqs_n[0]}]
+set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dqs_n[0]}]
 
 # ddram:0.dqs_n
 set_property LOC D1 [get_ports {ddram_dqs_n[1]}]
 set_property SLEW FAST [get_ports {ddram_dqs_n[1]}]
-set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddram_dqs_n[1]}]
+set_property IOSTANDARD DIFF_SSTL135 [get_ports {ddram_dqs_n[1]}]
+set_property IN_TERM UNTUNED_SPLIT_40 [get_ports {ddram_dqs_n[1]}]
 
 # ddram:0.clk_p
 set_property LOC P5 [get_ports {ddram_clk_p}]
 set_property SLEW FAST [get_ports {ddram_clk_p}]
-set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddram_clk_p}]
+set_property IOSTANDARD DIFF_SSTL135 [get_ports {ddram_clk_p}]
 
 # ddram:0.clk_n
 set_property LOC P4 [get_ports {ddram_clk_n}]
 set_property SLEW FAST [get_ports {ddram_clk_n}]
-set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddram_clk_n}]
+set_property IOSTANDARD DIFF_SSTL135 [get_ports {ddram_clk_n}]
 
 # ddram:0.cke
 set_property LOC J6 [get_ports {ddram_cke}]
 set_property SLEW FAST [get_ports {ddram_cke}]
-set_property IOSTANDARD SSTL15 [get_ports {ddram_cke}]
+set_property IOSTANDARD SSTL135 [get_ports {ddram_cke}]
 
 # ddram:0.odt
 set_property LOC K4 [get_ports {ddram_odt}]
 set_property SLEW FAST [get_ports {ddram_odt}]
-set_property IOSTANDARD SSTL15 [get_ports {ddram_odt}]
+set_property IOSTANDARD SSTL135 [get_ports {ddram_odt}]
 
 # ddram:0.reset_n
 set_property LOC G1 [get_ports {ddram_reset_n}]
 set_property SLEW FAST [get_ports {ddram_reset_n}]
-set_property IOSTANDARD SSTL15 [get_ports {ddram_reset_n}]
+set_property IOSTANDARD SSTL135 [get_ports {ddram_reset_n}]
 
 ################################################################################
 # Design constraints and bitsteam attributes