Implement the addpcis instruction

This commit adds support for the addpcis instruction from ISA 3.0.

A new input_reg_b_t type, CONST_DX_HI, was added to support the
shifted immediate value used in DX-Form instructions.

Signed-off-by: Shawn Anastasio <shawn@anastas.io>

decode1.vhdl

@@ -106,8 +106,8 @@ architecture behaviour of decode1 is
 		--                               op                                            in   out   A   out  in    out  len        ext                                 pipe
                 -- mcrf; and cr logical ops
 		2#000#    =>       (ALU,    OP_CROP,      NONE,       NONE,        NONE, NONE, '1', '1', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0'),
-		-- addpcis not implemented yet
+		-- addpcis
-		2#001#    =>       (ALU,    OP_ILLEGAL,   NONE,       NONE,        NONE, NONE, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC,   '0', '1'),
+		2#001#    =>       (ALU,    OP_ADDPCIS,   NONE,       CONST_DX_HI, NONE, RT,   '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC,   '0', '0'),
                 -- bclr, bcctr, bctar
 		2#100#    =>       (ALU,    OP_BCREG,     SPR,        SPR,         NONE, SPR,  '1', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '1', '0'),
                 -- isync

decode2.vhdl

@@ -100,6 +100,8 @@ architecture behaviour of decode2 is
 			ret := ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_bd(insn_in)) & "00", 64)));
 		when CONST_DS =>
 			ret := ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_ds(insn_in)) & "00", 64)));
+		when CONST_DX_HI =>
+			ret := ('0', (others => '0'), std_ulogic_vector(resize(signed(insn_dx(insn_in)) & x"0000", 64)));
                 when CONST_M1 =>
 			ret := ('0', (others => '0'), x"FFFFFFFFFFFFFFFF");
 		when CONST_SH =>

decode_types.vhdl

@@ -21,7 +21,7 @@ package decode_types is
                          OP_FETCH_FAILED
 			 );
     type input_reg_a_t is (NONE, RA, RA_OR_ZERO, SPR);
-    type input_reg_b_t is (NONE, RB, CONST_UI, CONST_SI, CONST_SI_HI, CONST_UI_HI, CONST_LI, CONST_BD, CONST_DS, CONST_M1, CONST_SH, CONST_SH32, SPR);
+    type input_reg_b_t is (NONE, RB, CONST_UI, CONST_SI, CONST_SI_HI, CONST_UI_HI, CONST_LI, CONST_BD, CONST_DX_HI, CONST_DS, CONST_M1, CONST_SH, CONST_SH32, SPR);
     type input_reg_c_t is (NONE, RS);
     type output_reg_a_t is (NONE, RT, RA, SPR);
     type rc_t is (NONE, ONE, RC);

execute1.vhdl

@@ -528,6 +528,9 @@ begin
                 end if;
 	    when OP_NOP =>
 		-- Do nothing
+	    when OP_ADDPCIS =>
+		result := ppc_adde(next_nia, b_in, '0')(63 downto 0);
+		result_en := '1';
 	    when OP_ADD | OP_CMP | OP_TRAP =>
 		if e_in.invert_a = '0' then
 		    a_inv := a_in;

insn_helpers.vhdl

@@ -30,6 +30,7 @@ package insn_helpers is
     function insn_bh (insn_in : std_ulogic_vector) return std_ulogic_vector;
     function insn_d (insn_in : std_ulogic_vector) return std_ulogic_vector;
     function insn_ds (insn_in : std_ulogic_vector) return std_ulogic_vector;
+    function insn_dx (insn_in : std_ulogic_vector) return std_ulogic_vector;
     function insn_to (insn_in : std_ulogic_vector) return std_ulogic_vector;
     function insn_bc (insn_in : std_ulogic_vector) return std_ulogic_vector;
     function insn_sh (insn_in : std_ulogic_vector) return std_ulogic_vector;
@@ -178,6 +179,11 @@ package body insn_helpers is
         return insn_in(15 downto 2);
     end;
 
+    function insn_dx (insn_in : std_ulogic_vector) return std_ulogic_vector is
+    begin
+        return insn_in(15 downto 6) & insn_in(20 downto 16) & insn_in(0);
+    end;
+
     function insn_to (insn_in : std_ulogic_vector) return std_ulogic_vector is
     begin
         return insn_in(25 downto 21);