antmicro-artix-dc-scm: Add Ethernet pins

Signed-off-by: Joel Stanley <joel@jms.id.au>
pull/401/head
Joel Stanley 2 years ago
parent 87a875b940
commit e2ae325d5c

@ -295,6 +295,76 @@ set_property LOC G1 [get_ports {ddram_reset_n}]
set_property SLEW FAST [get_ports {ddram_reset_n}] set_property SLEW FAST [get_ports {ddram_reset_n}]
set_property IOSTANDARD SSTL135 [get_ports {ddram_reset_n}] set_property IOSTANDARD SSTL135 [get_ports {ddram_reset_n}]


################################################################################
# Ethernet (generated by LiteX)
################################################################################

# eth_clocks:0.tx
set_property LOC J19 [get_ports {eth_clocks_tx}]
set_property IOSTANDARD LVCMOS33 [get_ports {eth_clocks_tx}]

# eth_clocks:0.rx
set_property LOC K19 [get_ports {eth_clocks_rx}]
set_property IOSTANDARD LVCMOS33 [get_ports {eth_clocks_rx}]

# eth:0.rst_n
set_property LOC N18 [get_ports {eth_rst_n}]
set_property IOSTANDARD LVCMOS33 [get_ports {eth_rst_n}]

# eth:0.int_n
set_property LOC N20 [get_ports {eth_int_n}]
set_property IOSTANDARD LVCMOS33 [get_ports {eth_int_n}]

# eth:0.mdio
set_property LOC M21 [get_ports {eth_mdio}]
set_property IOSTANDARD LVCMOS33 [get_ports {eth_mdio}]

# eth:0.mdc
set_property LOC N22 [get_ports {eth_mdc}]
set_property IOSTANDARD LVCMOS33 [get_ports {eth_mdc}]

# eth:0.rx_ctl
set_property LOC M22 [get_ports {eth_rx_ctl}]
set_property IOSTANDARD LVCMOS33 [get_ports {eth_rx_ctl}]

# eth:0.rx_data
set_property LOC L20 [get_ports {eth_rx_data[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {eth_rx_data[0]}]

# eth:0.rx_data
set_property LOC L21 [get_ports {eth_rx_data[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {eth_rx_data[1]}]

# eth:0.rx_data
set_property LOC K21 [get_ports {eth_rx_data[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {eth_rx_data[2]}]

# eth:0.rx_data
set_property LOC K22 [get_ports {eth_rx_data[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {eth_rx_data[3]}]

# eth:0.tx_ctl
set_property LOC J22 [get_ports {eth_tx_ctl}]
set_property IOSTANDARD LVCMOS33 [get_ports {eth_tx_ctl}]

# eth:0.tx_data
set_property LOC G20 [get_ports {eth_tx_data[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {eth_tx_data[0]}]

# eth:0.tx_data
set_property LOC H20 [get_ports {eth_tx_data[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {eth_tx_data[1]}]

# eth:0.tx_data
set_property LOC H22 [get_ports {eth_tx_data[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {eth_tx_data[2]}]

# eth:0.tx_data
set_property LOC J21 [get_ports {eth_tx_data[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {eth_tx_data[3]}]



################################################################################ ################################################################################
# Design constraints and bitsteam attributes # Design constraints and bitsteam attributes
################################################################################ ################################################################################
@ -310,8 +380,33 @@ set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property BITSTREAM.CONFIG.CONFIGRATE 33 [current_design] set_property BITSTREAM.CONFIG.CONFIGRATE 33 [current_design]
set_property CONFIG_MODE SPIx4 [current_design] set_property CONFIG_MODE SPIx4 [current_design]


#set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets main_ethphy_eth_rx_clk_ibuf]
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets {has_liteeth.liteeth/main_maccore_ethphy_eth_rx_clk_ibuf}]

################################################################################ ################################################################################
# Clock constraints # Clock constraints
################################################################################ ################################################################################


create_clock -name sys_clk_pin -period 10.00 [get_ports { ext_clk }]; create_clock -name sys_clk_pin -period 10.00 [get_ports { ext_clk }];

create_clock -name eth_clocks_rx -period 8.0 [get_ports { eth_clocks_rx }]

create_clock -name eth_clocks_tx -period 8.0 [get_ports { eth_clocks_tx }]


set_clock_groups -asynchronous -group [get_clocks sys_clk_pin -include_generated_clocks] -group [get_clocks eth_clocks_rx -include_generated_clocks]

set_clock_groups -asynchronous -group [get_clocks sys_clk_pin -include_generated_clocks] -group [get_clocks eth_clocks_tx -include_generated_clocks]



################################################################################
# False path constraints (from LiteX as they relate to LiteDRAM and LiteEth)
################################################################################


set_false_path -quiet -through [get_nets -hierarchical -filter {mr_ff == TRUE}]

set_false_path -quiet -to [get_pins -filter {REF_PIN_NAME == PRE} -of_objects [get_cells -hierarchical -filter {ars_ff1 == TRUE || ars_ff2 == TRUE}]]

set_max_delay 2 -quiet -from [get_pins -filter {REF_PIN_NAME == C} -of_objects [get_cells -hierarchical -filter {ars_ff1 == TRUE}]] -to [get_pins -filter {REF_PIN_NAME == D} -of_objects [get_cells -hierarchical -filter {ars_ff2 == TRUE}]]

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