loads don't do both byte reversal and sign extension

Give the synthesis tools a clue that we don't need to do both byte reversal
and sign extension.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
pull/65/head
Anton Blanchard 5 years ago committed by Anton Blanchard
parent 550b2b8608
commit e1a71e4545

@ -62,6 +62,7 @@ begin
loadstore2_0: process(clk) loadstore2_0: process(clk)
variable tmp : std_ulogic_vector(63 downto 0); variable tmp : std_ulogic_vector(63 downto 0);
variable data : std_ulogic_vector(63 downto 0); variable data : std_ulogic_vector(63 downto 0);
variable sign_extend_byte_reverse : std_ulogic_vector(1 downto 0);
begin begin
if rising_edge(clk) then if rising_edge(clk) then
tmp := (others => '0'); tmp := (others => '0');
@ -127,13 +128,15 @@ begin
assert false report "invalid length" severity failure; assert false report "invalid length" severity failure;
end case; end case;


if l_saved.sign_extend = '1' then sign_extend_byte_reverse := l_saved.sign_extend & l_saved.byte_reverse;
data := sign_extend(data, to_integer(unsigned(l_saved.length)));
end if;


if l_saved.byte_reverse = '1' then case sign_extend_byte_reverse is
when "10" =>
data := sign_extend(data, to_integer(unsigned(l_saved.length)));
when "01" =>
data := byte_reverse(data, to_integer(unsigned(l_saved.length))); data := byte_reverse(data, to_integer(unsigned(l_saved.length)));
end if; when others =>
end case;


w_tmp.write_data <= data; w_tmp.write_data <= data;



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