Use register addresses from decode1 for dependency tracking

This improves timing a little because the register addresses now come
directly from a latch instead of being calculated by
decode_input_reg_*.  The asserts that check that the two are the same
are now in decode2 rather than register_file.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>

common.vhdl

@@ -265,11 +265,15 @@ package common is
         big_endian: std_ulogic;
         spr_info : spr_id;
         ram_spr : ram_spr_info;
+        reg_a : gspr_index_t;
+        reg_b : gspr_index_t;
+        reg_c : gspr_index_t;
     end record;
     constant Decode1ToDecode2Init : Decode1ToDecode2Type :=
         (valid => '0', stop_mark => '0', nia => (others => '0'), insn => (others => '0'),
          decode => decode_rom_init, br_pred => '0', big_endian => '0',
-         spr_info => spr_id_init, ram_spr => ram_spr_info_init);
+         spr_info => spr_id_init, ram_spr => ram_spr_info_init,
+         reg_a => (others => '0'), reg_b => (others => '0'), reg_c => (others => '0'));
 
     type Decode1ToFetch1Type is record
         redirect     : std_ulogic;
@@ -449,11 +453,8 @@ package common is
 
     type Decode2ToRegisterFileType is record
 	read1_enable : std_ulogic;
-	read1_reg : gspr_index_t;
 	read2_enable : std_ulogic;
-	read2_reg : gspr_index_t;
 	read3_enable : std_ulogic;
-	read3_reg : gspr_index_t;
     end record;
 
     type RegisterFileToDecode2Type is record

decode1.vhdl

@@ -792,6 +792,10 @@ begin
         vr.read_2_enable := f_in.valid and not f_in.fetch_failed and may_read_rb;
         vr.read_3_enable := f_in.valid and not f_in.fetch_failed;
 
+        v.reg_a := vr.reg_1_addr;
+        v.reg_b := vr.reg_2_addr;
+        v.reg_c := vr.reg_3_addr;
+
         if f_in.fetch_failed = '1' then
             v.valid := '1';
             vi.override := '1';

decode2.vhdl

@@ -360,6 +360,11 @@ begin
                 dc2.e.ramspr_odd_rdaddr <= dc2in.e.ramspr_odd_rdaddr;
                 dc2.e.ramspr_rd_odd <= dc2in.e.ramspr_rd_odd;
             end if;
+            if d_in.valid = '1' then
+                assert decoded_reg_a.reg_valid = '0' or decoded_reg_a.reg = d_in.reg_a severity failure;
+                assert decoded_reg_b.reg_valid = '0' or decoded_reg_b.reg = d_in.reg_b severity failure;
+                assert decoded_reg_c.reg_valid = '0' or decoded_reg_c.reg = d_in.reg_c severity failure;
+            end if;
         end if;
     end process;
 
@@ -379,11 +384,8 @@ begin
         end if;
 
         r_out.read1_enable <= decoded_reg_a.reg_valid;
-        r_out.read1_reg    <= decoded_reg_a.reg;
         r_out.read2_enable <= decoded_reg_b.reg_valid;
-        r_out.read2_reg    <= decoded_reg_b.reg;
         r_out.read3_enable <= decoded_reg_c.reg_valid;
-        r_out.read3_reg    <= decoded_reg_c.reg;
 
     end process;
 
@@ -537,9 +539,9 @@ begin
             v.e.nia := d_in.nia;
             v.e.unit := d_in.decode.unit;
             v.e.fac := d_in.decode.facility;
-            v.e.read_reg1 := decoded_reg_a.reg;
+            v.e.read_reg1 := d_in.reg_a;
-            v.e.read_reg2 := decoded_reg_b.reg;
+            v.e.read_reg2 := d_in.reg_b;
-            v.e.read_reg3 := decoded_reg_c.reg;
+            v.e.read_reg3 := d_in.reg_c;
             v.e.write_reg := decoded_reg_o.reg;
             v.e.write_reg_enable := decoded_reg_o.reg_valid;
             v.e.invert_a := d_in.decode.invert_a;

register_file.vhdl

@@ -125,10 +125,6 @@ begin
             data_3 <= registers(to_integer(unsigned(c_addr)));
 
             prev_write_data <= w_in.write_data;
-
-            assert (d_in.read1_enable = '0') or (d_in.read1_reg = addr_1_reg) severity failure;
-            assert (d_in.read2_enable = '0') or (d_in.read2_reg = addr_2_reg) severity failure;
-            assert (d_in.read3_enable = '0') or (d_in.read3_reg = addr_3_reg) severity failure;
         end if;
     end process register_write_0;