diff --git a/litedram/generated/acorn-cle-215/litedram_core.init b/litedram/generated/acorn-cle-215/litedram_core.init
index 5bfb299..5b1a383 100644
--- a/litedram/generated/acorn-cle-215/litedram_core.init
+++ b/litedram/generated/acorn-cle-215/litedram_core.init
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@@ -1918,9 +1938,9 @@ e8010010ebc1fff0
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 0000000000000000
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 4d4152446574694c
 6620746c69756220
 6567694d206d6f72
@@ -2013,6 +2033,10 @@ e8010010ebc1fff0
 64656570736d654d
 2820702520746120
 0000000000000000
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+0000000000000000
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 0000000a2e2e2e29
 2065746972572020
 00203a6465657073
diff --git a/litedram/generated/acorn-cle-215/litedram_core.v b/litedram/generated/acorn-cle-215/litedram_core.v
index cb57b44..41a3761 100644
--- a/litedram/generated/acorn-cle-215/litedram_core.v
+++ b/litedram/generated/acorn-cle-215/litedram_core.v
@@ -1,5 +1,5 @@
 //--------------------------------------------------------------------------------
-// Auto-generated by Migen (27dbf03) & LiteX (78c1751c) on 2021-08-15 06:19:17
+// Auto-generated by Migen (a5bc262) & LiteX (de028765) on 2021-09-24 12:36:37
 //--------------------------------------------------------------------------------
 module litedram_core(
 	input wire clk,
@@ -3684,6 +3684,35 @@ assign main_litedramcore_dfi_p3_rddata_valid = main_litedramcore_slave_p3_rddata
 // synthesis translate_off
 reg dummy_d_42;
 // synthesis translate_on
+always @(*) begin
+	main_litedramcore_master_p2_wrdata_en <= 1'd0;
+	if (main_litedramcore_sel) begin
+		main_litedramcore_master_p2_wrdata_en <= main_litedramcore_slave_p2_wrdata_en;
+	end else begin
+		main_litedramcore_master_p2_wrdata_en <= main_litedramcore_inti_p2_wrdata_en;
+	end
+// synthesis translate_off
+	dummy_d_42 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_43;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_inti_p3_rddata_valid <= 1'd0;
+	if (main_litedramcore_sel) begin
+	end else begin
+		main_litedramcore_inti_p3_rddata_valid <= main_litedramcore_master_p3_rddata_valid;
+	end
+// synthesis translate_off
+	dummy_d_43 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_44;
+// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p2_wrdata_mask <= 4'd0;
 	if (main_litedramcore_sel) begin
@@ -3692,12 +3721,12 @@ always @(*) begin
 		main_litedramcore_master_p2_wrdata_mask <= main_litedramcore_inti_p2_wrdata_mask;
 	end
 // synthesis translate_off
-	dummy_d_42 = dummy_s;
+	dummy_d_44 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_43;
+reg dummy_d_45;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p2_rddata_en <= 1'd0;
@@ -3707,12 +3736,12 @@ always @(*) begin
 		main_litedramcore_master_p2_rddata_en <= main_litedramcore_inti_p2_rddata_en;
 	end
 // synthesis translate_off
-	dummy_d_43 = dummy_s;
+	dummy_d_45 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_44;
+reg dummy_d_46;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p3_address <= 16'd0;
@@ -3722,12 +3751,12 @@ always @(*) begin
 		main_litedramcore_master_p3_address <= main_litedramcore_inti_p3_address;
 	end
 // synthesis translate_off
-	dummy_d_44 = dummy_s;
+	dummy_d_46 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_45;
+reg dummy_d_47;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p3_bank <= 3'd0;
@@ -3737,12 +3766,12 @@ always @(*) begin
 		main_litedramcore_master_p3_bank <= main_litedramcore_inti_p3_bank;
 	end
 // synthesis translate_off
-	dummy_d_45 = dummy_s;
+	dummy_d_47 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_46;
+reg dummy_d_48;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p3_cas_n <= 1'd1;
@@ -3752,12 +3781,12 @@ always @(*) begin
 		main_litedramcore_master_p3_cas_n <= main_litedramcore_inti_p3_cas_n;
 	end
 // synthesis translate_off
-	dummy_d_46 = dummy_s;
+	dummy_d_48 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_47;
+reg dummy_d_49;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p3_cs_n <= 1'd1;
@@ -3767,12 +3796,12 @@ always @(*) begin
 		main_litedramcore_master_p3_cs_n <= main_litedramcore_inti_p3_cs_n;
 	end
 // synthesis translate_off
-	dummy_d_47 = dummy_s;
+	dummy_d_49 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_48;
+reg dummy_d_50;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p3_ras_n <= 1'd1;
@@ -3782,12 +3811,12 @@ always @(*) begin
 		main_litedramcore_master_p3_ras_n <= main_litedramcore_inti_p3_ras_n;
 	end
 // synthesis translate_off
-	dummy_d_48 = dummy_s;
+	dummy_d_50 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_49;
+reg dummy_d_51;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_slave_p3_rddata <= 32'd0;
@@ -3796,12 +3825,12 @@ always @(*) begin
 	end else begin
 	end
 // synthesis translate_off
-	dummy_d_49 = dummy_s;
+	dummy_d_51 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_50;
+reg dummy_d_52;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p3_we_n <= 1'd1;
@@ -3811,12 +3840,12 @@ always @(*) begin
 		main_litedramcore_master_p3_we_n <= main_litedramcore_inti_p3_we_n;
 	end
 // synthesis translate_off
-	dummy_d_50 = dummy_s;
+	dummy_d_52 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_51;
+reg dummy_d_53;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_slave_p3_rddata_valid <= 1'd0;
@@ -3825,12 +3854,12 @@ always @(*) begin
 	end else begin
 	end
 // synthesis translate_off
-	dummy_d_51 = dummy_s;
+	dummy_d_53 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_52;
+reg dummy_d_54;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p3_cke <= 1'd0;
@@ -3840,12 +3869,12 @@ always @(*) begin
 		main_litedramcore_master_p3_cke <= main_litedramcore_inti_p3_cke;
 	end
 // synthesis translate_off
-	dummy_d_52 = dummy_s;
+	dummy_d_54 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_53;
+reg dummy_d_55;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p3_odt <= 1'd0;
@@ -3855,12 +3884,12 @@ always @(*) begin
 		main_litedramcore_master_p3_odt <= main_litedramcore_inti_p3_odt;
 	end
 // synthesis translate_off
-	dummy_d_53 = dummy_s;
+	dummy_d_55 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_54;
+reg dummy_d_56;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p3_reset_n <= 1'd0;
@@ -3870,12 +3899,12 @@ always @(*) begin
 		main_litedramcore_master_p3_reset_n <= main_litedramcore_inti_p3_reset_n;
 	end
 // synthesis translate_off
-	dummy_d_54 = dummy_s;
+	dummy_d_56 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_55;
+reg dummy_d_57;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p3_act_n <= 1'd1;
@@ -3885,12 +3914,12 @@ always @(*) begin
 		main_litedramcore_master_p3_act_n <= main_litedramcore_inti_p3_act_n;
 	end
 // synthesis translate_off
-	dummy_d_55 = dummy_s;
+	dummy_d_57 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_56;
+reg dummy_d_58;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p3_wrdata <= 32'd0;
@@ -3900,12 +3929,12 @@ always @(*) begin
 		main_litedramcore_master_p3_wrdata <= main_litedramcore_inti_p3_wrdata;
 	end
 // synthesis translate_off
-	dummy_d_56 = dummy_s;
+	dummy_d_58 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_57;
+reg dummy_d_59;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_inti_p0_rddata <= 32'd0;
@@ -3914,12 +3943,12 @@ always @(*) begin
 		main_litedramcore_inti_p0_rddata <= main_litedramcore_master_p0_rddata;
 	end
 // synthesis translate_off
-	dummy_d_57 = dummy_s;
+	dummy_d_59 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_58;
+reg dummy_d_60;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p3_wrdata_en <= 1'd0;
@@ -3929,12 +3958,12 @@ always @(*) begin
 		main_litedramcore_master_p3_wrdata_en <= main_litedramcore_inti_p3_wrdata_en;
 	end
 // synthesis translate_off
-	dummy_d_58 = dummy_s;
+	dummy_d_60 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_59;
+reg dummy_d_61;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_inti_p0_rddata_valid <= 1'd0;
@@ -3943,12 +3972,12 @@ always @(*) begin
 		main_litedramcore_inti_p0_rddata_valid <= main_litedramcore_master_p0_rddata_valid;
 	end
 // synthesis translate_off
-	dummy_d_59 = dummy_s;
+	dummy_d_61 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_60;
+reg dummy_d_62;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p3_wrdata_mask <= 4'd0;
@@ -3958,12 +3987,12 @@ always @(*) begin
 		main_litedramcore_master_p3_wrdata_mask <= main_litedramcore_inti_p3_wrdata_mask;
 	end
 // synthesis translate_off
-	dummy_d_60 = dummy_s;
+	dummy_d_62 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_61;
+reg dummy_d_63;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p3_rddata_en <= 1'd0;
@@ -3973,12 +4002,12 @@ always @(*) begin
 		main_litedramcore_master_p3_rddata_en <= main_litedramcore_inti_p3_rddata_en;
 	end
 // synthesis translate_off
-	dummy_d_61 = dummy_s;
+	dummy_d_63 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_62;
+reg dummy_d_64;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p0_address <= 16'd0;
@@ -3988,12 +4017,12 @@ always @(*) begin
 		main_litedramcore_master_p0_address <= main_litedramcore_inti_p0_address;
 	end
 // synthesis translate_off
-	dummy_d_62 = dummy_s;
+	dummy_d_64 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_63;
+reg dummy_d_65;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p0_bank <= 3'd0;
@@ -4003,12 +4032,12 @@ always @(*) begin
 		main_litedramcore_master_p0_bank <= main_litedramcore_inti_p0_bank;
 	end
 // synthesis translate_off
-	dummy_d_63 = dummy_s;
+	dummy_d_65 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_64;
+reg dummy_d_66;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p0_cas_n <= 1'd1;
@@ -4018,12 +4047,12 @@ always @(*) begin
 		main_litedramcore_master_p0_cas_n <= main_litedramcore_inti_p0_cas_n;
 	end
 // synthesis translate_off
-	dummy_d_64 = dummy_s;
+	dummy_d_66 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_65;
+reg dummy_d_67;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p0_cs_n <= 1'd1;
@@ -4033,12 +4062,12 @@ always @(*) begin
 		main_litedramcore_master_p0_cs_n <= main_litedramcore_inti_p0_cs_n;
 	end
 // synthesis translate_off
-	dummy_d_65 = dummy_s;
+	dummy_d_67 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_66;
+reg dummy_d_68;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p0_ras_n <= 1'd1;
@@ -4048,12 +4077,12 @@ always @(*) begin
 		main_litedramcore_master_p0_ras_n <= main_litedramcore_inti_p0_ras_n;
 	end
 // synthesis translate_off
-	dummy_d_66 = dummy_s;
+	dummy_d_68 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_67;
+reg dummy_d_69;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_slave_p0_rddata <= 32'd0;
@@ -4062,12 +4091,12 @@ always @(*) begin
 	end else begin
 	end
 // synthesis translate_off
-	dummy_d_67 = dummy_s;
+	dummy_d_69 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_68;
+reg dummy_d_70;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p0_we_n <= 1'd1;
@@ -4077,12 +4106,12 @@ always @(*) begin
 		main_litedramcore_master_p0_we_n <= main_litedramcore_inti_p0_we_n;
 	end
 // synthesis translate_off
-	dummy_d_68 = dummy_s;
+	dummy_d_70 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_69;
+reg dummy_d_71;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_slave_p0_rddata_valid <= 1'd0;
@@ -4091,12 +4120,12 @@ always @(*) begin
 	end else begin
 	end
 // synthesis translate_off
-	dummy_d_69 = dummy_s;
+	dummy_d_71 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_70;
+reg dummy_d_72;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p0_cke <= 1'd0;
@@ -4106,12 +4135,12 @@ always @(*) begin
 		main_litedramcore_master_p0_cke <= main_litedramcore_inti_p0_cke;
 	end
 // synthesis translate_off
-	dummy_d_70 = dummy_s;
+	dummy_d_72 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_71;
+reg dummy_d_73;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p0_odt <= 1'd0;
@@ -4121,12 +4150,12 @@ always @(*) begin
 		main_litedramcore_master_p0_odt <= main_litedramcore_inti_p0_odt;
 	end
 // synthesis translate_off
-	dummy_d_71 = dummy_s;
+	dummy_d_73 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_72;
+reg dummy_d_74;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p0_reset_n <= 1'd0;
@@ -4136,12 +4165,12 @@ always @(*) begin
 		main_litedramcore_master_p0_reset_n <= main_litedramcore_inti_p0_reset_n;
 	end
 // synthesis translate_off
-	dummy_d_72 = dummy_s;
+	dummy_d_74 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_73;
+reg dummy_d_75;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p0_act_n <= 1'd1;
@@ -4151,12 +4180,12 @@ always @(*) begin
 		main_litedramcore_master_p0_act_n <= main_litedramcore_inti_p0_act_n;
 	end
 // synthesis translate_off
-	dummy_d_73 = dummy_s;
+	dummy_d_75 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_74;
+reg dummy_d_76;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p0_wrdata <= 32'd0;
@@ -4166,12 +4195,12 @@ always @(*) begin
 		main_litedramcore_master_p0_wrdata <= main_litedramcore_inti_p0_wrdata;
 	end
 // synthesis translate_off
-	dummy_d_74 = dummy_s;
+	dummy_d_76 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_75;
+reg dummy_d_77;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_inti_p1_rddata <= 32'd0;
@@ -4180,12 +4209,12 @@ always @(*) begin
 		main_litedramcore_inti_p1_rddata <= main_litedramcore_master_p1_rddata;
 	end
 // synthesis translate_off
-	dummy_d_75 = dummy_s;
+	dummy_d_77 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_76;
+reg dummy_d_78;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p0_wrdata_en <= 1'd0;
@@ -4195,12 +4224,12 @@ always @(*) begin
 		main_litedramcore_master_p0_wrdata_en <= main_litedramcore_inti_p0_wrdata_en;
 	end
 // synthesis translate_off
-	dummy_d_76 = dummy_s;
+	dummy_d_78 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_77;
+reg dummy_d_79;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_inti_p1_rddata_valid <= 1'd0;
@@ -4209,12 +4238,12 @@ always @(*) begin
 		main_litedramcore_inti_p1_rddata_valid <= main_litedramcore_master_p1_rddata_valid;
 	end
 // synthesis translate_off
-	dummy_d_77 = dummy_s;
+	dummy_d_79 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_78;
+reg dummy_d_80;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p0_wrdata_mask <= 4'd0;
@@ -4224,12 +4253,12 @@ always @(*) begin
 		main_litedramcore_master_p0_wrdata_mask <= main_litedramcore_inti_p0_wrdata_mask;
 	end
 // synthesis translate_off
-	dummy_d_78 = dummy_s;
+	dummy_d_80 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_79;
+reg dummy_d_81;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p0_rddata_en <= 1'd0;
@@ -4239,12 +4268,12 @@ always @(*) begin
 		main_litedramcore_master_p0_rddata_en <= main_litedramcore_inti_p0_rddata_en;
 	end
 // synthesis translate_off
-	dummy_d_79 = dummy_s;
+	dummy_d_81 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_80;
+reg dummy_d_82;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p1_address <= 16'd0;
@@ -4254,12 +4283,12 @@ always @(*) begin
 		main_litedramcore_master_p1_address <= main_litedramcore_inti_p1_address;
 	end
 // synthesis translate_off
-	dummy_d_80 = dummy_s;
+	dummy_d_82 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_81;
+reg dummy_d_83;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p1_bank <= 3'd0;
@@ -4269,12 +4298,12 @@ always @(*) begin
 		main_litedramcore_master_p1_bank <= main_litedramcore_inti_p1_bank;
 	end
 // synthesis translate_off
-	dummy_d_81 = dummy_s;
+	dummy_d_83 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_82;
+reg dummy_d_84;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p1_cas_n <= 1'd1;
@@ -4284,12 +4313,12 @@ always @(*) begin
 		main_litedramcore_master_p1_cas_n <= main_litedramcore_inti_p1_cas_n;
 	end
 // synthesis translate_off
-	dummy_d_82 = dummy_s;
+	dummy_d_84 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_83;
+reg dummy_d_85;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p1_cs_n <= 1'd1;
@@ -4299,12 +4328,12 @@ always @(*) begin
 		main_litedramcore_master_p1_cs_n <= main_litedramcore_inti_p1_cs_n;
 	end
 // synthesis translate_off
-	dummy_d_83 = dummy_s;
+	dummy_d_85 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_84;
+reg dummy_d_86;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p1_ras_n <= 1'd1;
@@ -4314,12 +4343,12 @@ always @(*) begin
 		main_litedramcore_master_p1_ras_n <= main_litedramcore_inti_p1_ras_n;
 	end
 // synthesis translate_off
-	dummy_d_84 = dummy_s;
+	dummy_d_86 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_85;
+reg dummy_d_87;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_slave_p1_rddata <= 32'd0;
@@ -4328,12 +4357,12 @@ always @(*) begin
 	end else begin
 	end
 // synthesis translate_off
-	dummy_d_85 = dummy_s;
+	dummy_d_87 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_86;
+reg dummy_d_88;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p1_we_n <= 1'd1;
@@ -4343,12 +4372,12 @@ always @(*) begin
 		main_litedramcore_master_p1_we_n <= main_litedramcore_inti_p1_we_n;
 	end
 // synthesis translate_off
-	dummy_d_86 = dummy_s;
+	dummy_d_88 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_87;
+reg dummy_d_89;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_slave_p1_rddata_valid <= 1'd0;
@@ -4357,12 +4386,12 @@ always @(*) begin
 	end else begin
 	end
 // synthesis translate_off
-	dummy_d_87 = dummy_s;
+	dummy_d_89 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_88;
+reg dummy_d_90;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p1_cke <= 1'd0;
@@ -4372,12 +4401,12 @@ always @(*) begin
 		main_litedramcore_master_p1_cke <= main_litedramcore_inti_p1_cke;
 	end
 // synthesis translate_off
-	dummy_d_88 = dummy_s;
+	dummy_d_90 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_89;
+reg dummy_d_91;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p1_odt <= 1'd0;
@@ -4387,26 +4416,12 @@ always @(*) begin
 		main_litedramcore_master_p1_odt <= main_litedramcore_inti_p1_odt;
 	end
 // synthesis translate_off
-	dummy_d_89 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_90;
-// synthesis translate_on
-always @(*) begin
-	main_litedramcore_inti_p3_rddata_valid <= 1'd0;
-	if (main_litedramcore_sel) begin
-	end else begin
-		main_litedramcore_inti_p3_rddata_valid <= main_litedramcore_master_p3_rddata_valid;
-	end
-// synthesis translate_off
-	dummy_d_90 = dummy_s;
+	dummy_d_91 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_91;
+reg dummy_d_92;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p1_reset_n <= 1'd0;
@@ -4416,12 +4431,12 @@ always @(*) begin
 		main_litedramcore_master_p1_reset_n <= main_litedramcore_inti_p1_reset_n;
 	end
 // synthesis translate_off
-	dummy_d_91 = dummy_s;
+	dummy_d_92 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_92;
+reg dummy_d_93;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p1_act_n <= 1'd1;
@@ -4431,12 +4446,12 @@ always @(*) begin
 		main_litedramcore_master_p1_act_n <= main_litedramcore_inti_p1_act_n;
 	end
 // synthesis translate_off
-	dummy_d_92 = dummy_s;
+	dummy_d_93 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_93;
+reg dummy_d_94;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p1_wrdata <= 32'd0;
@@ -4446,12 +4461,12 @@ always @(*) begin
 		main_litedramcore_master_p1_wrdata <= main_litedramcore_inti_p1_wrdata;
 	end
 // synthesis translate_off
-	dummy_d_93 = dummy_s;
+	dummy_d_94 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_94;
+reg dummy_d_95;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_inti_p2_rddata <= 32'd0;
@@ -4460,12 +4475,12 @@ always @(*) begin
 		main_litedramcore_inti_p2_rddata <= main_litedramcore_master_p2_rddata;
 	end
 // synthesis translate_off
-	dummy_d_94 = dummy_s;
+	dummy_d_95 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_95;
+reg dummy_d_96;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p1_wrdata_en <= 1'd0;
@@ -4475,12 +4490,12 @@ always @(*) begin
 		main_litedramcore_master_p1_wrdata_en <= main_litedramcore_inti_p1_wrdata_en;
 	end
 // synthesis translate_off
-	dummy_d_95 = dummy_s;
+	dummy_d_96 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_96;
+reg dummy_d_97;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_inti_p2_rddata_valid <= 1'd0;
@@ -4489,12 +4504,12 @@ always @(*) begin
 		main_litedramcore_inti_p2_rddata_valid <= main_litedramcore_master_p2_rddata_valid;
 	end
 // synthesis translate_off
-	dummy_d_96 = dummy_s;
+	dummy_d_97 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_97;
+reg dummy_d_98;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p1_wrdata_mask <= 4'd0;
@@ -4504,12 +4519,12 @@ always @(*) begin
 		main_litedramcore_master_p1_wrdata_mask <= main_litedramcore_inti_p1_wrdata_mask;
 	end
 // synthesis translate_off
-	dummy_d_97 = dummy_s;
+	dummy_d_98 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_98;
+reg dummy_d_99;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p1_rddata_en <= 1'd0;
@@ -4519,12 +4534,12 @@ always @(*) begin
 		main_litedramcore_master_p1_rddata_en <= main_litedramcore_inti_p1_rddata_en;
 	end
 // synthesis translate_off
-	dummy_d_98 = dummy_s;
+	dummy_d_99 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_99;
+reg dummy_d_100;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p2_address <= 16'd0;
@@ -4534,12 +4549,12 @@ always @(*) begin
 		main_litedramcore_master_p2_address <= main_litedramcore_inti_p2_address;
 	end
 // synthesis translate_off
-	dummy_d_99 = dummy_s;
+	dummy_d_100 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_100;
+reg dummy_d_101;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p2_bank <= 3'd0;
@@ -4548,21 +4563,6 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p2_bank <= main_litedramcore_inti_p2_bank;
 	end
-// synthesis translate_off
-	dummy_d_100 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_101;
-// synthesis translate_on
-always @(*) begin
-	main_litedramcore_master_p2_cas_n <= 1'd1;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p2_cas_n <= main_litedramcore_slave_p2_cas_n;
-	end else begin
-		main_litedramcore_master_p2_cas_n <= main_litedramcore_inti_p2_cas_n;
-	end
 // synthesis translate_off
 	dummy_d_101 = dummy_s;
 // synthesis translate_on
@@ -4572,10 +4572,11 @@ end
 reg dummy_d_102;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_inti_p3_rddata <= 32'd0;
+	main_litedramcore_master_p2_cas_n <= 1'd1;
 	if (main_litedramcore_sel) begin
+		main_litedramcore_master_p2_cas_n <= main_litedramcore_slave_p2_cas_n;
 	end else begin
-		main_litedramcore_inti_p3_rddata <= main_litedramcore_master_p3_rddata;
+		main_litedramcore_master_p2_cas_n <= main_litedramcore_inti_p2_cas_n;
 	end
 // synthesis translate_off
 	dummy_d_102 = dummy_s;
@@ -4674,11 +4675,10 @@ end
 reg dummy_d_109;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_master_p2_odt <= 1'd0;
+	main_litedramcore_inti_p3_rddata <= 32'd0;
 	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p2_odt <= main_litedramcore_slave_p2_odt;
 	end else begin
-		main_litedramcore_master_p2_odt <= main_litedramcore_inti_p2_odt;
+		main_litedramcore_inti_p3_rddata <= main_litedramcore_master_p3_rddata;
 	end
 // synthesis translate_off
 	dummy_d_109 = dummy_s;
@@ -4689,11 +4689,11 @@ end
 reg dummy_d_110;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_master_p2_reset_n <= 1'd0;
+	main_litedramcore_master_p2_odt <= 1'd0;
 	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p2_reset_n <= main_litedramcore_slave_p2_reset_n;
+		main_litedramcore_master_p2_odt <= main_litedramcore_slave_p2_odt;
 	end else begin
-		main_litedramcore_master_p2_reset_n <= main_litedramcore_inti_p2_reset_n;
+		main_litedramcore_master_p2_odt <= main_litedramcore_inti_p2_odt;
 	end
 // synthesis translate_off
 	dummy_d_110 = dummy_s;
@@ -4704,11 +4704,11 @@ end
 reg dummy_d_111;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_master_p2_act_n <= 1'd1;
+	main_litedramcore_master_p2_reset_n <= 1'd0;
 	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p2_act_n <= main_litedramcore_slave_p2_act_n;
+		main_litedramcore_master_p2_reset_n <= main_litedramcore_slave_p2_reset_n;
 	end else begin
-		main_litedramcore_master_p2_act_n <= main_litedramcore_inti_p2_act_n;
+		main_litedramcore_master_p2_reset_n <= main_litedramcore_inti_p2_reset_n;
 	end
 // synthesis translate_off
 	dummy_d_111 = dummy_s;
@@ -4719,11 +4719,11 @@ end
 reg dummy_d_112;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_master_p2_wrdata <= 32'd0;
+	main_litedramcore_master_p2_act_n <= 1'd1;
 	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p2_wrdata <= main_litedramcore_slave_p2_wrdata;
+		main_litedramcore_master_p2_act_n <= main_litedramcore_slave_p2_act_n;
 	end else begin
-		main_litedramcore_master_p2_wrdata <= main_litedramcore_inti_p2_wrdata;
+		main_litedramcore_master_p2_act_n <= main_litedramcore_inti_p2_act_n;
 	end
 // synthesis translate_off
 	dummy_d_112 = dummy_s;
@@ -4734,11 +4734,11 @@ end
 reg dummy_d_113;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_master_p2_wrdata_en <= 1'd0;
+	main_litedramcore_master_p2_wrdata <= 32'd0;
 	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p2_wrdata_en <= main_litedramcore_slave_p2_wrdata_en;
+		main_litedramcore_master_p2_wrdata <= main_litedramcore_slave_p2_wrdata;
 	end else begin
-		main_litedramcore_master_p2_wrdata_en <= main_litedramcore_inti_p2_wrdata_en;
+		main_litedramcore_master_p2_wrdata <= main_litedramcore_inti_p2_wrdata;
 	end
 // synthesis translate_off
 	dummy_d_113 = dummy_s;
@@ -4761,11 +4761,11 @@ assign main_litedramcore_inti_p3_reset_n = main_litedramcore_reset_n;
 reg dummy_d_114;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_inti_p0_ras_n <= 1'd1;
+	main_litedramcore_inti_p0_cs_n <= 1'd1;
 	if (main_litedramcore_phaseinjector0_command_issue_re) begin
-		main_litedramcore_inti_p0_ras_n <= (~main_litedramcore_phaseinjector0_command_storage[3]);
+		main_litedramcore_inti_p0_cs_n <= {1{(~main_litedramcore_phaseinjector0_command_storage[0])}};
 	end else begin
-		main_litedramcore_inti_p0_ras_n <= 1'd1;
+		main_litedramcore_inti_p0_cs_n <= {1{1'd1}};
 	end
 // synthesis translate_off
 	dummy_d_114 = dummy_s;
@@ -4776,11 +4776,11 @@ end
 reg dummy_d_115;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_inti_p0_we_n <= 1'd1;
+	main_litedramcore_inti_p0_ras_n <= 1'd1;
 	if (main_litedramcore_phaseinjector0_command_issue_re) begin
-		main_litedramcore_inti_p0_we_n <= (~main_litedramcore_phaseinjector0_command_storage[1]);
+		main_litedramcore_inti_p0_ras_n <= (~main_litedramcore_phaseinjector0_command_storage[3]);
 	end else begin
-		main_litedramcore_inti_p0_we_n <= 1'd1;
+		main_litedramcore_inti_p0_ras_n <= 1'd1;
 	end
 // synthesis translate_off
 	dummy_d_115 = dummy_s;
@@ -4791,11 +4791,11 @@ end
 reg dummy_d_116;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_inti_p0_cas_n <= 1'd1;
+	main_litedramcore_inti_p0_we_n <= 1'd1;
 	if (main_litedramcore_phaseinjector0_command_issue_re) begin
-		main_litedramcore_inti_p0_cas_n <= (~main_litedramcore_phaseinjector0_command_storage[2]);
+		main_litedramcore_inti_p0_we_n <= (~main_litedramcore_phaseinjector0_command_storage[1]);
 	end else begin
-		main_litedramcore_inti_p0_cas_n <= 1'd1;
+		main_litedramcore_inti_p0_we_n <= 1'd1;
 	end
 // synthesis translate_off
 	dummy_d_116 = dummy_s;
@@ -4806,11 +4806,11 @@ end
 reg dummy_d_117;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_inti_p0_cs_n <= 1'd1;
+	main_litedramcore_inti_p0_cas_n <= 1'd1;
 	if (main_litedramcore_phaseinjector0_command_issue_re) begin
-		main_litedramcore_inti_p0_cs_n <= {1{(~main_litedramcore_phaseinjector0_command_storage[0])}};
+		main_litedramcore_inti_p0_cas_n <= (~main_litedramcore_phaseinjector0_command_storage[2]);
 	end else begin
-		main_litedramcore_inti_p0_cs_n <= {1{1'd1}};
+		main_litedramcore_inti_p0_cas_n <= 1'd1;
 	end
 // synthesis translate_off
 	dummy_d_117 = dummy_s;
@@ -4827,11 +4827,11 @@ assign main_litedramcore_inti_p0_wrdata_mask = 1'd0;
 reg dummy_d_118;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_inti_p1_ras_n <= 1'd1;
+	main_litedramcore_inti_p1_cs_n <= 1'd1;
 	if (main_litedramcore_phaseinjector1_command_issue_re) begin
-		main_litedramcore_inti_p1_ras_n <= (~main_litedramcore_phaseinjector1_command_storage[3]);
+		main_litedramcore_inti_p1_cs_n <= {1{(~main_litedramcore_phaseinjector1_command_storage[0])}};
 	end else begin
-		main_litedramcore_inti_p1_ras_n <= 1'd1;
+		main_litedramcore_inti_p1_cs_n <= {1{1'd1}};
 	end
 // synthesis translate_off
 	dummy_d_118 = dummy_s;
@@ -4842,11 +4842,11 @@ end
 reg dummy_d_119;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_inti_p1_we_n <= 1'd1;
+	main_litedramcore_inti_p1_ras_n <= 1'd1;
 	if (main_litedramcore_phaseinjector1_command_issue_re) begin
-		main_litedramcore_inti_p1_we_n <= (~main_litedramcore_phaseinjector1_command_storage[1]);
+		main_litedramcore_inti_p1_ras_n <= (~main_litedramcore_phaseinjector1_command_storage[3]);
 	end else begin
-		main_litedramcore_inti_p1_we_n <= 1'd1;
+		main_litedramcore_inti_p1_ras_n <= 1'd1;
 	end
 // synthesis translate_off
 	dummy_d_119 = dummy_s;
@@ -4857,11 +4857,11 @@ end
 reg dummy_d_120;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_inti_p1_cas_n <= 1'd1;
+	main_litedramcore_inti_p1_we_n <= 1'd1;
 	if (main_litedramcore_phaseinjector1_command_issue_re) begin
-		main_litedramcore_inti_p1_cas_n <= (~main_litedramcore_phaseinjector1_command_storage[2]);
+		main_litedramcore_inti_p1_we_n <= (~main_litedramcore_phaseinjector1_command_storage[1]);
 	end else begin
-		main_litedramcore_inti_p1_cas_n <= 1'd1;
+		main_litedramcore_inti_p1_we_n <= 1'd1;
 	end
 // synthesis translate_off
 	dummy_d_120 = dummy_s;
@@ -4872,11 +4872,11 @@ end
 reg dummy_d_121;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_inti_p1_cs_n <= 1'd1;
+	main_litedramcore_inti_p1_cas_n <= 1'd1;
 	if (main_litedramcore_phaseinjector1_command_issue_re) begin
-		main_litedramcore_inti_p1_cs_n <= {1{(~main_litedramcore_phaseinjector1_command_storage[0])}};
+		main_litedramcore_inti_p1_cas_n <= (~main_litedramcore_phaseinjector1_command_storage[2]);
 	end else begin
-		main_litedramcore_inti_p1_cs_n <= {1{1'd1}};
+		main_litedramcore_inti_p1_cas_n <= 1'd1;
 	end
 // synthesis translate_off
 	dummy_d_121 = dummy_s;
@@ -4893,11 +4893,11 @@ assign main_litedramcore_inti_p1_wrdata_mask = 1'd0;
 reg dummy_d_122;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_inti_p2_ras_n <= 1'd1;
+	main_litedramcore_inti_p2_cs_n <= 1'd1;
 	if (main_litedramcore_phaseinjector2_command_issue_re) begin
-		main_litedramcore_inti_p2_ras_n <= (~main_litedramcore_phaseinjector2_command_storage[3]);
+		main_litedramcore_inti_p2_cs_n <= {1{(~main_litedramcore_phaseinjector2_command_storage[0])}};
 	end else begin
-		main_litedramcore_inti_p2_ras_n <= 1'd1;
+		main_litedramcore_inti_p2_cs_n <= {1{1'd1}};
 	end
 // synthesis translate_off
 	dummy_d_122 = dummy_s;
@@ -4908,11 +4908,11 @@ end
 reg dummy_d_123;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_inti_p2_we_n <= 1'd1;
+	main_litedramcore_inti_p2_ras_n <= 1'd1;
 	if (main_litedramcore_phaseinjector2_command_issue_re) begin
-		main_litedramcore_inti_p2_we_n <= (~main_litedramcore_phaseinjector2_command_storage[1]);
+		main_litedramcore_inti_p2_ras_n <= (~main_litedramcore_phaseinjector2_command_storage[3]);
 	end else begin
-		main_litedramcore_inti_p2_we_n <= 1'd1;
+		main_litedramcore_inti_p2_ras_n <= 1'd1;
 	end
 // synthesis translate_off
 	dummy_d_123 = dummy_s;
@@ -4923,11 +4923,11 @@ end
 reg dummy_d_124;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_inti_p2_cas_n <= 1'd1;
+	main_litedramcore_inti_p2_we_n <= 1'd1;
 	if (main_litedramcore_phaseinjector2_command_issue_re) begin
-		main_litedramcore_inti_p2_cas_n <= (~main_litedramcore_phaseinjector2_command_storage[2]);
+		main_litedramcore_inti_p2_we_n <= (~main_litedramcore_phaseinjector2_command_storage[1]);
 	end else begin
-		main_litedramcore_inti_p2_cas_n <= 1'd1;
+		main_litedramcore_inti_p2_we_n <= 1'd1;
 	end
 // synthesis translate_off
 	dummy_d_124 = dummy_s;
@@ -4938,11 +4938,11 @@ end
 reg dummy_d_125;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_inti_p2_cs_n <= 1'd1;
+	main_litedramcore_inti_p2_cas_n <= 1'd1;
 	if (main_litedramcore_phaseinjector2_command_issue_re) begin
-		main_litedramcore_inti_p2_cs_n <= {1{(~main_litedramcore_phaseinjector2_command_storage[0])}};
+		main_litedramcore_inti_p2_cas_n <= (~main_litedramcore_phaseinjector2_command_storage[2]);
 	end else begin
-		main_litedramcore_inti_p2_cs_n <= {1{1'd1}};
+		main_litedramcore_inti_p2_cas_n <= 1'd1;
 	end
 // synthesis translate_off
 	dummy_d_125 = dummy_s;
@@ -4959,11 +4959,11 @@ assign main_litedramcore_inti_p2_wrdata_mask = 1'd0;
 reg dummy_d_126;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_inti_p3_ras_n <= 1'd1;
+	main_litedramcore_inti_p3_cs_n <= 1'd1;
 	if (main_litedramcore_phaseinjector3_command_issue_re) begin
-		main_litedramcore_inti_p3_ras_n <= (~main_litedramcore_phaseinjector3_command_storage[3]);
+		main_litedramcore_inti_p3_cs_n <= {1{(~main_litedramcore_phaseinjector3_command_storage[0])}};
 	end else begin
-		main_litedramcore_inti_p3_ras_n <= 1'd1;
+		main_litedramcore_inti_p3_cs_n <= {1{1'd1}};
 	end
 // synthesis translate_off
 	dummy_d_126 = dummy_s;
@@ -4974,11 +4974,11 @@ end
 reg dummy_d_127;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_inti_p3_we_n <= 1'd1;
+	main_litedramcore_inti_p3_ras_n <= 1'd1;
 	if (main_litedramcore_phaseinjector3_command_issue_re) begin
-		main_litedramcore_inti_p3_we_n <= (~main_litedramcore_phaseinjector3_command_storage[1]);
+		main_litedramcore_inti_p3_ras_n <= (~main_litedramcore_phaseinjector3_command_storage[3]);
 	end else begin
-		main_litedramcore_inti_p3_we_n <= 1'd1;
+		main_litedramcore_inti_p3_ras_n <= 1'd1;
 	end
 // synthesis translate_off
 	dummy_d_127 = dummy_s;
@@ -4989,11 +4989,11 @@ end
 reg dummy_d_128;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_inti_p3_cas_n <= 1'd1;
+	main_litedramcore_inti_p3_we_n <= 1'd1;
 	if (main_litedramcore_phaseinjector3_command_issue_re) begin
-		main_litedramcore_inti_p3_cas_n <= (~main_litedramcore_phaseinjector3_command_storage[2]);
+		main_litedramcore_inti_p3_we_n <= (~main_litedramcore_phaseinjector3_command_storage[1]);
 	end else begin
-		main_litedramcore_inti_p3_cas_n <= 1'd1;
+		main_litedramcore_inti_p3_we_n <= 1'd1;
 	end
 // synthesis translate_off
 	dummy_d_128 = dummy_s;
@@ -5004,11 +5004,11 @@ end
 reg dummy_d_129;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_inti_p3_cs_n <= 1'd1;
+	main_litedramcore_inti_p3_cas_n <= 1'd1;
 	if (main_litedramcore_phaseinjector3_command_issue_re) begin
-		main_litedramcore_inti_p3_cs_n <= {1{(~main_litedramcore_phaseinjector3_command_storage[0])}};
+		main_litedramcore_inti_p3_cas_n <= (~main_litedramcore_phaseinjector3_command_storage[2]);
 	end else begin
-		main_litedramcore_inti_p3_cs_n <= {1{1'd1}};
+		main_litedramcore_inti_p3_cas_n <= 1'd1;
 	end
 // synthesis translate_off
 	dummy_d_129 = dummy_s;
@@ -5545,7 +5545,7 @@ end
 reg dummy_d_143;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine0_req_rdata_valid <= 1'd0;
+	main_litedramcore_bankmachine0_cmd_payload_cas <= 1'd0;
 	case (builder_bankmachine0_state)
 		1'd1: begin
 		end
@@ -5569,10 +5569,7 @@ always @(*) begin
 				if (main_litedramcore_bankmachine0_cmd_buffer_source_valid) begin
 					if (main_litedramcore_bankmachine0_row_opened) begin
 						if (main_litedramcore_bankmachine0_row_hit) begin
-							if (main_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
-							end else begin
-								main_litedramcore_bankmachine0_req_rdata_valid <= main_litedramcore_bankmachine0_cmd_ready;
-							end
+							main_litedramcore_bankmachine0_cmd_payload_cas <= 1'd1;
 						end else begin
 						end
 					end else begin
@@ -5590,7 +5587,7 @@ end
 reg dummy_d_144;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine0_cmd_payload_cas <= 1'd0;
+	main_litedramcore_bankmachine0_req_rdata_valid <= 1'd0;
 	case (builder_bankmachine0_state)
 		1'd1: begin
 		end
@@ -5614,7 +5611,10 @@ always @(*) begin
 				if (main_litedramcore_bankmachine0_cmd_buffer_source_valid) begin
 					if (main_litedramcore_bankmachine0_row_opened) begin
 						if (main_litedramcore_bankmachine0_row_hit) begin
-							main_litedramcore_bankmachine0_cmd_payload_cas <= 1'd1;
+							if (main_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
+							end else begin
+								main_litedramcore_bankmachine0_req_rdata_valid <= main_litedramcore_bankmachine0_cmd_ready;
+							end
 						end else begin
 						end
 					end else begin
@@ -6419,7 +6419,7 @@ end
 reg dummy_d_165;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine1_req_rdata_valid <= 1'd0;
+	main_litedramcore_bankmachine1_cmd_payload_is_read <= 1'd0;
 	case (builder_bankmachine1_state)
 		1'd1: begin
 		end
@@ -6445,7 +6445,7 @@ always @(*) begin
 						if (main_litedramcore_bankmachine1_row_hit) begin
 							if (main_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
 							end else begin
-								main_litedramcore_bankmachine1_req_rdata_valid <= main_litedramcore_bankmachine1_cmd_ready;
+								main_litedramcore_bankmachine1_cmd_payload_is_read <= 1'd1;
 							end
 						end else begin
 						end
@@ -6464,7 +6464,7 @@ end
 reg dummy_d_166;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine1_cmd_payload_is_read <= 1'd0;
+	main_litedramcore_bankmachine1_cmd_payload_is_write <= 1'd0;
 	case (builder_bankmachine1_state)
 		1'd1: begin
 		end
@@ -6489,8 +6489,8 @@ always @(*) begin
 					if (main_litedramcore_bankmachine1_row_opened) begin
 						if (main_litedramcore_bankmachine1_row_hit) begin
 							if (main_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
+								main_litedramcore_bankmachine1_cmd_payload_is_write <= 1'd1;
 							end else begin
-								main_litedramcore_bankmachine1_cmd_payload_is_read <= 1'd1;
 							end
 						end else begin
 						end
@@ -6509,7 +6509,7 @@ end
 reg dummy_d_167;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine1_cmd_payload_is_write <= 1'd0;
+	main_litedramcore_bankmachine1_req_rdata_valid <= 1'd0;
 	case (builder_bankmachine1_state)
 		1'd1: begin
 		end
@@ -6534,8 +6534,8 @@ always @(*) begin
 					if (main_litedramcore_bankmachine1_row_opened) begin
 						if (main_litedramcore_bankmachine1_row_hit) begin
 							if (main_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
-								main_litedramcore_bankmachine1_cmd_payload_is_write <= 1'd1;
 							end else begin
+								main_litedramcore_bankmachine1_req_rdata_valid <= main_litedramcore_bankmachine1_cmd_ready;
 							end
 						end else begin
 						end
@@ -6834,6 +6834,51 @@ end
 // synthesis translate_off
 reg dummy_d_175;
 // synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine2_req_rdata_valid <= 1'd0;
+	case (builder_bankmachine2_state)
+		1'd1: begin
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+			if (main_litedramcore_bankmachine2_refresh_req) begin
+			end else begin
+				if (main_litedramcore_bankmachine2_cmd_buffer_source_valid) begin
+					if (main_litedramcore_bankmachine2_row_opened) begin
+						if (main_litedramcore_bankmachine2_row_hit) begin
+							if (main_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
+							end else begin
+								main_litedramcore_bankmachine2_req_rdata_valid <= main_litedramcore_bankmachine2_cmd_ready;
+							end
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_175 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_176;
+// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine2_row_open <= 1'd0;
 	case (builder_bankmachine2_state)
@@ -6860,12 +6905,12 @@ always @(*) begin
 		end
 	endcase
 // synthesis translate_off
-	dummy_d_175 = dummy_s;
+	dummy_d_176 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_176;
+reg dummy_d_177;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine2_row_close <= 1'd0;
@@ -6893,12 +6938,12 @@ always @(*) begin
 		end
 	endcase
 // synthesis translate_off
-	dummy_d_176 = dummy_s;
+	dummy_d_177 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_177;
+reg dummy_d_178;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine2_cmd_payload_cas <= 1'd0;
@@ -6935,12 +6980,12 @@ always @(*) begin
 		end
 	endcase
 // synthesis translate_off
-	dummy_d_177 = dummy_s;
+	dummy_d_178 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_178;
+reg dummy_d_179;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine2_cmd_payload_ras <= 1'd0;
@@ -6971,12 +7016,12 @@ always @(*) begin
 		end
 	endcase
 // synthesis translate_off
-	dummy_d_178 = dummy_s;
+	dummy_d_179 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_179;
+reg dummy_d_180;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine2_cmd_payload_we <= 1'd0;
@@ -7019,12 +7064,12 @@ always @(*) begin
 		end
 	endcase
 // synthesis translate_off
-	dummy_d_179 = dummy_s;
+	dummy_d_180 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_180;
+reg dummy_d_181;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd0;
@@ -7052,12 +7097,12 @@ always @(*) begin
 		end
 	endcase
 // synthesis translate_off
-	dummy_d_180 = dummy_s;
+	dummy_d_181 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_181;
+reg dummy_d_182;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd0;
@@ -7075,37 +7120,7 @@ always @(*) begin
 			end
 		end
 		3'd4: begin
-			main_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
-		end
-		3'd5: begin
-		end
-		3'd6: begin
-		end
-		3'd7: begin
-		end
-		4'd8: begin
-		end
-		default: begin
-		end
-	endcase
-// synthesis translate_off
-	dummy_d_181 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_182;
-// synthesis translate_on
-always @(*) begin
-	main_litedramcore_bankmachine2_cmd_payload_is_read <= 1'd0;
-	case (builder_bankmachine2_state)
-		1'd1: begin
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-		end
-		3'd4: begin
+			main_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
 		end
 		3'd5: begin
 		end
@@ -7116,21 +7131,6 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine2_refresh_req) begin
-			end else begin
-				if (main_litedramcore_bankmachine2_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine2_row_opened) begin
-						if (main_litedramcore_bankmachine2_row_hit) begin
-							if (main_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
-							end else begin
-								main_litedramcore_bankmachine2_cmd_payload_is_read <= 1'd1;
-							end
-						end else begin
-						end
-					end else begin
-					end
-				end
-			end
 		end
 	endcase
 // synthesis translate_off
@@ -7142,7 +7142,7 @@ end
 reg dummy_d_183;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine2_cmd_payload_is_write <= 1'd0;
+	main_litedramcore_bankmachine2_cmd_payload_is_read <= 1'd0;
 	case (builder_bankmachine2_state)
 		1'd1: begin
 		end
@@ -7167,8 +7167,8 @@ always @(*) begin
 					if (main_litedramcore_bankmachine2_row_opened) begin
 						if (main_litedramcore_bankmachine2_row_hit) begin
 							if (main_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
-								main_litedramcore_bankmachine2_cmd_payload_is_write <= 1'd1;
 							end else begin
+								main_litedramcore_bankmachine2_cmd_payload_is_read <= 1'd1;
 							end
 						end else begin
 						end
@@ -7187,7 +7187,7 @@ end
 reg dummy_d_184;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine2_req_wdata_ready <= 1'd0;
+	main_litedramcore_bankmachine2_cmd_payload_is_write <= 1'd0;
 	case (builder_bankmachine2_state)
 		1'd1: begin
 		end
@@ -7212,7 +7212,7 @@ always @(*) begin
 					if (main_litedramcore_bankmachine2_row_opened) begin
 						if (main_litedramcore_bankmachine2_row_hit) begin
 							if (main_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
-								main_litedramcore_bankmachine2_req_wdata_ready <= main_litedramcore_bankmachine2_cmd_ready;
+								main_litedramcore_bankmachine2_cmd_payload_is_write <= 1'd1;
 							end else begin
 							end
 						end else begin
@@ -7232,7 +7232,7 @@ end
 reg dummy_d_185;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine2_req_rdata_valid <= 1'd0;
+	main_litedramcore_bankmachine2_req_wdata_ready <= 1'd0;
 	case (builder_bankmachine2_state)
 		1'd1: begin
 		end
@@ -7257,8 +7257,8 @@ always @(*) begin
 					if (main_litedramcore_bankmachine2_row_opened) begin
 						if (main_litedramcore_bankmachine2_row_hit) begin
 							if (main_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
+								main_litedramcore_bankmachine2_req_wdata_ready <= main_litedramcore_bankmachine2_cmd_ready;
 							end else begin
-								main_litedramcore_bankmachine2_req_rdata_valid <= main_litedramcore_bankmachine2_cmd_ready;
 							end
 						end else begin
 						end
@@ -7513,13 +7513,16 @@ end
 reg dummy_d_192;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine3_req_rdata_valid <= 1'd0;
+	main_litedramcore_bankmachine3_row_open <= 1'd0;
 	case (builder_bankmachine3_state)
 		1'd1: begin
 		end
 		2'd2: begin
 		end
 		2'd3: begin
+			if (main_litedramcore_bankmachine3_trccon_ready) begin
+				main_litedramcore_bankmachine3_row_open <= 1'd1;
+			end
 		end
 		3'd4: begin
 		end
@@ -7532,21 +7535,6 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine3_refresh_req) begin
-			end else begin
-				if (main_litedramcore_bankmachine3_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine3_row_opened) begin
-						if (main_litedramcore_bankmachine3_row_hit) begin
-							if (main_litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
-							end else begin
-								main_litedramcore_bankmachine3_req_rdata_valid <= main_litedramcore_bankmachine3_cmd_ready;
-							end
-						end else begin
-						end
-					end else begin
-					end
-				end
-			end
 		end
 	endcase
 // synthesis translate_off
@@ -7558,16 +7546,13 @@ end
 reg dummy_d_193;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine3_row_open <= 1'd0;
+	main_litedramcore_bankmachine3_req_rdata_valid <= 1'd0;
 	case (builder_bankmachine3_state)
 		1'd1: begin
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine3_trccon_ready) begin
-				main_litedramcore_bankmachine3_row_open <= 1'd1;
-			end
 		end
 		3'd4: begin
 		end
@@ -7580,6 +7565,21 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
+			if (main_litedramcore_bankmachine3_refresh_req) begin
+			end else begin
+				if (main_litedramcore_bankmachine3_cmd_buffer_source_valid) begin
+					if (main_litedramcore_bankmachine3_row_opened) begin
+						if (main_litedramcore_bankmachine3_row_hit) begin
+							if (main_litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
+							end else begin
+								main_litedramcore_bankmachine3_req_rdata_valid <= main_litedramcore_bankmachine3_cmd_ready;
+							end
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
 		end
 	endcase
 // synthesis translate_off
@@ -8299,13 +8299,19 @@ end
 reg dummy_d_212;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine4_req_rdata_valid <= 1'd0;
+	main_litedramcore_bankmachine4_cmd_payload_ras <= 1'd0;
 	case (builder_bankmachine4_state)
 		1'd1: begin
+			if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin
+				main_litedramcore_bankmachine4_cmd_payload_ras <= 1'd1;
+			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
+			if (main_litedramcore_bankmachine4_trccon_ready) begin
+				main_litedramcore_bankmachine4_cmd_payload_ras <= 1'd1;
+			end
 		end
 		3'd4: begin
 		end
@@ -8318,21 +8324,6 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine4_refresh_req) begin
-			end else begin
-				if (main_litedramcore_bankmachine4_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine4_row_opened) begin
-						if (main_litedramcore_bankmachine4_row_hit) begin
-							if (main_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
-							end else begin
-								main_litedramcore_bankmachine4_req_rdata_valid <= main_litedramcore_bankmachine4_cmd_ready;
-							end
-						end else begin
-						end
-					end else begin
-					end
-				end
-			end
 		end
 	endcase
 // synthesis translate_off
@@ -8344,19 +8335,16 @@ end
 reg dummy_d_213;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine4_cmd_payload_ras <= 1'd0;
+	main_litedramcore_bankmachine4_cmd_payload_we <= 1'd0;
 	case (builder_bankmachine4_state)
 		1'd1: begin
 			if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin
-				main_litedramcore_bankmachine4_cmd_payload_ras <= 1'd1;
+				main_litedramcore_bankmachine4_cmd_payload_we <= 1'd1;
 			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine4_trccon_ready) begin
-				main_litedramcore_bankmachine4_cmd_payload_ras <= 1'd1;
-			end
 		end
 		3'd4: begin
 		end
@@ -8369,6 +8357,21 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
+			if (main_litedramcore_bankmachine4_refresh_req) begin
+			end else begin
+				if (main_litedramcore_bankmachine4_cmd_buffer_source_valid) begin
+					if (main_litedramcore_bankmachine4_row_opened) begin
+						if (main_litedramcore_bankmachine4_row_hit) begin
+							if (main_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
+								main_litedramcore_bankmachine4_cmd_payload_we <= 1'd1;
+							end else begin
+							end
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
 		end
 	endcase
 // synthesis translate_off
@@ -8380,16 +8383,16 @@ end
 reg dummy_d_214;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine4_cmd_payload_we <= 1'd0;
+	main_litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd0;
 	case (builder_bankmachine4_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin
-				main_litedramcore_bankmachine4_cmd_payload_we <= 1'd1;
-			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
+			if (main_litedramcore_bankmachine4_trccon_ready) begin
+				main_litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd1;
+			end
 		end
 		3'd4: begin
 		end
@@ -8402,21 +8405,6 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine4_refresh_req) begin
-			end else begin
-				if (main_litedramcore_bankmachine4_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine4_row_opened) begin
-						if (main_litedramcore_bankmachine4_row_hit) begin
-							if (main_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
-								main_litedramcore_bankmachine4_cmd_payload_we <= 1'd1;
-							end else begin
-							end
-						end else begin
-						end
-					end else begin
-					end
-				end
-			end
 		end
 	endcase
 // synthesis translate_off
@@ -8428,16 +8416,13 @@ end
 reg dummy_d_215;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd0;
+	main_litedramcore_bankmachine4_req_rdata_valid <= 1'd0;
 	case (builder_bankmachine4_state)
 		1'd1: begin
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine4_trccon_ready) begin
-				main_litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd1;
-			end
 		end
 		3'd4: begin
 		end
@@ -8450,6 +8435,21 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
+			if (main_litedramcore_bankmachine4_refresh_req) begin
+			end else begin
+				if (main_litedramcore_bankmachine4_cmd_buffer_source_valid) begin
+					if (main_litedramcore_bankmachine4_row_opened) begin
+						if (main_litedramcore_bankmachine4_row_hit) begin
+							if (main_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
+							end else begin
+								main_litedramcore_bankmachine4_req_rdata_valid <= main_litedramcore_bankmachine4_cmd_ready;
+							end
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
 		end
 	endcase
 // synthesis translate_off
@@ -9221,7 +9221,7 @@ end
 reg dummy_d_235;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine5_req_rdata_valid <= 1'd0;
+	main_litedramcore_bankmachine5_req_wdata_ready <= 1'd0;
 	case (builder_bankmachine5_state)
 		1'd1: begin
 		end
@@ -9246,8 +9246,8 @@ always @(*) begin
 					if (main_litedramcore_bankmachine5_row_opened) begin
 						if (main_litedramcore_bankmachine5_row_hit) begin
 							if (main_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
+								main_litedramcore_bankmachine5_req_wdata_ready <= main_litedramcore_bankmachine5_cmd_ready;
 							end else begin
-								main_litedramcore_bankmachine5_req_rdata_valid <= main_litedramcore_bankmachine5_cmd_ready;
 							end
 						end else begin
 						end
@@ -9266,7 +9266,7 @@ end
 reg dummy_d_236;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine5_req_wdata_ready <= 1'd0;
+	main_litedramcore_bankmachine5_req_rdata_valid <= 1'd0;
 	case (builder_bankmachine5_state)
 		1'd1: begin
 		end
@@ -9291,8 +9291,8 @@ always @(*) begin
 					if (main_litedramcore_bankmachine5_row_opened) begin
 						if (main_litedramcore_bankmachine5_row_hit) begin
 							if (main_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
-								main_litedramcore_bankmachine5_req_wdata_ready <= main_litedramcore_bankmachine5_cmd_ready;
 							end else begin
+								main_litedramcore_bankmachine5_req_rdata_valid <= main_litedramcore_bankmachine5_cmd_ready;
 							end
 						end else begin
 						end
@@ -10258,15 +10258,18 @@ end
 reg dummy_d_261;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine7_req_rdata_valid <= 1'd0;
+	main_litedramcore_bankmachine7_row_close <= 1'd0;
 	case (builder_bankmachine7_state)
 		1'd1: begin
+			main_litedramcore_bankmachine7_row_close <= 1'd1;
 		end
 		2'd2: begin
+			main_litedramcore_bankmachine7_row_close <= 1'd1;
 		end
 		2'd3: begin
 		end
 		3'd4: begin
+			main_litedramcore_bankmachine7_row_close <= 1'd1;
 		end
 		3'd5: begin
 		end
@@ -10277,21 +10280,6 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine7_refresh_req) begin
-			end else begin
-				if (main_litedramcore_bankmachine7_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine7_row_opened) begin
-						if (main_litedramcore_bankmachine7_row_hit) begin
-							if (main_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
-							end else begin
-								main_litedramcore_bankmachine7_req_rdata_valid <= main_litedramcore_bankmachine7_cmd_ready;
-							end
-						end else begin
-						end
-					end else begin
-					end
-				end
-			end
 		end
 	endcase
 // synthesis translate_off
@@ -10303,18 +10291,15 @@ end
 reg dummy_d_262;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine7_row_close <= 1'd0;
+	main_litedramcore_bankmachine7_cmd_payload_cas <= 1'd0;
 	case (builder_bankmachine7_state)
 		1'd1: begin
-			main_litedramcore_bankmachine7_row_close <= 1'd1;
 		end
 		2'd2: begin
-			main_litedramcore_bankmachine7_row_close <= 1'd1;
 		end
 		2'd3: begin
 		end
 		3'd4: begin
-			main_litedramcore_bankmachine7_row_close <= 1'd1;
 		end
 		3'd5: begin
 		end
@@ -10325,6 +10310,18 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
+			if (main_litedramcore_bankmachine7_refresh_req) begin
+			end else begin
+				if (main_litedramcore_bankmachine7_cmd_buffer_source_valid) begin
+					if (main_litedramcore_bankmachine7_row_opened) begin
+						if (main_litedramcore_bankmachine7_row_hit) begin
+							main_litedramcore_bankmachine7_cmd_payload_cas <= 1'd1;
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
 		end
 	endcase
 // synthesis translate_off
@@ -10336,7 +10333,7 @@ end
 reg dummy_d_263;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine7_cmd_payload_cas <= 1'd0;
+	main_litedramcore_bankmachine7_req_rdata_valid <= 1'd0;
 	case (builder_bankmachine7_state)
 		1'd1: begin
 		end
@@ -10360,7 +10357,10 @@ always @(*) begin
 				if (main_litedramcore_bankmachine7_cmd_buffer_source_valid) begin
 					if (main_litedramcore_bankmachine7_row_opened) begin
 						if (main_litedramcore_bankmachine7_row_hit) begin
-							main_litedramcore_bankmachine7_cmd_payload_cas <= 1'd1;
+							if (main_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
+							end else begin
+								main_litedramcore_bankmachine7_req_rdata_valid <= main_litedramcore_bankmachine7_cmd_ready;
+							end
 						end else begin
 						end
 					end else begin
@@ -11031,6 +11031,54 @@ end
 // synthesis translate_off
 reg dummy_d_288;
 // synthesis translate_on
+always @(*) begin
+	main_litedramcore_steerer_sel1 <= 2'd0;
+	case (builder_multiplexer_state)
+		1'd1: begin
+			main_litedramcore_steerer_sel1 <= 1'd0;
+			if ((main_a7ddrphy_wrphase_storage == 1'd1)) begin
+				main_litedramcore_steerer_sel1 <= 2'd2;
+			end
+			if ((main_litedramcore_wrcmdphase == 1'd1)) begin
+				main_litedramcore_steerer_sel1 <= 1'd1;
+			end
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		4'd9: begin
+		end
+		4'd10: begin
+		end
+		default: begin
+			main_litedramcore_steerer_sel1 <= 1'd0;
+			if ((main_a7ddrphy_rdphase_storage == 1'd1)) begin
+				main_litedramcore_steerer_sel1 <= 2'd2;
+			end
+			if ((main_litedramcore_rdcmdphase == 1'd1)) begin
+				main_litedramcore_steerer_sel1 <= 1'd1;
+			end
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_288 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_289;
+// synthesis translate_on
 always @(*) begin
 	main_litedramcore_steerer_sel2 <= 2'd0;
 	case (builder_multiplexer_state)
@@ -11072,12 +11120,12 @@ always @(*) begin
 		end
 	endcase
 // synthesis translate_off
-	dummy_d_288 = dummy_s;
+	dummy_d_289 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_289;
+reg dummy_d_290;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_choose_cmd_want_activates <= 1'd0;
@@ -11114,12 +11162,12 @@ always @(*) begin
 		end
 	endcase
 // synthesis translate_off
-	dummy_d_289 = dummy_s;
+	dummy_d_290 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_290;
+reg dummy_d_291;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_steerer_sel3 <= 2'd0;
@@ -11162,12 +11210,12 @@ always @(*) begin
 		end
 	endcase
 // synthesis translate_off
-	dummy_d_290 = dummy_s;
+	dummy_d_291 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_291;
+reg dummy_d_292;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_en0 <= 1'd0;
@@ -11197,12 +11245,12 @@ always @(*) begin
 		end
 	endcase
 // synthesis translate_off
-	dummy_d_291 = dummy_s;
+	dummy_d_292 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_292;
+reg dummy_d_293;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_choose_cmd_cmd_ready <= 1'd0;
@@ -11239,12 +11287,12 @@ always @(*) begin
 		end
 	endcase
 // synthesis translate_off
-	dummy_d_292 = dummy_s;
+	dummy_d_293 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_293;
+reg dummy_d_294;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_choose_req_want_reads <= 1'd0;
@@ -11274,12 +11322,12 @@ always @(*) begin
 		end
 	endcase
 // synthesis translate_off
-	dummy_d_293 = dummy_s;
+	dummy_d_294 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_294;
+reg dummy_d_295;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_choose_req_want_writes <= 1'd0;
@@ -11309,12 +11357,12 @@ always @(*) begin
 		end
 	endcase
 // synthesis translate_off
-	dummy_d_294 = dummy_s;
+	dummy_d_295 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_295;
+reg dummy_d_296;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_choose_req_cmd_ready <= 1'd0;
@@ -11353,12 +11401,12 @@ always @(*) begin
 		end
 	endcase
 // synthesis translate_off
-	dummy_d_295 = dummy_s;
+	dummy_d_296 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_296;
+reg dummy_d_297;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_en1 <= 1'd0;
@@ -11388,12 +11436,12 @@ always @(*) begin
 		end
 	endcase
 // synthesis translate_off
-	dummy_d_296 = dummy_s;
+	dummy_d_297 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_297;
+reg dummy_d_298;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_steerer_sel0 <= 2'd0;
@@ -11436,41 +11484,6 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_297 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_298;
-// synthesis translate_on
-always @(*) begin
-	main_litedramcore_cmd_ready <= 1'd0;
-	case (builder_multiplexer_state)
-		1'd1: begin
-		end
-		2'd2: begin
-			main_litedramcore_cmd_ready <= 1'd1;
-		end
-		2'd3: begin
-		end
-		3'd4: begin
-		end
-		3'd5: begin
-		end
-		3'd6: begin
-		end
-		3'd7: begin
-		end
-		4'd8: begin
-		end
-		4'd9: begin
-		end
-		4'd10: begin
-		end
-		default: begin
-		end
-	endcase
 // synthesis translate_off
 	dummy_d_298 = dummy_s;
 // synthesis translate_on
@@ -11480,18 +11493,12 @@ end
 reg dummy_d_299;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_steerer_sel1 <= 2'd0;
+	main_litedramcore_cmd_ready <= 1'd0;
 	case (builder_multiplexer_state)
 		1'd1: begin
-			main_litedramcore_steerer_sel1 <= 1'd0;
-			if ((main_a7ddrphy_wrphase_storage == 1'd1)) begin
-				main_litedramcore_steerer_sel1 <= 2'd2;
-			end
-			if ((main_litedramcore_wrcmdphase == 1'd1)) begin
-				main_litedramcore_steerer_sel1 <= 1'd1;
-			end
 		end
 		2'd2: begin
+			main_litedramcore_cmd_ready <= 1'd1;
 		end
 		2'd3: begin
 		end
@@ -11510,13 +11517,6 @@ always @(*) begin
 		4'd10: begin
 		end
 		default: begin
-			main_litedramcore_steerer_sel1 <= 1'd0;
-			if ((main_a7ddrphy_rdphase_storage == 1'd1)) begin
-				main_litedramcore_steerer_sel1 <= 2'd2;
-			end
-			if ((main_litedramcore_rdcmdphase == 1'd1)) begin
-				main_litedramcore_steerer_sel1 <= 1'd1;
-			end
 		end
 	endcase
 // synthesis translate_off
@@ -11810,7 +11810,7 @@ assign builder_litedramcore_wishbone_we = main_wb_bus_we;
 assign builder_litedramcore_wishbone_cti = main_wb_bus_cti;
 assign builder_litedramcore_wishbone_bte = main_wb_bus_bte;
 assign main_wb_bus_err = builder_litedramcore_wishbone_err;
-assign builder_csrbank0_sel = (builder_interface0_bank_bus_adr[13:9] == 1'd0);
+assign builder_csrbank0_sel = (builder_interface0_bank_bus_adr[13:9] == 1'd1);
 assign builder_csrbank0_init_done0_r = builder_interface0_bank_bus_dat_w[0];
 
 // synthesis translate_off
@@ -11867,7 +11867,7 @@ always @(*) begin
 end
 assign builder_csrbank0_init_done0_w = main_init_done_storage;
 assign builder_csrbank0_init_error0_w = main_init_error_storage;
-assign builder_csrbank1_sel = (builder_interface1_bank_bus_adr[13:9] == 1'd1);
+assign builder_csrbank1_sel = (builder_interface1_bank_bus_adr[13:9] == 2'd2);
 assign builder_csrbank1_rst0_r = builder_interface1_bank_bus_dat_w[0];
 
 // synthesis translate_off
@@ -11901,9 +11901,9 @@ assign builder_csrbank1_half_sys8x_taps0_r = builder_interface1_bank_bus_dat_w[4
 reg dummy_d_317;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank1_half_sys8x_taps0_re <= 1'd0;
+	builder_csrbank1_half_sys8x_taps0_we <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd1))) begin
-		builder_csrbank1_half_sys8x_taps0_re <= builder_interface1_bank_bus_we;
+		builder_csrbank1_half_sys8x_taps0_we <= (~builder_interface1_bank_bus_we);
 	end
 // synthesis translate_off
 	dummy_d_317 = dummy_s;
@@ -11914,9 +11914,9 @@ end
 reg dummy_d_318;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank1_half_sys8x_taps0_we <= 1'd0;
+	builder_csrbank1_half_sys8x_taps0_re <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd1))) begin
-		builder_csrbank1_half_sys8x_taps0_we <= (~builder_interface1_bank_bus_we);
+		builder_csrbank1_half_sys8x_taps0_re <= builder_interface1_bank_bus_we;
 	end
 // synthesis translate_off
 	dummy_d_318 = dummy_s;
@@ -11955,9 +11955,9 @@ assign main_a7ddrphy_wlevel_strobe_r = builder_interface1_bank_bus_dat_w[0];
 reg dummy_d_321;
 // synthesis translate_on
 always @(*) begin
-	main_a7ddrphy_wlevel_strobe_re <= 1'd0;
+	main_a7ddrphy_wlevel_strobe_we <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd3))) begin
-		main_a7ddrphy_wlevel_strobe_re <= builder_interface1_bank_bus_we;
+		main_a7ddrphy_wlevel_strobe_we <= (~builder_interface1_bank_bus_we);
 	end
 // synthesis translate_off
 	dummy_d_321 = dummy_s;
@@ -11968,9 +11968,9 @@ end
 reg dummy_d_322;
 // synthesis translate_on
 always @(*) begin
-	main_a7ddrphy_wlevel_strobe_we <= 1'd0;
+	main_a7ddrphy_wlevel_strobe_re <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd3))) begin
-		main_a7ddrphy_wlevel_strobe_we <= (~builder_interface1_bank_bus_we);
+		main_a7ddrphy_wlevel_strobe_re <= builder_interface1_bank_bus_we;
 	end
 // synthesis translate_off
 	dummy_d_322 = dummy_s;
@@ -12063,9 +12063,9 @@ assign main_a7ddrphy_rdly_dq_bitslip_rst_r = builder_interface1_bank_bus_dat_w[0
 reg dummy_d_329;
 // synthesis translate_on
 always @(*) begin
-	main_a7ddrphy_rdly_dq_bitslip_rst_re <= 1'd0;
+	main_a7ddrphy_rdly_dq_bitslip_rst_we <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd7))) begin
-		main_a7ddrphy_rdly_dq_bitslip_rst_re <= builder_interface1_bank_bus_we;
+		main_a7ddrphy_rdly_dq_bitslip_rst_we <= (~builder_interface1_bank_bus_we);
 	end
 // synthesis translate_off
 	dummy_d_329 = dummy_s;
@@ -12076,9 +12076,9 @@ end
 reg dummy_d_330;
 // synthesis translate_on
 always @(*) begin
-	main_a7ddrphy_rdly_dq_bitslip_rst_we <= 1'd0;
+	main_a7ddrphy_rdly_dq_bitslip_rst_re <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd7))) begin
-		main_a7ddrphy_rdly_dq_bitslip_rst_we <= (~builder_interface1_bank_bus_we);
+		main_a7ddrphy_rdly_dq_bitslip_rst_re <= builder_interface1_bank_bus_we;
 	end
 // synthesis translate_off
 	dummy_d_330 = dummy_s;
@@ -12198,9 +12198,9 @@ assign builder_csrbank1_wrphase0_r = builder_interface1_bank_bus_dat_w[1:0];
 reg dummy_d_339;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank1_wrphase0_we <= 1'd0;
+	builder_csrbank1_wrphase0_re <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd12))) begin
-		builder_csrbank1_wrphase0_we <= (~builder_interface1_bank_bus_we);
+		builder_csrbank1_wrphase0_re <= builder_interface1_bank_bus_we;
 	end
 // synthesis translate_off
 	dummy_d_339 = dummy_s;
@@ -12211,9 +12211,9 @@ end
 reg dummy_d_340;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank1_wrphase0_re <= 1'd0;
+	builder_csrbank1_wrphase0_we <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd12))) begin
-		builder_csrbank1_wrphase0_re <= builder_interface1_bank_bus_we;
+		builder_csrbank1_wrphase0_we <= (~builder_interface1_bank_bus_we);
 	end
 // synthesis translate_off
 	dummy_d_340 = dummy_s;
@@ -12225,7 +12225,7 @@ assign builder_csrbank1_wlevel_en0_w = main_a7ddrphy_wlevel_en_storage;
 assign builder_csrbank1_dly_sel0_w = main_a7ddrphy_dly_sel_storage[1:0];
 assign builder_csrbank1_rdphase0_w = main_a7ddrphy_rdphase_storage[1:0];
 assign builder_csrbank1_wrphase0_w = main_a7ddrphy_wrphase_storage[1:0];
-assign builder_csrbank2_sel = (builder_interface2_bank_bus_adr[13:9] == 2'd2);
+assign builder_csrbank2_sel = (builder_interface2_bank_bus_adr[13:9] == 1'd0);
 assign builder_csrbank2_dfii_control0_r = builder_interface2_bank_bus_dat_w[3:0];
 
 // synthesis translate_off
@@ -12259,9 +12259,9 @@ assign builder_csrbank2_dfii_pi0_command0_r = builder_interface2_bank_bus_dat_w[
 reg dummy_d_343;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi0_command0_we <= 1'd0;
+	builder_csrbank2_dfii_pi0_command0_re <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd1))) begin
-		builder_csrbank2_dfii_pi0_command0_we <= (~builder_interface2_bank_bus_we);
+		builder_csrbank2_dfii_pi0_command0_re <= builder_interface2_bank_bus_we;
 	end
 // synthesis translate_off
 	dummy_d_343 = dummy_s;
@@ -12272,9 +12272,9 @@ end
 reg dummy_d_344;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi0_command0_re <= 1'd0;
+	builder_csrbank2_dfii_pi0_command0_we <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd1))) begin
-		builder_csrbank2_dfii_pi0_command0_re <= builder_interface2_bank_bus_we;
+		builder_csrbank2_dfii_pi0_command0_we <= (~builder_interface2_bank_bus_we);
 	end
 // synthesis translate_off
 	dummy_d_344 = dummy_s;
@@ -12394,9 +12394,9 @@ assign builder_csrbank2_dfii_pi0_wrdata3_r = builder_interface2_bank_bus_dat_w[7
 reg dummy_d_353;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi0_wrdata3_re <= 1'd0;
+	builder_csrbank2_dfii_pi0_wrdata3_we <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd6))) begin
-		builder_csrbank2_dfii_pi0_wrdata3_re <= builder_interface2_bank_bus_we;
+		builder_csrbank2_dfii_pi0_wrdata3_we <= (~builder_interface2_bank_bus_we);
 	end
 // synthesis translate_off
 	dummy_d_353 = dummy_s;
@@ -12407,9 +12407,9 @@ end
 reg dummy_d_354;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi0_wrdata3_we <= 1'd0;
+	builder_csrbank2_dfii_pi0_wrdata3_re <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd6))) begin
-		builder_csrbank2_dfii_pi0_wrdata3_we <= (~builder_interface2_bank_bus_we);
+		builder_csrbank2_dfii_pi0_wrdata3_re <= builder_interface2_bank_bus_we;
 	end
 // synthesis translate_off
 	dummy_d_354 = dummy_s;
@@ -12502,9 +12502,9 @@ assign builder_csrbank2_dfii_pi0_rddata3_r = builder_interface2_bank_bus_dat_w[7
 reg dummy_d_361;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi0_rddata3_we <= 1'd0;
+	builder_csrbank2_dfii_pi0_rddata3_re <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd10))) begin
-		builder_csrbank2_dfii_pi0_rddata3_we <= (~builder_interface2_bank_bus_we);
+		builder_csrbank2_dfii_pi0_rddata3_re <= builder_interface2_bank_bus_we;
 	end
 // synthesis translate_off
 	dummy_d_361 = dummy_s;
@@ -12515,9 +12515,9 @@ end
 reg dummy_d_362;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi0_rddata3_re <= 1'd0;
+	builder_csrbank2_dfii_pi0_rddata3_we <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd10))) begin
-		builder_csrbank2_dfii_pi0_rddata3_re <= builder_interface2_bank_bus_we;
+		builder_csrbank2_dfii_pi0_rddata3_we <= (~builder_interface2_bank_bus_we);
 	end
 // synthesis translate_off
 	dummy_d_362 = dummy_s;
@@ -12556,9 +12556,9 @@ assign builder_csrbank2_dfii_pi0_rddata1_r = builder_interface2_bank_bus_dat_w[7
 reg dummy_d_365;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi0_rddata1_re <= 1'd0;
+	builder_csrbank2_dfii_pi0_rddata1_we <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd12))) begin
-		builder_csrbank2_dfii_pi0_rddata1_re <= builder_interface2_bank_bus_we;
+		builder_csrbank2_dfii_pi0_rddata1_we <= (~builder_interface2_bank_bus_we);
 	end
 // synthesis translate_off
 	dummy_d_365 = dummy_s;
@@ -12569,9 +12569,9 @@ end
 reg dummy_d_366;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi0_rddata1_we <= 1'd0;
+	builder_csrbank2_dfii_pi0_rddata1_re <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd12))) begin
-		builder_csrbank2_dfii_pi0_rddata1_we <= (~builder_interface2_bank_bus_we);
+		builder_csrbank2_dfii_pi0_rddata1_re <= builder_interface2_bank_bus_we;
 	end
 // synthesis translate_off
 	dummy_d_366 = dummy_s;
@@ -12610,9 +12610,9 @@ assign builder_csrbank2_dfii_pi1_command0_r = builder_interface2_bank_bus_dat_w[
 reg dummy_d_369;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi1_command0_we <= 1'd0;
+	builder_csrbank2_dfii_pi1_command0_re <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd14))) begin
-		builder_csrbank2_dfii_pi1_command0_we <= (~builder_interface2_bank_bus_we);
+		builder_csrbank2_dfii_pi1_command0_re <= builder_interface2_bank_bus_we;
 	end
 // synthesis translate_off
 	dummy_d_369 = dummy_s;
@@ -12623,9 +12623,9 @@ end
 reg dummy_d_370;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi1_command0_re <= 1'd0;
+	builder_csrbank2_dfii_pi1_command0_we <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd14))) begin
-		builder_csrbank2_dfii_pi1_command0_re <= builder_interface2_bank_bus_we;
+		builder_csrbank2_dfii_pi1_command0_we <= (~builder_interface2_bank_bus_we);
 	end
 // synthesis translate_off
 	dummy_d_370 = dummy_s;
@@ -12637,9 +12637,9 @@ assign main_litedramcore_phaseinjector1_command_issue_r = builder_interface2_ban
 reg dummy_d_371;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_phaseinjector1_command_issue_re <= 1'd0;
+	main_litedramcore_phaseinjector1_command_issue_we <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd15))) begin
-		main_litedramcore_phaseinjector1_command_issue_re <= builder_interface2_bank_bus_we;
+		main_litedramcore_phaseinjector1_command_issue_we <= (~builder_interface2_bank_bus_we);
 	end
 // synthesis translate_off
 	dummy_d_371 = dummy_s;
@@ -12650,9 +12650,9 @@ end
 reg dummy_d_372;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_phaseinjector1_command_issue_we <= 1'd0;
+	main_litedramcore_phaseinjector1_command_issue_re <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd15))) begin
-		main_litedramcore_phaseinjector1_command_issue_we <= (~builder_interface2_bank_bus_we);
+		main_litedramcore_phaseinjector1_command_issue_re <= builder_interface2_bank_bus_we;
 	end
 // synthesis translate_off
 	dummy_d_372 = dummy_s;
@@ -12745,9 +12745,9 @@ assign builder_csrbank2_dfii_pi1_wrdata3_r = builder_interface2_bank_bus_dat_w[7
 reg dummy_d_379;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi1_wrdata3_re <= 1'd0;
+	builder_csrbank2_dfii_pi1_wrdata3_we <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd19))) begin
-		builder_csrbank2_dfii_pi1_wrdata3_re <= builder_interface2_bank_bus_we;
+		builder_csrbank2_dfii_pi1_wrdata3_we <= (~builder_interface2_bank_bus_we);
 	end
 // synthesis translate_off
 	dummy_d_379 = dummy_s;
@@ -12758,9 +12758,9 @@ end
 reg dummy_d_380;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi1_wrdata3_we <= 1'd0;
+	builder_csrbank2_dfii_pi1_wrdata3_re <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd19))) begin
-		builder_csrbank2_dfii_pi1_wrdata3_we <= (~builder_interface2_bank_bus_we);
+		builder_csrbank2_dfii_pi1_wrdata3_re <= builder_interface2_bank_bus_we;
 	end
 // synthesis translate_off
 	dummy_d_380 = dummy_s;
@@ -12853,9 +12853,9 @@ assign builder_csrbank2_dfii_pi1_rddata3_r = builder_interface2_bank_bus_dat_w[7
 reg dummy_d_387;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi1_rddata3_we <= 1'd0;
+	builder_csrbank2_dfii_pi1_rddata3_re <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd23))) begin
-		builder_csrbank2_dfii_pi1_rddata3_we <= (~builder_interface2_bank_bus_we);
+		builder_csrbank2_dfii_pi1_rddata3_re <= builder_interface2_bank_bus_we;
 	end
 // synthesis translate_off
 	dummy_d_387 = dummy_s;
@@ -12866,9 +12866,9 @@ end
 reg dummy_d_388;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi1_rddata3_re <= 1'd0;
+	builder_csrbank2_dfii_pi1_rddata3_we <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd23))) begin
-		builder_csrbank2_dfii_pi1_rddata3_re <= builder_interface2_bank_bus_we;
+		builder_csrbank2_dfii_pi1_rddata3_we <= (~builder_interface2_bank_bus_we);
 	end
 // synthesis translate_off
 	dummy_d_388 = dummy_s;
@@ -12907,9 +12907,9 @@ assign builder_csrbank2_dfii_pi1_rddata1_r = builder_interface2_bank_bus_dat_w[7
 reg dummy_d_391;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi1_rddata1_re <= 1'd0;
+	builder_csrbank2_dfii_pi1_rddata1_we <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd25))) begin
-		builder_csrbank2_dfii_pi1_rddata1_re <= builder_interface2_bank_bus_we;
+		builder_csrbank2_dfii_pi1_rddata1_we <= (~builder_interface2_bank_bus_we);
 	end
 // synthesis translate_off
 	dummy_d_391 = dummy_s;
@@ -12920,9 +12920,9 @@ end
 reg dummy_d_392;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi1_rddata1_we <= 1'd0;
+	builder_csrbank2_dfii_pi1_rddata1_re <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd25))) begin
-		builder_csrbank2_dfii_pi1_rddata1_we <= (~builder_interface2_bank_bus_we);
+		builder_csrbank2_dfii_pi1_rddata1_re <= builder_interface2_bank_bus_we;
 	end
 // synthesis translate_off
 	dummy_d_392 = dummy_s;
@@ -12961,9 +12961,9 @@ assign builder_csrbank2_dfii_pi2_command0_r = builder_interface2_bank_bus_dat_w[
 reg dummy_d_395;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi2_command0_we <= 1'd0;
+	builder_csrbank2_dfii_pi2_command0_re <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd27))) begin
-		builder_csrbank2_dfii_pi2_command0_we <= (~builder_interface2_bank_bus_we);
+		builder_csrbank2_dfii_pi2_command0_re <= builder_interface2_bank_bus_we;
 	end
 // synthesis translate_off
 	dummy_d_395 = dummy_s;
@@ -12974,9 +12974,9 @@ end
 reg dummy_d_396;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi2_command0_re <= 1'd0;
+	builder_csrbank2_dfii_pi2_command0_we <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd27))) begin
-		builder_csrbank2_dfii_pi2_command0_re <= builder_interface2_bank_bus_we;
+		builder_csrbank2_dfii_pi2_command0_we <= (~builder_interface2_bank_bus_we);
 	end
 // synthesis translate_off
 	dummy_d_396 = dummy_s;
@@ -13096,9 +13096,9 @@ assign builder_csrbank2_dfii_pi2_wrdata3_r = builder_interface2_bank_bus_dat_w[7
 reg dummy_d_405;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi2_wrdata3_re <= 1'd0;
+	builder_csrbank2_dfii_pi2_wrdata3_we <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd32))) begin
-		builder_csrbank2_dfii_pi2_wrdata3_re <= builder_interface2_bank_bus_we;
+		builder_csrbank2_dfii_pi2_wrdata3_we <= (~builder_interface2_bank_bus_we);
 	end
 // synthesis translate_off
 	dummy_d_405 = dummy_s;
@@ -13109,9 +13109,9 @@ end
 reg dummy_d_406;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi2_wrdata3_we <= 1'd0;
+	builder_csrbank2_dfii_pi2_wrdata3_re <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd32))) begin
-		builder_csrbank2_dfii_pi2_wrdata3_we <= (~builder_interface2_bank_bus_we);
+		builder_csrbank2_dfii_pi2_wrdata3_re <= builder_interface2_bank_bus_we;
 	end
 // synthesis translate_off
 	dummy_d_406 = dummy_s;
@@ -13204,9 +13204,9 @@ assign builder_csrbank2_dfii_pi2_rddata3_r = builder_interface2_bank_bus_dat_w[7
 reg dummy_d_413;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi2_rddata3_we <= 1'd0;
+	builder_csrbank2_dfii_pi2_rddata3_re <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd36))) begin
-		builder_csrbank2_dfii_pi2_rddata3_we <= (~builder_interface2_bank_bus_we);
+		builder_csrbank2_dfii_pi2_rddata3_re <= builder_interface2_bank_bus_we;
 	end
 // synthesis translate_off
 	dummy_d_413 = dummy_s;
@@ -13217,9 +13217,9 @@ end
 reg dummy_d_414;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi2_rddata3_re <= 1'd0;
+	builder_csrbank2_dfii_pi2_rddata3_we <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd36))) begin
-		builder_csrbank2_dfii_pi2_rddata3_re <= builder_interface2_bank_bus_we;
+		builder_csrbank2_dfii_pi2_rddata3_we <= (~builder_interface2_bank_bus_we);
 	end
 // synthesis translate_off
 	dummy_d_414 = dummy_s;
@@ -13258,9 +13258,9 @@ assign builder_csrbank2_dfii_pi2_rddata1_r = builder_interface2_bank_bus_dat_w[7
 reg dummy_d_417;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi2_rddata1_re <= 1'd0;
+	builder_csrbank2_dfii_pi2_rddata1_we <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd38))) begin
-		builder_csrbank2_dfii_pi2_rddata1_re <= builder_interface2_bank_bus_we;
+		builder_csrbank2_dfii_pi2_rddata1_we <= (~builder_interface2_bank_bus_we);
 	end
 // synthesis translate_off
 	dummy_d_417 = dummy_s;
@@ -13271,9 +13271,9 @@ end
 reg dummy_d_418;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi2_rddata1_we <= 1'd0;
+	builder_csrbank2_dfii_pi2_rddata1_re <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd38))) begin
-		builder_csrbank2_dfii_pi2_rddata1_we <= (~builder_interface2_bank_bus_we);
+		builder_csrbank2_dfii_pi2_rddata1_re <= builder_interface2_bank_bus_we;
 	end
 // synthesis translate_off
 	dummy_d_418 = dummy_s;
@@ -13312,9 +13312,9 @@ assign builder_csrbank2_dfii_pi3_command0_r = builder_interface2_bank_bus_dat_w[
 reg dummy_d_421;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi3_command0_we <= 1'd0;
+	builder_csrbank2_dfii_pi3_command0_re <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd40))) begin
-		builder_csrbank2_dfii_pi3_command0_we <= (~builder_interface2_bank_bus_we);
+		builder_csrbank2_dfii_pi3_command0_re <= builder_interface2_bank_bus_we;
 	end
 // synthesis translate_off
 	dummy_d_421 = dummy_s;
@@ -13325,9 +13325,9 @@ end
 reg dummy_d_422;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi3_command0_re <= 1'd0;
+	builder_csrbank2_dfii_pi3_command0_we <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd40))) begin
-		builder_csrbank2_dfii_pi3_command0_re <= builder_interface2_bank_bus_we;
+		builder_csrbank2_dfii_pi3_command0_we <= (~builder_interface2_bank_bus_we);
 	end
 // synthesis translate_off
 	dummy_d_422 = dummy_s;
@@ -13447,9 +13447,9 @@ assign builder_csrbank2_dfii_pi3_wrdata3_r = builder_interface2_bank_bus_dat_w[7
 reg dummy_d_431;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi3_wrdata3_re <= 1'd0;
+	builder_csrbank2_dfii_pi3_wrdata3_we <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd45))) begin
-		builder_csrbank2_dfii_pi3_wrdata3_re <= builder_interface2_bank_bus_we;
+		builder_csrbank2_dfii_pi3_wrdata3_we <= (~builder_interface2_bank_bus_we);
 	end
 // synthesis translate_off
 	dummy_d_431 = dummy_s;
@@ -13460,9 +13460,9 @@ end
 reg dummy_d_432;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi3_wrdata3_we <= 1'd0;
+	builder_csrbank2_dfii_pi3_wrdata3_re <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd45))) begin
-		builder_csrbank2_dfii_pi3_wrdata3_we <= (~builder_interface2_bank_bus_we);
+		builder_csrbank2_dfii_pi3_wrdata3_re <= builder_interface2_bank_bus_we;
 	end
 // synthesis translate_off
 	dummy_d_432 = dummy_s;
@@ -13555,9 +13555,9 @@ assign builder_csrbank2_dfii_pi3_rddata3_r = builder_interface2_bank_bus_dat_w[7
 reg dummy_d_439;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi3_rddata3_we <= 1'd0;
+	builder_csrbank2_dfii_pi3_rddata3_re <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd49))) begin
-		builder_csrbank2_dfii_pi3_rddata3_we <= (~builder_interface2_bank_bus_we);
+		builder_csrbank2_dfii_pi3_rddata3_re <= builder_interface2_bank_bus_we;
 	end
 // synthesis translate_off
 	dummy_d_439 = dummy_s;
@@ -13568,9 +13568,9 @@ end
 reg dummy_d_440;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi3_rddata3_re <= 1'd0;
+	builder_csrbank2_dfii_pi3_rddata3_we <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd49))) begin
-		builder_csrbank2_dfii_pi3_rddata3_re <= builder_interface2_bank_bus_we;
+		builder_csrbank2_dfii_pi3_rddata3_we <= (~builder_interface2_bank_bus_we);
 	end
 // synthesis translate_off
 	dummy_d_440 = dummy_s;
@@ -13609,9 +13609,9 @@ assign builder_csrbank2_dfii_pi3_rddata1_r = builder_interface2_bank_bus_dat_w[7
 reg dummy_d_443;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi3_rddata1_re <= 1'd0;
+	builder_csrbank2_dfii_pi3_rddata1_we <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd51))) begin
-		builder_csrbank2_dfii_pi3_rddata1_re <= builder_interface2_bank_bus_we;
+		builder_csrbank2_dfii_pi3_rddata1_we <= (~builder_interface2_bank_bus_we);
 	end
 // synthesis translate_off
 	dummy_d_443 = dummy_s;
@@ -13622,9 +13622,9 @@ end
 reg dummy_d_444;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi3_rddata1_we <= 1'd0;
+	builder_csrbank2_dfii_pi3_rddata1_re <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd51))) begin
-		builder_csrbank2_dfii_pi3_rddata1_we <= (~builder_interface2_bank_bus_we);
+		builder_csrbank2_dfii_pi3_rddata1_re <= builder_interface2_bank_bus_we;
 	end
 // synthesis translate_off
 	dummy_d_444 = dummy_s;
diff --git a/litedram/generated/arty/litedram_core.init b/litedram/generated/arty/litedram_core.init
index 5bfb299..5b1a383 100644
--- a/litedram/generated/arty/litedram_core.init
+++ b/litedram/generated/arty/litedram_core.init
@@ -7,7 +7,7 @@ a64b5a7d14004a39
 6421ff00782107c6
 3d80000060215f00
 798c07c6618c0000
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 4e8004217d8903a6
 4e8004207c6903a6
 0000000000000000
@@ -519,80 +519,81 @@ a64b5a7d14004a39
 0000000000000000
 3c4c000100000000
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 000000004e800020
 0000000000000000
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 000000004e800020
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 614a600439200002
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 3fe0c0007d2057aa
@@ -600,1274 +601,1293 @@ f9410108f9210100
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diff --git a/litedram/generated/arty/litedram_core.v b/litedram/generated/arty/litedram_core.v
index b571b6c..525dde1 100644
--- a/litedram/generated/arty/litedram_core.v
+++ b/litedram/generated/arty/litedram_core.v
@@ -1,5 +1,5 @@
 //--------------------------------------------------------------------------------
-// Auto-generated by Migen (27dbf03) & LiteX (78c1751c) on 2021-08-15 06:19:10
+// Auto-generated by Migen (a5bc262) & LiteX (de028765) on 2021-09-24 12:36:31
 //--------------------------------------------------------------------------------
 module litedram_core(
 	input wire clk,
@@ -4409,10 +4409,11 @@ end
 reg dummy_d_91;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_inti_p0_rddata_valid <= 1'd0;
+	main_litedramcore_master_p2_wrdata <= 32'd0;
 	if (main_litedramcore_sel) begin
+		main_litedramcore_master_p2_wrdata <= main_litedramcore_slave_p2_wrdata;
 	end else begin
-		main_litedramcore_inti_p0_rddata_valid <= main_litedramcore_master_p0_rddata_valid;
+		main_litedramcore_master_p2_wrdata <= main_litedramcore_inti_p2_wrdata;
 	end
 // synthesis translate_off
 	dummy_d_91 = dummy_s;
@@ -4423,11 +4424,10 @@ end
 reg dummy_d_92;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_master_p2_wrdata <= 32'd0;
+	main_litedramcore_inti_p3_rddata <= 32'd0;
 	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p2_wrdata <= main_litedramcore_slave_p2_wrdata;
 	end else begin
-		main_litedramcore_master_p2_wrdata <= main_litedramcore_inti_p2_wrdata;
+		main_litedramcore_inti_p3_rddata <= main_litedramcore_master_p3_rddata;
 	end
 // synthesis translate_off
 	dummy_d_92 = dummy_s;
@@ -4438,10 +4438,11 @@ end
 reg dummy_d_93;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_inti_p3_rddata <= 32'd0;
+	main_litedramcore_master_p2_wrdata_en <= 1'd0;
 	if (main_litedramcore_sel) begin
+		main_litedramcore_master_p2_wrdata_en <= main_litedramcore_slave_p2_wrdata_en;
 	end else begin
-		main_litedramcore_inti_p3_rddata <= main_litedramcore_master_p3_rddata;
+		main_litedramcore_master_p2_wrdata_en <= main_litedramcore_inti_p2_wrdata_en;
 	end
 // synthesis translate_off
 	dummy_d_93 = dummy_s;
@@ -4452,11 +4453,10 @@ end
 reg dummy_d_94;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_master_p2_wrdata_en <= 1'd0;
+	main_litedramcore_inti_p0_rddata_valid <= 1'd0;
 	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p2_wrdata_en <= main_litedramcore_slave_p2_wrdata_en;
 	end else begin
-		main_litedramcore_master_p2_wrdata_en <= main_litedramcore_inti_p2_wrdata_en;
+		main_litedramcore_inti_p0_rddata_valid <= main_litedramcore_master_p0_rddata_valid;
 	end
 // synthesis translate_off
 	dummy_d_94 = dummy_s;
@@ -4467,10 +4467,11 @@ end
 reg dummy_d_95;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_inti_p3_rddata_valid <= 1'd0;
+	main_litedramcore_master_p2_wrdata_mask <= 4'd0;
 	if (main_litedramcore_sel) begin
+		main_litedramcore_master_p2_wrdata_mask <= main_litedramcore_slave_p2_wrdata_mask;
 	end else begin
-		main_litedramcore_inti_p3_rddata_valid <= main_litedramcore_master_p3_rddata_valid;
+		main_litedramcore_master_p2_wrdata_mask <= main_litedramcore_inti_p2_wrdata_mask;
 	end
 // synthesis translate_off
 	dummy_d_95 = dummy_s;
@@ -4481,11 +4482,10 @@ end
 reg dummy_d_96;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_master_p2_wrdata_mask <= 4'd0;
+	main_litedramcore_inti_p3_rddata_valid <= 1'd0;
 	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p2_wrdata_mask <= main_litedramcore_slave_p2_wrdata_mask;
 	end else begin
-		main_litedramcore_master_p2_wrdata_mask <= main_litedramcore_inti_p2_wrdata_mask;
+		main_litedramcore_inti_p3_rddata_valid <= main_litedramcore_master_p3_rddata_valid;
 	end
 // synthesis translate_off
 	dummy_d_96 = dummy_s;
@@ -4761,11 +4761,11 @@ assign main_litedramcore_inti_p3_reset_n = main_litedramcore_reset_n;
 reg dummy_d_114;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_inti_p0_cs_n <= 1'd1;
+	main_litedramcore_inti_p0_cas_n <= 1'd1;
 	if (main_litedramcore_phaseinjector0_command_issue_re) begin
-		main_litedramcore_inti_p0_cs_n <= {1{(~main_litedramcore_phaseinjector0_command_storage[0])}};
+		main_litedramcore_inti_p0_cas_n <= (~main_litedramcore_phaseinjector0_command_storage[2]);
 	end else begin
-		main_litedramcore_inti_p0_cs_n <= {1{1'd1}};
+		main_litedramcore_inti_p0_cas_n <= 1'd1;
 	end
 // synthesis translate_off
 	dummy_d_114 = dummy_s;
@@ -4776,11 +4776,11 @@ end
 reg dummy_d_115;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_inti_p0_ras_n <= 1'd1;
+	main_litedramcore_inti_p0_cs_n <= 1'd1;
 	if (main_litedramcore_phaseinjector0_command_issue_re) begin
-		main_litedramcore_inti_p0_ras_n <= (~main_litedramcore_phaseinjector0_command_storage[3]);
+		main_litedramcore_inti_p0_cs_n <= {1{(~main_litedramcore_phaseinjector0_command_storage[0])}};
 	end else begin
-		main_litedramcore_inti_p0_ras_n <= 1'd1;
+		main_litedramcore_inti_p0_cs_n <= {1{1'd1}};
 	end
 // synthesis translate_off
 	dummy_d_115 = dummy_s;
@@ -4791,11 +4791,11 @@ end
 reg dummy_d_116;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_inti_p0_we_n <= 1'd1;
+	main_litedramcore_inti_p0_ras_n <= 1'd1;
 	if (main_litedramcore_phaseinjector0_command_issue_re) begin
-		main_litedramcore_inti_p0_we_n <= (~main_litedramcore_phaseinjector0_command_storage[1]);
+		main_litedramcore_inti_p0_ras_n <= (~main_litedramcore_phaseinjector0_command_storage[3]);
 	end else begin
-		main_litedramcore_inti_p0_we_n <= 1'd1;
+		main_litedramcore_inti_p0_ras_n <= 1'd1;
 	end
 // synthesis translate_off
 	dummy_d_116 = dummy_s;
@@ -4806,11 +4806,11 @@ end
 reg dummy_d_117;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_inti_p0_cas_n <= 1'd1;
+	main_litedramcore_inti_p0_we_n <= 1'd1;
 	if (main_litedramcore_phaseinjector0_command_issue_re) begin
-		main_litedramcore_inti_p0_cas_n <= (~main_litedramcore_phaseinjector0_command_storage[2]);
+		main_litedramcore_inti_p0_we_n <= (~main_litedramcore_phaseinjector0_command_storage[1]);
 	end else begin
-		main_litedramcore_inti_p0_cas_n <= 1'd1;
+		main_litedramcore_inti_p0_we_n <= 1'd1;
 	end
 // synthesis translate_off
 	dummy_d_117 = dummy_s;
@@ -4827,11 +4827,11 @@ assign main_litedramcore_inti_p0_wrdata_mask = 1'd0;
 reg dummy_d_118;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_inti_p1_cs_n <= 1'd1;
+	main_litedramcore_inti_p1_cas_n <= 1'd1;
 	if (main_litedramcore_phaseinjector1_command_issue_re) begin
-		main_litedramcore_inti_p1_cs_n <= {1{(~main_litedramcore_phaseinjector1_command_storage[0])}};
+		main_litedramcore_inti_p1_cas_n <= (~main_litedramcore_phaseinjector1_command_storage[2]);
 	end else begin
-		main_litedramcore_inti_p1_cs_n <= {1{1'd1}};
+		main_litedramcore_inti_p1_cas_n <= 1'd1;
 	end
 // synthesis translate_off
 	dummy_d_118 = dummy_s;
@@ -4842,11 +4842,11 @@ end
 reg dummy_d_119;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_inti_p1_ras_n <= 1'd1;
+	main_litedramcore_inti_p1_cs_n <= 1'd1;
 	if (main_litedramcore_phaseinjector1_command_issue_re) begin
-		main_litedramcore_inti_p1_ras_n <= (~main_litedramcore_phaseinjector1_command_storage[3]);
+		main_litedramcore_inti_p1_cs_n <= {1{(~main_litedramcore_phaseinjector1_command_storage[0])}};
 	end else begin
-		main_litedramcore_inti_p1_ras_n <= 1'd1;
+		main_litedramcore_inti_p1_cs_n <= {1{1'd1}};
 	end
 // synthesis translate_off
 	dummy_d_119 = dummy_s;
@@ -4857,11 +4857,11 @@ end
 reg dummy_d_120;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_inti_p1_we_n <= 1'd1;
+	main_litedramcore_inti_p1_ras_n <= 1'd1;
 	if (main_litedramcore_phaseinjector1_command_issue_re) begin
-		main_litedramcore_inti_p1_we_n <= (~main_litedramcore_phaseinjector1_command_storage[1]);
+		main_litedramcore_inti_p1_ras_n <= (~main_litedramcore_phaseinjector1_command_storage[3]);
 	end else begin
-		main_litedramcore_inti_p1_we_n <= 1'd1;
+		main_litedramcore_inti_p1_ras_n <= 1'd1;
 	end
 // synthesis translate_off
 	dummy_d_120 = dummy_s;
@@ -4872,11 +4872,11 @@ end
 reg dummy_d_121;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_inti_p1_cas_n <= 1'd1;
+	main_litedramcore_inti_p1_we_n <= 1'd1;
 	if (main_litedramcore_phaseinjector1_command_issue_re) begin
-		main_litedramcore_inti_p1_cas_n <= (~main_litedramcore_phaseinjector1_command_storage[2]);
+		main_litedramcore_inti_p1_we_n <= (~main_litedramcore_phaseinjector1_command_storage[1]);
 	end else begin
-		main_litedramcore_inti_p1_cas_n <= 1'd1;
+		main_litedramcore_inti_p1_we_n <= 1'd1;
 	end
 // synthesis translate_off
 	dummy_d_121 = dummy_s;
@@ -4893,11 +4893,11 @@ assign main_litedramcore_inti_p1_wrdata_mask = 1'd0;
 reg dummy_d_122;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_inti_p2_cs_n <= 1'd1;
+	main_litedramcore_inti_p2_cas_n <= 1'd1;
 	if (main_litedramcore_phaseinjector2_command_issue_re) begin
-		main_litedramcore_inti_p2_cs_n <= {1{(~main_litedramcore_phaseinjector2_command_storage[0])}};
+		main_litedramcore_inti_p2_cas_n <= (~main_litedramcore_phaseinjector2_command_storage[2]);
 	end else begin
-		main_litedramcore_inti_p2_cs_n <= {1{1'd1}};
+		main_litedramcore_inti_p2_cas_n <= 1'd1;
 	end
 // synthesis translate_off
 	dummy_d_122 = dummy_s;
@@ -4908,11 +4908,11 @@ end
 reg dummy_d_123;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_inti_p2_ras_n <= 1'd1;
+	main_litedramcore_inti_p2_cs_n <= 1'd1;
 	if (main_litedramcore_phaseinjector2_command_issue_re) begin
-		main_litedramcore_inti_p2_ras_n <= (~main_litedramcore_phaseinjector2_command_storage[3]);
+		main_litedramcore_inti_p2_cs_n <= {1{(~main_litedramcore_phaseinjector2_command_storage[0])}};
 	end else begin
-		main_litedramcore_inti_p2_ras_n <= 1'd1;
+		main_litedramcore_inti_p2_cs_n <= {1{1'd1}};
 	end
 // synthesis translate_off
 	dummy_d_123 = dummy_s;
@@ -4923,11 +4923,11 @@ end
 reg dummy_d_124;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_inti_p2_we_n <= 1'd1;
+	main_litedramcore_inti_p2_ras_n <= 1'd1;
 	if (main_litedramcore_phaseinjector2_command_issue_re) begin
-		main_litedramcore_inti_p2_we_n <= (~main_litedramcore_phaseinjector2_command_storage[1]);
+		main_litedramcore_inti_p2_ras_n <= (~main_litedramcore_phaseinjector2_command_storage[3]);
 	end else begin
-		main_litedramcore_inti_p2_we_n <= 1'd1;
+		main_litedramcore_inti_p2_ras_n <= 1'd1;
 	end
 // synthesis translate_off
 	dummy_d_124 = dummy_s;
@@ -4938,11 +4938,11 @@ end
 reg dummy_d_125;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_inti_p2_cas_n <= 1'd1;
+	main_litedramcore_inti_p2_we_n <= 1'd1;
 	if (main_litedramcore_phaseinjector2_command_issue_re) begin
-		main_litedramcore_inti_p2_cas_n <= (~main_litedramcore_phaseinjector2_command_storage[2]);
+		main_litedramcore_inti_p2_we_n <= (~main_litedramcore_phaseinjector2_command_storage[1]);
 	end else begin
-		main_litedramcore_inti_p2_cas_n <= 1'd1;
+		main_litedramcore_inti_p2_we_n <= 1'd1;
 	end
 // synthesis translate_off
 	dummy_d_125 = dummy_s;
@@ -4959,11 +4959,11 @@ assign main_litedramcore_inti_p2_wrdata_mask = 1'd0;
 reg dummy_d_126;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_inti_p3_cs_n <= 1'd1;
+	main_litedramcore_inti_p3_cas_n <= 1'd1;
 	if (main_litedramcore_phaseinjector3_command_issue_re) begin
-		main_litedramcore_inti_p3_cs_n <= {1{(~main_litedramcore_phaseinjector3_command_storage[0])}};
+		main_litedramcore_inti_p3_cas_n <= (~main_litedramcore_phaseinjector3_command_storage[2]);
 	end else begin
-		main_litedramcore_inti_p3_cs_n <= {1{1'd1}};
+		main_litedramcore_inti_p3_cas_n <= 1'd1;
 	end
 // synthesis translate_off
 	dummy_d_126 = dummy_s;
@@ -4974,11 +4974,11 @@ end
 reg dummy_d_127;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_inti_p3_ras_n <= 1'd1;
+	main_litedramcore_inti_p3_cs_n <= 1'd1;
 	if (main_litedramcore_phaseinjector3_command_issue_re) begin
-		main_litedramcore_inti_p3_ras_n <= (~main_litedramcore_phaseinjector3_command_storage[3]);
+		main_litedramcore_inti_p3_cs_n <= {1{(~main_litedramcore_phaseinjector3_command_storage[0])}};
 	end else begin
-		main_litedramcore_inti_p3_ras_n <= 1'd1;
+		main_litedramcore_inti_p3_cs_n <= {1{1'd1}};
 	end
 // synthesis translate_off
 	dummy_d_127 = dummy_s;
@@ -4989,11 +4989,11 @@ end
 reg dummy_d_128;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_inti_p3_we_n <= 1'd1;
+	main_litedramcore_inti_p3_ras_n <= 1'd1;
 	if (main_litedramcore_phaseinjector3_command_issue_re) begin
-		main_litedramcore_inti_p3_we_n <= (~main_litedramcore_phaseinjector3_command_storage[1]);
+		main_litedramcore_inti_p3_ras_n <= (~main_litedramcore_phaseinjector3_command_storage[3]);
 	end else begin
-		main_litedramcore_inti_p3_we_n <= 1'd1;
+		main_litedramcore_inti_p3_ras_n <= 1'd1;
 	end
 // synthesis translate_off
 	dummy_d_128 = dummy_s;
@@ -5004,11 +5004,11 @@ end
 reg dummy_d_129;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_inti_p3_cas_n <= 1'd1;
+	main_litedramcore_inti_p3_we_n <= 1'd1;
 	if (main_litedramcore_phaseinjector3_command_issue_re) begin
-		main_litedramcore_inti_p3_cas_n <= (~main_litedramcore_phaseinjector3_command_storage[2]);
+		main_litedramcore_inti_p3_we_n <= (~main_litedramcore_phaseinjector3_command_storage[1]);
 	end else begin
-		main_litedramcore_inti_p3_cas_n <= 1'd1;
+		main_litedramcore_inti_p3_we_n <= 1'd1;
 	end
 // synthesis translate_off
 	dummy_d_129 = dummy_s;
@@ -5590,13 +5590,16 @@ end
 reg dummy_d_144;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine0_req_rdata_valid <= 1'd0;
+	main_litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd0;
 	case (builder_bankmachine0_state)
 		1'd1: begin
 		end
 		2'd2: begin
 		end
 		2'd3: begin
+			if (main_litedramcore_bankmachine0_trccon_ready) begin
+				main_litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd1;
+			end
 		end
 		3'd4: begin
 		end
@@ -5609,21 +5612,6 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine0_refresh_req) begin
-			end else begin
-				if (main_litedramcore_bankmachine0_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine0_row_opened) begin
-						if (main_litedramcore_bankmachine0_row_hit) begin
-							if (main_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
-							end else begin
-								main_litedramcore_bankmachine0_req_rdata_valid <= main_litedramcore_bankmachine0_cmd_ready;
-							end
-						end else begin
-						end
-					end else begin
-					end
-				end
-			end
 		end
 	endcase
 // synthesis translate_off
@@ -5672,16 +5660,13 @@ end
 reg dummy_d_146;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd0;
+	main_litedramcore_bankmachine0_cmd_payload_is_read <= 1'd0;
 	case (builder_bankmachine0_state)
 		1'd1: begin
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine0_trccon_ready) begin
-				main_litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd1;
-			end
 		end
 		3'd4: begin
 		end
@@ -5694,6 +5679,21 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
+			if (main_litedramcore_bankmachine0_refresh_req) begin
+			end else begin
+				if (main_litedramcore_bankmachine0_cmd_buffer_source_valid) begin
+					if (main_litedramcore_bankmachine0_row_opened) begin
+						if (main_litedramcore_bankmachine0_row_hit) begin
+							if (main_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
+							end else begin
+								main_litedramcore_bankmachine0_cmd_payload_is_read <= 1'd1;
+							end
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
 		end
 	endcase
 // synthesis translate_off
@@ -5705,7 +5705,7 @@ end
 reg dummy_d_147;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine0_cmd_payload_is_read <= 1'd0;
+	main_litedramcore_bankmachine0_req_rdata_valid <= 1'd0;
 	case (builder_bankmachine0_state)
 		1'd1: begin
 		end
@@ -5731,7 +5731,7 @@ always @(*) begin
 						if (main_litedramcore_bankmachine0_row_hit) begin
 							if (main_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
 							end else begin
-								main_litedramcore_bankmachine0_cmd_payload_is_read <= 1'd1;
+								main_litedramcore_bankmachine0_req_rdata_valid <= main_litedramcore_bankmachine0_cmd_ready;
 							end
 						end else begin
 						end
@@ -6338,7 +6338,7 @@ end
 reg dummy_d_163;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine1_cmd_payload_is_read <= 1'd0;
+	main_litedramcore_bankmachine1_refresh_gnt <= 1'd0;
 	case (builder_bankmachine1_state)
 		1'd1: begin
 		end
@@ -6347,6 +6347,9 @@ always @(*) begin
 		2'd3: begin
 		end
 		3'd4: begin
+			if (main_litedramcore_bankmachine1_twtpcon_ready) begin
+				main_litedramcore_bankmachine1_refresh_gnt <= 1'd1;
+			end
 		end
 		3'd5: begin
 		end
@@ -6357,21 +6360,6 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine1_refresh_req) begin
-			end else begin
-				if (main_litedramcore_bankmachine1_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine1_row_opened) begin
-						if (main_litedramcore_bankmachine1_row_hit) begin
-							if (main_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
-							end else begin
-								main_litedramcore_bankmachine1_cmd_payload_is_read <= 1'd1;
-							end
-						end else begin
-						end
-					end else begin
-					end
-				end
-			end
 		end
 	endcase
 // synthesis translate_off
@@ -6383,7 +6371,7 @@ end
 reg dummy_d_164;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine1_cmd_payload_is_write <= 1'd0;
+	main_litedramcore_bankmachine1_cmd_payload_is_read <= 1'd0;
 	case (builder_bankmachine1_state)
 		1'd1: begin
 		end
@@ -6408,8 +6396,8 @@ always @(*) begin
 					if (main_litedramcore_bankmachine1_row_opened) begin
 						if (main_litedramcore_bankmachine1_row_hit) begin
 							if (main_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
-								main_litedramcore_bankmachine1_cmd_payload_is_write <= 1'd1;
 							end else begin
+								main_litedramcore_bankmachine1_cmd_payload_is_read <= 1'd1;
 							end
 						end else begin
 						end
@@ -6428,7 +6416,7 @@ end
 reg dummy_d_165;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine1_req_wdata_ready <= 1'd0;
+	main_litedramcore_bankmachine1_cmd_payload_is_write <= 1'd0;
 	case (builder_bankmachine1_state)
 		1'd1: begin
 		end
@@ -6453,7 +6441,7 @@ always @(*) begin
 					if (main_litedramcore_bankmachine1_row_opened) begin
 						if (main_litedramcore_bankmachine1_row_hit) begin
 							if (main_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
-								main_litedramcore_bankmachine1_req_wdata_ready <= main_litedramcore_bankmachine1_cmd_ready;
+								main_litedramcore_bankmachine1_cmd_payload_is_write <= 1'd1;
 							end else begin
 							end
 						end else begin
@@ -6473,7 +6461,7 @@ end
 reg dummy_d_166;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine1_req_rdata_valid <= 1'd0;
+	main_litedramcore_bankmachine1_req_wdata_ready <= 1'd0;
 	case (builder_bankmachine1_state)
 		1'd1: begin
 		end
@@ -6498,8 +6486,8 @@ always @(*) begin
 					if (main_litedramcore_bankmachine1_row_opened) begin
 						if (main_litedramcore_bankmachine1_row_hit) begin
 							if (main_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
+								main_litedramcore_bankmachine1_req_wdata_ready <= main_litedramcore_bankmachine1_cmd_ready;
 							end else begin
-								main_litedramcore_bankmachine1_req_rdata_valid <= main_litedramcore_bankmachine1_cmd_ready;
 							end
 						end else begin
 						end
@@ -6518,7 +6506,7 @@ end
 reg dummy_d_167;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine1_refresh_gnt <= 1'd0;
+	main_litedramcore_bankmachine1_req_rdata_valid <= 1'd0;
 	case (builder_bankmachine1_state)
 		1'd1: begin
 		end
@@ -6527,9 +6515,6 @@ always @(*) begin
 		2'd3: begin
 		end
 		3'd4: begin
-			if (main_litedramcore_bankmachine1_twtpcon_ready) begin
-				main_litedramcore_bankmachine1_refresh_gnt <= 1'd1;
-			end
 		end
 		3'd5: begin
 		end
@@ -6540,6 +6525,21 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
+			if (main_litedramcore_bankmachine1_refresh_req) begin
+			end else begin
+				if (main_litedramcore_bankmachine1_cmd_buffer_source_valid) begin
+					if (main_litedramcore_bankmachine1_row_opened) begin
+						if (main_litedramcore_bankmachine1_row_hit) begin
+							if (main_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
+							end else begin
+								main_litedramcore_bankmachine1_req_rdata_valid <= main_litedramcore_bankmachine1_cmd_ready;
+							end
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
 		end
 	endcase
 // synthesis translate_off
@@ -7498,7 +7498,7 @@ end
 reg dummy_d_192;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine3_req_rdata_valid <= 1'd0;
+	main_litedramcore_bankmachine3_cmd_payload_cas <= 1'd0;
 	case (builder_bankmachine3_state)
 		1'd1: begin
 		end
@@ -7522,10 +7522,7 @@ always @(*) begin
 				if (main_litedramcore_bankmachine3_cmd_buffer_source_valid) begin
 					if (main_litedramcore_bankmachine3_row_opened) begin
 						if (main_litedramcore_bankmachine3_row_hit) begin
-							if (main_litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
-							end else begin
-								main_litedramcore_bankmachine3_req_rdata_valid <= main_litedramcore_bankmachine3_cmd_ready;
-							end
+							main_litedramcore_bankmachine3_cmd_payload_cas <= 1'd1;
 						end else begin
 						end
 					end else begin
@@ -7543,13 +7540,19 @@ end
 reg dummy_d_193;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine3_cmd_payload_cas <= 1'd0;
+	main_litedramcore_bankmachine3_cmd_payload_ras <= 1'd0;
 	case (builder_bankmachine3_state)
 		1'd1: begin
+			if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin
+				main_litedramcore_bankmachine3_cmd_payload_ras <= 1'd1;
+			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
+			if (main_litedramcore_bankmachine3_trccon_ready) begin
+				main_litedramcore_bankmachine3_cmd_payload_ras <= 1'd1;
+			end
 		end
 		3'd4: begin
 		end
@@ -7562,18 +7565,6 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine3_refresh_req) begin
-			end else begin
-				if (main_litedramcore_bankmachine3_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine3_row_opened) begin
-						if (main_litedramcore_bankmachine3_row_hit) begin
-							main_litedramcore_bankmachine3_cmd_payload_cas <= 1'd1;
-						end else begin
-						end
-					end else begin
-					end
-				end
-			end
 		end
 	endcase
 // synthesis translate_off
@@ -7585,19 +7576,16 @@ end
 reg dummy_d_194;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine3_cmd_payload_ras <= 1'd0;
+	main_litedramcore_bankmachine3_cmd_payload_we <= 1'd0;
 	case (builder_bankmachine3_state)
 		1'd1: begin
 			if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin
-				main_litedramcore_bankmachine3_cmd_payload_ras <= 1'd1;
+				main_litedramcore_bankmachine3_cmd_payload_we <= 1'd1;
 			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine3_trccon_ready) begin
-				main_litedramcore_bankmachine3_cmd_payload_ras <= 1'd1;
-			end
 		end
 		3'd4: begin
 		end
@@ -7610,6 +7598,21 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
+			if (main_litedramcore_bankmachine3_refresh_req) begin
+			end else begin
+				if (main_litedramcore_bankmachine3_cmd_buffer_source_valid) begin
+					if (main_litedramcore_bankmachine3_row_opened) begin
+						if (main_litedramcore_bankmachine3_row_hit) begin
+							if (main_litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
+								main_litedramcore_bankmachine3_cmd_payload_we <= 1'd1;
+							end else begin
+							end
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
 		end
 	endcase
 // synthesis translate_off
@@ -7621,12 +7624,9 @@ end
 reg dummy_d_195;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine3_cmd_payload_we <= 1'd0;
+	main_litedramcore_bankmachine3_req_rdata_valid <= 1'd0;
 	case (builder_bankmachine3_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin
-				main_litedramcore_bankmachine3_cmd_payload_we <= 1'd1;
-			end
 		end
 		2'd2: begin
 		end
@@ -7649,8 +7649,8 @@ always @(*) begin
 					if (main_litedramcore_bankmachine3_row_opened) begin
 						if (main_litedramcore_bankmachine3_row_hit) begin
 							if (main_litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
-								main_litedramcore_bankmachine3_cmd_payload_we <= 1'd1;
 							end else begin
+								main_litedramcore_bankmachine3_req_rdata_valid <= main_litedramcore_bankmachine3_cmd_ready;
 							end
 						end else begin
 						end
@@ -7669,18 +7669,22 @@ end
 reg dummy_d_196;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd0;
+	main_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd0;
 	case (builder_bankmachine3_state)
 		1'd1: begin
+			if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin
+				main_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
+			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
 			if (main_litedramcore_bankmachine3_trccon_ready) begin
-				main_litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd1;
+				main_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
 			end
 		end
 		3'd4: begin
+			main_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
 		end
 		3'd5: begin
 		end
@@ -7702,22 +7706,18 @@ end
 reg dummy_d_197;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd0;
+	main_litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd0;
 	case (builder_bankmachine3_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin
-				main_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
-			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
 			if (main_litedramcore_bankmachine3_trccon_ready) begin
-				main_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
+				main_litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd1;
 			end
 		end
 		3'd4: begin
-			main_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
 		end
 		3'd5: begin
 		end
@@ -8417,7 +8417,7 @@ end
 reg dummy_d_215;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine4_req_rdata_valid <= 1'd0;
+	main_litedramcore_bankmachine4_cmd_payload_is_write <= 1'd0;
 	case (builder_bankmachine4_state)
 		1'd1: begin
 		end
@@ -8442,8 +8442,8 @@ always @(*) begin
 					if (main_litedramcore_bankmachine4_row_opened) begin
 						if (main_litedramcore_bankmachine4_row_hit) begin
 							if (main_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
+								main_litedramcore_bankmachine4_cmd_payload_is_write <= 1'd1;
 							end else begin
-								main_litedramcore_bankmachine4_req_rdata_valid <= main_litedramcore_bankmachine4_cmd_ready;
 							end
 						end else begin
 						end
@@ -8462,7 +8462,7 @@ end
 reg dummy_d_216;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine4_cmd_payload_is_write <= 1'd0;
+	main_litedramcore_bankmachine4_req_wdata_ready <= 1'd0;
 	case (builder_bankmachine4_state)
 		1'd1: begin
 		end
@@ -8487,7 +8487,7 @@ always @(*) begin
 					if (main_litedramcore_bankmachine4_row_opened) begin
 						if (main_litedramcore_bankmachine4_row_hit) begin
 							if (main_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
-								main_litedramcore_bankmachine4_cmd_payload_is_write <= 1'd1;
+								main_litedramcore_bankmachine4_req_wdata_ready <= main_litedramcore_bankmachine4_cmd_ready;
 							end else begin
 							end
 						end else begin
@@ -8507,7 +8507,7 @@ end
 reg dummy_d_217;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine4_req_wdata_ready <= 1'd0;
+	main_litedramcore_bankmachine4_req_rdata_valid <= 1'd0;
 	case (builder_bankmachine4_state)
 		1'd1: begin
 		end
@@ -8532,8 +8532,8 @@ always @(*) begin
 					if (main_litedramcore_bankmachine4_row_opened) begin
 						if (main_litedramcore_bankmachine4_row_hit) begin
 							if (main_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
-								main_litedramcore_bankmachine4_req_wdata_ready <= main_litedramcore_bankmachine4_cmd_ready;
 							end else begin
+								main_litedramcore_bankmachine4_req_rdata_valid <= main_litedramcore_bankmachine4_cmd_ready;
 							end
 						end else begin
 						end
@@ -8787,6 +8787,51 @@ end
 // synthesis translate_off
 reg dummy_d_224;
 // synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine5_req_rdata_valid <= 1'd0;
+	case (builder_bankmachine5_state)
+		1'd1: begin
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+			if (main_litedramcore_bankmachine5_refresh_req) begin
+			end else begin
+				if (main_litedramcore_bankmachine5_cmd_buffer_source_valid) begin
+					if (main_litedramcore_bankmachine5_row_opened) begin
+						if (main_litedramcore_bankmachine5_row_hit) begin
+							if (main_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
+							end else begin
+								main_litedramcore_bankmachine5_req_rdata_valid <= main_litedramcore_bankmachine5_cmd_ready;
+							end
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_224 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_225;
+// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine5_row_open <= 1'd0;
 	case (builder_bankmachine5_state)
@@ -8813,12 +8858,12 @@ always @(*) begin
 		end
 	endcase
 // synthesis translate_off
-	dummy_d_224 = dummy_s;
+	dummy_d_225 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_225;
+reg dummy_d_226;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine5_row_close <= 1'd0;
@@ -8846,12 +8891,12 @@ always @(*) begin
 		end
 	endcase
 // synthesis translate_off
-	dummy_d_225 = dummy_s;
+	dummy_d_226 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_226;
+reg dummy_d_227;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine5_cmd_payload_cas <= 1'd0;
@@ -8888,12 +8933,12 @@ always @(*) begin
 		end
 	endcase
 // synthesis translate_off
-	dummy_d_226 = dummy_s;
+	dummy_d_227 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_227;
+reg dummy_d_228;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine5_cmd_payload_ras <= 1'd0;
@@ -8924,12 +8969,12 @@ always @(*) begin
 		end
 	endcase
 // synthesis translate_off
-	dummy_d_227 = dummy_s;
+	dummy_d_228 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_228;
+reg dummy_d_229;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine5_cmd_payload_we <= 1'd0;
@@ -8972,12 +9017,12 @@ always @(*) begin
 		end
 	endcase
 // synthesis translate_off
-	dummy_d_228 = dummy_s;
+	dummy_d_229 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_229;
+reg dummy_d_230;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd0;
@@ -9005,12 +9050,12 @@ always @(*) begin
 		end
 	endcase
 // synthesis translate_off
-	dummy_d_229 = dummy_s;
+	dummy_d_230 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_230;
+reg dummy_d_231;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd0;
@@ -9041,39 +9086,6 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_230 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_231;
-// synthesis translate_on
-always @(*) begin
-	main_litedramcore_bankmachine5_refresh_gnt <= 1'd0;
-	case (builder_bankmachine5_state)
-		1'd1: begin
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-		end
-		3'd4: begin
-			if (main_litedramcore_bankmachine5_twtpcon_ready) begin
-				main_litedramcore_bankmachine5_refresh_gnt <= 1'd1;
-			end
-		end
-		3'd5: begin
-		end
-		3'd6: begin
-		end
-		3'd7: begin
-		end
-		4'd8: begin
-		end
-		default: begin
-		end
-	endcase
 // synthesis translate_off
 	dummy_d_231 = dummy_s;
 // synthesis translate_on
@@ -9218,7 +9230,7 @@ end
 reg dummy_d_235;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine5_req_rdata_valid <= 1'd0;
+	main_litedramcore_bankmachine5_refresh_gnt <= 1'd0;
 	case (builder_bankmachine5_state)
 		1'd1: begin
 		end
@@ -9227,6 +9239,9 @@ always @(*) begin
 		2'd3: begin
 		end
 		3'd4: begin
+			if (main_litedramcore_bankmachine5_twtpcon_ready) begin
+				main_litedramcore_bankmachine5_refresh_gnt <= 1'd1;
+			end
 		end
 		3'd5: begin
 		end
@@ -9237,21 +9252,6 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine5_refresh_req) begin
-			end else begin
-				if (main_litedramcore_bankmachine5_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine5_row_opened) begin
-						if (main_litedramcore_bankmachine5_row_hit) begin
-							if (main_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
-							end else begin
-								main_litedramcore_bankmachine5_req_rdata_valid <= main_litedramcore_bankmachine5_cmd_ready;
-							end
-						end else begin
-						end
-					end else begin
-					end
-				end
-			end
 		end
 	endcase
 // synthesis translate_off
@@ -9466,13 +9466,16 @@ end
 reg dummy_d_241;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine6_req_rdata_valid <= 1'd0;
+	main_litedramcore_bankmachine6_row_open <= 1'd0;
 	case (builder_bankmachine6_state)
 		1'd1: begin
 		end
 		2'd2: begin
 		end
 		2'd3: begin
+			if (main_litedramcore_bankmachine6_trccon_ready) begin
+				main_litedramcore_bankmachine6_row_open <= 1'd1;
+			end
 		end
 		3'd4: begin
 		end
@@ -9485,21 +9488,6 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine6_refresh_req) begin
-			end else begin
-				if (main_litedramcore_bankmachine6_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine6_row_opened) begin
-						if (main_litedramcore_bankmachine6_row_hit) begin
-							if (main_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
-							end else begin
-								main_litedramcore_bankmachine6_req_rdata_valid <= main_litedramcore_bankmachine6_cmd_ready;
-							end
-						end else begin
-						end
-					end else begin
-					end
-				end
-			end
 		end
 	endcase
 // synthesis translate_off
@@ -9511,18 +9499,18 @@ end
 reg dummy_d_242;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine6_row_open <= 1'd0;
+	main_litedramcore_bankmachine6_row_close <= 1'd0;
 	case (builder_bankmachine6_state)
 		1'd1: begin
+			main_litedramcore_bankmachine6_row_close <= 1'd1;
 		end
 		2'd2: begin
+			main_litedramcore_bankmachine6_row_close <= 1'd1;
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine6_trccon_ready) begin
-				main_litedramcore_bankmachine6_row_open <= 1'd1;
-			end
 		end
 		3'd4: begin
+			main_litedramcore_bankmachine6_row_close <= 1'd1;
 		end
 		3'd5: begin
 		end
@@ -9544,18 +9532,15 @@ end
 reg dummy_d_243;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine6_row_close <= 1'd0;
+	main_litedramcore_bankmachine6_req_rdata_valid <= 1'd0;
 	case (builder_bankmachine6_state)
 		1'd1: begin
-			main_litedramcore_bankmachine6_row_close <= 1'd1;
 		end
 		2'd2: begin
-			main_litedramcore_bankmachine6_row_close <= 1'd1;
 		end
 		2'd3: begin
 		end
 		3'd4: begin
-			main_litedramcore_bankmachine6_row_close <= 1'd1;
 		end
 		3'd5: begin
 		end
@@ -9566,6 +9551,21 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
+			if (main_litedramcore_bankmachine6_refresh_req) begin
+			end else begin
+				if (main_litedramcore_bankmachine6_cmd_buffer_source_valid) begin
+					if (main_litedramcore_bankmachine6_row_opened) begin
+						if (main_litedramcore_bankmachine6_row_hit) begin
+							if (main_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
+							end else begin
+								main_litedramcore_bankmachine6_req_rdata_valid <= main_litedramcore_bankmachine6_cmd_ready;
+							end
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
 		end
 	endcase
 // synthesis translate_off
@@ -10336,13 +10336,16 @@ end
 reg dummy_d_263;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine7_req_rdata_valid <= 1'd0;
+	main_litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd0;
 	case (builder_bankmachine7_state)
 		1'd1: begin
 		end
 		2'd2: begin
 		end
 		2'd3: begin
+			if (main_litedramcore_bankmachine7_trccon_ready) begin
+				main_litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd1;
+			end
 		end
 		3'd4: begin
 		end
@@ -10355,21 +10358,6 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine7_refresh_req) begin
-			end else begin
-				if (main_litedramcore_bankmachine7_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine7_row_opened) begin
-						if (main_litedramcore_bankmachine7_row_hit) begin
-							if (main_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
-							end else begin
-								main_litedramcore_bankmachine7_req_rdata_valid <= main_litedramcore_bankmachine7_cmd_ready;
-							end
-						end else begin
-						end
-					end else begin
-					end
-				end
-			end
 		end
 	endcase
 // synthesis translate_off
@@ -10418,16 +10406,13 @@ end
 reg dummy_d_265;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd0;
+	main_litedramcore_bankmachine7_req_rdata_valid <= 1'd0;
 	case (builder_bankmachine7_state)
 		1'd1: begin
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine7_trccon_ready) begin
-				main_litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd1;
-			end
 		end
 		3'd4: begin
 		end
@@ -10440,17 +10425,32 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-		end
-	endcase
-// synthesis translate_off
-	dummy_d_265 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_266;
-// synthesis translate_on
-always @(*) begin
+			if (main_litedramcore_bankmachine7_refresh_req) begin
+			end else begin
+				if (main_litedramcore_bankmachine7_cmd_buffer_source_valid) begin
+					if (main_litedramcore_bankmachine7_row_opened) begin
+						if (main_litedramcore_bankmachine7_row_hit) begin
+							if (main_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
+							end else begin
+								main_litedramcore_bankmachine7_req_rdata_valid <= main_litedramcore_bankmachine7_cmd_ready;
+							end
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_265 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_266;
+// synthesis translate_on
+always @(*) begin
 	main_litedramcore_bankmachine7_cmd_payload_is_read <= 1'd0;
 	case (builder_bankmachine7_state)
 		1'd1: begin
@@ -11032,13 +11032,9 @@ end
 reg dummy_d_288;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_choose_cmd_cmd_ready <= 1'd0;
+	main_litedramcore_en0 <= 1'd0;
 	case (builder_multiplexer_state)
 		1'd1: begin
-			if (1'd0) begin
-			end else begin
-				main_litedramcore_choose_cmd_cmd_ready <= ((~((main_litedramcore_choose_cmd_cmd_payload_ras & (~main_litedramcore_choose_cmd_cmd_payload_cas)) & (~main_litedramcore_choose_cmd_cmd_payload_we))) | main_litedramcore_ras_allowed);
-			end
 		end
 		2'd2: begin
 		end
@@ -11059,10 +11055,7 @@ always @(*) begin
 		4'd10: begin
 		end
 		default: begin
-			if (1'd0) begin
-			end else begin
-				main_litedramcore_choose_cmd_cmd_ready <= ((~((main_litedramcore_choose_cmd_cmd_payload_ras & (~main_litedramcore_choose_cmd_cmd_payload_cas)) & (~main_litedramcore_choose_cmd_cmd_payload_we))) | main_litedramcore_ras_allowed);
-			end
+			main_litedramcore_en0 <= 1'd1;
 		end
 	endcase
 // synthesis translate_off
@@ -11074,9 +11067,13 @@ end
 reg dummy_d_289;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_choose_req_want_reads <= 1'd0;
+	main_litedramcore_choose_cmd_cmd_ready <= 1'd0;
 	case (builder_multiplexer_state)
 		1'd1: begin
+			if (1'd0) begin
+			end else begin
+				main_litedramcore_choose_cmd_cmd_ready <= ((~((main_litedramcore_choose_cmd_cmd_payload_ras & (~main_litedramcore_choose_cmd_cmd_payload_cas)) & (~main_litedramcore_choose_cmd_cmd_payload_we))) | main_litedramcore_ras_allowed);
+			end
 		end
 		2'd2: begin
 		end
@@ -11097,7 +11094,10 @@ always @(*) begin
 		4'd10: begin
 		end
 		default: begin
-			main_litedramcore_choose_req_want_reads <= 1'd1;
+			if (1'd0) begin
+			end else begin
+				main_litedramcore_choose_cmd_cmd_ready <= ((~((main_litedramcore_choose_cmd_cmd_payload_ras & (~main_litedramcore_choose_cmd_cmd_payload_cas)) & (~main_litedramcore_choose_cmd_cmd_payload_we))) | main_litedramcore_ras_allowed);
+			end
 		end
 	endcase
 // synthesis translate_off
@@ -11109,10 +11109,9 @@ end
 reg dummy_d_290;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_choose_req_want_writes <= 1'd0;
+	main_litedramcore_choose_req_want_reads <= 1'd0;
 	case (builder_multiplexer_state)
 		1'd1: begin
-			main_litedramcore_choose_req_want_writes <= 1'd1;
 		end
 		2'd2: begin
 		end
@@ -11133,6 +11132,7 @@ always @(*) begin
 		4'd10: begin
 		end
 		default: begin
+			main_litedramcore_choose_req_want_reads <= 1'd1;
 		end
 	endcase
 // synthesis translate_off
@@ -11144,16 +11144,10 @@ end
 reg dummy_d_291;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_steerer_sel3 <= 2'd0;
+	main_litedramcore_choose_req_want_writes <= 1'd0;
 	case (builder_multiplexer_state)
 		1'd1: begin
-			main_litedramcore_steerer_sel3 <= 1'd0;
-			if ((main_a7ddrphy_wrphase_storage == 2'd3)) begin
-				main_litedramcore_steerer_sel3 <= 2'd2;
-			end
-			if ((main_litedramcore_wrcmdphase == 2'd3)) begin
-				main_litedramcore_steerer_sel3 <= 1'd1;
-			end
+			main_litedramcore_choose_req_want_writes <= 1'd1;
 		end
 		2'd2: begin
 		end
@@ -11174,13 +11168,6 @@ always @(*) begin
 		4'd10: begin
 		end
 		default: begin
-			main_litedramcore_steerer_sel3 <= 1'd0;
-			if ((main_a7ddrphy_rdphase_storage == 2'd3)) begin
-				main_litedramcore_steerer_sel3 <= 2'd2;
-			end
-			if ((main_litedramcore_rdcmdphase == 2'd3)) begin
-				main_litedramcore_steerer_sel3 <= 1'd1;
-			end
 		end
 	endcase
 // synthesis translate_off
@@ -11236,10 +11223,16 @@ end
 reg dummy_d_293;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_en1 <= 1'd0;
+	main_litedramcore_steerer_sel3 <= 2'd0;
 	case (builder_multiplexer_state)
 		1'd1: begin
-			main_litedramcore_en1 <= 1'd1;
+			main_litedramcore_steerer_sel3 <= 1'd0;
+			if ((main_a7ddrphy_wrphase_storage == 2'd3)) begin
+				main_litedramcore_steerer_sel3 <= 2'd2;
+			end
+			if ((main_litedramcore_wrcmdphase == 2'd3)) begin
+				main_litedramcore_steerer_sel3 <= 1'd1;
+			end
 		end
 		2'd2: begin
 		end
@@ -11260,6 +11253,13 @@ always @(*) begin
 		4'd10: begin
 		end
 		default: begin
+			main_litedramcore_steerer_sel3 <= 1'd0;
+			if ((main_a7ddrphy_rdphase_storage == 2'd3)) begin
+				main_litedramcore_steerer_sel3 <= 2'd2;
+			end
+			if ((main_litedramcore_rdcmdphase == 2'd3)) begin
+				main_litedramcore_steerer_sel3 <= 1'd1;
+			end
 		end
 	endcase
 // synthesis translate_off
@@ -11270,6 +11270,41 @@ end
 // synthesis translate_off
 reg dummy_d_294;
 // synthesis translate_on
+always @(*) begin
+	main_litedramcore_en1 <= 1'd0;
+	case (builder_multiplexer_state)
+		1'd1: begin
+			main_litedramcore_en1 <= 1'd1;
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		4'd9: begin
+		end
+		4'd10: begin
+		end
+		default: begin
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_294 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_295;
+// synthesis translate_on
 always @(*) begin
 	main_litedramcore_steerer_sel0 <= 2'd0;
 	case (builder_multiplexer_state)
@@ -11312,12 +11347,12 @@ always @(*) begin
 		end
 	endcase
 // synthesis translate_off
-	dummy_d_294 = dummy_s;
+	dummy_d_295 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_295;
+reg dummy_d_296;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_cmd_ready <= 1'd0;
@@ -11347,12 +11382,12 @@ always @(*) begin
 		end
 	endcase
 // synthesis translate_off
-	dummy_d_295 = dummy_s;
+	dummy_d_296 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_296;
+reg dummy_d_297;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_steerer_sel1 <= 2'd0;
@@ -11395,12 +11430,12 @@ always @(*) begin
 		end
 	endcase
 // synthesis translate_off
-	dummy_d_296 = dummy_s;
+	dummy_d_297 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_297;
+reg dummy_d_298;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_steerer_sel2 <= 2'd0;
@@ -11443,12 +11478,12 @@ always @(*) begin
 		end
 	endcase
 // synthesis translate_off
-	dummy_d_297 = dummy_s;
+	dummy_d_298 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_298;
+reg dummy_d_299;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_choose_cmd_want_activates <= 1'd0;
@@ -11484,41 +11519,6 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_298 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_299;
-// synthesis translate_on
-always @(*) begin
-	main_litedramcore_en0 <= 1'd0;
-	case (builder_multiplexer_state)
-		1'd1: begin
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-		end
-		3'd4: begin
-		end
-		3'd5: begin
-		end
-		3'd6: begin
-		end
-		3'd7: begin
-		end
-		4'd8: begin
-		end
-		4'd9: begin
-		end
-		4'd10: begin
-		end
-		default: begin
-			main_litedramcore_en0 <= 1'd1;
-		end
-	endcase
 // synthesis translate_off
 	dummy_d_299 = dummy_s;
 // synthesis translate_on
@@ -11810,16 +11810,16 @@ assign builder_litedramcore_wishbone_we = main_wb_bus_we;
 assign builder_litedramcore_wishbone_cti = main_wb_bus_cti;
 assign builder_litedramcore_wishbone_bte = main_wb_bus_bte;
 assign main_wb_bus_err = builder_litedramcore_wishbone_err;
-assign builder_csrbank0_sel = (builder_interface0_bank_bus_adr[13:9] == 1'd0);
+assign builder_csrbank0_sel = (builder_interface0_bank_bus_adr[13:9] == 1'd1);
 assign builder_csrbank0_init_done0_r = builder_interface0_bank_bus_dat_w[0];
 
 // synthesis translate_off
 reg dummy_d_311;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank0_init_done0_we <= 1'd0;
+	builder_csrbank0_init_done0_re <= 1'd0;
 	if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd0))) begin
-		builder_csrbank0_init_done0_we <= (~builder_interface0_bank_bus_we);
+		builder_csrbank0_init_done0_re <= builder_interface0_bank_bus_we;
 	end
 // synthesis translate_off
 	dummy_d_311 = dummy_s;
@@ -11830,9 +11830,9 @@ end
 reg dummy_d_312;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank0_init_done0_re <= 1'd0;
+	builder_csrbank0_init_done0_we <= 1'd0;
 	if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd0))) begin
-		builder_csrbank0_init_done0_re <= builder_interface0_bank_bus_we;
+		builder_csrbank0_init_done0_we <= (~builder_interface0_bank_bus_we);
 	end
 // synthesis translate_off
 	dummy_d_312 = dummy_s;
@@ -11867,7 +11867,7 @@ always @(*) begin
 end
 assign builder_csrbank0_init_done0_w = main_init_done_storage;
 assign builder_csrbank0_init_error0_w = main_init_error_storage;
-assign builder_csrbank1_sel = (builder_interface1_bank_bus_adr[13:9] == 1'd1);
+assign builder_csrbank1_sel = (builder_interface1_bank_bus_adr[13:9] == 2'd2);
 assign builder_csrbank1_rst0_r = builder_interface1_bank_bus_dat_w[0];
 
 // synthesis translate_off
@@ -11955,9 +11955,9 @@ assign main_a7ddrphy_wlevel_strobe_r = builder_interface1_bank_bus_dat_w[0];
 reg dummy_d_321;
 // synthesis translate_on
 always @(*) begin
-	main_a7ddrphy_wlevel_strobe_re <= 1'd0;
+	main_a7ddrphy_wlevel_strobe_we <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd3))) begin
-		main_a7ddrphy_wlevel_strobe_re <= builder_interface1_bank_bus_we;
+		main_a7ddrphy_wlevel_strobe_we <= (~builder_interface1_bank_bus_we);
 	end
 // synthesis translate_off
 	dummy_d_321 = dummy_s;
@@ -11968,9 +11968,9 @@ end
 reg dummy_d_322;
 // synthesis translate_on
 always @(*) begin
-	main_a7ddrphy_wlevel_strobe_we <= 1'd0;
+	main_a7ddrphy_wlevel_strobe_re <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd3))) begin
-		main_a7ddrphy_wlevel_strobe_we <= (~builder_interface1_bank_bus_we);
+		main_a7ddrphy_wlevel_strobe_re <= builder_interface1_bank_bus_we;
 	end
 // synthesis translate_off
 	dummy_d_322 = dummy_s;
@@ -11982,9 +11982,9 @@ assign builder_csrbank1_dly_sel0_r = builder_interface1_bank_bus_dat_w[1:0];
 reg dummy_d_323;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank1_dly_sel0_re <= 1'd0;
+	builder_csrbank1_dly_sel0_we <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd4))) begin
-		builder_csrbank1_dly_sel0_re <= builder_interface1_bank_bus_we;
+		builder_csrbank1_dly_sel0_we <= (~builder_interface1_bank_bus_we);
 	end
 // synthesis translate_off
 	dummy_d_323 = dummy_s;
@@ -11995,9 +11995,9 @@ end
 reg dummy_d_324;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank1_dly_sel0_we <= 1'd0;
+	builder_csrbank1_dly_sel0_re <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd4))) begin
-		builder_csrbank1_dly_sel0_we <= (~builder_interface1_bank_bus_we);
+		builder_csrbank1_dly_sel0_re <= builder_interface1_bank_bus_we;
 	end
 // synthesis translate_off
 	dummy_d_324 = dummy_s;
@@ -12063,9 +12063,9 @@ assign main_a7ddrphy_rdly_dq_bitslip_rst_r = builder_interface1_bank_bus_dat_w[0
 reg dummy_d_329;
 // synthesis translate_on
 always @(*) begin
-	main_a7ddrphy_rdly_dq_bitslip_rst_re <= 1'd0;
+	main_a7ddrphy_rdly_dq_bitslip_rst_we <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd7))) begin
-		main_a7ddrphy_rdly_dq_bitslip_rst_re <= builder_interface1_bank_bus_we;
+		main_a7ddrphy_rdly_dq_bitslip_rst_we <= (~builder_interface1_bank_bus_we);
 	end
 // synthesis translate_off
 	dummy_d_329 = dummy_s;
@@ -12076,9 +12076,9 @@ end
 reg dummy_d_330;
 // synthesis translate_on
 always @(*) begin
-	main_a7ddrphy_rdly_dq_bitslip_rst_we <= 1'd0;
+	main_a7ddrphy_rdly_dq_bitslip_rst_re <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd7))) begin
-		main_a7ddrphy_rdly_dq_bitslip_rst_we <= (~builder_interface1_bank_bus_we);
+		main_a7ddrphy_rdly_dq_bitslip_rst_re <= builder_interface1_bank_bus_we;
 	end
 // synthesis translate_off
 	dummy_d_330 = dummy_s;
@@ -12225,7 +12225,7 @@ assign builder_csrbank1_wlevel_en0_w = main_a7ddrphy_wlevel_en_storage;
 assign builder_csrbank1_dly_sel0_w = main_a7ddrphy_dly_sel_storage[1:0];
 assign builder_csrbank1_rdphase0_w = main_a7ddrphy_rdphase_storage[1:0];
 assign builder_csrbank1_wrphase0_w = main_a7ddrphy_wrphase_storage[1:0];
-assign builder_csrbank2_sel = (builder_interface2_bank_bus_adr[13:9] == 2'd2);
+assign builder_csrbank2_sel = (builder_interface2_bank_bus_adr[13:9] == 1'd0);
 assign builder_csrbank2_dfii_control0_r = builder_interface2_bank_bus_dat_w[3:0];
 
 // synthesis translate_off
@@ -12340,9 +12340,9 @@ assign builder_csrbank2_dfii_pi0_address0_r = builder_interface2_bank_bus_dat_w[
 reg dummy_d_349;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi0_address0_we <= 1'd0;
+	builder_csrbank2_dfii_pi0_address0_re <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd4))) begin
-		builder_csrbank2_dfii_pi0_address0_we <= (~builder_interface2_bank_bus_we);
+		builder_csrbank2_dfii_pi0_address0_re <= builder_interface2_bank_bus_we;
 	end
 // synthesis translate_off
 	dummy_d_349 = dummy_s;
@@ -12353,9 +12353,9 @@ end
 reg dummy_d_350;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi0_address0_re <= 1'd0;
+	builder_csrbank2_dfii_pi0_address0_we <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd4))) begin
-		builder_csrbank2_dfii_pi0_address0_re <= builder_interface2_bank_bus_we;
+		builder_csrbank2_dfii_pi0_address0_we <= (~builder_interface2_bank_bus_we);
 	end
 // synthesis translate_off
 	dummy_d_350 = dummy_s;
@@ -12448,9 +12448,9 @@ assign builder_csrbank2_dfii_pi0_wrdata1_r = builder_interface2_bank_bus_dat_w[7
 reg dummy_d_357;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi0_wrdata1_re <= 1'd0;
+	builder_csrbank2_dfii_pi0_wrdata1_we <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd8))) begin
-		builder_csrbank2_dfii_pi0_wrdata1_re <= builder_interface2_bank_bus_we;
+		builder_csrbank2_dfii_pi0_wrdata1_we <= (~builder_interface2_bank_bus_we);
 	end
 // synthesis translate_off
 	dummy_d_357 = dummy_s;
@@ -12461,9 +12461,9 @@ end
 reg dummy_d_358;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi0_wrdata1_we <= 1'd0;
+	builder_csrbank2_dfii_pi0_wrdata1_re <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd8))) begin
-		builder_csrbank2_dfii_pi0_wrdata1_we <= (~builder_interface2_bank_bus_we);
+		builder_csrbank2_dfii_pi0_wrdata1_re <= builder_interface2_bank_bus_we;
 	end
 // synthesis translate_off
 	dummy_d_358 = dummy_s;
@@ -12529,9 +12529,9 @@ assign builder_csrbank2_dfii_pi0_rddata2_r = builder_interface2_bank_bus_dat_w[7
 reg dummy_d_363;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi0_rddata2_re <= 1'd0;
+	builder_csrbank2_dfii_pi0_rddata2_we <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd11))) begin
-		builder_csrbank2_dfii_pi0_rddata2_re <= builder_interface2_bank_bus_we;
+		builder_csrbank2_dfii_pi0_rddata2_we <= (~builder_interface2_bank_bus_we);
 	end
 // synthesis translate_off
 	dummy_d_363 = dummy_s;
@@ -12542,9 +12542,9 @@ end
 reg dummy_d_364;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi0_rddata2_we <= 1'd0;
+	builder_csrbank2_dfii_pi0_rddata2_re <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd11))) begin
-		builder_csrbank2_dfii_pi0_rddata2_we <= (~builder_interface2_bank_bus_we);
+		builder_csrbank2_dfii_pi0_rddata2_re <= builder_interface2_bank_bus_we;
 	end
 // synthesis translate_off
 	dummy_d_364 = dummy_s;
@@ -12583,9 +12583,9 @@ assign builder_csrbank2_dfii_pi0_rddata0_r = builder_interface2_bank_bus_dat_w[7
 reg dummy_d_367;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi0_rddata0_we <= 1'd0;
+	builder_csrbank2_dfii_pi0_rddata0_re <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd13))) begin
-		builder_csrbank2_dfii_pi0_rddata0_we <= (~builder_interface2_bank_bus_we);
+		builder_csrbank2_dfii_pi0_rddata0_re <= builder_interface2_bank_bus_we;
 	end
 // synthesis translate_off
 	dummy_d_367 = dummy_s;
@@ -12596,9 +12596,9 @@ end
 reg dummy_d_368;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi0_rddata0_re <= 1'd0;
+	builder_csrbank2_dfii_pi0_rddata0_we <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd13))) begin
-		builder_csrbank2_dfii_pi0_rddata0_re <= builder_interface2_bank_bus_we;
+		builder_csrbank2_dfii_pi0_rddata0_we <= (~builder_interface2_bank_bus_we);
 	end
 // synthesis translate_off
 	dummy_d_368 = dummy_s;
@@ -12691,9 +12691,9 @@ assign builder_csrbank2_dfii_pi1_address0_r = builder_interface2_bank_bus_dat_w[
 reg dummy_d_375;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi1_address0_we <= 1'd0;
+	builder_csrbank2_dfii_pi1_address0_re <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd17))) begin
-		builder_csrbank2_dfii_pi1_address0_we <= (~builder_interface2_bank_bus_we);
+		builder_csrbank2_dfii_pi1_address0_re <= builder_interface2_bank_bus_we;
 	end
 // synthesis translate_off
 	dummy_d_375 = dummy_s;
@@ -12704,9 +12704,9 @@ end
 reg dummy_d_376;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi1_address0_re <= 1'd0;
+	builder_csrbank2_dfii_pi1_address0_we <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd17))) begin
-		builder_csrbank2_dfii_pi1_address0_re <= builder_interface2_bank_bus_we;
+		builder_csrbank2_dfii_pi1_address0_we <= (~builder_interface2_bank_bus_we);
 	end
 // synthesis translate_off
 	dummy_d_376 = dummy_s;
@@ -12799,9 +12799,9 @@ assign builder_csrbank2_dfii_pi1_wrdata1_r = builder_interface2_bank_bus_dat_w[7
 reg dummy_d_383;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi1_wrdata1_re <= 1'd0;
+	builder_csrbank2_dfii_pi1_wrdata1_we <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd21))) begin
-		builder_csrbank2_dfii_pi1_wrdata1_re <= builder_interface2_bank_bus_we;
+		builder_csrbank2_dfii_pi1_wrdata1_we <= (~builder_interface2_bank_bus_we);
 	end
 // synthesis translate_off
 	dummy_d_383 = dummy_s;
@@ -12812,9 +12812,9 @@ end
 reg dummy_d_384;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi1_wrdata1_we <= 1'd0;
+	builder_csrbank2_dfii_pi1_wrdata1_re <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd21))) begin
-		builder_csrbank2_dfii_pi1_wrdata1_we <= (~builder_interface2_bank_bus_we);
+		builder_csrbank2_dfii_pi1_wrdata1_re <= builder_interface2_bank_bus_we;
 	end
 // synthesis translate_off
 	dummy_d_384 = dummy_s;
@@ -12880,9 +12880,9 @@ assign builder_csrbank2_dfii_pi1_rddata2_r = builder_interface2_bank_bus_dat_w[7
 reg dummy_d_389;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi1_rddata2_re <= 1'd0;
+	builder_csrbank2_dfii_pi1_rddata2_we <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd24))) begin
-		builder_csrbank2_dfii_pi1_rddata2_re <= builder_interface2_bank_bus_we;
+		builder_csrbank2_dfii_pi1_rddata2_we <= (~builder_interface2_bank_bus_we);
 	end
 // synthesis translate_off
 	dummy_d_389 = dummy_s;
@@ -12893,9 +12893,9 @@ end
 reg dummy_d_390;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi1_rddata2_we <= 1'd0;
+	builder_csrbank2_dfii_pi1_rddata2_re <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd24))) begin
-		builder_csrbank2_dfii_pi1_rddata2_we <= (~builder_interface2_bank_bus_we);
+		builder_csrbank2_dfii_pi1_rddata2_re <= builder_interface2_bank_bus_we;
 	end
 // synthesis translate_off
 	dummy_d_390 = dummy_s;
@@ -12934,9 +12934,9 @@ assign builder_csrbank2_dfii_pi1_rddata0_r = builder_interface2_bank_bus_dat_w[7
 reg dummy_d_393;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi1_rddata0_we <= 1'd0;
+	builder_csrbank2_dfii_pi1_rddata0_re <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd26))) begin
-		builder_csrbank2_dfii_pi1_rddata0_we <= (~builder_interface2_bank_bus_we);
+		builder_csrbank2_dfii_pi1_rddata0_re <= builder_interface2_bank_bus_we;
 	end
 // synthesis translate_off
 	dummy_d_393 = dummy_s;
@@ -12947,9 +12947,9 @@ end
 reg dummy_d_394;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi1_rddata0_re <= 1'd0;
+	builder_csrbank2_dfii_pi1_rddata0_we <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd26))) begin
-		builder_csrbank2_dfii_pi1_rddata0_re <= builder_interface2_bank_bus_we;
+		builder_csrbank2_dfii_pi1_rddata0_we <= (~builder_interface2_bank_bus_we);
 	end
 // synthesis translate_off
 	dummy_d_394 = dummy_s;
@@ -13042,9 +13042,9 @@ assign builder_csrbank2_dfii_pi2_address0_r = builder_interface2_bank_bus_dat_w[
 reg dummy_d_401;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi2_address0_we <= 1'd0;
+	builder_csrbank2_dfii_pi2_address0_re <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd30))) begin
-		builder_csrbank2_dfii_pi2_address0_we <= (~builder_interface2_bank_bus_we);
+		builder_csrbank2_dfii_pi2_address0_re <= builder_interface2_bank_bus_we;
 	end
 // synthesis translate_off
 	dummy_d_401 = dummy_s;
@@ -13055,9 +13055,9 @@ end
 reg dummy_d_402;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi2_address0_re <= 1'd0;
+	builder_csrbank2_dfii_pi2_address0_we <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd30))) begin
-		builder_csrbank2_dfii_pi2_address0_re <= builder_interface2_bank_bus_we;
+		builder_csrbank2_dfii_pi2_address0_we <= (~builder_interface2_bank_bus_we);
 	end
 // synthesis translate_off
 	dummy_d_402 = dummy_s;
@@ -13150,9 +13150,9 @@ assign builder_csrbank2_dfii_pi2_wrdata1_r = builder_interface2_bank_bus_dat_w[7
 reg dummy_d_409;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi2_wrdata1_re <= 1'd0;
+	builder_csrbank2_dfii_pi2_wrdata1_we <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd34))) begin
-		builder_csrbank2_dfii_pi2_wrdata1_re <= builder_interface2_bank_bus_we;
+		builder_csrbank2_dfii_pi2_wrdata1_we <= (~builder_interface2_bank_bus_we);
 	end
 // synthesis translate_off
 	dummy_d_409 = dummy_s;
@@ -13163,9 +13163,9 @@ end
 reg dummy_d_410;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi2_wrdata1_we <= 1'd0;
+	builder_csrbank2_dfii_pi2_wrdata1_re <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd34))) begin
-		builder_csrbank2_dfii_pi2_wrdata1_we <= (~builder_interface2_bank_bus_we);
+		builder_csrbank2_dfii_pi2_wrdata1_re <= builder_interface2_bank_bus_we;
 	end
 // synthesis translate_off
 	dummy_d_410 = dummy_s;
@@ -13231,9 +13231,9 @@ assign builder_csrbank2_dfii_pi2_rddata2_r = builder_interface2_bank_bus_dat_w[7
 reg dummy_d_415;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi2_rddata2_re <= 1'd0;
+	builder_csrbank2_dfii_pi2_rddata2_we <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd37))) begin
-		builder_csrbank2_dfii_pi2_rddata2_re <= builder_interface2_bank_bus_we;
+		builder_csrbank2_dfii_pi2_rddata2_we <= (~builder_interface2_bank_bus_we);
 	end
 // synthesis translate_off
 	dummy_d_415 = dummy_s;
@@ -13244,9 +13244,9 @@ end
 reg dummy_d_416;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi2_rddata2_we <= 1'd0;
+	builder_csrbank2_dfii_pi2_rddata2_re <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd37))) begin
-		builder_csrbank2_dfii_pi2_rddata2_we <= (~builder_interface2_bank_bus_we);
+		builder_csrbank2_dfii_pi2_rddata2_re <= builder_interface2_bank_bus_we;
 	end
 // synthesis translate_off
 	dummy_d_416 = dummy_s;
@@ -13285,9 +13285,9 @@ assign builder_csrbank2_dfii_pi2_rddata0_r = builder_interface2_bank_bus_dat_w[7
 reg dummy_d_419;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi2_rddata0_we <= 1'd0;
+	builder_csrbank2_dfii_pi2_rddata0_re <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd39))) begin
-		builder_csrbank2_dfii_pi2_rddata0_we <= (~builder_interface2_bank_bus_we);
+		builder_csrbank2_dfii_pi2_rddata0_re <= builder_interface2_bank_bus_we;
 	end
 // synthesis translate_off
 	dummy_d_419 = dummy_s;
@@ -13298,9 +13298,9 @@ end
 reg dummy_d_420;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi2_rddata0_re <= 1'd0;
+	builder_csrbank2_dfii_pi2_rddata0_we <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd39))) begin
-		builder_csrbank2_dfii_pi2_rddata0_re <= builder_interface2_bank_bus_we;
+		builder_csrbank2_dfii_pi2_rddata0_we <= (~builder_interface2_bank_bus_we);
 	end
 // synthesis translate_off
 	dummy_d_420 = dummy_s;
@@ -13339,9 +13339,9 @@ assign main_litedramcore_phaseinjector3_command_issue_r = builder_interface2_ban
 reg dummy_d_423;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_phaseinjector3_command_issue_re <= 1'd0;
+	main_litedramcore_phaseinjector3_command_issue_we <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd41))) begin
-		main_litedramcore_phaseinjector3_command_issue_re <= builder_interface2_bank_bus_we;
+		main_litedramcore_phaseinjector3_command_issue_we <= (~builder_interface2_bank_bus_we);
 	end
 // synthesis translate_off
 	dummy_d_423 = dummy_s;
@@ -13352,9 +13352,9 @@ end
 reg dummy_d_424;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_phaseinjector3_command_issue_we <= 1'd0;
+	main_litedramcore_phaseinjector3_command_issue_re <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd41))) begin
-		main_litedramcore_phaseinjector3_command_issue_we <= (~builder_interface2_bank_bus_we);
+		main_litedramcore_phaseinjector3_command_issue_re <= builder_interface2_bank_bus_we;
 	end
 // synthesis translate_off
 	dummy_d_424 = dummy_s;
@@ -13393,9 +13393,9 @@ assign builder_csrbank2_dfii_pi3_address0_r = builder_interface2_bank_bus_dat_w[
 reg dummy_d_427;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi3_address0_we <= 1'd0;
+	builder_csrbank2_dfii_pi3_address0_re <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd43))) begin
-		builder_csrbank2_dfii_pi3_address0_we <= (~builder_interface2_bank_bus_we);
+		builder_csrbank2_dfii_pi3_address0_re <= builder_interface2_bank_bus_we;
 	end
 // synthesis translate_off
 	dummy_d_427 = dummy_s;
@@ -13406,9 +13406,9 @@ end
 reg dummy_d_428;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi3_address0_re <= 1'd0;
+	builder_csrbank2_dfii_pi3_address0_we <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd43))) begin
-		builder_csrbank2_dfii_pi3_address0_re <= builder_interface2_bank_bus_we;
+		builder_csrbank2_dfii_pi3_address0_we <= (~builder_interface2_bank_bus_we);
 	end
 // synthesis translate_off
 	dummy_d_428 = dummy_s;
@@ -13501,9 +13501,9 @@ assign builder_csrbank2_dfii_pi3_wrdata1_r = builder_interface2_bank_bus_dat_w[7
 reg dummy_d_435;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi3_wrdata1_re <= 1'd0;
+	builder_csrbank2_dfii_pi3_wrdata1_we <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd47))) begin
-		builder_csrbank2_dfii_pi3_wrdata1_re <= builder_interface2_bank_bus_we;
+		builder_csrbank2_dfii_pi3_wrdata1_we <= (~builder_interface2_bank_bus_we);
 	end
 // synthesis translate_off
 	dummy_d_435 = dummy_s;
@@ -13514,9 +13514,9 @@ end
 reg dummy_d_436;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi3_wrdata1_we <= 1'd0;
+	builder_csrbank2_dfii_pi3_wrdata1_re <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd47))) begin
-		builder_csrbank2_dfii_pi3_wrdata1_we <= (~builder_interface2_bank_bus_we);
+		builder_csrbank2_dfii_pi3_wrdata1_re <= builder_interface2_bank_bus_we;
 	end
 // synthesis translate_off
 	dummy_d_436 = dummy_s;
@@ -13582,9 +13582,9 @@ assign builder_csrbank2_dfii_pi3_rddata2_r = builder_interface2_bank_bus_dat_w[7
 reg dummy_d_441;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi3_rddata2_re <= 1'd0;
+	builder_csrbank2_dfii_pi3_rddata2_we <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd50))) begin
-		builder_csrbank2_dfii_pi3_rddata2_re <= builder_interface2_bank_bus_we;
+		builder_csrbank2_dfii_pi3_rddata2_we <= (~builder_interface2_bank_bus_we);
 	end
 // synthesis translate_off
 	dummy_d_441 = dummy_s;
@@ -13595,9 +13595,9 @@ end
 reg dummy_d_442;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi3_rddata2_we <= 1'd0;
+	builder_csrbank2_dfii_pi3_rddata2_re <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd50))) begin
-		builder_csrbank2_dfii_pi3_rddata2_we <= (~builder_interface2_bank_bus_we);
+		builder_csrbank2_dfii_pi3_rddata2_re <= builder_interface2_bank_bus_we;
 	end
 // synthesis translate_off
 	dummy_d_442 = dummy_s;
@@ -13636,9 +13636,9 @@ assign builder_csrbank2_dfii_pi3_rddata0_r = builder_interface2_bank_bus_dat_w[7
 reg dummy_d_445;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi3_rddata0_we <= 1'd0;
+	builder_csrbank2_dfii_pi3_rddata0_re <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd52))) begin
-		builder_csrbank2_dfii_pi3_rddata0_we <= (~builder_interface2_bank_bus_we);
+		builder_csrbank2_dfii_pi3_rddata0_re <= builder_interface2_bank_bus_we;
 	end
 // synthesis translate_off
 	dummy_d_445 = dummy_s;
@@ -13649,9 +13649,9 @@ end
 reg dummy_d_446;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi3_rddata0_re <= 1'd0;
+	builder_csrbank2_dfii_pi3_rddata0_we <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd52))) begin
-		builder_csrbank2_dfii_pi3_rddata0_re <= builder_interface2_bank_bus_we;
+		builder_csrbank2_dfii_pi3_rddata0_we <= (~builder_interface2_bank_bus_we);
 	end
 // synthesis translate_off
 	dummy_d_446 = dummy_s;
diff --git a/litedram/generated/genesys2/litedram_core.init b/litedram/generated/genesys2/litedram_core.init
index 6f5084f..6b2631b 100644
--- a/litedram/generated/genesys2/litedram_core.init
+++ b/litedram/generated/genesys2/litedram_core.init
@@ -7,7 +7,7 @@ a64b5a7d14004a39
 6421ff00782107c6
 3d80000060215f00
 798c07c6618c0000
-618c10d8658cff00
+618c10e0658cff00
 4e8004217d8903a6
 4e8004207c6903a6
 0000000000000000
@@ -518,81 +518,82 @@ a64b5a7d14004a39
 4e80002060000000
 0000000000000000
 3c4c000100000000
-7c0802a63842bbc4
-f8010010fbe1fff8
-f88100d8f821ff51
+7c0802a63842bcc4
+fbe1fff8fbc1fff0
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+f88100d83bc10020
 38800080f8a100e0
 f8c100e87c651b78
-38c100d838610020
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 f90100f8f8e100f0
 f9410108f9210100
-6000000048002f71
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-600000004800298d
+6000000048002fc5
+7fc3f3787c7f1b78
+60000000480029d1
 7fe3fb78382100b0
-0000000048003554
-0000018001000000
+00000000480035bc
+0000028001000000
 000000004e800020
 0000000000000000
 4c00012c7c0007ac
 000000004e800020
 0000000000000000
-3842bb283c4c0001
+3842bc203c4c0001
 7d8000267c0802a6
-9181000848003491
-48002989f821fed1
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+480029cdf821fed1
 3c62ffff60000000
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 788400203c80c000
 7c8026ea7c0004ac
 3fe0c0003c62ffff
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 73e900017fe0feea
 3c62ffff41820010
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 4e00000073e90002
 3c62ffff41820010
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 4d80000073e90004
 3c62ffff41820010
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 4d00000073e90008
 3c62ffff41820010
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 4182001073e90010
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 3c62ffff41820010
-4bfffe8138637a98
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+4bfffe7938637a08
+3b7b7a103f62ffff
+4bfffe697f63db78
 3c80c000418e0028
 7884002060840010
 7c8026ea7c0004ac
 7884b5823c62ffff
-4bfffe4938637aa8
+4bfffe4138637a18
 3c80c0004192004c
 7884002060840018
 7c8026ea7c0004ac
 788460223c62ffff
-4bfffe2138637ac0
+4bfffe1938637a30
 608400303c80c000
 7c0004ac78840020
 3c62ffff7c8026ea
-38637ad87884b282
-3d20c0004bfffdfd
+38637a487884b282
+3d20c0004bfffdf5
 7929002061290020
 7d204eea7c0004ac
 792906003c80000f
 3c62ffff60844240
-38637af07c892392
-418a02584bfffdcd
-63de00383fc0c000
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-3d40c0007fc0f6ea
+38637a607c892392
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+63bd00383fa0c000
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+3d40c0007fa0eeea
 614a600439200002
 7c0004ac794a0020
 3fe0c0007d2057aa
@@ -600,1645 +601,1658 @@ f9410108f9210100
 7c0004ac7bff0020
 7c0004ac7d20ffaa
 579c063e7f80feaa
-7fa0feaa7c0004ac
-7c0004ac57bd063e
-4bfffd1d7fe0feaa
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+4bfffd157fe0feaa
 3c62ffff57ff063e
-7fa5eb787fe6fb78
-38637b107f84e378
-7f89eb784bfffd45
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 2c0900007d29fb78
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 2c0900ff7d29f838
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 7d20ffaa7c0004ac
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diff --git a/litedram/generated/genesys2/litedram_core.v b/litedram/generated/genesys2/litedram_core.v
index b25cf01..edd354a 100644
--- a/litedram/generated/genesys2/litedram_core.v
+++ b/litedram/generated/genesys2/litedram_core.v
@@ -1,5 +1,5 @@
 //--------------------------------------------------------------------------------
-// Auto-generated by Migen (27dbf03) & LiteX (78c1751c) on 2021-08-15 06:19:14
+// Auto-generated by Migen (a5bc262) & LiteX (de028765) on 2021-09-24 12:36:35
 //--------------------------------------------------------------------------------
 module litedram_core(
 	input wire clk,
@@ -5519,6 +5519,21 @@ assign main_litedramcore_dfi_p3_rddata_valid = main_litedramcore_slave_p3_rddata
 // synthesis translate_off
 reg dummy_d_78;
 // synthesis translate_on
+always @(*) begin
+	main_litedramcore_master_p0_rddata_en <= 1'd0;
+	if (main_litedramcore_sel) begin
+		main_litedramcore_master_p0_rddata_en <= main_litedramcore_slave_p0_rddata_en;
+	end else begin
+		main_litedramcore_master_p0_rddata_en <= main_litedramcore_inti_p0_rddata_en;
+	end
+// synthesis translate_off
+	dummy_d_78 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_79;
+// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p1_address <= 15'd0;
 	if (main_litedramcore_sel) begin
@@ -5527,12 +5542,12 @@ always @(*) begin
 		main_litedramcore_master_p1_address <= main_litedramcore_inti_p1_address;
 	end
 // synthesis translate_off
-	dummy_d_78 = dummy_s;
+	dummy_d_79 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_79;
+reg dummy_d_80;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p1_bank <= 3'd0;
@@ -5542,12 +5557,12 @@ always @(*) begin
 		main_litedramcore_master_p1_bank <= main_litedramcore_inti_p1_bank;
 	end
 // synthesis translate_off
-	dummy_d_79 = dummy_s;
+	dummy_d_80 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_80;
+reg dummy_d_81;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p1_cas_n <= 1'd1;
@@ -5557,12 +5572,12 @@ always @(*) begin
 		main_litedramcore_master_p1_cas_n <= main_litedramcore_inti_p1_cas_n;
 	end
 // synthesis translate_off
-	dummy_d_80 = dummy_s;
+	dummy_d_81 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_81;
+reg dummy_d_82;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p1_cs_n <= 1'd1;
@@ -5572,12 +5587,12 @@ always @(*) begin
 		main_litedramcore_master_p1_cs_n <= main_litedramcore_inti_p1_cs_n;
 	end
 // synthesis translate_off
-	dummy_d_81 = dummy_s;
+	dummy_d_82 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_82;
+reg dummy_d_83;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p1_ras_n <= 1'd1;
@@ -5587,12 +5602,12 @@ always @(*) begin
 		main_litedramcore_master_p1_ras_n <= main_litedramcore_inti_p1_ras_n;
 	end
 // synthesis translate_off
-	dummy_d_82 = dummy_s;
+	dummy_d_83 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_83;
+reg dummy_d_84;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_slave_p1_rddata <= 64'd0;
@@ -5601,12 +5616,12 @@ always @(*) begin
 	end else begin
 	end
 // synthesis translate_off
-	dummy_d_83 = dummy_s;
+	dummy_d_84 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_84;
+reg dummy_d_85;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p1_we_n <= 1'd1;
@@ -5616,12 +5631,12 @@ always @(*) begin
 		main_litedramcore_master_p1_we_n <= main_litedramcore_inti_p1_we_n;
 	end
 // synthesis translate_off
-	dummy_d_84 = dummy_s;
+	dummy_d_85 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_85;
+reg dummy_d_86;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_slave_p1_rddata_valid <= 1'd0;
@@ -5630,12 +5645,12 @@ always @(*) begin
 	end else begin
 	end
 // synthesis translate_off
-	dummy_d_85 = dummy_s;
+	dummy_d_86 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_86;
+reg dummy_d_87;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p1_cke <= 1'd0;
@@ -5645,12 +5660,12 @@ always @(*) begin
 		main_litedramcore_master_p1_cke <= main_litedramcore_inti_p1_cke;
 	end
 // synthesis translate_off
-	dummy_d_86 = dummy_s;
+	dummy_d_87 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_87;
+reg dummy_d_88;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p1_odt <= 1'd0;
@@ -5660,12 +5675,12 @@ always @(*) begin
 		main_litedramcore_master_p1_odt <= main_litedramcore_inti_p1_odt;
 	end
 // synthesis translate_off
-	dummy_d_87 = dummy_s;
+	dummy_d_88 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_88;
+reg dummy_d_89;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p1_reset_n <= 1'd0;
@@ -5675,12 +5690,12 @@ always @(*) begin
 		main_litedramcore_master_p1_reset_n <= main_litedramcore_inti_p1_reset_n;
 	end
 // synthesis translate_off
-	dummy_d_88 = dummy_s;
+	dummy_d_89 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_89;
+reg dummy_d_90;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p1_act_n <= 1'd1;
@@ -5690,12 +5705,12 @@ always @(*) begin
 		main_litedramcore_master_p1_act_n <= main_litedramcore_inti_p1_act_n;
 	end
 // synthesis translate_off
-	dummy_d_89 = dummy_s;
+	dummy_d_90 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_90;
+reg dummy_d_91;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p1_wrdata <= 64'd0;
@@ -5705,12 +5720,12 @@ always @(*) begin
 		main_litedramcore_master_p1_wrdata <= main_litedramcore_inti_p1_wrdata;
 	end
 // synthesis translate_off
-	dummy_d_90 = dummy_s;
+	dummy_d_91 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_91;
+reg dummy_d_92;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_inti_p2_rddata <= 64'd0;
@@ -5719,12 +5734,12 @@ always @(*) begin
 		main_litedramcore_inti_p2_rddata <= main_litedramcore_master_p2_rddata;
 	end
 // synthesis translate_off
-	dummy_d_91 = dummy_s;
+	dummy_d_92 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_92;
+reg dummy_d_93;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p1_wrdata_en <= 1'd0;
@@ -5734,12 +5749,12 @@ always @(*) begin
 		main_litedramcore_master_p1_wrdata_en <= main_litedramcore_inti_p1_wrdata_en;
 	end
 // synthesis translate_off
-	dummy_d_92 = dummy_s;
+	dummy_d_93 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_93;
+reg dummy_d_94;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_inti_p2_rddata_valid <= 1'd0;
@@ -5748,12 +5763,12 @@ always @(*) begin
 		main_litedramcore_inti_p2_rddata_valid <= main_litedramcore_master_p2_rddata_valid;
 	end
 // synthesis translate_off
-	dummy_d_93 = dummy_s;
+	dummy_d_94 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_94;
+reg dummy_d_95;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p1_wrdata_mask <= 8'd0;
@@ -5763,12 +5778,12 @@ always @(*) begin
 		main_litedramcore_master_p1_wrdata_mask <= main_litedramcore_inti_p1_wrdata_mask;
 	end
 // synthesis translate_off
-	dummy_d_94 = dummy_s;
+	dummy_d_95 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_95;
+reg dummy_d_96;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p1_rddata_en <= 1'd0;
@@ -5778,12 +5793,12 @@ always @(*) begin
 		main_litedramcore_master_p1_rddata_en <= main_litedramcore_inti_p1_rddata_en;
 	end
 // synthesis translate_off
-	dummy_d_95 = dummy_s;
+	dummy_d_96 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_96;
+reg dummy_d_97;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p2_address <= 15'd0;
@@ -5793,12 +5808,12 @@ always @(*) begin
 		main_litedramcore_master_p2_address <= main_litedramcore_inti_p2_address;
 	end
 // synthesis translate_off
-	dummy_d_96 = dummy_s;
+	dummy_d_97 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_97;
+reg dummy_d_98;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p2_bank <= 3'd0;
@@ -5808,12 +5823,12 @@ always @(*) begin
 		main_litedramcore_master_p2_bank <= main_litedramcore_inti_p2_bank;
 	end
 // synthesis translate_off
-	dummy_d_97 = dummy_s;
+	dummy_d_98 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_98;
+reg dummy_d_99;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p2_cas_n <= 1'd1;
@@ -5823,12 +5838,12 @@ always @(*) begin
 		main_litedramcore_master_p2_cas_n <= main_litedramcore_inti_p2_cas_n;
 	end
 // synthesis translate_off
-	dummy_d_98 = dummy_s;
+	dummy_d_99 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_99;
+reg dummy_d_100;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p2_cs_n <= 1'd1;
@@ -5838,12 +5853,12 @@ always @(*) begin
 		main_litedramcore_master_p2_cs_n <= main_litedramcore_inti_p2_cs_n;
 	end
 // synthesis translate_off
-	dummy_d_99 = dummy_s;
+	dummy_d_100 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_100;
+reg dummy_d_101;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p2_ras_n <= 1'd1;
@@ -5853,12 +5868,12 @@ always @(*) begin
 		main_litedramcore_master_p2_ras_n <= main_litedramcore_inti_p2_ras_n;
 	end
 // synthesis translate_off
-	dummy_d_100 = dummy_s;
+	dummy_d_101 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_101;
+reg dummy_d_102;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_slave_p2_rddata <= 64'd0;
@@ -5867,12 +5882,12 @@ always @(*) begin
 	end else begin
 	end
 // synthesis translate_off
-	dummy_d_101 = dummy_s;
+	dummy_d_102 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_102;
+reg dummy_d_103;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p2_we_n <= 1'd1;
@@ -5882,12 +5897,12 @@ always @(*) begin
 		main_litedramcore_master_p2_we_n <= main_litedramcore_inti_p2_we_n;
 	end
 // synthesis translate_off
-	dummy_d_102 = dummy_s;
+	dummy_d_103 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_103;
+reg dummy_d_104;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_slave_p2_rddata_valid <= 1'd0;
@@ -5896,12 +5911,12 @@ always @(*) begin
 	end else begin
 	end
 // synthesis translate_off
-	dummy_d_103 = dummy_s;
+	dummy_d_104 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_104;
+reg dummy_d_105;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p2_cke <= 1'd0;
@@ -5911,12 +5926,12 @@ always @(*) begin
 		main_litedramcore_master_p2_cke <= main_litedramcore_inti_p2_cke;
 	end
 // synthesis translate_off
-	dummy_d_104 = dummy_s;
+	dummy_d_105 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_105;
+reg dummy_d_106;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p2_odt <= 1'd0;
@@ -5926,12 +5941,12 @@ always @(*) begin
 		main_litedramcore_master_p2_odt <= main_litedramcore_inti_p2_odt;
 	end
 // synthesis translate_off
-	dummy_d_105 = dummy_s;
+	dummy_d_106 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_106;
+reg dummy_d_107;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p2_reset_n <= 1'd0;
@@ -5941,12 +5956,12 @@ always @(*) begin
 		main_litedramcore_master_p2_reset_n <= main_litedramcore_inti_p2_reset_n;
 	end
 // synthesis translate_off
-	dummy_d_106 = dummy_s;
+	dummy_d_107 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_107;
+reg dummy_d_108;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p2_act_n <= 1'd1;
@@ -5956,12 +5971,12 @@ always @(*) begin
 		main_litedramcore_master_p2_act_n <= main_litedramcore_inti_p2_act_n;
 	end
 // synthesis translate_off
-	dummy_d_107 = dummy_s;
+	dummy_d_108 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_108;
+reg dummy_d_109;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p2_wrdata <= 64'd0;
@@ -5971,12 +5986,12 @@ always @(*) begin
 		main_litedramcore_master_p2_wrdata <= main_litedramcore_inti_p2_wrdata;
 	end
 // synthesis translate_off
-	dummy_d_108 = dummy_s;
+	dummy_d_109 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_109;
+reg dummy_d_110;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_inti_p3_rddata <= 64'd0;
@@ -5985,12 +6000,12 @@ always @(*) begin
 		main_litedramcore_inti_p3_rddata <= main_litedramcore_master_p3_rddata;
 	end
 // synthesis translate_off
-	dummy_d_109 = dummy_s;
+	dummy_d_110 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_110;
+reg dummy_d_111;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p2_wrdata_en <= 1'd0;
@@ -6000,12 +6015,12 @@ always @(*) begin
 		main_litedramcore_master_p2_wrdata_en <= main_litedramcore_inti_p2_wrdata_en;
 	end
 // synthesis translate_off
-	dummy_d_110 = dummy_s;
+	dummy_d_111 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_111;
+reg dummy_d_112;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_inti_p3_rddata_valid <= 1'd0;
@@ -6014,12 +6029,12 @@ always @(*) begin
 		main_litedramcore_inti_p3_rddata_valid <= main_litedramcore_master_p3_rddata_valid;
 	end
 // synthesis translate_off
-	dummy_d_111 = dummy_s;
+	dummy_d_112 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_112;
+reg dummy_d_113;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p2_wrdata_mask <= 8'd0;
@@ -6029,12 +6044,12 @@ always @(*) begin
 		main_litedramcore_master_p2_wrdata_mask <= main_litedramcore_inti_p2_wrdata_mask;
 	end
 // synthesis translate_off
-	dummy_d_112 = dummy_s;
+	dummy_d_113 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_113;
+reg dummy_d_114;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p2_rddata_en <= 1'd0;
@@ -6044,12 +6059,12 @@ always @(*) begin
 		main_litedramcore_master_p2_rddata_en <= main_litedramcore_inti_p2_rddata_en;
 	end
 // synthesis translate_off
-	dummy_d_113 = dummy_s;
+	dummy_d_114 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_114;
+reg dummy_d_115;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p3_address <= 15'd0;
@@ -6059,12 +6074,12 @@ always @(*) begin
 		main_litedramcore_master_p3_address <= main_litedramcore_inti_p3_address;
 	end
 // synthesis translate_off
-	dummy_d_114 = dummy_s;
+	dummy_d_115 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_115;
+reg dummy_d_116;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p3_bank <= 3'd0;
@@ -6074,12 +6089,12 @@ always @(*) begin
 		main_litedramcore_master_p3_bank <= main_litedramcore_inti_p3_bank;
 	end
 // synthesis translate_off
-	dummy_d_115 = dummy_s;
+	dummy_d_116 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_116;
+reg dummy_d_117;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p3_cas_n <= 1'd1;
@@ -6089,12 +6104,12 @@ always @(*) begin
 		main_litedramcore_master_p3_cas_n <= main_litedramcore_inti_p3_cas_n;
 	end
 // synthesis translate_off
-	dummy_d_116 = dummy_s;
+	dummy_d_117 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_117;
+reg dummy_d_118;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p3_cs_n <= 1'd1;
@@ -6104,12 +6119,12 @@ always @(*) begin
 		main_litedramcore_master_p3_cs_n <= main_litedramcore_inti_p3_cs_n;
 	end
 // synthesis translate_off
-	dummy_d_117 = dummy_s;
+	dummy_d_118 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_118;
+reg dummy_d_119;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p3_ras_n <= 1'd1;
@@ -6119,12 +6134,12 @@ always @(*) begin
 		main_litedramcore_master_p3_ras_n <= main_litedramcore_inti_p3_ras_n;
 	end
 // synthesis translate_off
-	dummy_d_118 = dummy_s;
+	dummy_d_119 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_119;
+reg dummy_d_120;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_slave_p3_rddata <= 64'd0;
@@ -6133,12 +6148,12 @@ always @(*) begin
 	end else begin
 	end
 // synthesis translate_off
-	dummy_d_119 = dummy_s;
+	dummy_d_120 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_120;
+reg dummy_d_121;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p3_we_n <= 1'd1;
@@ -6148,12 +6163,12 @@ always @(*) begin
 		main_litedramcore_master_p3_we_n <= main_litedramcore_inti_p3_we_n;
 	end
 // synthesis translate_off
-	dummy_d_120 = dummy_s;
+	dummy_d_121 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_121;
+reg dummy_d_122;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_slave_p3_rddata_valid <= 1'd0;
@@ -6162,12 +6177,12 @@ always @(*) begin
 	end else begin
 	end
 // synthesis translate_off
-	dummy_d_121 = dummy_s;
+	dummy_d_122 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_122;
+reg dummy_d_123;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p3_cke <= 1'd0;
@@ -6176,20 +6191,6 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p3_cke <= main_litedramcore_inti_p3_cke;
 	end
-// synthesis translate_off
-	dummy_d_122 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_123;
-// synthesis translate_on
-always @(*) begin
-	main_litedramcore_inti_p1_rddata <= 64'd0;
-	if (main_litedramcore_sel) begin
-	end else begin
-		main_litedramcore_inti_p1_rddata <= main_litedramcore_master_p1_rddata;
-	end
 // synthesis translate_off
 	dummy_d_123 = dummy_s;
 // synthesis translate_on
@@ -6317,10 +6318,10 @@ end
 reg dummy_d_132;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_inti_p1_rddata_valid <= 1'd0;
+	main_litedramcore_inti_p1_rddata <= 64'd0;
 	if (main_litedramcore_sel) begin
 	end else begin
-		main_litedramcore_inti_p1_rddata_valid <= main_litedramcore_master_p1_rddata_valid;
+		main_litedramcore_inti_p1_rddata <= main_litedramcore_master_p1_rddata;
 	end
 // synthesis translate_off
 	dummy_d_132 = dummy_s;
@@ -6345,6 +6346,20 @@ end
 // synthesis translate_off
 reg dummy_d_134;
 // synthesis translate_on
+always @(*) begin
+	main_litedramcore_inti_p1_rddata_valid <= 1'd0;
+	if (main_litedramcore_sel) begin
+	end else begin
+		main_litedramcore_inti_p1_rddata_valid <= main_litedramcore_master_p1_rddata_valid;
+	end
+// synthesis translate_off
+	dummy_d_134 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_135;
+// synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p0_address <= 15'd0;
 	if (main_litedramcore_sel) begin
@@ -6353,12 +6368,12 @@ always @(*) begin
 		main_litedramcore_master_p0_address <= main_litedramcore_inti_p0_address;
 	end
 // synthesis translate_off
-	dummy_d_134 = dummy_s;
+	dummy_d_135 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_135;
+reg dummy_d_136;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p0_bank <= 3'd0;
@@ -6368,12 +6383,12 @@ always @(*) begin
 		main_litedramcore_master_p0_bank <= main_litedramcore_inti_p0_bank;
 	end
 // synthesis translate_off
-	dummy_d_135 = dummy_s;
+	dummy_d_136 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_136;
+reg dummy_d_137;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p0_cas_n <= 1'd1;
@@ -6383,12 +6398,12 @@ always @(*) begin
 		main_litedramcore_master_p0_cas_n <= main_litedramcore_inti_p0_cas_n;
 	end
 // synthesis translate_off
-	dummy_d_136 = dummy_s;
+	dummy_d_137 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_137;
+reg dummy_d_138;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p0_cs_n <= 1'd1;
@@ -6398,12 +6413,12 @@ always @(*) begin
 		main_litedramcore_master_p0_cs_n <= main_litedramcore_inti_p0_cs_n;
 	end
 // synthesis translate_off
-	dummy_d_137 = dummy_s;
+	dummy_d_138 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_138;
+reg dummy_d_139;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p0_ras_n <= 1'd1;
@@ -6413,12 +6428,12 @@ always @(*) begin
 		main_litedramcore_master_p0_ras_n <= main_litedramcore_inti_p0_ras_n;
 	end
 // synthesis translate_off
-	dummy_d_138 = dummy_s;
+	dummy_d_139 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_139;
+reg dummy_d_140;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_slave_p0_rddata <= 64'd0;
@@ -6427,12 +6442,12 @@ always @(*) begin
 	end else begin
 	end
 // synthesis translate_off
-	dummy_d_139 = dummy_s;
+	dummy_d_140 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_140;
+reg dummy_d_141;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p0_we_n <= 1'd1;
@@ -6442,12 +6457,12 @@ always @(*) begin
 		main_litedramcore_master_p0_we_n <= main_litedramcore_inti_p0_we_n;
 	end
 // synthesis translate_off
-	dummy_d_140 = dummy_s;
+	dummy_d_141 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_141;
+reg dummy_d_142;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_slave_p0_rddata_valid <= 1'd0;
@@ -6456,12 +6471,12 @@ always @(*) begin
 	end else begin
 	end
 // synthesis translate_off
-	dummy_d_141 = dummy_s;
+	dummy_d_142 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_142;
+reg dummy_d_143;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p0_cke <= 1'd0;
@@ -6471,12 +6486,12 @@ always @(*) begin
 		main_litedramcore_master_p0_cke <= main_litedramcore_inti_p0_cke;
 	end
 // synthesis translate_off
-	dummy_d_142 = dummy_s;
+	dummy_d_143 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_143;
+reg dummy_d_144;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p0_odt <= 1'd0;
@@ -6486,12 +6501,12 @@ always @(*) begin
 		main_litedramcore_master_p0_odt <= main_litedramcore_inti_p0_odt;
 	end
 // synthesis translate_off
-	dummy_d_143 = dummy_s;
+	dummy_d_144 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_144;
+reg dummy_d_145;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p0_reset_n <= 1'd0;
@@ -6501,12 +6516,12 @@ always @(*) begin
 		main_litedramcore_master_p0_reset_n <= main_litedramcore_inti_p0_reset_n;
 	end
 // synthesis translate_off
-	dummy_d_144 = dummy_s;
+	dummy_d_145 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_145;
+reg dummy_d_146;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p0_act_n <= 1'd1;
@@ -6516,12 +6531,12 @@ always @(*) begin
 		main_litedramcore_master_p0_act_n <= main_litedramcore_inti_p0_act_n;
 	end
 // synthesis translate_off
-	dummy_d_145 = dummy_s;
+	dummy_d_146 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_146;
+reg dummy_d_147;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p0_wrdata <= 64'd0;
@@ -6531,12 +6546,12 @@ always @(*) begin
 		main_litedramcore_master_p0_wrdata <= main_litedramcore_inti_p0_wrdata;
 	end
 // synthesis translate_off
-	dummy_d_146 = dummy_s;
+	dummy_d_147 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_147;
+reg dummy_d_148;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p0_wrdata_en <= 1'd0;
@@ -6546,12 +6561,12 @@ always @(*) begin
 		main_litedramcore_master_p0_wrdata_en <= main_litedramcore_inti_p0_wrdata_en;
 	end
 // synthesis translate_off
-	dummy_d_147 = dummy_s;
+	dummy_d_148 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_148;
+reg dummy_d_149;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_master_p0_wrdata_mask <= 8'd0;
@@ -6560,21 +6575,6 @@ always @(*) begin
 	end else begin
 		main_litedramcore_master_p0_wrdata_mask <= main_litedramcore_inti_p0_wrdata_mask;
 	end
-// synthesis translate_off
-	dummy_d_148 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_149;
-// synthesis translate_on
-always @(*) begin
-	main_litedramcore_master_p0_rddata_en <= 1'd0;
-	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p0_rddata_en <= main_litedramcore_slave_p0_rddata_en;
-	end else begin
-		main_litedramcore_master_p0_rddata_en <= main_litedramcore_inti_p0_rddata_en;
-	end
 // synthesis translate_off
 	dummy_d_149 = dummy_s;
 // synthesis translate_on
@@ -6596,11 +6596,11 @@ assign main_litedramcore_inti_p3_reset_n = main_litedramcore_reset_n;
 reg dummy_d_150;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_inti_p0_cas_n <= 1'd1;
+	main_litedramcore_inti_p0_we_n <= 1'd1;
 	if (main_litedramcore_phaseinjector0_command_issue_re) begin
-		main_litedramcore_inti_p0_cas_n <= (~main_litedramcore_phaseinjector0_command_storage[2]);
+		main_litedramcore_inti_p0_we_n <= (~main_litedramcore_phaseinjector0_command_storage[1]);
 	end else begin
-		main_litedramcore_inti_p0_cas_n <= 1'd1;
+		main_litedramcore_inti_p0_we_n <= 1'd1;
 	end
 // synthesis translate_off
 	dummy_d_150 = dummy_s;
@@ -6611,11 +6611,11 @@ end
 reg dummy_d_151;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_inti_p0_cs_n <= 1'd1;
+	main_litedramcore_inti_p0_cas_n <= 1'd1;
 	if (main_litedramcore_phaseinjector0_command_issue_re) begin
-		main_litedramcore_inti_p0_cs_n <= {1{(~main_litedramcore_phaseinjector0_command_storage[0])}};
+		main_litedramcore_inti_p0_cas_n <= (~main_litedramcore_phaseinjector0_command_storage[2]);
 	end else begin
-		main_litedramcore_inti_p0_cs_n <= {1{1'd1}};
+		main_litedramcore_inti_p0_cas_n <= 1'd1;
 	end
 // synthesis translate_off
 	dummy_d_151 = dummy_s;
@@ -6626,11 +6626,11 @@ end
 reg dummy_d_152;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_inti_p0_ras_n <= 1'd1;
+	main_litedramcore_inti_p0_cs_n <= 1'd1;
 	if (main_litedramcore_phaseinjector0_command_issue_re) begin
-		main_litedramcore_inti_p0_ras_n <= (~main_litedramcore_phaseinjector0_command_storage[3]);
+		main_litedramcore_inti_p0_cs_n <= {1{(~main_litedramcore_phaseinjector0_command_storage[0])}};
 	end else begin
-		main_litedramcore_inti_p0_ras_n <= 1'd1;
+		main_litedramcore_inti_p0_cs_n <= {1{1'd1}};
 	end
 // synthesis translate_off
 	dummy_d_152 = dummy_s;
@@ -6641,11 +6641,11 @@ end
 reg dummy_d_153;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_inti_p0_we_n <= 1'd1;
+	main_litedramcore_inti_p0_ras_n <= 1'd1;
 	if (main_litedramcore_phaseinjector0_command_issue_re) begin
-		main_litedramcore_inti_p0_we_n <= (~main_litedramcore_phaseinjector0_command_storage[1]);
+		main_litedramcore_inti_p0_ras_n <= (~main_litedramcore_phaseinjector0_command_storage[3]);
 	end else begin
-		main_litedramcore_inti_p0_we_n <= 1'd1;
+		main_litedramcore_inti_p0_ras_n <= 1'd1;
 	end
 // synthesis translate_off
 	dummy_d_153 = dummy_s;
@@ -6662,11 +6662,11 @@ assign main_litedramcore_inti_p0_wrdata_mask = 1'd0;
 reg dummy_d_154;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_inti_p1_cas_n <= 1'd1;
+	main_litedramcore_inti_p1_we_n <= 1'd1;
 	if (main_litedramcore_phaseinjector1_command_issue_re) begin
-		main_litedramcore_inti_p1_cas_n <= (~main_litedramcore_phaseinjector1_command_storage[2]);
+		main_litedramcore_inti_p1_we_n <= (~main_litedramcore_phaseinjector1_command_storage[1]);
 	end else begin
-		main_litedramcore_inti_p1_cas_n <= 1'd1;
+		main_litedramcore_inti_p1_we_n <= 1'd1;
 	end
 // synthesis translate_off
 	dummy_d_154 = dummy_s;
@@ -6677,11 +6677,11 @@ end
 reg dummy_d_155;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_inti_p1_cs_n <= 1'd1;
+	main_litedramcore_inti_p1_cas_n <= 1'd1;
 	if (main_litedramcore_phaseinjector1_command_issue_re) begin
-		main_litedramcore_inti_p1_cs_n <= {1{(~main_litedramcore_phaseinjector1_command_storage[0])}};
+		main_litedramcore_inti_p1_cas_n <= (~main_litedramcore_phaseinjector1_command_storage[2]);
 	end else begin
-		main_litedramcore_inti_p1_cs_n <= {1{1'd1}};
+		main_litedramcore_inti_p1_cas_n <= 1'd1;
 	end
 // synthesis translate_off
 	dummy_d_155 = dummy_s;
@@ -6692,11 +6692,11 @@ end
 reg dummy_d_156;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_inti_p1_ras_n <= 1'd1;
+	main_litedramcore_inti_p1_cs_n <= 1'd1;
 	if (main_litedramcore_phaseinjector1_command_issue_re) begin
-		main_litedramcore_inti_p1_ras_n <= (~main_litedramcore_phaseinjector1_command_storage[3]);
+		main_litedramcore_inti_p1_cs_n <= {1{(~main_litedramcore_phaseinjector1_command_storage[0])}};
 	end else begin
-		main_litedramcore_inti_p1_ras_n <= 1'd1;
+		main_litedramcore_inti_p1_cs_n <= {1{1'd1}};
 	end
 // synthesis translate_off
 	dummy_d_156 = dummy_s;
@@ -6707,11 +6707,11 @@ end
 reg dummy_d_157;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_inti_p1_we_n <= 1'd1;
+	main_litedramcore_inti_p1_ras_n <= 1'd1;
 	if (main_litedramcore_phaseinjector1_command_issue_re) begin
-		main_litedramcore_inti_p1_we_n <= (~main_litedramcore_phaseinjector1_command_storage[1]);
+		main_litedramcore_inti_p1_ras_n <= (~main_litedramcore_phaseinjector1_command_storage[3]);
 	end else begin
-		main_litedramcore_inti_p1_we_n <= 1'd1;
+		main_litedramcore_inti_p1_ras_n <= 1'd1;
 	end
 // synthesis translate_off
 	dummy_d_157 = dummy_s;
@@ -6728,11 +6728,11 @@ assign main_litedramcore_inti_p1_wrdata_mask = 1'd0;
 reg dummy_d_158;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_inti_p2_cas_n <= 1'd1;
+	main_litedramcore_inti_p2_we_n <= 1'd1;
 	if (main_litedramcore_phaseinjector2_command_issue_re) begin
-		main_litedramcore_inti_p2_cas_n <= (~main_litedramcore_phaseinjector2_command_storage[2]);
+		main_litedramcore_inti_p2_we_n <= (~main_litedramcore_phaseinjector2_command_storage[1]);
 	end else begin
-		main_litedramcore_inti_p2_cas_n <= 1'd1;
+		main_litedramcore_inti_p2_we_n <= 1'd1;
 	end
 // synthesis translate_off
 	dummy_d_158 = dummy_s;
@@ -6743,11 +6743,11 @@ end
 reg dummy_d_159;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_inti_p2_cs_n <= 1'd1;
+	main_litedramcore_inti_p2_cas_n <= 1'd1;
 	if (main_litedramcore_phaseinjector2_command_issue_re) begin
-		main_litedramcore_inti_p2_cs_n <= {1{(~main_litedramcore_phaseinjector2_command_storage[0])}};
+		main_litedramcore_inti_p2_cas_n <= (~main_litedramcore_phaseinjector2_command_storage[2]);
 	end else begin
-		main_litedramcore_inti_p2_cs_n <= {1{1'd1}};
+		main_litedramcore_inti_p2_cas_n <= 1'd1;
 	end
 // synthesis translate_off
 	dummy_d_159 = dummy_s;
@@ -6758,11 +6758,11 @@ end
 reg dummy_d_160;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_inti_p2_ras_n <= 1'd1;
+	main_litedramcore_inti_p2_cs_n <= 1'd1;
 	if (main_litedramcore_phaseinjector2_command_issue_re) begin
-		main_litedramcore_inti_p2_ras_n <= (~main_litedramcore_phaseinjector2_command_storage[3]);
+		main_litedramcore_inti_p2_cs_n <= {1{(~main_litedramcore_phaseinjector2_command_storage[0])}};
 	end else begin
-		main_litedramcore_inti_p2_ras_n <= 1'd1;
+		main_litedramcore_inti_p2_cs_n <= {1{1'd1}};
 	end
 // synthesis translate_off
 	dummy_d_160 = dummy_s;
@@ -6773,11 +6773,11 @@ end
 reg dummy_d_161;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_inti_p2_we_n <= 1'd1;
+	main_litedramcore_inti_p2_ras_n <= 1'd1;
 	if (main_litedramcore_phaseinjector2_command_issue_re) begin
-		main_litedramcore_inti_p2_we_n <= (~main_litedramcore_phaseinjector2_command_storage[1]);
+		main_litedramcore_inti_p2_ras_n <= (~main_litedramcore_phaseinjector2_command_storage[3]);
 	end else begin
-		main_litedramcore_inti_p2_we_n <= 1'd1;
+		main_litedramcore_inti_p2_ras_n <= 1'd1;
 	end
 // synthesis translate_off
 	dummy_d_161 = dummy_s;
@@ -6794,11 +6794,11 @@ assign main_litedramcore_inti_p2_wrdata_mask = 1'd0;
 reg dummy_d_162;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_inti_p3_cas_n <= 1'd1;
+	main_litedramcore_inti_p3_we_n <= 1'd1;
 	if (main_litedramcore_phaseinjector3_command_issue_re) begin
-		main_litedramcore_inti_p3_cas_n <= (~main_litedramcore_phaseinjector3_command_storage[2]);
+		main_litedramcore_inti_p3_we_n <= (~main_litedramcore_phaseinjector3_command_storage[1]);
 	end else begin
-		main_litedramcore_inti_p3_cas_n <= 1'd1;
+		main_litedramcore_inti_p3_we_n <= 1'd1;
 	end
 // synthesis translate_off
 	dummy_d_162 = dummy_s;
@@ -6809,11 +6809,11 @@ end
 reg dummy_d_163;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_inti_p3_cs_n <= 1'd1;
+	main_litedramcore_inti_p3_cas_n <= 1'd1;
 	if (main_litedramcore_phaseinjector3_command_issue_re) begin
-		main_litedramcore_inti_p3_cs_n <= {1{(~main_litedramcore_phaseinjector3_command_storage[0])}};
+		main_litedramcore_inti_p3_cas_n <= (~main_litedramcore_phaseinjector3_command_storage[2]);
 	end else begin
-		main_litedramcore_inti_p3_cs_n <= {1{1'd1}};
+		main_litedramcore_inti_p3_cas_n <= 1'd1;
 	end
 // synthesis translate_off
 	dummy_d_163 = dummy_s;
@@ -6824,11 +6824,11 @@ end
 reg dummy_d_164;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_inti_p3_ras_n <= 1'd1;
+	main_litedramcore_inti_p3_cs_n <= 1'd1;
 	if (main_litedramcore_phaseinjector3_command_issue_re) begin
-		main_litedramcore_inti_p3_ras_n <= (~main_litedramcore_phaseinjector3_command_storage[3]);
+		main_litedramcore_inti_p3_cs_n <= {1{(~main_litedramcore_phaseinjector3_command_storage[0])}};
 	end else begin
-		main_litedramcore_inti_p3_ras_n <= 1'd1;
+		main_litedramcore_inti_p3_cs_n <= {1{1'd1}};
 	end
 // synthesis translate_off
 	dummy_d_164 = dummy_s;
@@ -6839,11 +6839,11 @@ end
 reg dummy_d_165;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_inti_p3_we_n <= 1'd1;
+	main_litedramcore_inti_p3_ras_n <= 1'd1;
 	if (main_litedramcore_phaseinjector3_command_issue_re) begin
-		main_litedramcore_inti_p3_we_n <= (~main_litedramcore_phaseinjector3_command_storage[1]);
+		main_litedramcore_inti_p3_ras_n <= (~main_litedramcore_phaseinjector3_command_storage[3]);
 	end else begin
-		main_litedramcore_inti_p3_we_n <= 1'd1;
+		main_litedramcore_inti_p3_ras_n <= 1'd1;
 	end
 // synthesis translate_off
 	dummy_d_165 = dummy_s;
@@ -7233,15 +7233,18 @@ end
 reg dummy_d_175;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine0_row_open <= 1'd0;
+	main_litedramcore_bankmachine0_cmd_valid <= 1'd0;
 	case (builder_bankmachine0_state)
 		1'd1: begin
+			if ((main_litedramcore_bankmachine0_twtpcon_ready & main_litedramcore_bankmachine0_trascon_ready)) begin
+				main_litedramcore_bankmachine0_cmd_valid <= 1'd1;
+			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
 			if (main_litedramcore_bankmachine0_trccon_ready) begin
-				main_litedramcore_bankmachine0_row_open <= 1'd1;
+				main_litedramcore_bankmachine0_cmd_valid <= 1'd1;
 			end
 		end
 		3'd4: begin
@@ -7255,6 +7258,18 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
+			if (main_litedramcore_bankmachine0_refresh_req) begin
+			end else begin
+				if (main_litedramcore_bankmachine0_cmd_buffer_source_valid) begin
+					if (main_litedramcore_bankmachine0_row_opened) begin
+						if (main_litedramcore_bankmachine0_row_hit) begin
+							main_litedramcore_bankmachine0_cmd_valid <= 1'd1;
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
 		end
 	endcase
 // synthesis translate_off
@@ -7265,6 +7280,39 @@ end
 // synthesis translate_off
 reg dummy_d_176;
 // synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine0_row_open <= 1'd0;
+	case (builder_bankmachine0_state)
+		1'd1: begin
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+			if (main_litedramcore_bankmachine0_trccon_ready) begin
+				main_litedramcore_bankmachine0_row_open <= 1'd1;
+			end
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_176 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_177;
+// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine0_row_close <= 1'd0;
 	case (builder_bankmachine0_state)
@@ -7291,12 +7339,12 @@ always @(*) begin
 		end
 	endcase
 // synthesis translate_off
-	dummy_d_176 = dummy_s;
+	dummy_d_177 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_177;
+reg dummy_d_178;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine0_cmd_payload_cas <= 1'd0;
@@ -7333,12 +7381,12 @@ always @(*) begin
 		end
 	endcase
 // synthesis translate_off
-	dummy_d_177 = dummy_s;
+	dummy_d_178 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_178;
+reg dummy_d_179;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine0_cmd_payload_ras <= 1'd0;
@@ -7369,12 +7417,12 @@ always @(*) begin
 		end
 	endcase
 // synthesis translate_off
-	dummy_d_178 = dummy_s;
+	dummy_d_179 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_179;
+reg dummy_d_180;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine0_cmd_payload_we <= 1'd0;
@@ -7417,12 +7465,12 @@ always @(*) begin
 		end
 	endcase
 // synthesis translate_off
-	dummy_d_179 = dummy_s;
+	dummy_d_180 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_180;
+reg dummy_d_181;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd0;
@@ -7450,12 +7498,12 @@ always @(*) begin
 		end
 	endcase
 // synthesis translate_off
-	dummy_d_180 = dummy_s;
+	dummy_d_181 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_181;
+reg dummy_d_182;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd0;
@@ -7487,15 +7535,15 @@ always @(*) begin
 		end
 	endcase
 // synthesis translate_off
-	dummy_d_181 = dummy_s;
+	dummy_d_182 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_182;
+reg dummy_d_183;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine0_req_rdata_valid <= 1'd0;
+	main_litedramcore_bankmachine0_cmd_payload_is_read <= 1'd0;
 	case (builder_bankmachine0_state)
 		1'd1: begin
 		end
@@ -7521,7 +7569,7 @@ always @(*) begin
 						if (main_litedramcore_bankmachine0_row_hit) begin
 							if (main_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
 							end else begin
-								main_litedramcore_bankmachine0_req_rdata_valid <= main_litedramcore_bankmachine0_cmd_ready;
+								main_litedramcore_bankmachine0_cmd_payload_is_read <= 1'd1;
 							end
 						end else begin
 						end
@@ -7532,15 +7580,15 @@ always @(*) begin
 		end
 	endcase
 // synthesis translate_off
-	dummy_d_182 = dummy_s;
+	dummy_d_183 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_183;
+reg dummy_d_184;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine0_cmd_payload_is_read <= 1'd0;
+	main_litedramcore_bankmachine0_cmd_payload_is_write <= 1'd0;
 	case (builder_bankmachine0_state)
 		1'd1: begin
 		end
@@ -7565,8 +7613,8 @@ always @(*) begin
 					if (main_litedramcore_bankmachine0_row_opened) begin
 						if (main_litedramcore_bankmachine0_row_hit) begin
 							if (main_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
+								main_litedramcore_bankmachine0_cmd_payload_is_write <= 1'd1;
 							end else begin
-								main_litedramcore_bankmachine0_cmd_payload_is_read <= 1'd1;
 							end
 						end else begin
 						end
@@ -7577,15 +7625,15 @@ always @(*) begin
 		end
 	endcase
 // synthesis translate_off
-	dummy_d_183 = dummy_s;
+	dummy_d_184 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_184;
+reg dummy_d_185;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine0_cmd_payload_is_write <= 1'd0;
+	main_litedramcore_bankmachine0_req_wdata_ready <= 1'd0;
 	case (builder_bankmachine0_state)
 		1'd1: begin
 		end
@@ -7610,7 +7658,7 @@ always @(*) begin
 					if (main_litedramcore_bankmachine0_row_opened) begin
 						if (main_litedramcore_bankmachine0_row_hit) begin
 							if (main_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
-								main_litedramcore_bankmachine0_cmd_payload_is_write <= 1'd1;
+								main_litedramcore_bankmachine0_req_wdata_ready <= main_litedramcore_bankmachine0_cmd_ready;
 							end else begin
 							end
 						end else begin
@@ -7622,15 +7670,15 @@ always @(*) begin
 		end
 	endcase
 // synthesis translate_off
-	dummy_d_184 = dummy_s;
+	dummy_d_185 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_185;
+reg dummy_d_186;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine0_req_wdata_ready <= 1'd0;
+	main_litedramcore_bankmachine0_req_rdata_valid <= 1'd0;
 	case (builder_bankmachine0_state)
 		1'd1: begin
 		end
@@ -7655,8 +7703,8 @@ always @(*) begin
 					if (main_litedramcore_bankmachine0_row_opened) begin
 						if (main_litedramcore_bankmachine0_row_hit) begin
 							if (main_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
-								main_litedramcore_bankmachine0_req_wdata_ready <= main_litedramcore_bankmachine0_cmd_ready;
 							end else begin
+								main_litedramcore_bankmachine0_req_rdata_valid <= main_litedramcore_bankmachine0_cmd_ready;
 							end
 						end else begin
 						end
@@ -7667,12 +7715,12 @@ always @(*) begin
 		end
 	endcase
 // synthesis translate_off
-	dummy_d_185 = dummy_s;
+	dummy_d_186 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_186;
+reg dummy_d_187;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine0_refresh_gnt <= 1'd0;
@@ -7700,55 +7748,7 @@ always @(*) begin
 		end
 	endcase
 // synthesis translate_off
-	dummy_d_186 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_187;
-// synthesis translate_on
-always @(*) begin
-	main_litedramcore_bankmachine0_cmd_valid <= 1'd0;
-	case (builder_bankmachine0_state)
-		1'd1: begin
-			if ((main_litedramcore_bankmachine0_twtpcon_ready & main_litedramcore_bankmachine0_trascon_ready)) begin
-				main_litedramcore_bankmachine0_cmd_valid <= 1'd1;
-			end
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-			if (main_litedramcore_bankmachine0_trccon_ready) begin
-				main_litedramcore_bankmachine0_cmd_valid <= 1'd1;
-			end
-		end
-		3'd4: begin
-		end
-		3'd5: begin
-		end
-		3'd6: begin
-		end
-		3'd7: begin
-		end
-		4'd8: begin
-		end
-		default: begin
-			if (main_litedramcore_bankmachine0_refresh_req) begin
-			end else begin
-				if (main_litedramcore_bankmachine0_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine0_row_opened) begin
-						if (main_litedramcore_bankmachine0_row_hit) begin
-							main_litedramcore_bankmachine0_cmd_valid <= 1'd1;
-						end else begin
-						end
-					end else begin
-					end
-				end
-			end
-		end
-	endcase
-// synthesis translate_off
-	dummy_d_187 = dummy_s;
+	dummy_d_187 = dummy_s;
 // synthesis translate_on
 end
 assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine1_req_valid;
@@ -7911,15 +7911,18 @@ end
 reg dummy_d_192;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine1_row_open <= 1'd0;
+	main_litedramcore_bankmachine1_cmd_valid <= 1'd0;
 	case (builder_bankmachine1_state)
 		1'd1: begin
+			if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin
+				main_litedramcore_bankmachine1_cmd_valid <= 1'd1;
+			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
 			if (main_litedramcore_bankmachine1_trccon_ready) begin
-				main_litedramcore_bankmachine1_row_open <= 1'd1;
+				main_litedramcore_bankmachine1_cmd_valid <= 1'd1;
 			end
 		end
 		3'd4: begin
@@ -7933,6 +7936,18 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
+			if (main_litedramcore_bankmachine1_refresh_req) begin
+			end else begin
+				if (main_litedramcore_bankmachine1_cmd_buffer_source_valid) begin
+					if (main_litedramcore_bankmachine1_row_opened) begin
+						if (main_litedramcore_bankmachine1_row_hit) begin
+							main_litedramcore_bankmachine1_cmd_valid <= 1'd1;
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
 		end
 	endcase
 // synthesis translate_off
@@ -7944,18 +7959,15 @@ end
 reg dummy_d_193;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine1_row_close <= 1'd0;
+	main_litedramcore_bankmachine1_req_rdata_valid <= 1'd0;
 	case (builder_bankmachine1_state)
 		1'd1: begin
-			main_litedramcore_bankmachine1_row_close <= 1'd1;
 		end
 		2'd2: begin
-			main_litedramcore_bankmachine1_row_close <= 1'd1;
 		end
 		2'd3: begin
 		end
 		3'd4: begin
-			main_litedramcore_bankmachine1_row_close <= 1'd1;
 		end
 		3'd5: begin
 		end
@@ -7966,6 +7978,21 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
+			if (main_litedramcore_bankmachine1_refresh_req) begin
+			end else begin
+				if (main_litedramcore_bankmachine1_cmd_buffer_source_valid) begin
+					if (main_litedramcore_bankmachine1_row_opened) begin
+						if (main_litedramcore_bankmachine1_row_hit) begin
+							if (main_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
+							end else begin
+								main_litedramcore_bankmachine1_req_rdata_valid <= main_litedramcore_bankmachine1_cmd_ready;
+							end
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
 		end
 	endcase
 // synthesis translate_off
@@ -7977,13 +8004,16 @@ end
 reg dummy_d_194;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine1_cmd_payload_cas <= 1'd0;
+	main_litedramcore_bankmachine1_row_open <= 1'd0;
 	case (builder_bankmachine1_state)
 		1'd1: begin
 		end
 		2'd2: begin
 		end
 		2'd3: begin
+			if (main_litedramcore_bankmachine1_trccon_ready) begin
+				main_litedramcore_bankmachine1_row_open <= 1'd1;
+			end
 		end
 		3'd4: begin
 		end
@@ -7996,18 +8026,6 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine1_refresh_req) begin
-			end else begin
-				if (main_litedramcore_bankmachine1_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine1_row_opened) begin
-						if (main_litedramcore_bankmachine1_row_hit) begin
-							main_litedramcore_bankmachine1_cmd_payload_cas <= 1'd1;
-						end else begin
-						end
-					end else begin
-					end
-				end
-			end
 		end
 	endcase
 // synthesis translate_off
@@ -8019,21 +8037,18 @@ end
 reg dummy_d_195;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine1_cmd_payload_ras <= 1'd0;
+	main_litedramcore_bankmachine1_row_close <= 1'd0;
 	case (builder_bankmachine1_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin
-				main_litedramcore_bankmachine1_cmd_payload_ras <= 1'd1;
-			end
+			main_litedramcore_bankmachine1_row_close <= 1'd1;
 		end
 		2'd2: begin
+			main_litedramcore_bankmachine1_row_close <= 1'd1;
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine1_trccon_ready) begin
-				main_litedramcore_bankmachine1_cmd_payload_ras <= 1'd1;
-			end
 		end
 		3'd4: begin
+			main_litedramcore_bankmachine1_row_close <= 1'd1;
 		end
 		3'd5: begin
 		end
@@ -8055,12 +8070,9 @@ end
 reg dummy_d_196;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine1_cmd_payload_we <= 1'd0;
+	main_litedramcore_bankmachine1_cmd_payload_cas <= 1'd0;
 	case (builder_bankmachine1_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin
-				main_litedramcore_bankmachine1_cmd_payload_we <= 1'd1;
-			end
 		end
 		2'd2: begin
 		end
@@ -8082,10 +8094,7 @@ always @(*) begin
 				if (main_litedramcore_bankmachine1_cmd_buffer_source_valid) begin
 					if (main_litedramcore_bankmachine1_row_opened) begin
 						if (main_litedramcore_bankmachine1_row_hit) begin
-							if (main_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
-								main_litedramcore_bankmachine1_cmd_payload_we <= 1'd1;
-							end else begin
-							end
+							main_litedramcore_bankmachine1_cmd_payload_cas <= 1'd1;
 						end else begin
 						end
 					end else begin
@@ -8103,15 +8112,18 @@ end
 reg dummy_d_197;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd0;
+	main_litedramcore_bankmachine1_cmd_payload_ras <= 1'd0;
 	case (builder_bankmachine1_state)
 		1'd1: begin
+			if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin
+				main_litedramcore_bankmachine1_cmd_payload_ras <= 1'd1;
+			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
 			if (main_litedramcore_bankmachine1_trccon_ready) begin
-				main_litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd1;
+				main_litedramcore_bankmachine1_cmd_payload_ras <= 1'd1;
 			end
 		end
 		3'd4: begin
@@ -8136,22 +8148,18 @@ end
 reg dummy_d_198;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd0;
+	main_litedramcore_bankmachine1_cmd_payload_we <= 1'd0;
 	case (builder_bankmachine1_state)
 		1'd1: begin
 			if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin
-				main_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
+				main_litedramcore_bankmachine1_cmd_payload_we <= 1'd1;
 			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine1_trccon_ready) begin
-				main_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
-			end
 		end
 		3'd4: begin
-			main_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
 		end
 		3'd5: begin
 		end
@@ -8162,6 +8170,21 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
+			if (main_litedramcore_bankmachine1_refresh_req) begin
+			end else begin
+				if (main_litedramcore_bankmachine1_cmd_buffer_source_valid) begin
+					if (main_litedramcore_bankmachine1_row_opened) begin
+						if (main_litedramcore_bankmachine1_row_hit) begin
+							if (main_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
+								main_litedramcore_bankmachine1_cmd_payload_we <= 1'd1;
+							end else begin
+							end
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
 		end
 	endcase
 // synthesis translate_off
@@ -8173,13 +8196,16 @@ end
 reg dummy_d_199;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine1_cmd_payload_is_read <= 1'd0;
+	main_litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd0;
 	case (builder_bankmachine1_state)
 		1'd1: begin
 		end
 		2'd2: begin
 		end
 		2'd3: begin
+			if (main_litedramcore_bankmachine1_trccon_ready) begin
+				main_litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd1;
+			end
 		end
 		3'd4: begin
 		end
@@ -8192,21 +8218,6 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine1_refresh_req) begin
-			end else begin
-				if (main_litedramcore_bankmachine1_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine1_row_opened) begin
-						if (main_litedramcore_bankmachine1_row_hit) begin
-							if (main_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
-							end else begin
-								main_litedramcore_bankmachine1_cmd_payload_is_read <= 1'd1;
-							end
-						end else begin
-						end
-					end else begin
-					end
-				end
-			end
 		end
 	endcase
 // synthesis translate_off
@@ -8218,15 +8229,22 @@ end
 reg dummy_d_200;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine1_cmd_payload_is_write <= 1'd0;
+	main_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd0;
 	case (builder_bankmachine1_state)
 		1'd1: begin
+			if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin
+				main_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
+			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
+			if (main_litedramcore_bankmachine1_trccon_ready) begin
+				main_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
+			end
 		end
 		3'd4: begin
+			main_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
 		end
 		3'd5: begin
 		end
@@ -8237,21 +8255,6 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine1_refresh_req) begin
-			end else begin
-				if (main_litedramcore_bankmachine1_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine1_row_opened) begin
-						if (main_litedramcore_bankmachine1_row_hit) begin
-							if (main_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
-								main_litedramcore_bankmachine1_cmd_payload_is_write <= 1'd1;
-							end else begin
-							end
-						end else begin
-						end
-					end else begin
-					end
-				end
-			end
 		end
 	endcase
 // synthesis translate_off
@@ -8263,7 +8266,7 @@ end
 reg dummy_d_201;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine1_req_wdata_ready <= 1'd0;
+	main_litedramcore_bankmachine1_cmd_payload_is_read <= 1'd0;
 	case (builder_bankmachine1_state)
 		1'd1: begin
 		end
@@ -8288,8 +8291,8 @@ always @(*) begin
 					if (main_litedramcore_bankmachine1_row_opened) begin
 						if (main_litedramcore_bankmachine1_row_hit) begin
 							if (main_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
-								main_litedramcore_bankmachine1_req_wdata_ready <= main_litedramcore_bankmachine1_cmd_ready;
 							end else begin
+								main_litedramcore_bankmachine1_cmd_payload_is_read <= 1'd1;
 							end
 						end else begin
 						end
@@ -8308,7 +8311,7 @@ end
 reg dummy_d_202;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine1_req_rdata_valid <= 1'd0;
+	main_litedramcore_bankmachine1_cmd_payload_is_write <= 1'd0;
 	case (builder_bankmachine1_state)
 		1'd1: begin
 		end
@@ -8333,8 +8336,8 @@ always @(*) begin
 					if (main_litedramcore_bankmachine1_row_opened) begin
 						if (main_litedramcore_bankmachine1_row_hit) begin
 							if (main_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
+								main_litedramcore_bankmachine1_cmd_payload_is_write <= 1'd1;
 							end else begin
-								main_litedramcore_bankmachine1_req_rdata_valid <= main_litedramcore_bankmachine1_cmd_ready;
 							end
 						end else begin
 						end
@@ -8353,7 +8356,7 @@ end
 reg dummy_d_203;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine1_refresh_gnt <= 1'd0;
+	main_litedramcore_bankmachine1_req_wdata_ready <= 1'd0;
 	case (builder_bankmachine1_state)
 		1'd1: begin
 		end
@@ -8362,9 +8365,6 @@ always @(*) begin
 		2'd3: begin
 		end
 		3'd4: begin
-			if (main_litedramcore_bankmachine1_twtpcon_ready) begin
-				main_litedramcore_bankmachine1_refresh_gnt <= 1'd1;
-			end
 		end
 		3'd5: begin
 		end
@@ -8375,6 +8375,21 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
+			if (main_litedramcore_bankmachine1_refresh_req) begin
+			end else begin
+				if (main_litedramcore_bankmachine1_cmd_buffer_source_valid) begin
+					if (main_litedramcore_bankmachine1_row_opened) begin
+						if (main_litedramcore_bankmachine1_row_hit) begin
+							if (main_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
+								main_litedramcore_bankmachine1_req_wdata_ready <= main_litedramcore_bankmachine1_cmd_ready;
+							end else begin
+							end
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
 		end
 	endcase
 // synthesis translate_off
@@ -8386,21 +8401,18 @@ end
 reg dummy_d_204;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine1_cmd_valid <= 1'd0;
+	main_litedramcore_bankmachine1_refresh_gnt <= 1'd0;
 	case (builder_bankmachine1_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin
-				main_litedramcore_bankmachine1_cmd_valid <= 1'd1;
-			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine1_trccon_ready) begin
-				main_litedramcore_bankmachine1_cmd_valid <= 1'd1;
-			end
 		end
 		3'd4: begin
+			if (main_litedramcore_bankmachine1_twtpcon_ready) begin
+				main_litedramcore_bankmachine1_refresh_gnt <= 1'd1;
+			end
 		end
 		3'd5: begin
 		end
@@ -8411,18 +8423,6 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine1_refresh_req) begin
-			end else begin
-				if (main_litedramcore_bankmachine1_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine1_row_opened) begin
-						if (main_litedramcore_bankmachine1_row_hit) begin
-							main_litedramcore_bankmachine1_cmd_valid <= 1'd1;
-						end else begin
-						end
-					end else begin
-					end
-				end
-			end
 		end
 	endcase
 // synthesis translate_off
@@ -8589,13 +8589,19 @@ end
 reg dummy_d_209;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine2_req_rdata_valid <= 1'd0;
+	main_litedramcore_bankmachine2_cmd_valid <= 1'd0;
 	case (builder_bankmachine2_state)
 		1'd1: begin
+			if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin
+				main_litedramcore_bankmachine2_cmd_valid <= 1'd1;
+			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
+			if (main_litedramcore_bankmachine2_trccon_ready) begin
+				main_litedramcore_bankmachine2_cmd_valid <= 1'd1;
+			end
 		end
 		3'd4: begin
 		end
@@ -8613,10 +8619,7 @@ always @(*) begin
 				if (main_litedramcore_bankmachine2_cmd_buffer_source_valid) begin
 					if (main_litedramcore_bankmachine2_row_opened) begin
 						if (main_litedramcore_bankmachine2_row_hit) begin
-							if (main_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
-							end else begin
-								main_litedramcore_bankmachine2_req_rdata_valid <= main_litedramcore_bankmachine2_cmd_ready;
-							end
+							main_litedramcore_bankmachine2_cmd_valid <= 1'd1;
 						end else begin
 						end
 					end else begin
@@ -8742,12 +8745,57 @@ end
 reg dummy_d_213;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine2_cmd_payload_ras <= 1'd0;
+	main_litedramcore_bankmachine2_req_rdata_valid <= 1'd0;
 	case (builder_bankmachine2_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin
-				main_litedramcore_bankmachine2_cmd_payload_ras <= 1'd1;
-			end
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+			if (main_litedramcore_bankmachine2_refresh_req) begin
+			end else begin
+				if (main_litedramcore_bankmachine2_cmd_buffer_source_valid) begin
+					if (main_litedramcore_bankmachine2_row_opened) begin
+						if (main_litedramcore_bankmachine2_row_hit) begin
+							if (main_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
+							end else begin
+								main_litedramcore_bankmachine2_req_rdata_valid <= main_litedramcore_bankmachine2_cmd_ready;
+							end
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_213 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_214;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine2_cmd_payload_ras <= 1'd0;
+	case (builder_bankmachine2_state)
+		1'd1: begin
+			if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin
+				main_litedramcore_bankmachine2_cmd_payload_ras <= 1'd1;
+			end
 		end
 		2'd2: begin
 		end
@@ -8770,12 +8818,12 @@ always @(*) begin
 		end
 	endcase
 // synthesis translate_off
-	dummy_d_213 = dummy_s;
+	dummy_d_214 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_214;
+reg dummy_d_215;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine2_cmd_payload_we <= 1'd0;
@@ -8818,12 +8866,12 @@ always @(*) begin
 		end
 	endcase
 // synthesis translate_off
-	dummy_d_214 = dummy_s;
+	dummy_d_215 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_215;
+reg dummy_d_216;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd0;
@@ -8851,12 +8899,12 @@ always @(*) begin
 		end
 	endcase
 // synthesis translate_off
-	dummy_d_215 = dummy_s;
+	dummy_d_216 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_216;
+reg dummy_d_217;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd0;
@@ -8888,12 +8936,12 @@ always @(*) begin
 		end
 	endcase
 // synthesis translate_off
-	dummy_d_216 = dummy_s;
+	dummy_d_217 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_217;
+reg dummy_d_218;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine2_cmd_payload_is_read <= 1'd0;
@@ -8933,12 +8981,12 @@ always @(*) begin
 		end
 	endcase
 // synthesis translate_off
-	dummy_d_217 = dummy_s;
+	dummy_d_218 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_218;
+reg dummy_d_219;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine2_cmd_payload_is_write <= 1'd0;
@@ -8978,12 +9026,12 @@ always @(*) begin
 		end
 	endcase
 // synthesis translate_off
-	dummy_d_218 = dummy_s;
+	dummy_d_219 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_219;
+reg dummy_d_220;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine2_req_wdata_ready <= 1'd0;
@@ -9023,12 +9071,12 @@ always @(*) begin
 		end
 	endcase
 // synthesis translate_off
-	dummy_d_219 = dummy_s;
+	dummy_d_220 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_220;
+reg dummy_d_221;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine2_refresh_gnt <= 1'd0;
@@ -9055,54 +9103,6 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_220 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_221;
-// synthesis translate_on
-always @(*) begin
-	main_litedramcore_bankmachine2_cmd_valid <= 1'd0;
-	case (builder_bankmachine2_state)
-		1'd1: begin
-			if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin
-				main_litedramcore_bankmachine2_cmd_valid <= 1'd1;
-			end
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-			if (main_litedramcore_bankmachine2_trccon_ready) begin
-				main_litedramcore_bankmachine2_cmd_valid <= 1'd1;
-			end
-		end
-		3'd4: begin
-		end
-		3'd5: begin
-		end
-		3'd6: begin
-		end
-		3'd7: begin
-		end
-		4'd8: begin
-		end
-		default: begin
-			if (main_litedramcore_bankmachine2_refresh_req) begin
-			end else begin
-				if (main_litedramcore_bankmachine2_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine2_row_opened) begin
-						if (main_litedramcore_bankmachine2_row_hit) begin
-							main_litedramcore_bankmachine2_cmd_valid <= 1'd1;
-						end else begin
-						end
-					end else begin
-					end
-				end
-			end
-		end
-	endcase
 // synthesis translate_off
 	dummy_d_221 = dummy_s;
 // synthesis translate_on
@@ -9267,15 +9267,18 @@ end
 reg dummy_d_226;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine3_row_open <= 1'd0;
+	main_litedramcore_bankmachine3_cmd_valid <= 1'd0;
 	case (builder_bankmachine3_state)
 		1'd1: begin
+			if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin
+				main_litedramcore_bankmachine3_cmd_valid <= 1'd1;
+			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
 			if (main_litedramcore_bankmachine3_trccon_ready) begin
-				main_litedramcore_bankmachine3_row_open <= 1'd1;
+				main_litedramcore_bankmachine3_cmd_valid <= 1'd1;
 			end
 		end
 		3'd4: begin
@@ -9289,6 +9292,18 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
+			if (main_litedramcore_bankmachine3_refresh_req) begin
+			end else begin
+				if (main_litedramcore_bankmachine3_cmd_buffer_source_valid) begin
+					if (main_litedramcore_bankmachine3_row_opened) begin
+						if (main_litedramcore_bankmachine3_row_hit) begin
+							main_litedramcore_bankmachine3_cmd_valid <= 1'd1;
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
 		end
 	endcase
 // synthesis translate_off
@@ -9300,18 +9315,18 @@ end
 reg dummy_d_227;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine3_row_close <= 1'd0;
+	main_litedramcore_bankmachine3_row_open <= 1'd0;
 	case (builder_bankmachine3_state)
 		1'd1: begin
-			main_litedramcore_bankmachine3_row_close <= 1'd1;
 		end
 		2'd2: begin
-			main_litedramcore_bankmachine3_row_close <= 1'd1;
 		end
 		2'd3: begin
+			if (main_litedramcore_bankmachine3_trccon_ready) begin
+				main_litedramcore_bankmachine3_row_open <= 1'd1;
+			end
 		end
 		3'd4: begin
-			main_litedramcore_bankmachine3_row_close <= 1'd1;
 		end
 		3'd5: begin
 		end
@@ -9333,15 +9348,18 @@ end
 reg dummy_d_228;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine3_cmd_payload_cas <= 1'd0;
+	main_litedramcore_bankmachine3_row_close <= 1'd0;
 	case (builder_bankmachine3_state)
 		1'd1: begin
+			main_litedramcore_bankmachine3_row_close <= 1'd1;
 		end
 		2'd2: begin
+			main_litedramcore_bankmachine3_row_close <= 1'd1;
 		end
 		2'd3: begin
 		end
 		3'd4: begin
+			main_litedramcore_bankmachine3_row_close <= 1'd1;
 		end
 		3'd5: begin
 		end
@@ -9352,18 +9370,6 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine3_refresh_req) begin
-			end else begin
-				if (main_litedramcore_bankmachine3_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine3_row_opened) begin
-						if (main_litedramcore_bankmachine3_row_hit) begin
-							main_litedramcore_bankmachine3_cmd_payload_cas <= 1'd1;
-						end else begin
-						end
-					end else begin
-					end
-				end
-			end
 		end
 	endcase
 // synthesis translate_off
@@ -9375,19 +9381,13 @@ end
 reg dummy_d_229;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine3_cmd_payload_ras <= 1'd0;
+	main_litedramcore_bankmachine3_cmd_payload_cas <= 1'd0;
 	case (builder_bankmachine3_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin
-				main_litedramcore_bankmachine3_cmd_payload_ras <= 1'd1;
-			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine3_trccon_ready) begin
-				main_litedramcore_bankmachine3_cmd_payload_ras <= 1'd1;
-			end
 		end
 		3'd4: begin
 		end
@@ -9400,6 +9400,18 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
+			if (main_litedramcore_bankmachine3_refresh_req) begin
+			end else begin
+				if (main_litedramcore_bankmachine3_cmd_buffer_source_valid) begin
+					if (main_litedramcore_bankmachine3_row_opened) begin
+						if (main_litedramcore_bankmachine3_row_hit) begin
+							main_litedramcore_bankmachine3_cmd_payload_cas <= 1'd1;
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
 		end
 	endcase
 // synthesis translate_off
@@ -9411,13 +9423,19 @@ end
 reg dummy_d_230;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine3_req_rdata_valid <= 1'd0;
+	main_litedramcore_bankmachine3_cmd_payload_ras <= 1'd0;
 	case (builder_bankmachine3_state)
 		1'd1: begin
+			if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin
+				main_litedramcore_bankmachine3_cmd_payload_ras <= 1'd1;
+			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
+			if (main_litedramcore_bankmachine3_trccon_ready) begin
+				main_litedramcore_bankmachine3_cmd_payload_ras <= 1'd1;
+			end
 		end
 		3'd4: begin
 		end
@@ -9430,21 +9448,6 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine3_refresh_req) begin
-			end else begin
-				if (main_litedramcore_bankmachine3_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine3_row_opened) begin
-						if (main_litedramcore_bankmachine3_row_hit) begin
-							if (main_litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
-							end else begin
-								main_litedramcore_bankmachine3_req_rdata_valid <= main_litedramcore_bankmachine3_cmd_ready;
-							end
-						end else begin
-						end
-					end else begin
-					end
-				end
-			end
 		end
 	endcase
 // synthesis translate_off
@@ -9664,7 +9667,7 @@ end
 reg dummy_d_236;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine3_req_wdata_ready <= 1'd0;
+	main_litedramcore_bankmachine3_req_rdata_valid <= 1'd0;
 	case (builder_bankmachine3_state)
 		1'd1: begin
 		end
@@ -9689,8 +9692,8 @@ always @(*) begin
 					if (main_litedramcore_bankmachine3_row_opened) begin
 						if (main_litedramcore_bankmachine3_row_hit) begin
 							if (main_litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
-								main_litedramcore_bankmachine3_req_wdata_ready <= main_litedramcore_bankmachine3_cmd_ready;
 							end else begin
+								main_litedramcore_bankmachine3_req_rdata_valid <= main_litedramcore_bankmachine3_cmd_ready;
 							end
 						end else begin
 						end
@@ -9709,7 +9712,7 @@ end
 reg dummy_d_237;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine3_refresh_gnt <= 1'd0;
+	main_litedramcore_bankmachine3_req_wdata_ready <= 1'd0;
 	case (builder_bankmachine3_state)
 		1'd1: begin
 		end
@@ -9718,9 +9721,6 @@ always @(*) begin
 		2'd3: begin
 		end
 		3'd4: begin
-			if (main_litedramcore_bankmachine3_twtpcon_ready) begin
-				main_litedramcore_bankmachine3_refresh_gnt <= 1'd1;
-			end
 		end
 		3'd5: begin
 		end
@@ -9731,6 +9731,21 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
+			if (main_litedramcore_bankmachine3_refresh_req) begin
+			end else begin
+				if (main_litedramcore_bankmachine3_cmd_buffer_source_valid) begin
+					if (main_litedramcore_bankmachine3_row_opened) begin
+						if (main_litedramcore_bankmachine3_row_hit) begin
+							if (main_litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
+								main_litedramcore_bankmachine3_req_wdata_ready <= main_litedramcore_bankmachine3_cmd_ready;
+							end else begin
+							end
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
 		end
 	endcase
 // synthesis translate_off
@@ -9742,21 +9757,18 @@ end
 reg dummy_d_238;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine3_cmd_valid <= 1'd0;
+	main_litedramcore_bankmachine3_refresh_gnt <= 1'd0;
 	case (builder_bankmachine3_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin
-				main_litedramcore_bankmachine3_cmd_valid <= 1'd1;
-			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine3_trccon_ready) begin
-				main_litedramcore_bankmachine3_cmd_valid <= 1'd1;
-			end
 		end
 		3'd4: begin
+			if (main_litedramcore_bankmachine3_twtpcon_ready) begin
+				main_litedramcore_bankmachine3_refresh_gnt <= 1'd1;
+			end
 		end
 		3'd5: begin
 		end
@@ -9767,18 +9779,6 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine3_refresh_req) begin
-			end else begin
-				if (main_litedramcore_bankmachine3_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine3_row_opened) begin
-						if (main_litedramcore_bankmachine3_row_hit) begin
-							main_litedramcore_bankmachine3_cmd_valid <= 1'd1;
-						end else begin
-						end
-					end else begin
-					end
-				end
-			end
 		end
 	endcase
 // synthesis translate_off
@@ -9945,15 +9945,18 @@ end
 reg dummy_d_243;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine4_row_open <= 1'd0;
+	main_litedramcore_bankmachine4_cmd_valid <= 1'd0;
 	case (builder_bankmachine4_state)
 		1'd1: begin
+			if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin
+				main_litedramcore_bankmachine4_cmd_valid <= 1'd1;
+			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
 			if (main_litedramcore_bankmachine4_trccon_ready) begin
-				main_litedramcore_bankmachine4_row_open <= 1'd1;
+				main_litedramcore_bankmachine4_cmd_valid <= 1'd1;
 			end
 		end
 		3'd4: begin
@@ -9967,6 +9970,18 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
+			if (main_litedramcore_bankmachine4_refresh_req) begin
+			end else begin
+				if (main_litedramcore_bankmachine4_cmd_buffer_source_valid) begin
+					if (main_litedramcore_bankmachine4_row_opened) begin
+						if (main_litedramcore_bankmachine4_row_hit) begin
+							main_litedramcore_bankmachine4_cmd_valid <= 1'd1;
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
 		end
 	endcase
 // synthesis translate_off
@@ -9978,18 +9993,15 @@ end
 reg dummy_d_244;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine4_row_close <= 1'd0;
+	main_litedramcore_bankmachine4_req_rdata_valid <= 1'd0;
 	case (builder_bankmachine4_state)
 		1'd1: begin
-			main_litedramcore_bankmachine4_row_close <= 1'd1;
 		end
 		2'd2: begin
-			main_litedramcore_bankmachine4_row_close <= 1'd1;
 		end
 		2'd3: begin
 		end
 		3'd4: begin
-			main_litedramcore_bankmachine4_row_close <= 1'd1;
 		end
 		3'd5: begin
 		end
@@ -10000,6 +10012,21 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
+			if (main_litedramcore_bankmachine4_refresh_req) begin
+			end else begin
+				if (main_litedramcore_bankmachine4_cmd_buffer_source_valid) begin
+					if (main_litedramcore_bankmachine4_row_opened) begin
+						if (main_litedramcore_bankmachine4_row_hit) begin
+							if (main_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
+							end else begin
+								main_litedramcore_bankmachine4_req_rdata_valid <= main_litedramcore_bankmachine4_cmd_ready;
+							end
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
 		end
 	endcase
 // synthesis translate_off
@@ -10011,13 +10038,16 @@ end
 reg dummy_d_245;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine4_cmd_payload_cas <= 1'd0;
+	main_litedramcore_bankmachine4_row_open <= 1'd0;
 	case (builder_bankmachine4_state)
 		1'd1: begin
 		end
 		2'd2: begin
 		end
 		2'd3: begin
+			if (main_litedramcore_bankmachine4_trccon_ready) begin
+				main_litedramcore_bankmachine4_row_open <= 1'd1;
+			end
 		end
 		3'd4: begin
 		end
@@ -10030,18 +10060,6 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine4_refresh_req) begin
-			end else begin
-				if (main_litedramcore_bankmachine4_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine4_row_opened) begin
-						if (main_litedramcore_bankmachine4_row_hit) begin
-							main_litedramcore_bankmachine4_cmd_payload_cas <= 1'd1;
-						end else begin
-						end
-					end else begin
-					end
-				end
-			end
 		end
 	endcase
 // synthesis translate_off
@@ -10053,21 +10071,18 @@ end
 reg dummy_d_246;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine4_cmd_payload_ras <= 1'd0;
+	main_litedramcore_bankmachine4_row_close <= 1'd0;
 	case (builder_bankmachine4_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin
-				main_litedramcore_bankmachine4_cmd_payload_ras <= 1'd1;
-			end
+			main_litedramcore_bankmachine4_row_close <= 1'd1;
 		end
 		2'd2: begin
+			main_litedramcore_bankmachine4_row_close <= 1'd1;
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine4_trccon_ready) begin
-				main_litedramcore_bankmachine4_cmd_payload_ras <= 1'd1;
-			end
 		end
 		3'd4: begin
+			main_litedramcore_bankmachine4_row_close <= 1'd1;
 		end
 		3'd5: begin
 		end
@@ -10089,12 +10104,9 @@ end
 reg dummy_d_247;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine4_cmd_payload_we <= 1'd0;
+	main_litedramcore_bankmachine4_cmd_payload_cas <= 1'd0;
 	case (builder_bankmachine4_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin
-				main_litedramcore_bankmachine4_cmd_payload_we <= 1'd1;
-			end
 		end
 		2'd2: begin
 		end
@@ -10116,10 +10128,7 @@ always @(*) begin
 				if (main_litedramcore_bankmachine4_cmd_buffer_source_valid) begin
 					if (main_litedramcore_bankmachine4_row_opened) begin
 						if (main_litedramcore_bankmachine4_row_hit) begin
-							if (main_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
-								main_litedramcore_bankmachine4_cmd_payload_we <= 1'd1;
-							end else begin
-							end
+							main_litedramcore_bankmachine4_cmd_payload_cas <= 1'd1;
 						end else begin
 						end
 					end else begin
@@ -10137,15 +10146,18 @@ end
 reg dummy_d_248;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd0;
+	main_litedramcore_bankmachine4_cmd_payload_ras <= 1'd0;
 	case (builder_bankmachine4_state)
 		1'd1: begin
+			if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin
+				main_litedramcore_bankmachine4_cmd_payload_ras <= 1'd1;
+			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
 			if (main_litedramcore_bankmachine4_trccon_ready) begin
-				main_litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd1;
+				main_litedramcore_bankmachine4_cmd_payload_ras <= 1'd1;
 			end
 		end
 		3'd4: begin
@@ -10170,22 +10182,18 @@ end
 reg dummy_d_249;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd0;
+	main_litedramcore_bankmachine4_cmd_payload_we <= 1'd0;
 	case (builder_bankmachine4_state)
 		1'd1: begin
 			if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin
-				main_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
+				main_litedramcore_bankmachine4_cmd_payload_we <= 1'd1;
 			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine4_trccon_ready) begin
-				main_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
-			end
 		end
 		3'd4: begin
-			main_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
 		end
 		3'd5: begin
 		end
@@ -10196,6 +10204,21 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
+			if (main_litedramcore_bankmachine4_refresh_req) begin
+			end else begin
+				if (main_litedramcore_bankmachine4_cmd_buffer_source_valid) begin
+					if (main_litedramcore_bankmachine4_row_opened) begin
+						if (main_litedramcore_bankmachine4_row_hit) begin
+							if (main_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
+								main_litedramcore_bankmachine4_cmd_payload_we <= 1'd1;
+							end else begin
+							end
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
 		end
 	endcase
 // synthesis translate_off
@@ -10207,13 +10230,16 @@ end
 reg dummy_d_250;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine4_cmd_payload_is_read <= 1'd0;
+	main_litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd0;
 	case (builder_bankmachine4_state)
 		1'd1: begin
 		end
 		2'd2: begin
 		end
 		2'd3: begin
+			if (main_litedramcore_bankmachine4_trccon_ready) begin
+				main_litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd1;
+			end
 		end
 		3'd4: begin
 		end
@@ -10226,21 +10252,6 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine4_refresh_req) begin
-			end else begin
-				if (main_litedramcore_bankmachine4_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine4_row_opened) begin
-						if (main_litedramcore_bankmachine4_row_hit) begin
-							if (main_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
-							end else begin
-								main_litedramcore_bankmachine4_cmd_payload_is_read <= 1'd1;
-							end
-						end else begin
-						end
-					end else begin
-					end
-				end
-			end
 		end
 	endcase
 // synthesis translate_off
@@ -10252,15 +10263,22 @@ end
 reg dummy_d_251;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine4_cmd_payload_is_write <= 1'd0;
+	main_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd0;
 	case (builder_bankmachine4_state)
 		1'd1: begin
+			if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin
+				main_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
+			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
+			if (main_litedramcore_bankmachine4_trccon_ready) begin
+				main_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
+			end
 		end
 		3'd4: begin
+			main_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
 		end
 		3'd5: begin
 		end
@@ -10271,21 +10289,6 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine4_refresh_req) begin
-			end else begin
-				if (main_litedramcore_bankmachine4_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine4_row_opened) begin
-						if (main_litedramcore_bankmachine4_row_hit) begin
-							if (main_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
-								main_litedramcore_bankmachine4_cmd_payload_is_write <= 1'd1;
-							end else begin
-							end
-						end else begin
-						end
-					end else begin
-					end
-				end
-			end
 		end
 	endcase
 // synthesis translate_off
@@ -10297,7 +10300,7 @@ end
 reg dummy_d_252;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine4_req_wdata_ready <= 1'd0;
+	main_litedramcore_bankmachine4_cmd_payload_is_read <= 1'd0;
 	case (builder_bankmachine4_state)
 		1'd1: begin
 		end
@@ -10322,8 +10325,8 @@ always @(*) begin
 					if (main_litedramcore_bankmachine4_row_opened) begin
 						if (main_litedramcore_bankmachine4_row_hit) begin
 							if (main_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
-								main_litedramcore_bankmachine4_req_wdata_ready <= main_litedramcore_bankmachine4_cmd_ready;
 							end else begin
+								main_litedramcore_bankmachine4_cmd_payload_is_read <= 1'd1;
 							end
 						end else begin
 						end
@@ -10342,7 +10345,7 @@ end
 reg dummy_d_253;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine4_req_rdata_valid <= 1'd0;
+	main_litedramcore_bankmachine4_cmd_payload_is_write <= 1'd0;
 	case (builder_bankmachine4_state)
 		1'd1: begin
 		end
@@ -10367,8 +10370,8 @@ always @(*) begin
 					if (main_litedramcore_bankmachine4_row_opened) begin
 						if (main_litedramcore_bankmachine4_row_hit) begin
 							if (main_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
+								main_litedramcore_bankmachine4_cmd_payload_is_write <= 1'd1;
 							end else begin
-								main_litedramcore_bankmachine4_req_rdata_valid <= main_litedramcore_bankmachine4_cmd_ready;
 							end
 						end else begin
 						end
@@ -10387,7 +10390,7 @@ end
 reg dummy_d_254;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine4_refresh_gnt <= 1'd0;
+	main_litedramcore_bankmachine4_req_wdata_ready <= 1'd0;
 	case (builder_bankmachine4_state)
 		1'd1: begin
 		end
@@ -10396,9 +10399,6 @@ always @(*) begin
 		2'd3: begin
 		end
 		3'd4: begin
-			if (main_litedramcore_bankmachine4_twtpcon_ready) begin
-				main_litedramcore_bankmachine4_refresh_gnt <= 1'd1;
-			end
 		end
 		3'd5: begin
 		end
@@ -10409,6 +10409,21 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
+			if (main_litedramcore_bankmachine4_refresh_req) begin
+			end else begin
+				if (main_litedramcore_bankmachine4_cmd_buffer_source_valid) begin
+					if (main_litedramcore_bankmachine4_row_opened) begin
+						if (main_litedramcore_bankmachine4_row_hit) begin
+							if (main_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
+								main_litedramcore_bankmachine4_req_wdata_ready <= main_litedramcore_bankmachine4_cmd_ready;
+							end else begin
+							end
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
 		end
 	endcase
 // synthesis translate_off
@@ -10420,21 +10435,18 @@ end
 reg dummy_d_255;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine4_cmd_valid <= 1'd0;
+	main_litedramcore_bankmachine4_refresh_gnt <= 1'd0;
 	case (builder_bankmachine4_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin
-				main_litedramcore_bankmachine4_cmd_valid <= 1'd1;
-			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine4_trccon_ready) begin
-				main_litedramcore_bankmachine4_cmd_valid <= 1'd1;
-			end
 		end
 		3'd4: begin
+			if (main_litedramcore_bankmachine4_twtpcon_ready) begin
+				main_litedramcore_bankmachine4_refresh_gnt <= 1'd1;
+			end
 		end
 		3'd5: begin
 		end
@@ -10445,18 +10457,6 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine4_refresh_req) begin
-			end else begin
-				if (main_litedramcore_bankmachine4_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine4_row_opened) begin
-						if (main_litedramcore_bankmachine4_row_hit) begin
-							main_litedramcore_bankmachine4_cmd_valid <= 1'd1;
-						end else begin
-						end
-					end else begin
-					end
-				end
-			end
 		end
 	endcase
 // synthesis translate_off
@@ -10623,15 +10623,18 @@ end
 reg dummy_d_260;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine5_row_open <= 1'd0;
+	main_litedramcore_bankmachine5_cmd_valid <= 1'd0;
 	case (builder_bankmachine5_state)
 		1'd1: begin
+			if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin
+				main_litedramcore_bankmachine5_cmd_valid <= 1'd1;
+			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
 			if (main_litedramcore_bankmachine5_trccon_ready) begin
-				main_litedramcore_bankmachine5_row_open <= 1'd1;
+				main_litedramcore_bankmachine5_cmd_valid <= 1'd1;
 			end
 		end
 		3'd4: begin
@@ -10645,6 +10648,18 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
+			if (main_litedramcore_bankmachine5_refresh_req) begin
+			end else begin
+				if (main_litedramcore_bankmachine5_cmd_buffer_source_valid) begin
+					if (main_litedramcore_bankmachine5_row_opened) begin
+						if (main_litedramcore_bankmachine5_row_hit) begin
+							main_litedramcore_bankmachine5_cmd_valid <= 1'd1;
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
 		end
 	endcase
 // synthesis translate_off
@@ -10656,18 +10671,18 @@ end
 reg dummy_d_261;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine5_row_close <= 1'd0;
+	main_litedramcore_bankmachine5_row_open <= 1'd0;
 	case (builder_bankmachine5_state)
 		1'd1: begin
-			main_litedramcore_bankmachine5_row_close <= 1'd1;
 		end
 		2'd2: begin
-			main_litedramcore_bankmachine5_row_close <= 1'd1;
 		end
 		2'd3: begin
+			if (main_litedramcore_bankmachine5_trccon_ready) begin
+				main_litedramcore_bankmachine5_row_open <= 1'd1;
+			end
 		end
 		3'd4: begin
-			main_litedramcore_bankmachine5_row_close <= 1'd1;
 		end
 		3'd5: begin
 		end
@@ -10689,7 +10704,7 @@ end
 reg dummy_d_262;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine5_cmd_payload_cas <= 1'd0;
+	main_litedramcore_bankmachine5_req_rdata_valid <= 1'd0;
 	case (builder_bankmachine5_state)
 		1'd1: begin
 		end
@@ -10713,7 +10728,10 @@ always @(*) begin
 				if (main_litedramcore_bankmachine5_cmd_buffer_source_valid) begin
 					if (main_litedramcore_bankmachine5_row_opened) begin
 						if (main_litedramcore_bankmachine5_row_hit) begin
-							main_litedramcore_bankmachine5_cmd_payload_cas <= 1'd1;
+							if (main_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
+							end else begin
+								main_litedramcore_bankmachine5_req_rdata_valid <= main_litedramcore_bankmachine5_cmd_ready;
+							end
 						end else begin
 						end
 					end else begin
@@ -10731,21 +10749,18 @@ end
 reg dummy_d_263;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine5_cmd_payload_ras <= 1'd0;
+	main_litedramcore_bankmachine5_row_close <= 1'd0;
 	case (builder_bankmachine5_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin
-				main_litedramcore_bankmachine5_cmd_payload_ras <= 1'd1;
-			end
+			main_litedramcore_bankmachine5_row_close <= 1'd1;
 		end
 		2'd2: begin
+			main_litedramcore_bankmachine5_row_close <= 1'd1;
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine5_trccon_ready) begin
-				main_litedramcore_bankmachine5_cmd_payload_ras <= 1'd1;
-			end
 		end
 		3'd4: begin
+			main_litedramcore_bankmachine5_row_close <= 1'd1;
 		end
 		3'd5: begin
 		end
@@ -10767,12 +10782,9 @@ end
 reg dummy_d_264;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine5_cmd_payload_we <= 1'd0;
+	main_litedramcore_bankmachine5_cmd_payload_cas <= 1'd0;
 	case (builder_bankmachine5_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin
-				main_litedramcore_bankmachine5_cmd_payload_we <= 1'd1;
-			end
 		end
 		2'd2: begin
 		end
@@ -10794,10 +10806,7 @@ always @(*) begin
 				if (main_litedramcore_bankmachine5_cmd_buffer_source_valid) begin
 					if (main_litedramcore_bankmachine5_row_opened) begin
 						if (main_litedramcore_bankmachine5_row_hit) begin
-							if (main_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
-								main_litedramcore_bankmachine5_cmd_payload_we <= 1'd1;
-							end else begin
-							end
+							main_litedramcore_bankmachine5_cmd_payload_cas <= 1'd1;
 						end else begin
 						end
 					end else begin
@@ -10815,15 +10824,18 @@ end
 reg dummy_d_265;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd0;
+	main_litedramcore_bankmachine5_cmd_payload_ras <= 1'd0;
 	case (builder_bankmachine5_state)
 		1'd1: begin
+			if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin
+				main_litedramcore_bankmachine5_cmd_payload_ras <= 1'd1;
+			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
 			if (main_litedramcore_bankmachine5_trccon_ready) begin
-				main_litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd1;
+				main_litedramcore_bankmachine5_cmd_payload_ras <= 1'd1;
 			end
 		end
 		3'd4: begin
@@ -10848,22 +10860,18 @@ end
 reg dummy_d_266;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd0;
+	main_litedramcore_bankmachine5_cmd_payload_we <= 1'd0;
 	case (builder_bankmachine5_state)
 		1'd1: begin
 			if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin
-				main_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
+				main_litedramcore_bankmachine5_cmd_payload_we <= 1'd1;
 			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine5_trccon_ready) begin
-				main_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
-			end
 		end
 		3'd4: begin
-			main_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
 		end
 		3'd5: begin
 		end
@@ -10874,6 +10882,21 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
+			if (main_litedramcore_bankmachine5_refresh_req) begin
+			end else begin
+				if (main_litedramcore_bankmachine5_cmd_buffer_source_valid) begin
+					if (main_litedramcore_bankmachine5_row_opened) begin
+						if (main_litedramcore_bankmachine5_row_hit) begin
+							if (main_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
+								main_litedramcore_bankmachine5_cmd_payload_we <= 1'd1;
+							end else begin
+							end
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
 		end
 	endcase
 // synthesis translate_off
@@ -10885,13 +10908,16 @@ end
 reg dummy_d_267;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine5_cmd_payload_is_read <= 1'd0;
+	main_litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd0;
 	case (builder_bankmachine5_state)
 		1'd1: begin
 		end
 		2'd2: begin
 		end
 		2'd3: begin
+			if (main_litedramcore_bankmachine5_trccon_ready) begin
+				main_litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd1;
+			end
 		end
 		3'd4: begin
 		end
@@ -10904,21 +10930,6 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine5_refresh_req) begin
-			end else begin
-				if (main_litedramcore_bankmachine5_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine5_row_opened) begin
-						if (main_litedramcore_bankmachine5_row_hit) begin
-							if (main_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
-							end else begin
-								main_litedramcore_bankmachine5_cmd_payload_is_read <= 1'd1;
-							end
-						end else begin
-						end
-					end else begin
-					end
-				end
-			end
 		end
 	endcase
 // synthesis translate_off
@@ -10930,15 +10941,22 @@ end
 reg dummy_d_268;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine5_cmd_payload_is_write <= 1'd0;
+	main_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd0;
 	case (builder_bankmachine5_state)
 		1'd1: begin
+			if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin
+				main_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
+			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
+			if (main_litedramcore_bankmachine5_trccon_ready) begin
+				main_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
+			end
 		end
 		3'd4: begin
+			main_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
 		end
 		3'd5: begin
 		end
@@ -10949,21 +10967,6 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine5_refresh_req) begin
-			end else begin
-				if (main_litedramcore_bankmachine5_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine5_row_opened) begin
-						if (main_litedramcore_bankmachine5_row_hit) begin
-							if (main_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
-								main_litedramcore_bankmachine5_cmd_payload_is_write <= 1'd1;
-							end else begin
-							end
-						end else begin
-						end
-					end else begin
-					end
-				end
-			end
 		end
 	endcase
 // synthesis translate_off
@@ -10975,7 +10978,7 @@ end
 reg dummy_d_269;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine5_req_wdata_ready <= 1'd0;
+	main_litedramcore_bankmachine5_cmd_payload_is_read <= 1'd0;
 	case (builder_bankmachine5_state)
 		1'd1: begin
 		end
@@ -11000,8 +11003,8 @@ always @(*) begin
 					if (main_litedramcore_bankmachine5_row_opened) begin
 						if (main_litedramcore_bankmachine5_row_hit) begin
 							if (main_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
-								main_litedramcore_bankmachine5_req_wdata_ready <= main_litedramcore_bankmachine5_cmd_ready;
 							end else begin
+								main_litedramcore_bankmachine5_cmd_payload_is_read <= 1'd1;
 							end
 						end else begin
 						end
@@ -11020,7 +11023,7 @@ end
 reg dummy_d_270;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine5_refresh_gnt <= 1'd0;
+	main_litedramcore_bankmachine5_cmd_payload_is_write <= 1'd0;
 	case (builder_bankmachine5_state)
 		1'd1: begin
 		end
@@ -11029,9 +11032,6 @@ always @(*) begin
 		2'd3: begin
 		end
 		3'd4: begin
-			if (main_litedramcore_bankmachine5_twtpcon_ready) begin
-				main_litedramcore_bankmachine5_refresh_gnt <= 1'd1;
-			end
 		end
 		3'd5: begin
 		end
@@ -11042,6 +11042,21 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
+			if (main_litedramcore_bankmachine5_refresh_req) begin
+			end else begin
+				if (main_litedramcore_bankmachine5_cmd_buffer_source_valid) begin
+					if (main_litedramcore_bankmachine5_row_opened) begin
+						if (main_litedramcore_bankmachine5_row_hit) begin
+							if (main_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
+								main_litedramcore_bankmachine5_cmd_payload_is_write <= 1'd1;
+							end else begin
+							end
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
 		end
 	endcase
 // synthesis translate_off
@@ -11053,19 +11068,13 @@ end
 reg dummy_d_271;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine5_cmd_valid <= 1'd0;
+	main_litedramcore_bankmachine5_req_wdata_ready <= 1'd0;
 	case (builder_bankmachine5_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin
-				main_litedramcore_bankmachine5_cmd_valid <= 1'd1;
-			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine5_trccon_ready) begin
-				main_litedramcore_bankmachine5_cmd_valid <= 1'd1;
-			end
 		end
 		3'd4: begin
 		end
@@ -11083,7 +11092,10 @@ always @(*) begin
 				if (main_litedramcore_bankmachine5_cmd_buffer_source_valid) begin
 					if (main_litedramcore_bankmachine5_row_opened) begin
 						if (main_litedramcore_bankmachine5_row_hit) begin
-							main_litedramcore_bankmachine5_cmd_valid <= 1'd1;
+							if (main_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
+								main_litedramcore_bankmachine5_req_wdata_ready <= main_litedramcore_bankmachine5_cmd_ready;
+							end else begin
+							end
 						end else begin
 						end
 					end else begin
@@ -11101,7 +11113,7 @@ end
 reg dummy_d_272;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine5_req_rdata_valid <= 1'd0;
+	main_litedramcore_bankmachine5_refresh_gnt <= 1'd0;
 	case (builder_bankmachine5_state)
 		1'd1: begin
 		end
@@ -11110,6 +11122,9 @@ always @(*) begin
 		2'd3: begin
 		end
 		3'd4: begin
+			if (main_litedramcore_bankmachine5_twtpcon_ready) begin
+				main_litedramcore_bankmachine5_refresh_gnt <= 1'd1;
+			end
 		end
 		3'd5: begin
 		end
@@ -11120,21 +11135,6 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine5_refresh_req) begin
-			end else begin
-				if (main_litedramcore_bankmachine5_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine5_row_opened) begin
-						if (main_litedramcore_bankmachine5_row_hit) begin
-							if (main_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
-							end else begin
-								main_litedramcore_bankmachine5_req_rdata_valid <= main_litedramcore_bankmachine5_cmd_ready;
-							end
-						end else begin
-						end
-					end else begin
-					end
-				end
-			end
 		end
 	endcase
 // synthesis translate_off
@@ -11301,15 +11301,18 @@ end
 reg dummy_d_277;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine6_row_open <= 1'd0;
+	main_litedramcore_bankmachine6_cmd_valid <= 1'd0;
 	case (builder_bankmachine6_state)
 		1'd1: begin
+			if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin
+				main_litedramcore_bankmachine6_cmd_valid <= 1'd1;
+			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
 			if (main_litedramcore_bankmachine6_trccon_ready) begin
-				main_litedramcore_bankmachine6_row_open <= 1'd1;
+				main_litedramcore_bankmachine6_cmd_valid <= 1'd1;
 			end
 		end
 		3'd4: begin
@@ -11323,6 +11326,18 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
+			if (main_litedramcore_bankmachine6_refresh_req) begin
+			end else begin
+				if (main_litedramcore_bankmachine6_cmd_buffer_source_valid) begin
+					if (main_litedramcore_bankmachine6_row_opened) begin
+						if (main_litedramcore_bankmachine6_row_hit) begin
+							main_litedramcore_bankmachine6_cmd_valid <= 1'd1;
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
 		end
 	endcase
 // synthesis translate_off
@@ -11334,18 +11349,18 @@ end
 reg dummy_d_278;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine6_row_close <= 1'd0;
+	main_litedramcore_bankmachine6_row_open <= 1'd0;
 	case (builder_bankmachine6_state)
 		1'd1: begin
-			main_litedramcore_bankmachine6_row_close <= 1'd1;
 		end
 		2'd2: begin
-			main_litedramcore_bankmachine6_row_close <= 1'd1;
 		end
 		2'd3: begin
+			if (main_litedramcore_bankmachine6_trccon_ready) begin
+				main_litedramcore_bankmachine6_row_open <= 1'd1;
+			end
 		end
 		3'd4: begin
-			main_litedramcore_bankmachine6_row_close <= 1'd1;
 		end
 		3'd5: begin
 		end
@@ -11367,15 +11382,18 @@ end
 reg dummy_d_279;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine6_req_rdata_valid <= 1'd0;
+	main_litedramcore_bankmachine6_row_close <= 1'd0;
 	case (builder_bankmachine6_state)
 		1'd1: begin
+			main_litedramcore_bankmachine6_row_close <= 1'd1;
 		end
 		2'd2: begin
+			main_litedramcore_bankmachine6_row_close <= 1'd1;
 		end
 		2'd3: begin
 		end
 		3'd4: begin
+			main_litedramcore_bankmachine6_row_close <= 1'd1;
 		end
 		3'd5: begin
 		end
@@ -11386,21 +11404,6 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine6_refresh_req) begin
-			end else begin
-				if (main_litedramcore_bankmachine6_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine6_row_opened) begin
-						if (main_litedramcore_bankmachine6_row_hit) begin
-							if (main_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
-							end else begin
-								main_litedramcore_bankmachine6_req_rdata_valid <= main_litedramcore_bankmachine6_cmd_ready;
-							end
-						end else begin
-						end
-					end else begin
-					end
-				end
-			end
 		end
 	endcase
 // synthesis translate_off
@@ -11571,22 +11574,15 @@ end
 reg dummy_d_284;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd0;
+	main_litedramcore_bankmachine6_req_rdata_valid <= 1'd0;
 	case (builder_bankmachine6_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin
-				main_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
-			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine6_trccon_ready) begin
-				main_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
-			end
 		end
 		3'd4: begin
-			main_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
 		end
 		3'd5: begin
 		end
@@ -11597,6 +11593,21 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
+			if (main_litedramcore_bankmachine6_refresh_req) begin
+			end else begin
+				if (main_litedramcore_bankmachine6_cmd_buffer_source_valid) begin
+					if (main_litedramcore_bankmachine6_row_opened) begin
+						if (main_litedramcore_bankmachine6_row_hit) begin
+							if (main_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
+							end else begin
+								main_litedramcore_bankmachine6_req_rdata_valid <= main_litedramcore_bankmachine6_cmd_ready;
+							end
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
 		end
 	endcase
 // synthesis translate_off
@@ -11608,15 +11619,22 @@ end
 reg dummy_d_285;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine6_cmd_payload_is_read <= 1'd0;
+	main_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd0;
 	case (builder_bankmachine6_state)
 		1'd1: begin
+			if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin
+				main_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
+			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
+			if (main_litedramcore_bankmachine6_trccon_ready) begin
+				main_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
+			end
 		end
 		3'd4: begin
+			main_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
 		end
 		3'd5: begin
 		end
@@ -11627,21 +11645,6 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
-			if (main_litedramcore_bankmachine6_refresh_req) begin
-			end else begin
-				if (main_litedramcore_bankmachine6_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine6_row_opened) begin
-						if (main_litedramcore_bankmachine6_row_hit) begin
-							if (main_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
-							end else begin
-								main_litedramcore_bankmachine6_cmd_payload_is_read <= 1'd1;
-							end
-						end else begin
-						end
-					end else begin
-					end
-				end
-			end
 		end
 	endcase
 // synthesis translate_off
@@ -11653,7 +11656,7 @@ end
 reg dummy_d_286;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine6_cmd_payload_is_write <= 1'd0;
+	main_litedramcore_bankmachine6_cmd_payload_is_read <= 1'd0;
 	case (builder_bankmachine6_state)
 		1'd1: begin
 		end
@@ -11678,8 +11681,8 @@ always @(*) begin
 					if (main_litedramcore_bankmachine6_row_opened) begin
 						if (main_litedramcore_bankmachine6_row_hit) begin
 							if (main_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
-								main_litedramcore_bankmachine6_cmd_payload_is_write <= 1'd1;
 							end else begin
+								main_litedramcore_bankmachine6_cmd_payload_is_read <= 1'd1;
 							end
 						end else begin
 						end
@@ -11698,7 +11701,7 @@ end
 reg dummy_d_287;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine6_req_wdata_ready <= 1'd0;
+	main_litedramcore_bankmachine6_cmd_payload_is_write <= 1'd0;
 	case (builder_bankmachine6_state)
 		1'd1: begin
 		end
@@ -11723,7 +11726,7 @@ always @(*) begin
 					if (main_litedramcore_bankmachine6_row_opened) begin
 						if (main_litedramcore_bankmachine6_row_hit) begin
 							if (main_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
-								main_litedramcore_bankmachine6_req_wdata_ready <= main_litedramcore_bankmachine6_cmd_ready;
+								main_litedramcore_bankmachine6_cmd_payload_is_write <= 1'd1;
 							end else begin
 							end
 						end else begin
@@ -11743,7 +11746,7 @@ end
 reg dummy_d_288;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine6_refresh_gnt <= 1'd0;
+	main_litedramcore_bankmachine6_req_wdata_ready <= 1'd0;
 	case (builder_bankmachine6_state)
 		1'd1: begin
 		end
@@ -11752,9 +11755,6 @@ always @(*) begin
 		2'd3: begin
 		end
 		3'd4: begin
-			if (main_litedramcore_bankmachine6_twtpcon_ready) begin
-				main_litedramcore_bankmachine6_refresh_gnt <= 1'd1;
-			end
 		end
 		3'd5: begin
 		end
@@ -11765,6 +11765,21 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
+			if (main_litedramcore_bankmachine6_refresh_req) begin
+			end else begin
+				if (main_litedramcore_bankmachine6_cmd_buffer_source_valid) begin
+					if (main_litedramcore_bankmachine6_row_opened) begin
+						if (main_litedramcore_bankmachine6_row_hit) begin
+							if (main_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
+								main_litedramcore_bankmachine6_req_wdata_ready <= main_litedramcore_bankmachine6_cmd_ready;
+							end else begin
+							end
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
 		end
 	endcase
 // synthesis translate_off
@@ -11776,44 +11791,29 @@ end
 reg dummy_d_289;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine6_cmd_valid <= 1'd0;
+	main_litedramcore_bankmachine6_refresh_gnt <= 1'd0;
 	case (builder_bankmachine6_state)
 		1'd1: begin
-			if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin
-				main_litedramcore_bankmachine6_cmd_valid <= 1'd1;
-			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
-			if (main_litedramcore_bankmachine6_trccon_ready) begin
-				main_litedramcore_bankmachine6_cmd_valid <= 1'd1;
-			end
 		end
 		3'd4: begin
-		end
-		3'd5: begin
-		end
-		3'd6: begin
-		end
-		3'd7: begin
-		end
-		4'd8: begin
-		end
-		default: begin
-			if (main_litedramcore_bankmachine6_refresh_req) begin
-			end else begin
-				if (main_litedramcore_bankmachine6_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine6_row_opened) begin
-						if (main_litedramcore_bankmachine6_row_hit) begin
-							main_litedramcore_bankmachine6_cmd_valid <= 1'd1;
-						end else begin
-						end
-					end else begin
-					end
-				end
+			if (main_litedramcore_bankmachine6_twtpcon_ready) begin
+				main_litedramcore_bankmachine6_refresh_gnt <= 1'd1;
 			end
 		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+		end
 	endcase
 // synthesis translate_off
 	dummy_d_289 = dummy_s;
@@ -11979,15 +11979,18 @@ end
 reg dummy_d_294;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine7_row_open <= 1'd0;
+	main_litedramcore_bankmachine7_cmd_valid <= 1'd0;
 	case (builder_bankmachine7_state)
 		1'd1: begin
+			if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin
+				main_litedramcore_bankmachine7_cmd_valid <= 1'd1;
+			end
 		end
 		2'd2: begin
 		end
 		2'd3: begin
 			if (main_litedramcore_bankmachine7_trccon_ready) begin
-				main_litedramcore_bankmachine7_row_open <= 1'd1;
+				main_litedramcore_bankmachine7_cmd_valid <= 1'd1;
 			end
 		end
 		3'd4: begin
@@ -12001,6 +12004,18 @@ always @(*) begin
 		4'd8: begin
 		end
 		default: begin
+			if (main_litedramcore_bankmachine7_refresh_req) begin
+			end else begin
+				if (main_litedramcore_bankmachine7_cmd_buffer_source_valid) begin
+					if (main_litedramcore_bankmachine7_row_opened) begin
+						if (main_litedramcore_bankmachine7_row_hit) begin
+							main_litedramcore_bankmachine7_cmd_valid <= 1'd1;
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
 		end
 	endcase
 // synthesis translate_off
@@ -12011,6 +12026,39 @@ end
 // synthesis translate_off
 reg dummy_d_295;
 // synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine7_row_open <= 1'd0;
+	case (builder_bankmachine7_state)
+		1'd1: begin
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+			if (main_litedramcore_bankmachine7_trccon_ready) begin
+				main_litedramcore_bankmachine7_row_open <= 1'd1;
+			end
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_295 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_296;
+// synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine7_row_close <= 1'd0;
 	case (builder_bankmachine7_state)
@@ -12037,12 +12085,12 @@ always @(*) begin
 		end
 	endcase
 // synthesis translate_off
-	dummy_d_295 = dummy_s;
+	dummy_d_296 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_296;
+reg dummy_d_297;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine7_cmd_payload_cas <= 1'd0;
@@ -12079,12 +12127,12 @@ always @(*) begin
 		end
 	endcase
 // synthesis translate_off
-	dummy_d_296 = dummy_s;
+	dummy_d_297 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_297;
+reg dummy_d_298;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine7_cmd_payload_ras <= 1'd0;
@@ -12115,12 +12163,12 @@ always @(*) begin
 		end
 	endcase
 // synthesis translate_off
-	dummy_d_297 = dummy_s;
+	dummy_d_298 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_298;
+reg dummy_d_299;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine7_cmd_payload_we <= 1'd0;
@@ -12163,12 +12211,12 @@ always @(*) begin
 		end
 	endcase
 // synthesis translate_off
-	dummy_d_298 = dummy_s;
+	dummy_d_299 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_299;
+reg dummy_d_300;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd0;
@@ -12196,12 +12244,12 @@ always @(*) begin
 		end
 	endcase
 // synthesis translate_off
-	dummy_d_299 = dummy_s;
+	dummy_d_300 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_300;
+reg dummy_d_301;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd0;
@@ -12233,15 +12281,15 @@ always @(*) begin
 		end
 	endcase
 // synthesis translate_off
-	dummy_d_300 = dummy_s;
+	dummy_d_301 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_301;
+reg dummy_d_302;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine7_req_rdata_valid <= 1'd0;
+	main_litedramcore_bankmachine7_cmd_payload_is_read <= 1'd0;
 	case (builder_bankmachine7_state)
 		1'd1: begin
 		end
@@ -12267,7 +12315,7 @@ always @(*) begin
 						if (main_litedramcore_bankmachine7_row_hit) begin
 							if (main_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
 							end else begin
-								main_litedramcore_bankmachine7_req_rdata_valid <= main_litedramcore_bankmachine7_cmd_ready;
+								main_litedramcore_bankmachine7_cmd_payload_is_read <= 1'd1;
 							end
 						end else begin
 						end
@@ -12278,15 +12326,15 @@ always @(*) begin
 		end
 	endcase
 // synthesis translate_off
-	dummy_d_301 = dummy_s;
+	dummy_d_302 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_302;
+reg dummy_d_303;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine7_cmd_payload_is_read <= 1'd0;
+	main_litedramcore_bankmachine7_cmd_payload_is_write <= 1'd0;
 	case (builder_bankmachine7_state)
 		1'd1: begin
 		end
@@ -12311,8 +12359,8 @@ always @(*) begin
 					if (main_litedramcore_bankmachine7_row_opened) begin
 						if (main_litedramcore_bankmachine7_row_hit) begin
 							if (main_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
+								main_litedramcore_bankmachine7_cmd_payload_is_write <= 1'd1;
 							end else begin
-								main_litedramcore_bankmachine7_cmd_payload_is_read <= 1'd1;
 							end
 						end else begin
 						end
@@ -12323,15 +12371,15 @@ always @(*) begin
 		end
 	endcase
 // synthesis translate_off
-	dummy_d_302 = dummy_s;
+	dummy_d_303 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_303;
+reg dummy_d_304;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine7_cmd_payload_is_write <= 1'd0;
+	main_litedramcore_bankmachine7_req_wdata_ready <= 1'd0;
 	case (builder_bankmachine7_state)
 		1'd1: begin
 		end
@@ -12356,7 +12404,7 @@ always @(*) begin
 					if (main_litedramcore_bankmachine7_row_opened) begin
 						if (main_litedramcore_bankmachine7_row_hit) begin
 							if (main_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
-								main_litedramcore_bankmachine7_cmd_payload_is_write <= 1'd1;
+								main_litedramcore_bankmachine7_req_wdata_ready <= main_litedramcore_bankmachine7_cmd_ready;
 							end else begin
 							end
 						end else begin
@@ -12368,15 +12416,15 @@ always @(*) begin
 		end
 	endcase
 // synthesis translate_off
-	dummy_d_303 = dummy_s;
+	dummy_d_304 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_304;
+reg dummy_d_305;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_bankmachine7_req_wdata_ready <= 1'd0;
+	main_litedramcore_bankmachine7_req_rdata_valid <= 1'd0;
 	case (builder_bankmachine7_state)
 		1'd1: begin
 		end
@@ -12401,8 +12449,8 @@ always @(*) begin
 					if (main_litedramcore_bankmachine7_row_opened) begin
 						if (main_litedramcore_bankmachine7_row_hit) begin
 							if (main_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
-								main_litedramcore_bankmachine7_req_wdata_ready <= main_litedramcore_bankmachine7_cmd_ready;
 							end else begin
+								main_litedramcore_bankmachine7_req_rdata_valid <= main_litedramcore_bankmachine7_cmd_ready;
 							end
 						end else begin
 						end
@@ -12413,12 +12461,12 @@ always @(*) begin
 		end
 	endcase
 // synthesis translate_off
-	dummy_d_304 = dummy_s;
+	dummy_d_305 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_305;
+reg dummy_d_306;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_bankmachine7_refresh_gnt <= 1'd0;
@@ -12445,54 +12493,6 @@ always @(*) begin
 		default: begin
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_305 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_306;
-// synthesis translate_on
-always @(*) begin
-	main_litedramcore_bankmachine7_cmd_valid <= 1'd0;
-	case (builder_bankmachine7_state)
-		1'd1: begin
-			if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin
-				main_litedramcore_bankmachine7_cmd_valid <= 1'd1;
-			end
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-			if (main_litedramcore_bankmachine7_trccon_ready) begin
-				main_litedramcore_bankmachine7_cmd_valid <= 1'd1;
-			end
-		end
-		3'd4: begin
-		end
-		3'd5: begin
-		end
-		3'd6: begin
-		end
-		3'd7: begin
-		end
-		4'd8: begin
-		end
-		default: begin
-			if (main_litedramcore_bankmachine7_refresh_req) begin
-			end else begin
-				if (main_litedramcore_bankmachine7_cmd_buffer_source_valid) begin
-					if (main_litedramcore_bankmachine7_row_opened) begin
-						if (main_litedramcore_bankmachine7_row_hit) begin
-							main_litedramcore_bankmachine7_cmd_valid <= 1'd1;
-						end else begin
-						end
-					end else begin
-					end
-				end
-			end
-		end
-	endcase
 // synthesis translate_off
 	dummy_d_306 = dummy_s;
 // synthesis translate_on
@@ -12867,9 +12867,13 @@ end
 reg dummy_d_324;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_en0 <= 1'd0;
+	main_litedramcore_choose_cmd_want_activates <= 1'd0;
 	case (builder_multiplexer_state)
 		1'd1: begin
+			if (1'd0) begin
+			end else begin
+				main_litedramcore_choose_cmd_want_activates <= main_litedramcore_ras_allowed;
+			end
 		end
 		2'd2: begin
 		end
@@ -12890,7 +12894,10 @@ always @(*) begin
 		4'd10: begin
 		end
 		default: begin
-			main_litedramcore_en0 <= 1'd1;
+			if (1'd0) begin
+			end else begin
+				main_litedramcore_choose_cmd_want_activates <= main_litedramcore_ras_allowed;
+			end
 		end
 	endcase
 // synthesis translate_off
@@ -12902,12 +12909,15 @@ end
 reg dummy_d_325;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_choose_cmd_cmd_ready <= 1'd0;
+	main_litedramcore_steerer_sel3 <= 2'd0;
 	case (builder_multiplexer_state)
 		1'd1: begin
-			if (1'd0) begin
-			end else begin
-				main_litedramcore_choose_cmd_cmd_ready <= ((~((main_litedramcore_choose_cmd_cmd_payload_ras & (~main_litedramcore_choose_cmd_cmd_payload_cas)) & (~main_litedramcore_choose_cmd_cmd_payload_we))) | main_litedramcore_ras_allowed);
+			main_litedramcore_steerer_sel3 <= 1'd0;
+			if ((main_k7ddrphy_wrphase_storage == 2'd3)) begin
+				main_litedramcore_steerer_sel3 <= 2'd2;
+			end
+			if ((main_litedramcore_wrcmdphase == 2'd3)) begin
+				main_litedramcore_steerer_sel3 <= 1'd1;
 			end
 		end
 		2'd2: begin
@@ -12929,9 +12939,12 @@ always @(*) begin
 		4'd10: begin
 		end
 		default: begin
-			if (1'd0) begin
-			end else begin
-				main_litedramcore_choose_cmd_cmd_ready <= ((~((main_litedramcore_choose_cmd_cmd_payload_ras & (~main_litedramcore_choose_cmd_cmd_payload_cas)) & (~main_litedramcore_choose_cmd_cmd_payload_we))) | main_litedramcore_ras_allowed);
+			main_litedramcore_steerer_sel3 <= 1'd0;
+			if ((main_k7ddrphy_rdphase_storage == 2'd3)) begin
+				main_litedramcore_steerer_sel3 <= 2'd2;
+			end
+			if ((main_litedramcore_rdcmdphase == 2'd3)) begin
+				main_litedramcore_steerer_sel3 <= 1'd1;
 			end
 		end
 	endcase
@@ -12944,7 +12957,7 @@ end
 reg dummy_d_326;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_choose_req_want_reads <= 1'd0;
+	main_litedramcore_en0 <= 1'd0;
 	case (builder_multiplexer_state)
 		1'd1: begin
 		end
@@ -12967,7 +12980,7 @@ always @(*) begin
 		4'd10: begin
 		end
 		default: begin
-			main_litedramcore_choose_req_want_reads <= 1'd1;
+			main_litedramcore_en0 <= 1'd1;
 		end
 	endcase
 // synthesis translate_off
@@ -12979,10 +12992,13 @@ end
 reg dummy_d_327;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_choose_req_want_writes <= 1'd0;
+	main_litedramcore_choose_cmd_cmd_ready <= 1'd0;
 	case (builder_multiplexer_state)
 		1'd1: begin
-			main_litedramcore_choose_req_want_writes <= 1'd1;
+			if (1'd0) begin
+			end else begin
+				main_litedramcore_choose_cmd_cmd_ready <= ((~((main_litedramcore_choose_cmd_cmd_payload_ras & (~main_litedramcore_choose_cmd_cmd_payload_cas)) & (~main_litedramcore_choose_cmd_cmd_payload_we))) | main_litedramcore_ras_allowed);
+			end
 		end
 		2'd2: begin
 		end
@@ -13003,6 +13019,10 @@ always @(*) begin
 		4'd10: begin
 		end
 		default: begin
+			if (1'd0) begin
+			end else begin
+				main_litedramcore_choose_cmd_cmd_ready <= ((~((main_litedramcore_choose_cmd_cmd_payload_ras & (~main_litedramcore_choose_cmd_cmd_payload_cas)) & (~main_litedramcore_choose_cmd_cmd_payload_we))) | main_litedramcore_ras_allowed);
+			end
 		end
 	endcase
 // synthesis translate_off
@@ -13014,14 +13034,9 @@ end
 reg dummy_d_328;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_choose_req_cmd_ready <= 1'd0;
+	main_litedramcore_choose_req_want_reads <= 1'd0;
 	case (builder_multiplexer_state)
 		1'd1: begin
-			if (1'd0) begin
-				main_litedramcore_choose_req_cmd_ready <= (main_litedramcore_cas_allowed & ((~((main_litedramcore_choose_req_cmd_payload_ras & (~main_litedramcore_choose_req_cmd_payload_cas)) & (~main_litedramcore_choose_req_cmd_payload_we))) | main_litedramcore_ras_allowed));
-			end else begin
-				main_litedramcore_choose_req_cmd_ready <= main_litedramcore_cas_allowed;
-			end
 		end
 		2'd2: begin
 		end
@@ -13042,31 +13057,60 @@ always @(*) begin
 		4'd10: begin
 		end
 		default: begin
-			if (1'd0) begin
-				main_litedramcore_choose_req_cmd_ready <= (main_litedramcore_cas_allowed & ((~((main_litedramcore_choose_req_cmd_payload_ras & (~main_litedramcore_choose_req_cmd_payload_cas)) & (~main_litedramcore_choose_req_cmd_payload_we))) | main_litedramcore_ras_allowed));
-			end else begin
-				main_litedramcore_choose_req_cmd_ready <= main_litedramcore_cas_allowed;
-			end
+			main_litedramcore_choose_req_want_reads <= 1'd1;
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_328 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_329;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_choose_req_want_writes <= 1'd0;
+	case (builder_multiplexer_state)
+		1'd1: begin
+			main_litedramcore_choose_req_want_writes <= 1'd1;
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		4'd9: begin
+		end
+		4'd10: begin
+		end
+		default: begin
 		end
 	endcase
 // synthesis translate_off
-	dummy_d_328 = dummy_s;
+	dummy_d_329 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_329;
+reg dummy_d_330;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_steerer_sel3 <= 2'd0;
+	main_litedramcore_choose_req_cmd_ready <= 1'd0;
 	case (builder_multiplexer_state)
 		1'd1: begin
-			main_litedramcore_steerer_sel3 <= 1'd0;
-			if ((main_k7ddrphy_wrphase_storage == 2'd3)) begin
-				main_litedramcore_steerer_sel3 <= 2'd2;
-			end
-			if ((main_litedramcore_wrcmdphase == 2'd3)) begin
-				main_litedramcore_steerer_sel3 <= 1'd1;
+			if (1'd0) begin
+				main_litedramcore_choose_req_cmd_ready <= (main_litedramcore_cas_allowed & ((~((main_litedramcore_choose_req_cmd_payload_ras & (~main_litedramcore_choose_req_cmd_payload_cas)) & (~main_litedramcore_choose_req_cmd_payload_we))) | main_litedramcore_ras_allowed));
+			end else begin
+				main_litedramcore_choose_req_cmd_ready <= main_litedramcore_cas_allowed;
 			end
 		end
 		2'd2: begin
@@ -13088,22 +13132,20 @@ always @(*) begin
 		4'd10: begin
 		end
 		default: begin
-			main_litedramcore_steerer_sel3 <= 1'd0;
-			if ((main_k7ddrphy_rdphase_storage == 2'd3)) begin
-				main_litedramcore_steerer_sel3 <= 2'd2;
-			end
-			if ((main_litedramcore_rdcmdphase == 2'd3)) begin
-				main_litedramcore_steerer_sel3 <= 1'd1;
+			if (1'd0) begin
+				main_litedramcore_choose_req_cmd_ready <= (main_litedramcore_cas_allowed & ((~((main_litedramcore_choose_req_cmd_payload_ras & (~main_litedramcore_choose_req_cmd_payload_cas)) & (~main_litedramcore_choose_req_cmd_payload_we))) | main_litedramcore_ras_allowed));
+			end else begin
+				main_litedramcore_choose_req_cmd_ready <= main_litedramcore_cas_allowed;
 			end
 		end
 	endcase
 // synthesis translate_off
-	dummy_d_329 = dummy_s;
+	dummy_d_330 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_330;
+reg dummy_d_331;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_en1 <= 1'd0;
@@ -13133,12 +13175,12 @@ always @(*) begin
 		end
 	endcase
 // synthesis translate_off
-	dummy_d_330 = dummy_s;
+	dummy_d_331 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_331;
+reg dummy_d_332;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_steerer_sel0 <= 2'd0;
@@ -13182,12 +13224,12 @@ always @(*) begin
 		end
 	endcase
 // synthesis translate_off
-	dummy_d_331 = dummy_s;
+	dummy_d_332 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_332;
+reg dummy_d_333;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_cmd_ready <= 1'd0;
@@ -13217,12 +13259,12 @@ always @(*) begin
 		end
 	endcase
 // synthesis translate_off
-	dummy_d_332 = dummy_s;
+	dummy_d_333 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_333;
+reg dummy_d_334;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_steerer_sel1 <= 2'd0;
@@ -13265,12 +13307,12 @@ always @(*) begin
 		end
 	endcase
 // synthesis translate_off
-	dummy_d_333 = dummy_s;
+	dummy_d_334 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_334;
+reg dummy_d_335;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_steerer_sel2 <= 2'd0;
@@ -13312,48 +13354,6 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_334 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_335;
-// synthesis translate_on
-always @(*) begin
-	main_litedramcore_choose_cmd_want_activates <= 1'd0;
-	case (builder_multiplexer_state)
-		1'd1: begin
-			if (1'd0) begin
-			end else begin
-				main_litedramcore_choose_cmd_want_activates <= main_litedramcore_ras_allowed;
-			end
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-		end
-		3'd4: begin
-		end
-		3'd5: begin
-		end
-		3'd6: begin
-		end
-		3'd7: begin
-		end
-		4'd8: begin
-		end
-		4'd9: begin
-		end
-		4'd10: begin
-		end
-		default: begin
-			if (1'd0) begin
-			end else begin
-				main_litedramcore_choose_cmd_want_activates <= main_litedramcore_ras_allowed;
-			end
-		end
-	endcase
 // synthesis translate_off
 	dummy_d_335 = dummy_s;
 // synthesis translate_on
@@ -13406,13 +13406,13 @@ assign main_user_port_rdata_valid = builder_new_master_rdata_valid8;
 reg dummy_d_336;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_interface_wdata <= 256'd0;
+	main_litedramcore_interface_wdata_we <= 32'd0;
 	case ({builder_new_master_wdata_ready1})
 		1'd1: begin
-			main_litedramcore_interface_wdata <= main_user_port_wdata_payload_data;
+			main_litedramcore_interface_wdata_we <= main_user_port_wdata_payload_we;
 		end
 		default: begin
-			main_litedramcore_interface_wdata <= 1'd0;
+			main_litedramcore_interface_wdata_we <= 1'd0;
 		end
 	endcase
 // synthesis translate_off
@@ -13424,13 +13424,13 @@ end
 reg dummy_d_337;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_interface_wdata_we <= 32'd0;
+	main_litedramcore_interface_wdata <= 256'd0;
 	case ({builder_new_master_wdata_ready1})
 		1'd1: begin
-			main_litedramcore_interface_wdata_we <= main_user_port_wdata_payload_we;
+			main_litedramcore_interface_wdata <= main_user_port_wdata_payload_data;
 		end
 		default: begin
-			main_litedramcore_interface_wdata_we <= 1'd0;
+			main_litedramcore_interface_wdata <= 1'd0;
 		end
 	endcase
 // synthesis translate_off
@@ -13645,7 +13645,7 @@ assign builder_litedramcore_wishbone_we = main_wb_bus_we;
 assign builder_litedramcore_wishbone_cti = main_wb_bus_cti;
 assign builder_litedramcore_wishbone_bte = main_wb_bus_bte;
 assign main_wb_bus_err = builder_litedramcore_wishbone_err;
-assign builder_csrbank0_sel = (builder_interface0_bank_bus_adr[13:9] == 1'd0);
+assign builder_csrbank0_sel = (builder_interface0_bank_bus_adr[13:9] == 1'd1);
 assign builder_csrbank0_init_done0_r = builder_interface0_bank_bus_dat_w[0];
 
 // synthesis translate_off
@@ -13679,9 +13679,9 @@ assign builder_csrbank0_init_error0_r = builder_interface0_bank_bus_dat_w[0];
 reg dummy_d_349;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank0_init_error0_re <= 1'd0;
+	builder_csrbank0_init_error0_we <= 1'd0;
 	if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd1))) begin
-		builder_csrbank0_init_error0_re <= builder_interface0_bank_bus_we;
+		builder_csrbank0_init_error0_we <= (~builder_interface0_bank_bus_we);
 	end
 // synthesis translate_off
 	dummy_d_349 = dummy_s;
@@ -13692,9 +13692,9 @@ end
 reg dummy_d_350;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank0_init_error0_we <= 1'd0;
+	builder_csrbank0_init_error0_re <= 1'd0;
 	if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd1))) begin
-		builder_csrbank0_init_error0_we <= (~builder_interface0_bank_bus_we);
+		builder_csrbank0_init_error0_re <= builder_interface0_bank_bus_we;
 	end
 // synthesis translate_off
 	dummy_d_350 = dummy_s;
@@ -13702,16 +13702,16 @@ always @(*) begin
 end
 assign builder_csrbank0_init_done0_w = main_init_done_storage;
 assign builder_csrbank0_init_error0_w = main_init_error_storage;
-assign builder_csrbank1_sel = (builder_interface1_bank_bus_adr[13:9] == 1'd1);
+assign builder_csrbank1_sel = (builder_interface1_bank_bus_adr[13:9] == 2'd2);
 assign builder_csrbank1_rst0_r = builder_interface1_bank_bus_dat_w[0];
 
 // synthesis translate_off
 reg dummy_d_351;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank1_rst0_re <= 1'd0;
+	builder_csrbank1_rst0_we <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd0))) begin
-		builder_csrbank1_rst0_re <= builder_interface1_bank_bus_we;
+		builder_csrbank1_rst0_we <= (~builder_interface1_bank_bus_we);
 	end
 // synthesis translate_off
 	dummy_d_351 = dummy_s;
@@ -13722,9 +13722,9 @@ end
 reg dummy_d_352;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank1_rst0_we <= 1'd0;
+	builder_csrbank1_rst0_re <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd0))) begin
-		builder_csrbank1_rst0_we <= (~builder_interface1_bank_bus_we);
+		builder_csrbank1_rst0_re <= builder_interface1_bank_bus_we;
 	end
 // synthesis translate_off
 	dummy_d_352 = dummy_s;
@@ -13736,9 +13736,9 @@ assign builder_csrbank1_half_sys8x_taps0_r = builder_interface1_bank_bus_dat_w[4
 reg dummy_d_353;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank1_half_sys8x_taps0_we <= 1'd0;
+	builder_csrbank1_half_sys8x_taps0_re <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd1))) begin
-		builder_csrbank1_half_sys8x_taps0_we <= (~builder_interface1_bank_bus_we);
+		builder_csrbank1_half_sys8x_taps0_re <= builder_interface1_bank_bus_we;
 	end
 // synthesis translate_off
 	dummy_d_353 = dummy_s;
@@ -13749,9 +13749,9 @@ end
 reg dummy_d_354;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank1_half_sys8x_taps0_re <= 1'd0;
+	builder_csrbank1_half_sys8x_taps0_we <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd1))) begin
-		builder_csrbank1_half_sys8x_taps0_re <= builder_interface1_bank_bus_we;
+		builder_csrbank1_half_sys8x_taps0_we <= (~builder_interface1_bank_bus_we);
 	end
 // synthesis translate_off
 	dummy_d_354 = dummy_s;
@@ -13790,9 +13790,9 @@ assign main_k7ddrphy_wlevel_strobe_r = builder_interface1_bank_bus_dat_w[0];
 reg dummy_d_357;
 // synthesis translate_on
 always @(*) begin
-	main_k7ddrphy_wlevel_strobe_re <= 1'd0;
+	main_k7ddrphy_wlevel_strobe_we <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd3))) begin
-		main_k7ddrphy_wlevel_strobe_re <= builder_interface1_bank_bus_we;
+		main_k7ddrphy_wlevel_strobe_we <= (~builder_interface1_bank_bus_we);
 	end
 // synthesis translate_off
 	dummy_d_357 = dummy_s;
@@ -13803,9 +13803,9 @@ end
 reg dummy_d_358;
 // synthesis translate_on
 always @(*) begin
-	main_k7ddrphy_wlevel_strobe_we <= 1'd0;
+	main_k7ddrphy_wlevel_strobe_re <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd3))) begin
-		main_k7ddrphy_wlevel_strobe_we <= (~builder_interface1_bank_bus_we);
+		main_k7ddrphy_wlevel_strobe_re <= builder_interface1_bank_bus_we;
 	end
 // synthesis translate_off
 	dummy_d_358 = dummy_s;
@@ -13898,9 +13898,9 @@ assign main_k7ddrphy_rdly_dq_rst_r = builder_interface1_bank_bus_dat_w[0];
 reg dummy_d_365;
 // synthesis translate_on
 always @(*) begin
-	main_k7ddrphy_rdly_dq_rst_re <= 1'd0;
+	main_k7ddrphy_rdly_dq_rst_we <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd7))) begin
-		main_k7ddrphy_rdly_dq_rst_re <= builder_interface1_bank_bus_we;
+		main_k7ddrphy_rdly_dq_rst_we <= (~builder_interface1_bank_bus_we);
 	end
 // synthesis translate_off
 	dummy_d_365 = dummy_s;
@@ -13911,9 +13911,9 @@ end
 reg dummy_d_366;
 // synthesis translate_on
 always @(*) begin
-	main_k7ddrphy_rdly_dq_rst_we <= 1'd0;
+	main_k7ddrphy_rdly_dq_rst_re <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd7))) begin
-		main_k7ddrphy_rdly_dq_rst_we <= (~builder_interface1_bank_bus_we);
+		main_k7ddrphy_rdly_dq_rst_re <= builder_interface1_bank_bus_we;
 	end
 // synthesis translate_off
 	dummy_d_366 = dummy_s;
@@ -14006,9 +14006,9 @@ assign main_k7ddrphy_wdly_dq_rst_r = builder_interface1_bank_bus_dat_w[0];
 reg dummy_d_373;
 // synthesis translate_on
 always @(*) begin
-	main_k7ddrphy_wdly_dq_rst_we <= 1'd0;
+	main_k7ddrphy_wdly_dq_rst_re <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd11))) begin
-		main_k7ddrphy_wdly_dq_rst_we <= (~builder_interface1_bank_bus_we);
+		main_k7ddrphy_wdly_dq_rst_re <= builder_interface1_bank_bus_we;
 	end
 // synthesis translate_off
 	dummy_d_373 = dummy_s;
@@ -14019,9 +14019,9 @@ end
 reg dummy_d_374;
 // synthesis translate_on
 always @(*) begin
-	main_k7ddrphy_wdly_dq_rst_re <= 1'd0;
+	main_k7ddrphy_wdly_dq_rst_we <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd11))) begin
-		main_k7ddrphy_wdly_dq_rst_re <= builder_interface1_bank_bus_we;
+		main_k7ddrphy_wdly_dq_rst_we <= (~builder_interface1_bank_bus_we);
 	end
 // synthesis translate_off
 	dummy_d_374 = dummy_s;
@@ -14114,9 +14114,9 @@ assign main_k7ddrphy_wdly_dq_bitslip_rst_r = builder_interface1_bank_bus_dat_w[0
 reg dummy_d_381;
 // synthesis translate_on
 always @(*) begin
-	main_k7ddrphy_wdly_dq_bitslip_rst_re <= 1'd0;
+	main_k7ddrphy_wdly_dq_bitslip_rst_we <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd15))) begin
-		main_k7ddrphy_wdly_dq_bitslip_rst_re <= builder_interface1_bank_bus_we;
+		main_k7ddrphy_wdly_dq_bitslip_rst_we <= (~builder_interface1_bank_bus_we);
 	end
 // synthesis translate_off
 	dummy_d_381 = dummy_s;
@@ -14127,9 +14127,9 @@ end
 reg dummy_d_382;
 // synthesis translate_on
 always @(*) begin
-	main_k7ddrphy_wdly_dq_bitslip_rst_we <= 1'd0;
+	main_k7ddrphy_wdly_dq_bitslip_rst_re <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd15))) begin
-		main_k7ddrphy_wdly_dq_bitslip_rst_we <= (~builder_interface1_bank_bus_we);
+		main_k7ddrphy_wdly_dq_bitslip_rst_re <= builder_interface1_bank_bus_we;
 	end
 // synthesis translate_off
 	dummy_d_382 = dummy_s;
@@ -14168,9 +14168,9 @@ assign builder_csrbank1_rdphase0_r = builder_interface1_bank_bus_dat_w[1:0];
 reg dummy_d_385;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank1_rdphase0_we <= 1'd0;
+	builder_csrbank1_rdphase0_re <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 5'd17))) begin
-		builder_csrbank1_rdphase0_we <= (~builder_interface1_bank_bus_we);
+		builder_csrbank1_rdphase0_re <= builder_interface1_bank_bus_we;
 	end
 // synthesis translate_off
 	dummy_d_385 = dummy_s;
@@ -14181,9 +14181,9 @@ end
 reg dummy_d_386;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank1_rdphase0_re <= 1'd0;
+	builder_csrbank1_rdphase0_we <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 5'd17))) begin
-		builder_csrbank1_rdphase0_re <= builder_interface1_bank_bus_we;
+		builder_csrbank1_rdphase0_we <= (~builder_interface1_bank_bus_we);
 	end
 // synthesis translate_off
 	dummy_d_386 = dummy_s;
@@ -14195,9 +14195,9 @@ assign builder_csrbank1_wrphase0_r = builder_interface1_bank_bus_dat_w[1:0];
 reg dummy_d_387;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank1_wrphase0_re <= 1'd0;
+	builder_csrbank1_wrphase0_we <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 5'd18))) begin
-		builder_csrbank1_wrphase0_re <= builder_interface1_bank_bus_we;
+		builder_csrbank1_wrphase0_we <= (~builder_interface1_bank_bus_we);
 	end
 // synthesis translate_off
 	dummy_d_387 = dummy_s;
@@ -14208,9 +14208,9 @@ end
 reg dummy_d_388;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank1_wrphase0_we <= 1'd0;
+	builder_csrbank1_wrphase0_re <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 5'd18))) begin
-		builder_csrbank1_wrphase0_we <= (~builder_interface1_bank_bus_we);
+		builder_csrbank1_wrphase0_re <= builder_interface1_bank_bus_we;
 	end
 // synthesis translate_off
 	dummy_d_388 = dummy_s;
@@ -14222,7 +14222,7 @@ assign builder_csrbank1_wlevel_en0_w = main_k7ddrphy_wlevel_en_storage;
 assign builder_csrbank1_dly_sel0_w = main_k7ddrphy_dly_sel_storage[3:0];
 assign builder_csrbank1_rdphase0_w = main_k7ddrphy_rdphase_storage[1:0];
 assign builder_csrbank1_wrphase0_w = main_k7ddrphy_wrphase_storage[1:0];
-assign builder_csrbank2_sel = (builder_interface2_bank_bus_adr[13:9] == 2'd2);
+assign builder_csrbank2_sel = (builder_interface2_bank_bus_adr[13:9] == 1'd0);
 assign builder_csrbank2_dfii_control0_r = builder_interface2_bank_bus_dat_w[3:0];
 
 // synthesis translate_off
@@ -14283,9 +14283,9 @@ assign main_litedramcore_phaseinjector0_command_issue_r = builder_interface2_ban
 reg dummy_d_393;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_phaseinjector0_command_issue_we <= 1'd0;
+	main_litedramcore_phaseinjector0_command_issue_re <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd2))) begin
-		main_litedramcore_phaseinjector0_command_issue_we <= (~builder_interface2_bank_bus_we);
+		main_litedramcore_phaseinjector0_command_issue_re <= builder_interface2_bank_bus_we;
 	end
 // synthesis translate_off
 	dummy_d_393 = dummy_s;
@@ -14296,9 +14296,9 @@ end
 reg dummy_d_394;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_phaseinjector0_command_issue_re <= 1'd0;
+	main_litedramcore_phaseinjector0_command_issue_we <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd2))) begin
-		main_litedramcore_phaseinjector0_command_issue_re <= builder_interface2_bank_bus_we;
+		main_litedramcore_phaseinjector0_command_issue_we <= (~builder_interface2_bank_bus_we);
 	end
 // synthesis translate_off
 	dummy_d_394 = dummy_s;
@@ -14310,9 +14310,9 @@ assign builder_csrbank2_dfii_pi0_address1_r = builder_interface2_bank_bus_dat_w[
 reg dummy_d_395;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi0_address1_we <= 1'd0;
+	builder_csrbank2_dfii_pi0_address1_re <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd3))) begin
-		builder_csrbank2_dfii_pi0_address1_we <= (~builder_interface2_bank_bus_we);
+		builder_csrbank2_dfii_pi0_address1_re <= builder_interface2_bank_bus_we;
 	end
 // synthesis translate_off
 	dummy_d_395 = dummy_s;
@@ -14323,9 +14323,9 @@ end
 reg dummy_d_396;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi0_address1_re <= 1'd0;
+	builder_csrbank2_dfii_pi0_address1_we <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd3))) begin
-		builder_csrbank2_dfii_pi0_address1_re <= builder_interface2_bank_bus_we;
+		builder_csrbank2_dfii_pi0_address1_we <= (~builder_interface2_bank_bus_we);
 	end
 // synthesis translate_off
 	dummy_d_396 = dummy_s;
@@ -14337,9 +14337,9 @@ assign builder_csrbank2_dfii_pi0_address0_r = builder_interface2_bank_bus_dat_w[
 reg dummy_d_397;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi0_address0_re <= 1'd0;
+	builder_csrbank2_dfii_pi0_address0_we <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd4))) begin
-		builder_csrbank2_dfii_pi0_address0_re <= builder_interface2_bank_bus_we;
+		builder_csrbank2_dfii_pi0_address0_we <= (~builder_interface2_bank_bus_we);
 	end
 // synthesis translate_off
 	dummy_d_397 = dummy_s;
@@ -14350,9 +14350,9 @@ end
 reg dummy_d_398;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi0_address0_we <= 1'd0;
+	builder_csrbank2_dfii_pi0_address0_re <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd4))) begin
-		builder_csrbank2_dfii_pi0_address0_we <= (~builder_interface2_bank_bus_we);
+		builder_csrbank2_dfii_pi0_address0_re <= builder_interface2_bank_bus_we;
 	end
 // synthesis translate_off
 	dummy_d_398 = dummy_s;
@@ -14418,9 +14418,9 @@ assign builder_csrbank2_dfii_pi0_wrdata6_r = builder_interface2_bank_bus_dat_w[7
 reg dummy_d_403;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi0_wrdata6_re <= 1'd0;
+	builder_csrbank2_dfii_pi0_wrdata6_we <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd7))) begin
-		builder_csrbank2_dfii_pi0_wrdata6_re <= builder_interface2_bank_bus_we;
+		builder_csrbank2_dfii_pi0_wrdata6_we <= (~builder_interface2_bank_bus_we);
 	end
 // synthesis translate_off
 	dummy_d_403 = dummy_s;
@@ -14431,9 +14431,9 @@ end
 reg dummy_d_404;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi0_wrdata6_we <= 1'd0;
+	builder_csrbank2_dfii_pi0_wrdata6_re <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd7))) begin
-		builder_csrbank2_dfii_pi0_wrdata6_we <= (~builder_interface2_bank_bus_we);
+		builder_csrbank2_dfii_pi0_wrdata6_re <= builder_interface2_bank_bus_we;
 	end
 // synthesis translate_off
 	dummy_d_404 = dummy_s;
@@ -14445,9 +14445,9 @@ assign builder_csrbank2_dfii_pi0_wrdata5_r = builder_interface2_bank_bus_dat_w[7
 reg dummy_d_405;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi0_wrdata5_we <= 1'd0;
+	builder_csrbank2_dfii_pi0_wrdata5_re <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd8))) begin
-		builder_csrbank2_dfii_pi0_wrdata5_we <= (~builder_interface2_bank_bus_we);
+		builder_csrbank2_dfii_pi0_wrdata5_re <= builder_interface2_bank_bus_we;
 	end
 // synthesis translate_off
 	dummy_d_405 = dummy_s;
@@ -14458,9 +14458,9 @@ end
 reg dummy_d_406;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi0_wrdata5_re <= 1'd0;
+	builder_csrbank2_dfii_pi0_wrdata5_we <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd8))) begin
-		builder_csrbank2_dfii_pi0_wrdata5_re <= builder_interface2_bank_bus_we;
+		builder_csrbank2_dfii_pi0_wrdata5_we <= (~builder_interface2_bank_bus_we);
 	end
 // synthesis translate_off
 	dummy_d_406 = dummy_s;
@@ -14526,9 +14526,9 @@ assign builder_csrbank2_dfii_pi0_wrdata2_r = builder_interface2_bank_bus_dat_w[7
 reg dummy_d_411;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi0_wrdata2_we <= 1'd0;
+	builder_csrbank2_dfii_pi0_wrdata2_re <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd11))) begin
-		builder_csrbank2_dfii_pi0_wrdata2_we <= (~builder_interface2_bank_bus_we);
+		builder_csrbank2_dfii_pi0_wrdata2_re <= builder_interface2_bank_bus_we;
 	end
 // synthesis translate_off
 	dummy_d_411 = dummy_s;
@@ -14539,9 +14539,9 @@ end
 reg dummy_d_412;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi0_wrdata2_re <= 1'd0;
+	builder_csrbank2_dfii_pi0_wrdata2_we <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd11))) begin
-		builder_csrbank2_dfii_pi0_wrdata2_re <= builder_interface2_bank_bus_we;
+		builder_csrbank2_dfii_pi0_wrdata2_we <= (~builder_interface2_bank_bus_we);
 	end
 // synthesis translate_off
 	dummy_d_412 = dummy_s;
@@ -14553,9 +14553,9 @@ assign builder_csrbank2_dfii_pi0_wrdata1_r = builder_interface2_bank_bus_dat_w[7
 reg dummy_d_413;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi0_wrdata1_re <= 1'd0;
+	builder_csrbank2_dfii_pi0_wrdata1_we <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd12))) begin
-		builder_csrbank2_dfii_pi0_wrdata1_re <= builder_interface2_bank_bus_we;
+		builder_csrbank2_dfii_pi0_wrdata1_we <= (~builder_interface2_bank_bus_we);
 	end
 // synthesis translate_off
 	dummy_d_413 = dummy_s;
@@ -14566,9 +14566,9 @@ end
 reg dummy_d_414;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi0_wrdata1_we <= 1'd0;
+	builder_csrbank2_dfii_pi0_wrdata1_re <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd12))) begin
-		builder_csrbank2_dfii_pi0_wrdata1_we <= (~builder_interface2_bank_bus_we);
+		builder_csrbank2_dfii_pi0_wrdata1_re <= builder_interface2_bank_bus_we;
 	end
 // synthesis translate_off
 	dummy_d_414 = dummy_s;
@@ -14634,9 +14634,9 @@ assign builder_csrbank2_dfii_pi0_rddata6_r = builder_interface2_bank_bus_dat_w[7
 reg dummy_d_419;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi0_rddata6_re <= 1'd0;
+	builder_csrbank2_dfii_pi0_rddata6_we <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd15))) begin
-		builder_csrbank2_dfii_pi0_rddata6_re <= builder_interface2_bank_bus_we;
+		builder_csrbank2_dfii_pi0_rddata6_we <= (~builder_interface2_bank_bus_we);
 	end
 // synthesis translate_off
 	dummy_d_419 = dummy_s;
@@ -14647,9 +14647,9 @@ end
 reg dummy_d_420;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi0_rddata6_we <= 1'd0;
+	builder_csrbank2_dfii_pi0_rddata6_re <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd15))) begin
-		builder_csrbank2_dfii_pi0_rddata6_we <= (~builder_interface2_bank_bus_we);
+		builder_csrbank2_dfii_pi0_rddata6_re <= builder_interface2_bank_bus_we;
 	end
 // synthesis translate_off
 	dummy_d_420 = dummy_s;
@@ -14688,9 +14688,9 @@ assign builder_csrbank2_dfii_pi0_rddata4_r = builder_interface2_bank_bus_dat_w[7
 reg dummy_d_423;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi0_rddata4_we <= 1'd0;
+	builder_csrbank2_dfii_pi0_rddata4_re <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd17))) begin
-		builder_csrbank2_dfii_pi0_rddata4_we <= (~builder_interface2_bank_bus_we);
+		builder_csrbank2_dfii_pi0_rddata4_re <= builder_interface2_bank_bus_we;
 	end
 // synthesis translate_off
 	dummy_d_423 = dummy_s;
@@ -14701,9 +14701,9 @@ end
 reg dummy_d_424;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi0_rddata4_re <= 1'd0;
+	builder_csrbank2_dfii_pi0_rddata4_we <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd17))) begin
-		builder_csrbank2_dfii_pi0_rddata4_re <= builder_interface2_bank_bus_we;
+		builder_csrbank2_dfii_pi0_rddata4_we <= (~builder_interface2_bank_bus_we);
 	end
 // synthesis translate_off
 	dummy_d_424 = dummy_s;
@@ -14742,9 +14742,9 @@ assign builder_csrbank2_dfii_pi0_rddata2_r = builder_interface2_bank_bus_dat_w[7
 reg dummy_d_427;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi0_rddata2_re <= 1'd0;
+	builder_csrbank2_dfii_pi0_rddata2_we <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd19))) begin
-		builder_csrbank2_dfii_pi0_rddata2_re <= builder_interface2_bank_bus_we;
+		builder_csrbank2_dfii_pi0_rddata2_we <= (~builder_interface2_bank_bus_we);
 	end
 // synthesis translate_off
 	dummy_d_427 = dummy_s;
@@ -14755,9 +14755,9 @@ end
 reg dummy_d_428;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi0_rddata2_we <= 1'd0;
+	builder_csrbank2_dfii_pi0_rddata2_re <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd19))) begin
-		builder_csrbank2_dfii_pi0_rddata2_we <= (~builder_interface2_bank_bus_we);
+		builder_csrbank2_dfii_pi0_rddata2_re <= builder_interface2_bank_bus_we;
 	end
 // synthesis translate_off
 	dummy_d_428 = dummy_s;
@@ -14796,9 +14796,9 @@ assign builder_csrbank2_dfii_pi0_rddata0_r = builder_interface2_bank_bus_dat_w[7
 reg dummy_d_431;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi0_rddata0_we <= 1'd0;
+	builder_csrbank2_dfii_pi0_rddata0_re <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd21))) begin
-		builder_csrbank2_dfii_pi0_rddata0_we <= (~builder_interface2_bank_bus_we);
+		builder_csrbank2_dfii_pi0_rddata0_re <= builder_interface2_bank_bus_we;
 	end
 // synthesis translate_off
 	dummy_d_431 = dummy_s;
@@ -14809,9 +14809,9 @@ end
 reg dummy_d_432;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi0_rddata0_re <= 1'd0;
+	builder_csrbank2_dfii_pi0_rddata0_we <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd21))) begin
-		builder_csrbank2_dfii_pi0_rddata0_re <= builder_interface2_bank_bus_we;
+		builder_csrbank2_dfii_pi0_rddata0_we <= (~builder_interface2_bank_bus_we);
 	end
 // synthesis translate_off
 	dummy_d_432 = dummy_s;
@@ -14850,9 +14850,9 @@ assign main_litedramcore_phaseinjector1_command_issue_r = builder_interface2_ban
 reg dummy_d_435;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_phaseinjector1_command_issue_we <= 1'd0;
+	main_litedramcore_phaseinjector1_command_issue_re <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd23))) begin
-		main_litedramcore_phaseinjector1_command_issue_we <= (~builder_interface2_bank_bus_we);
+		main_litedramcore_phaseinjector1_command_issue_re <= builder_interface2_bank_bus_we;
 	end
 // synthesis translate_off
 	dummy_d_435 = dummy_s;
@@ -14863,9 +14863,9 @@ end
 reg dummy_d_436;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_phaseinjector1_command_issue_re <= 1'd0;
+	main_litedramcore_phaseinjector1_command_issue_we <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd23))) begin
-		main_litedramcore_phaseinjector1_command_issue_re <= builder_interface2_bank_bus_we;
+		main_litedramcore_phaseinjector1_command_issue_we <= (~builder_interface2_bank_bus_we);
 	end
 // synthesis translate_off
 	dummy_d_436 = dummy_s;
@@ -14877,9 +14877,9 @@ assign builder_csrbank2_dfii_pi1_address1_r = builder_interface2_bank_bus_dat_w[
 reg dummy_d_437;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi1_address1_re <= 1'd0;
+	builder_csrbank2_dfii_pi1_address1_we <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd24))) begin
-		builder_csrbank2_dfii_pi1_address1_re <= builder_interface2_bank_bus_we;
+		builder_csrbank2_dfii_pi1_address1_we <= (~builder_interface2_bank_bus_we);
 	end
 // synthesis translate_off
 	dummy_d_437 = dummy_s;
@@ -14890,9 +14890,9 @@ end
 reg dummy_d_438;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi1_address1_we <= 1'd0;
+	builder_csrbank2_dfii_pi1_address1_re <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd24))) begin
-		builder_csrbank2_dfii_pi1_address1_we <= (~builder_interface2_bank_bus_we);
+		builder_csrbank2_dfii_pi1_address1_re <= builder_interface2_bank_bus_we;
 	end
 // synthesis translate_off
 	dummy_d_438 = dummy_s;
@@ -14904,9 +14904,9 @@ assign builder_csrbank2_dfii_pi1_address0_r = builder_interface2_bank_bus_dat_w[
 reg dummy_d_439;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi1_address0_we <= 1'd0;
+	builder_csrbank2_dfii_pi1_address0_re <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd25))) begin
-		builder_csrbank2_dfii_pi1_address0_we <= (~builder_interface2_bank_bus_we);
+		builder_csrbank2_dfii_pi1_address0_re <= builder_interface2_bank_bus_we;
 	end
 // synthesis translate_off
 	dummy_d_439 = dummy_s;
@@ -14917,9 +14917,9 @@ end
 reg dummy_d_440;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi1_address0_re <= 1'd0;
+	builder_csrbank2_dfii_pi1_address0_we <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd25))) begin
-		builder_csrbank2_dfii_pi1_address0_re <= builder_interface2_bank_bus_we;
+		builder_csrbank2_dfii_pi1_address0_we <= (~builder_interface2_bank_bus_we);
 	end
 // synthesis translate_off
 	dummy_d_440 = dummy_s;
@@ -14985,9 +14985,9 @@ assign builder_csrbank2_dfii_pi1_wrdata6_r = builder_interface2_bank_bus_dat_w[7
 reg dummy_d_445;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi1_wrdata6_we <= 1'd0;
+	builder_csrbank2_dfii_pi1_wrdata6_re <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd28))) begin
-		builder_csrbank2_dfii_pi1_wrdata6_we <= (~builder_interface2_bank_bus_we);
+		builder_csrbank2_dfii_pi1_wrdata6_re <= builder_interface2_bank_bus_we;
 	end
 // synthesis translate_off
 	dummy_d_445 = dummy_s;
@@ -14998,9 +14998,9 @@ end
 reg dummy_d_446;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi1_wrdata6_re <= 1'd0;
+	builder_csrbank2_dfii_pi1_wrdata6_we <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd28))) begin
-		builder_csrbank2_dfii_pi1_wrdata6_re <= builder_interface2_bank_bus_we;
+		builder_csrbank2_dfii_pi1_wrdata6_we <= (~builder_interface2_bank_bus_we);
 	end
 // synthesis translate_off
 	dummy_d_446 = dummy_s;
@@ -15012,9 +15012,9 @@ assign builder_csrbank2_dfii_pi1_wrdata5_r = builder_interface2_bank_bus_dat_w[7
 reg dummy_d_447;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi1_wrdata5_re <= 1'd0;
+	builder_csrbank2_dfii_pi1_wrdata5_we <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd29))) begin
-		builder_csrbank2_dfii_pi1_wrdata5_re <= builder_interface2_bank_bus_we;
+		builder_csrbank2_dfii_pi1_wrdata5_we <= (~builder_interface2_bank_bus_we);
 	end
 // synthesis translate_off
 	dummy_d_447 = dummy_s;
@@ -15025,9 +15025,9 @@ end
 reg dummy_d_448;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi1_wrdata5_we <= 1'd0;
+	builder_csrbank2_dfii_pi1_wrdata5_re <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd29))) begin
-		builder_csrbank2_dfii_pi1_wrdata5_we <= (~builder_interface2_bank_bus_we);
+		builder_csrbank2_dfii_pi1_wrdata5_re <= builder_interface2_bank_bus_we;
 	end
 // synthesis translate_off
 	dummy_d_448 = dummy_s;
@@ -15093,9 +15093,9 @@ assign builder_csrbank2_dfii_pi1_wrdata2_r = builder_interface2_bank_bus_dat_w[7
 reg dummy_d_453;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi1_wrdata2_re <= 1'd0;
+	builder_csrbank2_dfii_pi1_wrdata2_we <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd32))) begin
-		builder_csrbank2_dfii_pi1_wrdata2_re <= builder_interface2_bank_bus_we;
+		builder_csrbank2_dfii_pi1_wrdata2_we <= (~builder_interface2_bank_bus_we);
 	end
 // synthesis translate_off
 	dummy_d_453 = dummy_s;
@@ -15106,9 +15106,9 @@ end
 reg dummy_d_454;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi1_wrdata2_we <= 1'd0;
+	builder_csrbank2_dfii_pi1_wrdata2_re <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd32))) begin
-		builder_csrbank2_dfii_pi1_wrdata2_we <= (~builder_interface2_bank_bus_we);
+		builder_csrbank2_dfii_pi1_wrdata2_re <= builder_interface2_bank_bus_we;
 	end
 // synthesis translate_off
 	dummy_d_454 = dummy_s;
@@ -15120,9 +15120,9 @@ assign builder_csrbank2_dfii_pi1_wrdata1_r = builder_interface2_bank_bus_dat_w[7
 reg dummy_d_455;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi1_wrdata1_we <= 1'd0;
+	builder_csrbank2_dfii_pi1_wrdata1_re <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd33))) begin
-		builder_csrbank2_dfii_pi1_wrdata1_we <= (~builder_interface2_bank_bus_we);
+		builder_csrbank2_dfii_pi1_wrdata1_re <= builder_interface2_bank_bus_we;
 	end
 // synthesis translate_off
 	dummy_d_455 = dummy_s;
@@ -15133,9 +15133,9 @@ end
 reg dummy_d_456;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi1_wrdata1_re <= 1'd0;
+	builder_csrbank2_dfii_pi1_wrdata1_we <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd33))) begin
-		builder_csrbank2_dfii_pi1_wrdata1_re <= builder_interface2_bank_bus_we;
+		builder_csrbank2_dfii_pi1_wrdata1_we <= (~builder_interface2_bank_bus_we);
 	end
 // synthesis translate_off
 	dummy_d_456 = dummy_s;
@@ -15201,9 +15201,9 @@ assign builder_csrbank2_dfii_pi1_rddata6_r = builder_interface2_bank_bus_dat_w[7
 reg dummy_d_461;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi1_rddata6_we <= 1'd0;
+	builder_csrbank2_dfii_pi1_rddata6_re <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd36))) begin
-		builder_csrbank2_dfii_pi1_rddata6_we <= (~builder_interface2_bank_bus_we);
+		builder_csrbank2_dfii_pi1_rddata6_re <= builder_interface2_bank_bus_we;
 	end
 // synthesis translate_off
 	dummy_d_461 = dummy_s;
@@ -15214,9 +15214,9 @@ end
 reg dummy_d_462;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi1_rddata6_re <= 1'd0;
+	builder_csrbank2_dfii_pi1_rddata6_we <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd36))) begin
-		builder_csrbank2_dfii_pi1_rddata6_re <= builder_interface2_bank_bus_we;
+		builder_csrbank2_dfii_pi1_rddata6_we <= (~builder_interface2_bank_bus_we);
 	end
 // synthesis translate_off
 	dummy_d_462 = dummy_s;
@@ -15255,9 +15255,9 @@ assign builder_csrbank2_dfii_pi1_rddata4_r = builder_interface2_bank_bus_dat_w[7
 reg dummy_d_465;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi1_rddata4_re <= 1'd0;
+	builder_csrbank2_dfii_pi1_rddata4_we <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd38))) begin
-		builder_csrbank2_dfii_pi1_rddata4_re <= builder_interface2_bank_bus_we;
+		builder_csrbank2_dfii_pi1_rddata4_we <= (~builder_interface2_bank_bus_we);
 	end
 // synthesis translate_off
 	dummy_d_465 = dummy_s;
@@ -15268,9 +15268,9 @@ end
 reg dummy_d_466;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi1_rddata4_we <= 1'd0;
+	builder_csrbank2_dfii_pi1_rddata4_re <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd38))) begin
-		builder_csrbank2_dfii_pi1_rddata4_we <= (~builder_interface2_bank_bus_we);
+		builder_csrbank2_dfii_pi1_rddata4_re <= builder_interface2_bank_bus_we;
 	end
 // synthesis translate_off
 	dummy_d_466 = dummy_s;
@@ -15309,9 +15309,9 @@ assign builder_csrbank2_dfii_pi1_rddata2_r = builder_interface2_bank_bus_dat_w[7
 reg dummy_d_469;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi1_rddata2_we <= 1'd0;
+	builder_csrbank2_dfii_pi1_rddata2_re <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd40))) begin
-		builder_csrbank2_dfii_pi1_rddata2_we <= (~builder_interface2_bank_bus_we);
+		builder_csrbank2_dfii_pi1_rddata2_re <= builder_interface2_bank_bus_we;
 	end
 // synthesis translate_off
 	dummy_d_469 = dummy_s;
@@ -15322,9 +15322,9 @@ end
 reg dummy_d_470;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi1_rddata2_re <= 1'd0;
+	builder_csrbank2_dfii_pi1_rddata2_we <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd40))) begin
-		builder_csrbank2_dfii_pi1_rddata2_re <= builder_interface2_bank_bus_we;
+		builder_csrbank2_dfii_pi1_rddata2_we <= (~builder_interface2_bank_bus_we);
 	end
 // synthesis translate_off
 	dummy_d_470 = dummy_s;
@@ -15363,9 +15363,9 @@ assign builder_csrbank2_dfii_pi1_rddata0_r = builder_interface2_bank_bus_dat_w[7
 reg dummy_d_473;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi1_rddata0_re <= 1'd0;
+	builder_csrbank2_dfii_pi1_rddata0_we <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd42))) begin
-		builder_csrbank2_dfii_pi1_rddata0_re <= builder_interface2_bank_bus_we;
+		builder_csrbank2_dfii_pi1_rddata0_we <= (~builder_interface2_bank_bus_we);
 	end
 // synthesis translate_off
 	dummy_d_473 = dummy_s;
@@ -15376,9 +15376,9 @@ end
 reg dummy_d_474;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi1_rddata0_we <= 1'd0;
+	builder_csrbank2_dfii_pi1_rddata0_re <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd42))) begin
-		builder_csrbank2_dfii_pi1_rddata0_we <= (~builder_interface2_bank_bus_we);
+		builder_csrbank2_dfii_pi1_rddata0_re <= builder_interface2_bank_bus_we;
 	end
 // synthesis translate_off
 	dummy_d_474 = dummy_s;
@@ -15444,9 +15444,9 @@ assign builder_csrbank2_dfii_pi2_address1_r = builder_interface2_bank_bus_dat_w[
 reg dummy_d_479;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi2_address1_we <= 1'd0;
+	builder_csrbank2_dfii_pi2_address1_re <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd45))) begin
-		builder_csrbank2_dfii_pi2_address1_we <= (~builder_interface2_bank_bus_we);
+		builder_csrbank2_dfii_pi2_address1_re <= builder_interface2_bank_bus_we;
 	end
 // synthesis translate_off
 	dummy_d_479 = dummy_s;
@@ -15457,9 +15457,9 @@ end
 reg dummy_d_480;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi2_address1_re <= 1'd0;
+	builder_csrbank2_dfii_pi2_address1_we <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd45))) begin
-		builder_csrbank2_dfii_pi2_address1_re <= builder_interface2_bank_bus_we;
+		builder_csrbank2_dfii_pi2_address1_we <= (~builder_interface2_bank_bus_we);
 	end
 // synthesis translate_off
 	dummy_d_480 = dummy_s;
@@ -15471,9 +15471,9 @@ assign builder_csrbank2_dfii_pi2_address0_r = builder_interface2_bank_bus_dat_w[
 reg dummy_d_481;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi2_address0_re <= 1'd0;
+	builder_csrbank2_dfii_pi2_address0_we <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd46))) begin
-		builder_csrbank2_dfii_pi2_address0_re <= builder_interface2_bank_bus_we;
+		builder_csrbank2_dfii_pi2_address0_we <= (~builder_interface2_bank_bus_we);
 	end
 // synthesis translate_off
 	dummy_d_481 = dummy_s;
@@ -15484,9 +15484,9 @@ end
 reg dummy_d_482;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi2_address0_we <= 1'd0;
+	builder_csrbank2_dfii_pi2_address0_re <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd46))) begin
-		builder_csrbank2_dfii_pi2_address0_we <= (~builder_interface2_bank_bus_we);
+		builder_csrbank2_dfii_pi2_address0_re <= builder_interface2_bank_bus_we;
 	end
 // synthesis translate_off
 	dummy_d_482 = dummy_s;
@@ -15552,9 +15552,9 @@ assign builder_csrbank2_dfii_pi2_wrdata6_r = builder_interface2_bank_bus_dat_w[7
 reg dummy_d_487;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi2_wrdata6_re <= 1'd0;
+	builder_csrbank2_dfii_pi2_wrdata6_we <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd49))) begin
-		builder_csrbank2_dfii_pi2_wrdata6_re <= builder_interface2_bank_bus_we;
+		builder_csrbank2_dfii_pi2_wrdata6_we <= (~builder_interface2_bank_bus_we);
 	end
 // synthesis translate_off
 	dummy_d_487 = dummy_s;
@@ -15565,9 +15565,9 @@ end
 reg dummy_d_488;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi2_wrdata6_we <= 1'd0;
+	builder_csrbank2_dfii_pi2_wrdata6_re <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd49))) begin
-		builder_csrbank2_dfii_pi2_wrdata6_we <= (~builder_interface2_bank_bus_we);
+		builder_csrbank2_dfii_pi2_wrdata6_re <= builder_interface2_bank_bus_we;
 	end
 // synthesis translate_off
 	dummy_d_488 = dummy_s;
@@ -15579,9 +15579,9 @@ assign builder_csrbank2_dfii_pi2_wrdata5_r = builder_interface2_bank_bus_dat_w[7
 reg dummy_d_489;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi2_wrdata5_we <= 1'd0;
+	builder_csrbank2_dfii_pi2_wrdata5_re <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd50))) begin
-		builder_csrbank2_dfii_pi2_wrdata5_we <= (~builder_interface2_bank_bus_we);
+		builder_csrbank2_dfii_pi2_wrdata5_re <= builder_interface2_bank_bus_we;
 	end
 // synthesis translate_off
 	dummy_d_489 = dummy_s;
@@ -15592,9 +15592,9 @@ end
 reg dummy_d_490;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi2_wrdata5_re <= 1'd0;
+	builder_csrbank2_dfii_pi2_wrdata5_we <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd50))) begin
-		builder_csrbank2_dfii_pi2_wrdata5_re <= builder_interface2_bank_bus_we;
+		builder_csrbank2_dfii_pi2_wrdata5_we <= (~builder_interface2_bank_bus_we);
 	end
 // synthesis translate_off
 	dummy_d_490 = dummy_s;
@@ -15660,9 +15660,9 @@ assign builder_csrbank2_dfii_pi2_wrdata2_r = builder_interface2_bank_bus_dat_w[7
 reg dummy_d_495;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi2_wrdata2_we <= 1'd0;
+	builder_csrbank2_dfii_pi2_wrdata2_re <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd53))) begin
-		builder_csrbank2_dfii_pi2_wrdata2_we <= (~builder_interface2_bank_bus_we);
+		builder_csrbank2_dfii_pi2_wrdata2_re <= builder_interface2_bank_bus_we;
 	end
 // synthesis translate_off
 	dummy_d_495 = dummy_s;
@@ -15673,9 +15673,9 @@ end
 reg dummy_d_496;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi2_wrdata2_re <= 1'd0;
+	builder_csrbank2_dfii_pi2_wrdata2_we <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd53))) begin
-		builder_csrbank2_dfii_pi2_wrdata2_re <= builder_interface2_bank_bus_we;
+		builder_csrbank2_dfii_pi2_wrdata2_we <= (~builder_interface2_bank_bus_we);
 	end
 // synthesis translate_off
 	dummy_d_496 = dummy_s;
@@ -15687,9 +15687,9 @@ assign builder_csrbank2_dfii_pi2_wrdata1_r = builder_interface2_bank_bus_dat_w[7
 reg dummy_d_497;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi2_wrdata1_re <= 1'd0;
+	builder_csrbank2_dfii_pi2_wrdata1_we <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd54))) begin
-		builder_csrbank2_dfii_pi2_wrdata1_re <= builder_interface2_bank_bus_we;
+		builder_csrbank2_dfii_pi2_wrdata1_we <= (~builder_interface2_bank_bus_we);
 	end
 // synthesis translate_off
 	dummy_d_497 = dummy_s;
@@ -15700,9 +15700,9 @@ end
 reg dummy_d_498;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi2_wrdata1_we <= 1'd0;
+	builder_csrbank2_dfii_pi2_wrdata1_re <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd54))) begin
-		builder_csrbank2_dfii_pi2_wrdata1_we <= (~builder_interface2_bank_bus_we);
+		builder_csrbank2_dfii_pi2_wrdata1_re <= builder_interface2_bank_bus_we;
 	end
 // synthesis translate_off
 	dummy_d_498 = dummy_s;
@@ -15768,9 +15768,9 @@ assign builder_csrbank2_dfii_pi2_rddata6_r = builder_interface2_bank_bus_dat_w[7
 reg dummy_d_503;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi2_rddata6_re <= 1'd0;
+	builder_csrbank2_dfii_pi2_rddata6_we <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd57))) begin
-		builder_csrbank2_dfii_pi2_rddata6_re <= builder_interface2_bank_bus_we;
+		builder_csrbank2_dfii_pi2_rddata6_we <= (~builder_interface2_bank_bus_we);
 	end
 // synthesis translate_off
 	dummy_d_503 = dummy_s;
@@ -15781,9 +15781,9 @@ end
 reg dummy_d_504;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi2_rddata6_we <= 1'd0;
+	builder_csrbank2_dfii_pi2_rddata6_re <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd57))) begin
-		builder_csrbank2_dfii_pi2_rddata6_we <= (~builder_interface2_bank_bus_we);
+		builder_csrbank2_dfii_pi2_rddata6_re <= builder_interface2_bank_bus_we;
 	end
 // synthesis translate_off
 	dummy_d_504 = dummy_s;
@@ -15822,9 +15822,9 @@ assign builder_csrbank2_dfii_pi2_rddata4_r = builder_interface2_bank_bus_dat_w[7
 reg dummy_d_507;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi2_rddata4_we <= 1'd0;
+	builder_csrbank2_dfii_pi2_rddata4_re <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd59))) begin
-		builder_csrbank2_dfii_pi2_rddata4_we <= (~builder_interface2_bank_bus_we);
+		builder_csrbank2_dfii_pi2_rddata4_re <= builder_interface2_bank_bus_we;
 	end
 // synthesis translate_off
 	dummy_d_507 = dummy_s;
@@ -15835,9 +15835,9 @@ end
 reg dummy_d_508;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi2_rddata4_re <= 1'd0;
+	builder_csrbank2_dfii_pi2_rddata4_we <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd59))) begin
-		builder_csrbank2_dfii_pi2_rddata4_re <= builder_interface2_bank_bus_we;
+		builder_csrbank2_dfii_pi2_rddata4_we <= (~builder_interface2_bank_bus_we);
 	end
 // synthesis translate_off
 	dummy_d_508 = dummy_s;
@@ -15876,9 +15876,9 @@ assign builder_csrbank2_dfii_pi2_rddata2_r = builder_interface2_bank_bus_dat_w[7
 reg dummy_d_511;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi2_rddata2_re <= 1'd0;
+	builder_csrbank2_dfii_pi2_rddata2_we <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd61))) begin
-		builder_csrbank2_dfii_pi2_rddata2_re <= builder_interface2_bank_bus_we;
+		builder_csrbank2_dfii_pi2_rddata2_we <= (~builder_interface2_bank_bus_we);
 	end
 // synthesis translate_off
 	dummy_d_511 = dummy_s;
@@ -15889,9 +15889,9 @@ end
 reg dummy_d_512;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi2_rddata2_we <= 1'd0;
+	builder_csrbank2_dfii_pi2_rddata2_re <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd61))) begin
-		builder_csrbank2_dfii_pi2_rddata2_we <= (~builder_interface2_bank_bus_we);
+		builder_csrbank2_dfii_pi2_rddata2_re <= builder_interface2_bank_bus_we;
 	end
 // synthesis translate_off
 	dummy_d_512 = dummy_s;
@@ -15930,9 +15930,9 @@ assign builder_csrbank2_dfii_pi2_rddata0_r = builder_interface2_bank_bus_dat_w[7
 reg dummy_d_515;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi2_rddata0_we <= 1'd0;
+	builder_csrbank2_dfii_pi2_rddata0_re <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd63))) begin
-		builder_csrbank2_dfii_pi2_rddata0_we <= (~builder_interface2_bank_bus_we);
+		builder_csrbank2_dfii_pi2_rddata0_re <= builder_interface2_bank_bus_we;
 	end
 // synthesis translate_off
 	dummy_d_515 = dummy_s;
@@ -15943,9 +15943,9 @@ end
 reg dummy_d_516;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi2_rddata0_re <= 1'd0;
+	builder_csrbank2_dfii_pi2_rddata0_we <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd63))) begin
-		builder_csrbank2_dfii_pi2_rddata0_re <= builder_interface2_bank_bus_we;
+		builder_csrbank2_dfii_pi2_rddata0_we <= (~builder_interface2_bank_bus_we);
 	end
 // synthesis translate_off
 	dummy_d_516 = dummy_s;
@@ -16011,9 +16011,9 @@ assign builder_csrbank2_dfii_pi3_address1_r = builder_interface2_bank_bus_dat_w[
 reg dummy_d_521;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi3_address1_re <= 1'd0;
+	builder_csrbank2_dfii_pi3_address1_we <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 7'd66))) begin
-		builder_csrbank2_dfii_pi3_address1_re <= builder_interface2_bank_bus_we;
+		builder_csrbank2_dfii_pi3_address1_we <= (~builder_interface2_bank_bus_we);
 	end
 // synthesis translate_off
 	dummy_d_521 = dummy_s;
@@ -16024,9 +16024,9 @@ end
 reg dummy_d_522;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi3_address1_we <= 1'd0;
+	builder_csrbank2_dfii_pi3_address1_re <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 7'd66))) begin
-		builder_csrbank2_dfii_pi3_address1_we <= (~builder_interface2_bank_bus_we);
+		builder_csrbank2_dfii_pi3_address1_re <= builder_interface2_bank_bus_we;
 	end
 // synthesis translate_off
 	dummy_d_522 = dummy_s;
@@ -16038,9 +16038,9 @@ assign builder_csrbank2_dfii_pi3_address0_r = builder_interface2_bank_bus_dat_w[
 reg dummy_d_523;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi3_address0_we <= 1'd0;
+	builder_csrbank2_dfii_pi3_address0_re <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 7'd67))) begin
-		builder_csrbank2_dfii_pi3_address0_we <= (~builder_interface2_bank_bus_we);
+		builder_csrbank2_dfii_pi3_address0_re <= builder_interface2_bank_bus_we;
 	end
 // synthesis translate_off
 	dummy_d_523 = dummy_s;
@@ -16051,9 +16051,9 @@ end
 reg dummy_d_524;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi3_address0_re <= 1'd0;
+	builder_csrbank2_dfii_pi3_address0_we <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 7'd67))) begin
-		builder_csrbank2_dfii_pi3_address0_re <= builder_interface2_bank_bus_we;
+		builder_csrbank2_dfii_pi3_address0_we <= (~builder_interface2_bank_bus_we);
 	end
 // synthesis translate_off
 	dummy_d_524 = dummy_s;
@@ -16119,9 +16119,9 @@ assign builder_csrbank2_dfii_pi3_wrdata6_r = builder_interface2_bank_bus_dat_w[7
 reg dummy_d_529;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi3_wrdata6_we <= 1'd0;
+	builder_csrbank2_dfii_pi3_wrdata6_re <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 7'd70))) begin
-		builder_csrbank2_dfii_pi3_wrdata6_we <= (~builder_interface2_bank_bus_we);
+		builder_csrbank2_dfii_pi3_wrdata6_re <= builder_interface2_bank_bus_we;
 	end
 // synthesis translate_off
 	dummy_d_529 = dummy_s;
@@ -16132,9 +16132,9 @@ end
 reg dummy_d_530;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi3_wrdata6_re <= 1'd0;
+	builder_csrbank2_dfii_pi3_wrdata6_we <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 7'd70))) begin
-		builder_csrbank2_dfii_pi3_wrdata6_re <= builder_interface2_bank_bus_we;
+		builder_csrbank2_dfii_pi3_wrdata6_we <= (~builder_interface2_bank_bus_we);
 	end
 // synthesis translate_off
 	dummy_d_530 = dummy_s;
@@ -16146,9 +16146,9 @@ assign builder_csrbank2_dfii_pi3_wrdata5_r = builder_interface2_bank_bus_dat_w[7
 reg dummy_d_531;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi3_wrdata5_re <= 1'd0;
+	builder_csrbank2_dfii_pi3_wrdata5_we <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 7'd71))) begin
-		builder_csrbank2_dfii_pi3_wrdata5_re <= builder_interface2_bank_bus_we;
+		builder_csrbank2_dfii_pi3_wrdata5_we <= (~builder_interface2_bank_bus_we);
 	end
 // synthesis translate_off
 	dummy_d_531 = dummy_s;
@@ -16159,9 +16159,9 @@ end
 reg dummy_d_532;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi3_wrdata5_we <= 1'd0;
+	builder_csrbank2_dfii_pi3_wrdata5_re <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 7'd71))) begin
-		builder_csrbank2_dfii_pi3_wrdata5_we <= (~builder_interface2_bank_bus_we);
+		builder_csrbank2_dfii_pi3_wrdata5_re <= builder_interface2_bank_bus_we;
 	end
 // synthesis translate_off
 	dummy_d_532 = dummy_s;
@@ -16227,9 +16227,9 @@ assign builder_csrbank2_dfii_pi3_wrdata2_r = builder_interface2_bank_bus_dat_w[7
 reg dummy_d_537;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi3_wrdata2_re <= 1'd0;
+	builder_csrbank2_dfii_pi3_wrdata2_we <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 7'd74))) begin
-		builder_csrbank2_dfii_pi3_wrdata2_re <= builder_interface2_bank_bus_we;
+		builder_csrbank2_dfii_pi3_wrdata2_we <= (~builder_interface2_bank_bus_we);
 	end
 // synthesis translate_off
 	dummy_d_537 = dummy_s;
@@ -16240,9 +16240,9 @@ end
 reg dummy_d_538;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi3_wrdata2_we <= 1'd0;
+	builder_csrbank2_dfii_pi3_wrdata2_re <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 7'd74))) begin
-		builder_csrbank2_dfii_pi3_wrdata2_we <= (~builder_interface2_bank_bus_we);
+		builder_csrbank2_dfii_pi3_wrdata2_re <= builder_interface2_bank_bus_we;
 	end
 // synthesis translate_off
 	dummy_d_538 = dummy_s;
@@ -16254,9 +16254,9 @@ assign builder_csrbank2_dfii_pi3_wrdata1_r = builder_interface2_bank_bus_dat_w[7
 reg dummy_d_539;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi3_wrdata1_we <= 1'd0;
+	builder_csrbank2_dfii_pi3_wrdata1_re <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 7'd75))) begin
-		builder_csrbank2_dfii_pi3_wrdata1_we <= (~builder_interface2_bank_bus_we);
+		builder_csrbank2_dfii_pi3_wrdata1_re <= builder_interface2_bank_bus_we;
 	end
 // synthesis translate_off
 	dummy_d_539 = dummy_s;
@@ -16267,9 +16267,9 @@ end
 reg dummy_d_540;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi3_wrdata1_re <= 1'd0;
+	builder_csrbank2_dfii_pi3_wrdata1_we <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 7'd75))) begin
-		builder_csrbank2_dfii_pi3_wrdata1_re <= builder_interface2_bank_bus_we;
+		builder_csrbank2_dfii_pi3_wrdata1_we <= (~builder_interface2_bank_bus_we);
 	end
 // synthesis translate_off
 	dummy_d_540 = dummy_s;
@@ -16335,9 +16335,9 @@ assign builder_csrbank2_dfii_pi3_rddata6_r = builder_interface2_bank_bus_dat_w[7
 reg dummy_d_545;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi3_rddata6_we <= 1'd0;
+	builder_csrbank2_dfii_pi3_rddata6_re <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 7'd78))) begin
-		builder_csrbank2_dfii_pi3_rddata6_we <= (~builder_interface2_bank_bus_we);
+		builder_csrbank2_dfii_pi3_rddata6_re <= builder_interface2_bank_bus_we;
 	end
 // synthesis translate_off
 	dummy_d_545 = dummy_s;
@@ -16348,9 +16348,9 @@ end
 reg dummy_d_546;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi3_rddata6_re <= 1'd0;
+	builder_csrbank2_dfii_pi3_rddata6_we <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 7'd78))) begin
-		builder_csrbank2_dfii_pi3_rddata6_re <= builder_interface2_bank_bus_we;
+		builder_csrbank2_dfii_pi3_rddata6_we <= (~builder_interface2_bank_bus_we);
 	end
 // synthesis translate_off
 	dummy_d_546 = dummy_s;
@@ -16389,9 +16389,9 @@ assign builder_csrbank2_dfii_pi3_rddata4_r = builder_interface2_bank_bus_dat_w[7
 reg dummy_d_549;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi3_rddata4_re <= 1'd0;
+	builder_csrbank2_dfii_pi3_rddata4_we <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 7'd80))) begin
-		builder_csrbank2_dfii_pi3_rddata4_re <= builder_interface2_bank_bus_we;
+		builder_csrbank2_dfii_pi3_rddata4_we <= (~builder_interface2_bank_bus_we);
 	end
 // synthesis translate_off
 	dummy_d_549 = dummy_s;
@@ -16402,9 +16402,9 @@ end
 reg dummy_d_550;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi3_rddata4_we <= 1'd0;
+	builder_csrbank2_dfii_pi3_rddata4_re <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 7'd80))) begin
-		builder_csrbank2_dfii_pi3_rddata4_we <= (~builder_interface2_bank_bus_we);
+		builder_csrbank2_dfii_pi3_rddata4_re <= builder_interface2_bank_bus_we;
 	end
 // synthesis translate_off
 	dummy_d_550 = dummy_s;
@@ -16443,9 +16443,9 @@ assign builder_csrbank2_dfii_pi3_rddata2_r = builder_interface2_bank_bus_dat_w[7
 reg dummy_d_553;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi3_rddata2_we <= 1'd0;
+	builder_csrbank2_dfii_pi3_rddata2_re <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 7'd82))) begin
-		builder_csrbank2_dfii_pi3_rddata2_we <= (~builder_interface2_bank_bus_we);
+		builder_csrbank2_dfii_pi3_rddata2_re <= builder_interface2_bank_bus_we;
 	end
 // synthesis translate_off
 	dummy_d_553 = dummy_s;
@@ -16456,9 +16456,9 @@ end
 reg dummy_d_554;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi3_rddata2_re <= 1'd0;
+	builder_csrbank2_dfii_pi3_rddata2_we <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 7'd82))) begin
-		builder_csrbank2_dfii_pi3_rddata2_re <= builder_interface2_bank_bus_we;
+		builder_csrbank2_dfii_pi3_rddata2_we <= (~builder_interface2_bank_bus_we);
 	end
 // synthesis translate_off
 	dummy_d_554 = dummy_s;
@@ -16497,9 +16497,9 @@ assign builder_csrbank2_dfii_pi3_rddata0_r = builder_interface2_bank_bus_dat_w[7
 reg dummy_d_557;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi3_rddata0_re <= 1'd0;
+	builder_csrbank2_dfii_pi3_rddata0_we <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 7'd84))) begin
-		builder_csrbank2_dfii_pi3_rddata0_re <= builder_interface2_bank_bus_we;
+		builder_csrbank2_dfii_pi3_rddata0_we <= (~builder_interface2_bank_bus_we);
 	end
 // synthesis translate_off
 	dummy_d_557 = dummy_s;
@@ -16510,9 +16510,9 @@ end
 reg dummy_d_558;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi3_rddata0_we <= 1'd0;
+	builder_csrbank2_dfii_pi3_rddata0_re <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 7'd84))) begin
-		builder_csrbank2_dfii_pi3_rddata0_we <= (~builder_interface2_bank_bus_we);
+		builder_csrbank2_dfii_pi3_rddata0_re <= builder_interface2_bank_bus_we;
 	end
 // synthesis translate_off
 	dummy_d_558 = dummy_s;
@@ -21075,7 +21075,7 @@ ODELAYE2 #(
 	.C(sys_clk),
 	.CE(main_k7ddrphy_cdly_inc_re),
 	.INC(1'd1),
-	.LD((main_k7ddrphy_cdly_rst_re | main_k7ddrphy_rst_storage)),
+	.LD(((main_k7ddrphy_cdly_rst_re | main_k7ddrphy_rst_storage) | main_k7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
 	.DATAOUT(main_k7ddrphy_sd_clk_se_delayed),
 	.ODATAIN(main_k7ddrphy_sd_clk_se_nodelay)
@@ -21122,7 +21122,7 @@ ODELAYE2 #(
 	.C(sys_clk),
 	.CE(main_k7ddrphy_cdly_inc_re),
 	.INC(1'd1),
-	.LD((main_k7ddrphy_cdly_rst_re | main_k7ddrphy_rst_storage)),
+	.LD(((main_k7ddrphy_cdly_rst_re | main_k7ddrphy_rst_storage) | main_k7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
 	.DATAOUT(ddram_reset_n),
 	.ODATAIN(main_k7ddrphy_oq0)
@@ -21163,7 +21163,7 @@ ODELAYE2 #(
 	.C(sys_clk),
 	.CE(main_k7ddrphy_cdly_inc_re),
 	.INC(1'd1),
-	.LD((main_k7ddrphy_cdly_rst_re | main_k7ddrphy_rst_storage)),
+	.LD(((main_k7ddrphy_cdly_rst_re | main_k7ddrphy_rst_storage) | main_k7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
 	.DATAOUT(ddram_cs_n),
 	.ODATAIN(main_k7ddrphy_oq1)
@@ -21204,7 +21204,7 @@ ODELAYE2 #(
 	.C(sys_clk),
 	.CE(main_k7ddrphy_cdly_inc_re),
 	.INC(1'd1),
-	.LD((main_k7ddrphy_cdly_rst_re | main_k7ddrphy_rst_storage)),
+	.LD(((main_k7ddrphy_cdly_rst_re | main_k7ddrphy_rst_storage) | main_k7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
 	.DATAOUT(ddram_a[0]),
 	.ODATAIN(main_k7ddrphy_oq2)
@@ -21245,7 +21245,7 @@ ODELAYE2 #(
 	.C(sys_clk),
 	.CE(main_k7ddrphy_cdly_inc_re),
 	.INC(1'd1),
-	.LD((main_k7ddrphy_cdly_rst_re | main_k7ddrphy_rst_storage)),
+	.LD(((main_k7ddrphy_cdly_rst_re | main_k7ddrphy_rst_storage) | main_k7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
 	.DATAOUT(ddram_a[1]),
 	.ODATAIN(main_k7ddrphy_oq3)
@@ -21286,7 +21286,7 @@ ODELAYE2 #(
 	.C(sys_clk),
 	.CE(main_k7ddrphy_cdly_inc_re),
 	.INC(1'd1),
-	.LD((main_k7ddrphy_cdly_rst_re | main_k7ddrphy_rst_storage)),
+	.LD(((main_k7ddrphy_cdly_rst_re | main_k7ddrphy_rst_storage) | main_k7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
 	.DATAOUT(ddram_a[2]),
 	.ODATAIN(main_k7ddrphy_oq4)
@@ -21327,7 +21327,7 @@ ODELAYE2 #(
 	.C(sys_clk),
 	.CE(main_k7ddrphy_cdly_inc_re),
 	.INC(1'd1),
-	.LD((main_k7ddrphy_cdly_rst_re | main_k7ddrphy_rst_storage)),
+	.LD(((main_k7ddrphy_cdly_rst_re | main_k7ddrphy_rst_storage) | main_k7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
 	.DATAOUT(ddram_a[3]),
 	.ODATAIN(main_k7ddrphy_oq5)
@@ -21368,7 +21368,7 @@ ODELAYE2 #(
 	.C(sys_clk),
 	.CE(main_k7ddrphy_cdly_inc_re),
 	.INC(1'd1),
-	.LD((main_k7ddrphy_cdly_rst_re | main_k7ddrphy_rst_storage)),
+	.LD(((main_k7ddrphy_cdly_rst_re | main_k7ddrphy_rst_storage) | main_k7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
 	.DATAOUT(ddram_a[4]),
 	.ODATAIN(main_k7ddrphy_oq6)
@@ -21409,7 +21409,7 @@ ODELAYE2 #(
 	.C(sys_clk),
 	.CE(main_k7ddrphy_cdly_inc_re),
 	.INC(1'd1),
-	.LD((main_k7ddrphy_cdly_rst_re | main_k7ddrphy_rst_storage)),
+	.LD(((main_k7ddrphy_cdly_rst_re | main_k7ddrphy_rst_storage) | main_k7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
 	.DATAOUT(ddram_a[5]),
 	.ODATAIN(main_k7ddrphy_oq7)
@@ -21450,7 +21450,7 @@ ODELAYE2 #(
 	.C(sys_clk),
 	.CE(main_k7ddrphy_cdly_inc_re),
 	.INC(1'd1),
-	.LD((main_k7ddrphy_cdly_rst_re | main_k7ddrphy_rst_storage)),
+	.LD(((main_k7ddrphy_cdly_rst_re | main_k7ddrphy_rst_storage) | main_k7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
 	.DATAOUT(ddram_a[6]),
 	.ODATAIN(main_k7ddrphy_oq8)
@@ -21491,7 +21491,7 @@ ODELAYE2 #(
 	.C(sys_clk),
 	.CE(main_k7ddrphy_cdly_inc_re),
 	.INC(1'd1),
-	.LD((main_k7ddrphy_cdly_rst_re | main_k7ddrphy_rst_storage)),
+	.LD(((main_k7ddrphy_cdly_rst_re | main_k7ddrphy_rst_storage) | main_k7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
 	.DATAOUT(ddram_a[7]),
 	.ODATAIN(main_k7ddrphy_oq9)
@@ -21532,7 +21532,7 @@ ODELAYE2 #(
 	.C(sys_clk),
 	.CE(main_k7ddrphy_cdly_inc_re),
 	.INC(1'd1),
-	.LD((main_k7ddrphy_cdly_rst_re | main_k7ddrphy_rst_storage)),
+	.LD(((main_k7ddrphy_cdly_rst_re | main_k7ddrphy_rst_storage) | main_k7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
 	.DATAOUT(ddram_a[8]),
 	.ODATAIN(main_k7ddrphy_oq10)
@@ -21573,7 +21573,7 @@ ODELAYE2 #(
 	.C(sys_clk),
 	.CE(main_k7ddrphy_cdly_inc_re),
 	.INC(1'd1),
-	.LD((main_k7ddrphy_cdly_rst_re | main_k7ddrphy_rst_storage)),
+	.LD(((main_k7ddrphy_cdly_rst_re | main_k7ddrphy_rst_storage) | main_k7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
 	.DATAOUT(ddram_a[9]),
 	.ODATAIN(main_k7ddrphy_oq11)
@@ -21614,7 +21614,7 @@ ODELAYE2 #(
 	.C(sys_clk),
 	.CE(main_k7ddrphy_cdly_inc_re),
 	.INC(1'd1),
-	.LD((main_k7ddrphy_cdly_rst_re | main_k7ddrphy_rst_storage)),
+	.LD(((main_k7ddrphy_cdly_rst_re | main_k7ddrphy_rst_storage) | main_k7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
 	.DATAOUT(ddram_a[10]),
 	.ODATAIN(main_k7ddrphy_oq12)
@@ -21655,7 +21655,7 @@ ODELAYE2 #(
 	.C(sys_clk),
 	.CE(main_k7ddrphy_cdly_inc_re),
 	.INC(1'd1),
-	.LD((main_k7ddrphy_cdly_rst_re | main_k7ddrphy_rst_storage)),
+	.LD(((main_k7ddrphy_cdly_rst_re | main_k7ddrphy_rst_storage) | main_k7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
 	.DATAOUT(ddram_a[11]),
 	.ODATAIN(main_k7ddrphy_oq13)
@@ -21696,7 +21696,7 @@ ODELAYE2 #(
 	.C(sys_clk),
 	.CE(main_k7ddrphy_cdly_inc_re),
 	.INC(1'd1),
-	.LD((main_k7ddrphy_cdly_rst_re | main_k7ddrphy_rst_storage)),
+	.LD(((main_k7ddrphy_cdly_rst_re | main_k7ddrphy_rst_storage) | main_k7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
 	.DATAOUT(ddram_a[12]),
 	.ODATAIN(main_k7ddrphy_oq14)
@@ -21737,7 +21737,7 @@ ODELAYE2 #(
 	.C(sys_clk),
 	.CE(main_k7ddrphy_cdly_inc_re),
 	.INC(1'd1),
-	.LD((main_k7ddrphy_cdly_rst_re | main_k7ddrphy_rst_storage)),
+	.LD(((main_k7ddrphy_cdly_rst_re | main_k7ddrphy_rst_storage) | main_k7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
 	.DATAOUT(ddram_a[13]),
 	.ODATAIN(main_k7ddrphy_oq15)
@@ -21778,7 +21778,7 @@ ODELAYE2 #(
 	.C(sys_clk),
 	.CE(main_k7ddrphy_cdly_inc_re),
 	.INC(1'd1),
-	.LD((main_k7ddrphy_cdly_rst_re | main_k7ddrphy_rst_storage)),
+	.LD(((main_k7ddrphy_cdly_rst_re | main_k7ddrphy_rst_storage) | main_k7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
 	.DATAOUT(ddram_a[14]),
 	.ODATAIN(main_k7ddrphy_oq16)
@@ -21819,7 +21819,7 @@ ODELAYE2 #(
 	.C(sys_clk),
 	.CE(main_k7ddrphy_cdly_inc_re),
 	.INC(1'd1),
-	.LD((main_k7ddrphy_cdly_rst_re | main_k7ddrphy_rst_storage)),
+	.LD(((main_k7ddrphy_cdly_rst_re | main_k7ddrphy_rst_storage) | main_k7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
 	.DATAOUT(ddram_ba[0]),
 	.ODATAIN(main_k7ddrphy_oq17)
@@ -21860,7 +21860,7 @@ ODELAYE2 #(
 	.C(sys_clk),
 	.CE(main_k7ddrphy_cdly_inc_re),
 	.INC(1'd1),
-	.LD((main_k7ddrphy_cdly_rst_re | main_k7ddrphy_rst_storage)),
+	.LD(((main_k7ddrphy_cdly_rst_re | main_k7ddrphy_rst_storage) | main_k7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
 	.DATAOUT(ddram_ba[1]),
 	.ODATAIN(main_k7ddrphy_oq18)
@@ -21901,7 +21901,7 @@ ODELAYE2 #(
 	.C(sys_clk),
 	.CE(main_k7ddrphy_cdly_inc_re),
 	.INC(1'd1),
-	.LD((main_k7ddrphy_cdly_rst_re | main_k7ddrphy_rst_storage)),
+	.LD(((main_k7ddrphy_cdly_rst_re | main_k7ddrphy_rst_storage) | main_k7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
 	.DATAOUT(ddram_ba[2]),
 	.ODATAIN(main_k7ddrphy_oq19)
@@ -21942,7 +21942,7 @@ ODELAYE2 #(
 	.C(sys_clk),
 	.CE(main_k7ddrphy_cdly_inc_re),
 	.INC(1'd1),
-	.LD((main_k7ddrphy_cdly_rst_re | main_k7ddrphy_rst_storage)),
+	.LD(((main_k7ddrphy_cdly_rst_re | main_k7ddrphy_rst_storage) | main_k7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
 	.DATAOUT(ddram_ras_n),
 	.ODATAIN(main_k7ddrphy_oq20)
@@ -21983,7 +21983,7 @@ ODELAYE2 #(
 	.C(sys_clk),
 	.CE(main_k7ddrphy_cdly_inc_re),
 	.INC(1'd1),
-	.LD((main_k7ddrphy_cdly_rst_re | main_k7ddrphy_rst_storage)),
+	.LD(((main_k7ddrphy_cdly_rst_re | main_k7ddrphy_rst_storage) | main_k7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
 	.DATAOUT(ddram_cas_n),
 	.ODATAIN(main_k7ddrphy_oq21)
@@ -22024,7 +22024,7 @@ ODELAYE2 #(
 	.C(sys_clk),
 	.CE(main_k7ddrphy_cdly_inc_re),
 	.INC(1'd1),
-	.LD((main_k7ddrphy_cdly_rst_re | main_k7ddrphy_rst_storage)),
+	.LD(((main_k7ddrphy_cdly_rst_re | main_k7ddrphy_rst_storage) | main_k7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
 	.DATAOUT(ddram_we_n),
 	.ODATAIN(main_k7ddrphy_oq22)
@@ -22065,7 +22065,7 @@ ODELAYE2 #(
 	.C(sys_clk),
 	.CE(main_k7ddrphy_cdly_inc_re),
 	.INC(1'd1),
-	.LD((main_k7ddrphy_cdly_rst_re | main_k7ddrphy_rst_storage)),
+	.LD(((main_k7ddrphy_cdly_rst_re | main_k7ddrphy_rst_storage) | main_k7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
 	.DATAOUT(ddram_cke),
 	.ODATAIN(main_k7ddrphy_oq23)
@@ -22106,7 +22106,7 @@ ODELAYE2 #(
 	.C(sys_clk),
 	.CE(main_k7ddrphy_cdly_inc_re),
 	.INC(1'd1),
-	.LD((main_k7ddrphy_cdly_rst_re | main_k7ddrphy_rst_storage)),
+	.LD(((main_k7ddrphy_cdly_rst_re | main_k7ddrphy_rst_storage) | main_k7ddrphy_rst_storage)),
 	.LDPIPEEN(1'd0),
 	.DATAOUT(ddram_odt),
 	.ODATAIN(main_k7ddrphy_oq24)
diff --git a/litedram/generated/nexys-video/litedram_core.init b/litedram/generated/nexys-video/litedram_core.init
index 5bfb299..5b1a383 100644
--- a/litedram/generated/nexys-video/litedram_core.init
+++ b/litedram/generated/nexys-video/litedram_core.init
@@ -7,7 +7,7 @@ a64b5a7d14004a39
 6421ff00782107c6
 3d80000060215f00
 798c07c6618c0000
-618c10d8658cff00
+618c10e0658cff00
 4e8004217d8903a6
 4e8004207c6903a6
 0000000000000000
@@ -519,80 +519,81 @@ a64b5a7d14004a39
 0000000000000000
 3c4c000100000000
 7c0802a63842afc4
-f8010010fbe1fff8
-f88100d8f821ff51
+fbe1fff8fbc1fff0
+f821ff51f8010010
+f88100d83bc10020
 38800080f8a100e0
 f8c100e87c651b78
-38c100d838610020
+38c100d87fc3f378
 f90100f8f8e100f0
 f9410108f9210100
-60000000480023d9
-386100207c7f1b78
-6000000048001df5
+600000004800245d
+7fc3f3787c7f1b78
+6000000048001e69
 7fe3fb78382100b0
-00000000480029bc
-0000018001000000
+0000000048002a54
+0000028001000000
 000000004e800020
 0000000000000000
 4c00012c7c0007ac
 000000004e800020
 0000000000000000
-3842af283c4c0001
+3842af203c4c0001
 7d8000267c0802a6
-91810008480028f9
-48001df1f821fed1
+9181000848002991
+48001e65f821fed1
 3c62ffff60000000
-4bffff4138637a70
+4bffff3938637b10
 788400203c80c000
 7c8026ea7c0004ac
 3fe0c0003c62ffff
-63ff000838637a90
-3c62ffff4bffff1d
-38637ab07bff0020
-7c0004ac4bffff0d
+63ff000838637b30
+3c62ffff4bffff15
+38637b507bff0020
+7c0004ac4bffff05
 73e900017fe0feea
 3c62ffff41820010
-4bfffef138637ac8
+4bfffee938637b68
 4e00000073e90002
 3c62ffff41820010
-4bfffed938637ad0
+4bfffed138637b70
 4d80000073e90004
 3c62ffff41820010
-4bfffec138637ad8
+4bfffeb938637b78
 4d00000073e90008
 3c62ffff41820010
-4bfffea938637ae0
+4bfffea138637b80
 4182001073e90010
-38637af03c62ffff
-73e901004bfffe95
+38637b903c62ffff
+73e901004bfffe8d
 3c62ffff41820010
-4bfffe8138637b00
-3b7b7b083f62ffff
-4bfffe717f63db78
+4bfffe7938637ba0
+3b7b7ba83f62ffff
+4bfffe697f63db78
 3c80c000418e0028
 7884002060840010
 7c8026ea7c0004ac
 7884b5823c62ffff
-4bfffe4938637b10
+4bfffe4138637bb0
 3c80c0004192004c
 7884002060840018
 7c8026ea7c0004ac
 788460223c62ffff
-4bfffe2138637b28
+4bfffe1938637bc8
 608400303c80c000
 7c0004ac78840020
 3c62ffff7c8026ea
-38637b407884b282
-3d20c0004bfffdfd
+38637be07884b282
+3d20c0004bfffdf5
 7929002061290020
 7d204eea7c0004ac
 792906003c80000f
 3c62ffff60844240
-38637b587c892392
-418a02584bfffdcd
-63de00383fc0c000
-7c0004ac7bde0020
-3d40c0007fc0f6ea
+38637bf87c892392
+418a025c4bfffdc5
+63bd00383fa0c000
+7c0004ac7bbd0020
+3d40c0007fa0eeea
 614a600439200002
 7c0004ac794a0020
 3fe0c0007d2057aa
@@ -600,1274 +601,1293 @@ f9410108f9210100
 7c0004ac7bff0020
 7c0004ac7d20ffaa
 579c063e7f80feaa
-7fa0feaa7c0004ac
-7c0004ac57bd063e
-4bfffd1d7fe0feaa
+7fc0feaa7c0004ac
+7c0004ac57de063e
+4bfffd157fe0feaa
 3c62ffff57ff063e
-7fa5eb787fe6fb78
-38637b787f84e378
-7f89eb784bfffd45
+7fc5f3787fe6fb78
+38637c187f84e378
+7f89f3784bfffd3d
 2c0900007d29fb78
-7f89e83841820164
+7f89f03841820168
 2c0900ff7d29f838
-281c000141820154
-281d00024082036c
-281d00204182000c
-3bffffe840820134
-281f000157ff063e
-3fe0c00041810124
-63ff600039200035
-7c0004ac7bff0020
-3f80c0007d20ffaa
-639c60043b400002
-7c0004ac7b9c0020
-7c0004ac7f40e7aa
-7c0004ac7d20ffaa
-4bfffc757fa0feaa
-3c62ffff57bd063e
-38637b987fa4eb78
-73a900024bfffca5
-3c62ffff40820090
-4bfffc9138637bb8
-7f40e7aa7c0004ac
-7c0004ac39200006
-4bfffc357d20ffaa
-7f40e7aa7c0004ac
-7c0004ac39200001
-392000007d20ffaa
+281c000141820158
+281e000240820374
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@@ -1918,9 +1938,9 @@ e8010010ebc1fff0
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 0000000000000000
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 4d4152446574694c
 6620746c69756220
 6567694d206d6f72
@@ -2013,6 +2033,10 @@ e8010010ebc1fff0
 64656570736d654d
 2820702520746120
 0000000000000000
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 0000000a2e2e2e29
 2065746972572020
 00203a6465657073
diff --git a/litedram/generated/nexys-video/litedram_core.v b/litedram/generated/nexys-video/litedram_core.v
index a778be4..1a0ab93 100644
--- a/litedram/generated/nexys-video/litedram_core.v
+++ b/litedram/generated/nexys-video/litedram_core.v
@@ -1,5 +1,5 @@
 //--------------------------------------------------------------------------------
-// Auto-generated by Migen (27dbf03) & LiteX (78c1751c) on 2021-08-15 06:19:12
+// Auto-generated by Migen (a5bc262) & LiteX (de028765) on 2021-09-24 12:36:33
 //--------------------------------------------------------------------------------
 module litedram_core(
 	input wire clk,
@@ -4587,10 +4587,10 @@ end
 reg dummy_d_103;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_inti_p3_rddata <= 32'd0;
+	main_litedramcore_slave_p3_rddata <= 32'd0;
 	if (main_litedramcore_sel) begin
+		main_litedramcore_slave_p3_rddata <= main_litedramcore_master_p3_rddata;
 	end else begin
-		main_litedramcore_inti_p3_rddata <= main_litedramcore_master_p3_rddata;
 	end
 // synthesis translate_off
 	dummy_d_103 = dummy_s;
@@ -4616,10 +4616,10 @@ end
 reg dummy_d_105;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_inti_p3_rddata_valid <= 1'd0;
+	main_litedramcore_inti_p3_rddata <= 32'd0;
 	if (main_litedramcore_sel) begin
 	end else begin
-		main_litedramcore_inti_p3_rddata_valid <= main_litedramcore_master_p3_rddata_valid;
+		main_litedramcore_inti_p3_rddata <= main_litedramcore_master_p3_rddata;
 	end
 // synthesis translate_off
 	dummy_d_105 = dummy_s;
@@ -4645,11 +4645,10 @@ end
 reg dummy_d_107;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_master_p2_rddata_en <= 1'd0;
+	main_litedramcore_inti_p3_rddata_valid <= 1'd0;
 	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p2_rddata_en <= main_litedramcore_slave_p2_rddata_en;
 	end else begin
-		main_litedramcore_master_p2_rddata_en <= main_litedramcore_inti_p2_rddata_en;
+		main_litedramcore_inti_p3_rddata_valid <= main_litedramcore_master_p3_rddata_valid;
 	end
 // synthesis translate_off
 	dummy_d_107 = dummy_s;
@@ -4660,11 +4659,11 @@ end
 reg dummy_d_108;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_master_p3_address <= 15'd0;
+	main_litedramcore_master_p2_rddata_en <= 1'd0;
 	if (main_litedramcore_sel) begin
-		main_litedramcore_master_p3_address <= main_litedramcore_slave_p3_address;
+		main_litedramcore_master_p2_rddata_en <= main_litedramcore_slave_p2_rddata_en;
 	end else begin
-		main_litedramcore_master_p3_address <= main_litedramcore_inti_p3_address;
+		main_litedramcore_master_p2_rddata_en <= main_litedramcore_inti_p2_rddata_en;
 	end
 // synthesis translate_off
 	dummy_d_108 = dummy_s;
@@ -4675,10 +4674,11 @@ end
 reg dummy_d_109;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_slave_p3_rddata <= 32'd0;
+	main_litedramcore_master_p3_address <= 15'd0;
 	if (main_litedramcore_sel) begin
-		main_litedramcore_slave_p3_rddata <= main_litedramcore_master_p3_rddata;
+		main_litedramcore_master_p3_address <= main_litedramcore_slave_p3_address;
 	end else begin
+		main_litedramcore_master_p3_address <= main_litedramcore_inti_p3_address;
 	end
 // synthesis translate_off
 	dummy_d_109 = dummy_s;
@@ -11032,10 +11032,14 @@ end
 reg dummy_d_288;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_en1 <= 1'd0;
+	main_litedramcore_choose_req_cmd_ready <= 1'd0;
 	case (builder_multiplexer_state)
 		1'd1: begin
-			main_litedramcore_en1 <= 1'd1;
+			if (1'd0) begin
+				main_litedramcore_choose_req_cmd_ready <= (main_litedramcore_cas_allowed & ((~((main_litedramcore_choose_req_cmd_payload_ras & (~main_litedramcore_choose_req_cmd_payload_cas)) & (~main_litedramcore_choose_req_cmd_payload_we))) | main_litedramcore_ras_allowed));
+			end else begin
+				main_litedramcore_choose_req_cmd_ready <= main_litedramcore_cas_allowed;
+			end
 		end
 		2'd2: begin
 		end
@@ -11056,6 +11060,11 @@ always @(*) begin
 		4'd10: begin
 		end
 		default: begin
+			if (1'd0) begin
+				main_litedramcore_choose_req_cmd_ready <= (main_litedramcore_cas_allowed & ((~((main_litedramcore_choose_req_cmd_payload_ras & (~main_litedramcore_choose_req_cmd_payload_cas)) & (~main_litedramcore_choose_req_cmd_payload_we))) | main_litedramcore_ras_allowed));
+			end else begin
+				main_litedramcore_choose_req_cmd_ready <= main_litedramcore_cas_allowed;
+			end
 		end
 	endcase
 // synthesis translate_off
@@ -11066,6 +11075,41 @@ end
 // synthesis translate_off
 reg dummy_d_289;
 // synthesis translate_on
+always @(*) begin
+	main_litedramcore_en1 <= 1'd0;
+	case (builder_multiplexer_state)
+		1'd1: begin
+			main_litedramcore_en1 <= 1'd1;
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		4'd9: begin
+		end
+		4'd10: begin
+		end
+		default: begin
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_289 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_290;
+// synthesis translate_on
 always @(*) begin
 	main_litedramcore_steerer_sel0 <= 2'd0;
 	case (builder_multiplexer_state)
@@ -11108,12 +11152,12 @@ always @(*) begin
 		end
 	endcase
 // synthesis translate_off
-	dummy_d_289 = dummy_s;
+	dummy_d_290 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_290;
+reg dummy_d_291;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_steerer_sel1 <= 2'd0;
@@ -11156,12 +11200,12 @@ always @(*) begin
 		end
 	endcase
 // synthesis translate_off
-	dummy_d_290 = dummy_s;
+	dummy_d_291 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_291;
+reg dummy_d_292;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_cmd_ready <= 1'd0;
@@ -11191,12 +11235,12 @@ always @(*) begin
 		end
 	endcase
 // synthesis translate_off
-	dummy_d_291 = dummy_s;
+	dummy_d_292 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_292;
+reg dummy_d_293;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_steerer_sel2 <= 2'd0;
@@ -11239,12 +11283,12 @@ always @(*) begin
 		end
 	endcase
 // synthesis translate_off
-	dummy_d_292 = dummy_s;
+	dummy_d_293 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_293;
+reg dummy_d_294;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_choose_cmd_want_activates <= 1'd0;
@@ -11281,12 +11325,12 @@ always @(*) begin
 		end
 	endcase
 // synthesis translate_off
-	dummy_d_293 = dummy_s;
+	dummy_d_294 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_294;
+reg dummy_d_295;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_steerer_sel3 <= 2'd0;
@@ -11329,12 +11373,12 @@ always @(*) begin
 		end
 	endcase
 // synthesis translate_off
-	dummy_d_294 = dummy_s;
+	dummy_d_295 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_295;
+reg dummy_d_296;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_en0 <= 1'd0;
@@ -11364,12 +11408,12 @@ always @(*) begin
 		end
 	endcase
 // synthesis translate_off
-	dummy_d_295 = dummy_s;
+	dummy_d_296 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_296;
+reg dummy_d_297;
 // synthesis translate_on
 always @(*) begin
 	main_litedramcore_choose_cmd_cmd_ready <= 1'd0;
@@ -11405,41 +11449,6 @@ always @(*) begin
 			end
 		end
 	endcase
-// synthesis translate_off
-	dummy_d_296 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_297;
-// synthesis translate_on
-always @(*) begin
-	main_litedramcore_choose_req_want_reads <= 1'd0;
-	case (builder_multiplexer_state)
-		1'd1: begin
-		end
-		2'd2: begin
-		end
-		2'd3: begin
-		end
-		3'd4: begin
-		end
-		3'd5: begin
-		end
-		3'd6: begin
-		end
-		3'd7: begin
-		end
-		4'd8: begin
-		end
-		4'd9: begin
-		end
-		4'd10: begin
-		end
-		default: begin
-			main_litedramcore_choose_req_want_reads <= 1'd1;
-		end
-	endcase
 // synthesis translate_off
 	dummy_d_297 = dummy_s;
 // synthesis translate_on
@@ -11449,10 +11458,9 @@ end
 reg dummy_d_298;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_choose_req_want_writes <= 1'd0;
+	main_litedramcore_choose_req_want_reads <= 1'd0;
 	case (builder_multiplexer_state)
 		1'd1: begin
-			main_litedramcore_choose_req_want_writes <= 1'd1;
 		end
 		2'd2: begin
 		end
@@ -11473,6 +11481,7 @@ always @(*) begin
 		4'd10: begin
 		end
 		default: begin
+			main_litedramcore_choose_req_want_reads <= 1'd1;
 		end
 	endcase
 // synthesis translate_off
@@ -11484,14 +11493,10 @@ end
 reg dummy_d_299;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_choose_req_cmd_ready <= 1'd0;
+	main_litedramcore_choose_req_want_writes <= 1'd0;
 	case (builder_multiplexer_state)
 		1'd1: begin
-			if (1'd0) begin
-				main_litedramcore_choose_req_cmd_ready <= (main_litedramcore_cas_allowed & ((~((main_litedramcore_choose_req_cmd_payload_ras & (~main_litedramcore_choose_req_cmd_payload_cas)) & (~main_litedramcore_choose_req_cmd_payload_we))) | main_litedramcore_ras_allowed));
-			end else begin
-				main_litedramcore_choose_req_cmd_ready <= main_litedramcore_cas_allowed;
-			end
+			main_litedramcore_choose_req_want_writes <= 1'd1;
 		end
 		2'd2: begin
 		end
@@ -11512,11 +11517,6 @@ always @(*) begin
 		4'd10: begin
 		end
 		default: begin
-			if (1'd0) begin
-				main_litedramcore_choose_req_cmd_ready <= (main_litedramcore_cas_allowed & ((~((main_litedramcore_choose_req_cmd_payload_ras & (~main_litedramcore_choose_req_cmd_payload_cas)) & (~main_litedramcore_choose_req_cmd_payload_we))) | main_litedramcore_ras_allowed));
-			end else begin
-				main_litedramcore_choose_req_cmd_ready <= main_litedramcore_cas_allowed;
-			end
 		end
 	endcase
 // synthesis translate_off
@@ -11571,13 +11571,13 @@ assign main_user_port_rdata_valid = builder_new_master_rdata_valid8;
 reg dummy_d_300;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_interface_wdata_we <= 16'd0;
+	main_litedramcore_interface_wdata <= 128'd0;
 	case ({builder_new_master_wdata_ready1})
 		1'd1: begin
-			main_litedramcore_interface_wdata_we <= main_user_port_wdata_payload_we;
+			main_litedramcore_interface_wdata <= main_user_port_wdata_payload_data;
 		end
 		default: begin
-			main_litedramcore_interface_wdata_we <= 1'd0;
+			main_litedramcore_interface_wdata <= 1'd0;
 		end
 	endcase
 // synthesis translate_off
@@ -11589,13 +11589,13 @@ end
 reg dummy_d_301;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_interface_wdata <= 128'd0;
+	main_litedramcore_interface_wdata_we <= 16'd0;
 	case ({builder_new_master_wdata_ready1})
 		1'd1: begin
-			main_litedramcore_interface_wdata <= main_user_port_wdata_payload_data;
+			main_litedramcore_interface_wdata_we <= main_user_port_wdata_payload_we;
 		end
 		default: begin
-			main_litedramcore_interface_wdata <= 1'd0;
+			main_litedramcore_interface_wdata_we <= 1'd0;
 		end
 	endcase
 // synthesis translate_off
@@ -11810,7 +11810,7 @@ assign builder_litedramcore_wishbone_we = main_wb_bus_we;
 assign builder_litedramcore_wishbone_cti = main_wb_bus_cti;
 assign builder_litedramcore_wishbone_bte = main_wb_bus_bte;
 assign main_wb_bus_err = builder_litedramcore_wishbone_err;
-assign builder_csrbank0_sel = (builder_interface0_bank_bus_adr[13:9] == 1'd0);
+assign builder_csrbank0_sel = (builder_interface0_bank_bus_adr[13:9] == 1'd1);
 assign builder_csrbank0_init_done0_r = builder_interface0_bank_bus_dat_w[0];
 
 // synthesis translate_off
@@ -11867,7 +11867,7 @@ always @(*) begin
 end
 assign builder_csrbank0_init_done0_w = main_init_done_storage;
 assign builder_csrbank0_init_error0_w = main_init_error_storage;
-assign builder_csrbank1_sel = (builder_interface1_bank_bus_adr[13:9] == 1'd1);
+assign builder_csrbank1_sel = (builder_interface1_bank_bus_adr[13:9] == 2'd2);
 assign builder_csrbank1_rst0_r = builder_interface1_bank_bus_dat_w[0];
 
 // synthesis translate_off
@@ -11928,9 +11928,9 @@ assign builder_csrbank1_wlevel_en0_r = builder_interface1_bank_bus_dat_w[0];
 reg dummy_d_319;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank1_wlevel_en0_re <= 1'd0;
+	builder_csrbank1_wlevel_en0_we <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd2))) begin
-		builder_csrbank1_wlevel_en0_re <= builder_interface1_bank_bus_we;
+		builder_csrbank1_wlevel_en0_we <= (~builder_interface1_bank_bus_we);
 	end
 // synthesis translate_off
 	dummy_d_319 = dummy_s;
@@ -11941,9 +11941,9 @@ end
 reg dummy_d_320;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank1_wlevel_en0_we <= 1'd0;
+	builder_csrbank1_wlevel_en0_re <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd2))) begin
-		builder_csrbank1_wlevel_en0_we <= (~builder_interface1_bank_bus_we);
+		builder_csrbank1_wlevel_en0_re <= builder_interface1_bank_bus_we;
 	end
 // synthesis translate_off
 	dummy_d_320 = dummy_s;
@@ -11955,9 +11955,9 @@ assign main_a7ddrphy_wlevel_strobe_r = builder_interface1_bank_bus_dat_w[0];
 reg dummy_d_321;
 // synthesis translate_on
 always @(*) begin
-	main_a7ddrphy_wlevel_strobe_re <= 1'd0;
+	main_a7ddrphy_wlevel_strobe_we <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd3))) begin
-		main_a7ddrphy_wlevel_strobe_re <= builder_interface1_bank_bus_we;
+		main_a7ddrphy_wlevel_strobe_we <= (~builder_interface1_bank_bus_we);
 	end
 // synthesis translate_off
 	dummy_d_321 = dummy_s;
@@ -11968,9 +11968,9 @@ end
 reg dummy_d_322;
 // synthesis translate_on
 always @(*) begin
-	main_a7ddrphy_wlevel_strobe_we <= 1'd0;
+	main_a7ddrphy_wlevel_strobe_re <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd3))) begin
-		main_a7ddrphy_wlevel_strobe_we <= (~builder_interface1_bank_bus_we);
+		main_a7ddrphy_wlevel_strobe_re <= builder_interface1_bank_bus_we;
 	end
 // synthesis translate_off
 	dummy_d_322 = dummy_s;
@@ -12063,9 +12063,9 @@ assign main_a7ddrphy_rdly_dq_bitslip_rst_r = builder_interface1_bank_bus_dat_w[0
 reg dummy_d_329;
 // synthesis translate_on
 always @(*) begin
-	main_a7ddrphy_rdly_dq_bitslip_rst_re <= 1'd0;
+	main_a7ddrphy_rdly_dq_bitslip_rst_we <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd7))) begin
-		main_a7ddrphy_rdly_dq_bitslip_rst_re <= builder_interface1_bank_bus_we;
+		main_a7ddrphy_rdly_dq_bitslip_rst_we <= (~builder_interface1_bank_bus_we);
 	end
 // synthesis translate_off
 	dummy_d_329 = dummy_s;
@@ -12076,9 +12076,9 @@ end
 reg dummy_d_330;
 // synthesis translate_on
 always @(*) begin
-	main_a7ddrphy_rdly_dq_bitslip_rst_we <= 1'd0;
+	main_a7ddrphy_rdly_dq_bitslip_rst_re <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd7))) begin
-		main_a7ddrphy_rdly_dq_bitslip_rst_we <= (~builder_interface1_bank_bus_we);
+		main_a7ddrphy_rdly_dq_bitslip_rst_re <= builder_interface1_bank_bus_we;
 	end
 // synthesis translate_off
 	dummy_d_330 = dummy_s;
@@ -12225,7 +12225,7 @@ assign builder_csrbank1_wlevel_en0_w = main_a7ddrphy_wlevel_en_storage;
 assign builder_csrbank1_dly_sel0_w = main_a7ddrphy_dly_sel_storage[1:0];
 assign builder_csrbank1_rdphase0_w = main_a7ddrphy_rdphase_storage[1:0];
 assign builder_csrbank1_wrphase0_w = main_a7ddrphy_wrphase_storage[1:0];
-assign builder_csrbank2_sel = (builder_interface2_bank_bus_adr[13:9] == 2'd2);
+assign builder_csrbank2_sel = (builder_interface2_bank_bus_adr[13:9] == 1'd0);
 assign builder_csrbank2_dfii_control0_r = builder_interface2_bank_bus_dat_w[3:0];
 
 // synthesis translate_off
@@ -12313,9 +12313,9 @@ assign builder_csrbank2_dfii_pi0_address1_r = builder_interface2_bank_bus_dat_w[
 reg dummy_d_347;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi0_address1_we <= 1'd0;
+	builder_csrbank2_dfii_pi0_address1_re <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd3))) begin
-		builder_csrbank2_dfii_pi0_address1_we <= (~builder_interface2_bank_bus_we);
+		builder_csrbank2_dfii_pi0_address1_re <= builder_interface2_bank_bus_we;
 	end
 // synthesis translate_off
 	dummy_d_347 = dummy_s;
@@ -12326,9 +12326,9 @@ end
 reg dummy_d_348;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi0_address1_re <= 1'd0;
+	builder_csrbank2_dfii_pi0_address1_we <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd3))) begin
-		builder_csrbank2_dfii_pi0_address1_re <= builder_interface2_bank_bus_we;
+		builder_csrbank2_dfii_pi0_address1_we <= (~builder_interface2_bank_bus_we);
 	end
 // synthesis translate_off
 	dummy_d_348 = dummy_s;
@@ -12421,9 +12421,9 @@ assign builder_csrbank2_dfii_pi0_wrdata2_r = builder_interface2_bank_bus_dat_w[7
 reg dummy_d_355;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi0_wrdata2_re <= 1'd0;
+	builder_csrbank2_dfii_pi0_wrdata2_we <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd7))) begin
-		builder_csrbank2_dfii_pi0_wrdata2_re <= builder_interface2_bank_bus_we;
+		builder_csrbank2_dfii_pi0_wrdata2_we <= (~builder_interface2_bank_bus_we);
 	end
 // synthesis translate_off
 	dummy_d_355 = dummy_s;
@@ -12434,9 +12434,9 @@ end
 reg dummy_d_356;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi0_wrdata2_we <= 1'd0;
+	builder_csrbank2_dfii_pi0_wrdata2_re <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd7))) begin
-		builder_csrbank2_dfii_pi0_wrdata2_we <= (~builder_interface2_bank_bus_we);
+		builder_csrbank2_dfii_pi0_wrdata2_re <= builder_interface2_bank_bus_we;
 	end
 // synthesis translate_off
 	dummy_d_356 = dummy_s;
@@ -12664,9 +12664,9 @@ assign builder_csrbank2_dfii_pi1_address1_r = builder_interface2_bank_bus_dat_w[
 reg dummy_d_373;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi1_address1_we <= 1'd0;
+	builder_csrbank2_dfii_pi1_address1_re <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd16))) begin
-		builder_csrbank2_dfii_pi1_address1_we <= (~builder_interface2_bank_bus_we);
+		builder_csrbank2_dfii_pi1_address1_re <= builder_interface2_bank_bus_we;
 	end
 // synthesis translate_off
 	dummy_d_373 = dummy_s;
@@ -12677,9 +12677,9 @@ end
 reg dummy_d_374;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi1_address1_re <= 1'd0;
+	builder_csrbank2_dfii_pi1_address1_we <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd16))) begin
-		builder_csrbank2_dfii_pi1_address1_re <= builder_interface2_bank_bus_we;
+		builder_csrbank2_dfii_pi1_address1_we <= (~builder_interface2_bank_bus_we);
 	end
 // synthesis translate_off
 	dummy_d_374 = dummy_s;
@@ -12772,9 +12772,9 @@ assign builder_csrbank2_dfii_pi1_wrdata2_r = builder_interface2_bank_bus_dat_w[7
 reg dummy_d_381;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi1_wrdata2_re <= 1'd0;
+	builder_csrbank2_dfii_pi1_wrdata2_we <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd20))) begin
-		builder_csrbank2_dfii_pi1_wrdata2_re <= builder_interface2_bank_bus_we;
+		builder_csrbank2_dfii_pi1_wrdata2_we <= (~builder_interface2_bank_bus_we);
 	end
 // synthesis translate_off
 	dummy_d_381 = dummy_s;
@@ -12785,9 +12785,9 @@ end
 reg dummy_d_382;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi1_wrdata2_we <= 1'd0;
+	builder_csrbank2_dfii_pi1_wrdata2_re <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd20))) begin
-		builder_csrbank2_dfii_pi1_wrdata2_we <= (~builder_interface2_bank_bus_we);
+		builder_csrbank2_dfii_pi1_wrdata2_re <= builder_interface2_bank_bus_we;
 	end
 // synthesis translate_off
 	dummy_d_382 = dummy_s;
@@ -12988,9 +12988,9 @@ assign main_litedramcore_phaseinjector2_command_issue_r = builder_interface2_ban
 reg dummy_d_397;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_phaseinjector2_command_issue_we <= 1'd0;
+	main_litedramcore_phaseinjector2_command_issue_re <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd28))) begin
-		main_litedramcore_phaseinjector2_command_issue_we <= (~builder_interface2_bank_bus_we);
+		main_litedramcore_phaseinjector2_command_issue_re <= builder_interface2_bank_bus_we;
 	end
 // synthesis translate_off
 	dummy_d_397 = dummy_s;
@@ -13001,9 +13001,9 @@ end
 reg dummy_d_398;
 // synthesis translate_on
 always @(*) begin
-	main_litedramcore_phaseinjector2_command_issue_re <= 1'd0;
+	main_litedramcore_phaseinjector2_command_issue_we <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd28))) begin
-		main_litedramcore_phaseinjector2_command_issue_re <= builder_interface2_bank_bus_we;
+		main_litedramcore_phaseinjector2_command_issue_we <= (~builder_interface2_bank_bus_we);
 	end
 // synthesis translate_off
 	dummy_d_398 = dummy_s;
@@ -13015,9 +13015,9 @@ assign builder_csrbank2_dfii_pi2_address1_r = builder_interface2_bank_bus_dat_w[
 reg dummy_d_399;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi2_address1_we <= 1'd0;
+	builder_csrbank2_dfii_pi2_address1_re <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd29))) begin
-		builder_csrbank2_dfii_pi2_address1_we <= (~builder_interface2_bank_bus_we);
+		builder_csrbank2_dfii_pi2_address1_re <= builder_interface2_bank_bus_we;
 	end
 // synthesis translate_off
 	dummy_d_399 = dummy_s;
@@ -13028,9 +13028,9 @@ end
 reg dummy_d_400;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi2_address1_re <= 1'd0;
+	builder_csrbank2_dfii_pi2_address1_we <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd29))) begin
-		builder_csrbank2_dfii_pi2_address1_re <= builder_interface2_bank_bus_we;
+		builder_csrbank2_dfii_pi2_address1_we <= (~builder_interface2_bank_bus_we);
 	end
 // synthesis translate_off
 	dummy_d_400 = dummy_s;
@@ -13123,9 +13123,9 @@ assign builder_csrbank2_dfii_pi2_wrdata2_r = builder_interface2_bank_bus_dat_w[7
 reg dummy_d_407;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi2_wrdata2_re <= 1'd0;
+	builder_csrbank2_dfii_pi2_wrdata2_we <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd33))) begin
-		builder_csrbank2_dfii_pi2_wrdata2_re <= builder_interface2_bank_bus_we;
+		builder_csrbank2_dfii_pi2_wrdata2_we <= (~builder_interface2_bank_bus_we);
 	end
 // synthesis translate_off
 	dummy_d_407 = dummy_s;
@@ -13136,9 +13136,9 @@ end
 reg dummy_d_408;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi2_wrdata2_we <= 1'd0;
+	builder_csrbank2_dfii_pi2_wrdata2_re <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd33))) begin
-		builder_csrbank2_dfii_pi2_wrdata2_we <= (~builder_interface2_bank_bus_we);
+		builder_csrbank2_dfii_pi2_wrdata2_re <= builder_interface2_bank_bus_we;
 	end
 // synthesis translate_off
 	dummy_d_408 = dummy_s;
@@ -13366,9 +13366,9 @@ assign builder_csrbank2_dfii_pi3_address1_r = builder_interface2_bank_bus_dat_w[
 reg dummy_d_425;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi3_address1_we <= 1'd0;
+	builder_csrbank2_dfii_pi3_address1_re <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd42))) begin
-		builder_csrbank2_dfii_pi3_address1_we <= (~builder_interface2_bank_bus_we);
+		builder_csrbank2_dfii_pi3_address1_re <= builder_interface2_bank_bus_we;
 	end
 // synthesis translate_off
 	dummy_d_425 = dummy_s;
@@ -13379,9 +13379,9 @@ end
 reg dummy_d_426;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi3_address1_re <= 1'd0;
+	builder_csrbank2_dfii_pi3_address1_we <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd42))) begin
-		builder_csrbank2_dfii_pi3_address1_re <= builder_interface2_bank_bus_we;
+		builder_csrbank2_dfii_pi3_address1_we <= (~builder_interface2_bank_bus_we);
 	end
 // synthesis translate_off
 	dummy_d_426 = dummy_s;
@@ -13474,9 +13474,9 @@ assign builder_csrbank2_dfii_pi3_wrdata2_r = builder_interface2_bank_bus_dat_w[7
 reg dummy_d_433;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi3_wrdata2_re <= 1'd0;
+	builder_csrbank2_dfii_pi3_wrdata2_we <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd46))) begin
-		builder_csrbank2_dfii_pi3_wrdata2_re <= builder_interface2_bank_bus_we;
+		builder_csrbank2_dfii_pi3_wrdata2_we <= (~builder_interface2_bank_bus_we);
 	end
 // synthesis translate_off
 	dummy_d_433 = dummy_s;
@@ -13487,9 +13487,9 @@ end
 reg dummy_d_434;
 // synthesis translate_on
 always @(*) begin
-	builder_csrbank2_dfii_pi3_wrdata2_we <= 1'd0;
+	builder_csrbank2_dfii_pi3_wrdata2_re <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd46))) begin
-		builder_csrbank2_dfii_pi3_wrdata2_we <= (~builder_interface2_bank_bus_we);
+		builder_csrbank2_dfii_pi3_wrdata2_re <= builder_interface2_bank_bus_we;
 	end
 // synthesis translate_off
 	dummy_d_434 = dummy_s;
diff --git a/litedram/generated/sim/litedram_core.init b/litedram/generated/sim/litedram_core.init
index 145ccc2..542287d 100644
--- a/litedram/generated/sim/litedram_core.init
+++ b/litedram/generated/sim/litedram_core.init
@@ -7,7 +7,7 @@ a64b5a7d14004a39
 6421ff00782107c6
 3d80000060215f00
 798c07c6618c0000
-618c10d8658cff00
+618c10e0658cff00
 4e8004217d8903a6
 4e8004207c6903a6
 0000000000000000
@@ -518,81 +518,82 @@ a64b5a7d14004a39
 4e80002060000000
 0000000000000000
 3c4c000100000000
-7c0802a63842a2c4
-f8010010fbe1fff8
-f88100d8f821ff51
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 38800080f8a100e0
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 7fe3fb78382100b0
-0000000048001dc8
-0000018001000000
+0000000048001e68
+0000028001000000
 000000004e800020
 0000000000000000
 4c00012c7c0007ac
 000000004e800020
 0000000000000000
-3842a2283c4c0001
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 7d8000267c0802a6
-9181000848001d05
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 3c62ffff60000000
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 788400203c80c000
 7c8026ea7c0004ac
 3fe0c0003c62ffff
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 4d80000073e90004
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 4d00000073e90008
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 4182001073e90010
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 3c62ffff41820010
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 3c80c000418e0028
 7884002060840010
 7c8026ea7c0004ac
 7884b5823c62ffff
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 3c80c0004192004c
 7884002060840018
 7c8026ea7c0004ac
 788460223c62ffff
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 608400303c80c000
 7c0004ac78840020
 3c62ffff7c8026ea
-38637c487884b282
-3d20c0004bfffdfd
+38637bf87884b282
+3d20c0004bfffdf5
 7929002061290020
 7d204eea7c0004ac
 792906003c80000f
 3c62ffff60844240
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 614a600439200002
 7c0004ac794a0020
 3fe0c0007d2057aa
@@ -600,145 +601,146 @@ f9410108f9210100
 7c0004ac7bff0020
 7c0004ac7d20ffaa
 579c063e7f80feaa
-7fa0feaa7c0004ac
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 3c62ffff57ff063e
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 2c0900007d29fb78
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 3f9cf0007b450020
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diff --git a/litedram/generated/sim/litedram_core.v b/litedram/generated/sim/litedram_core.v
index 4129d77..398d7ad 100644
--- a/litedram/generated/sim/litedram_core.v
+++ b/litedram/generated/sim/litedram_core.v
@@ -1,5 +1,5 @@
 //--------------------------------------------------------------------------------
-// Auto-generated by Migen (27dbf03) & LiteX (78c1751c) on 2021-08-15 06:19:19
+// Auto-generated by Migen (a5bc262) & LiteX (de028765) on 2021-09-24 12:36:42
 //--------------------------------------------------------------------------------
 module litedram_core(
 	input wire sim_trace,
@@ -2124,36 +2124,36 @@ always @(*) begin
 	soc_ddrphy_activates1[3] = soc_ddrphy_dfiphasemodel3_activate;
 end
 always @(*) begin
-	soc_ddrphy_bankmodel1_activate = 1'd0;
+	soc_ddrphy_bankmodel1_activate_row = 14'd0;
 	case (soc_ddrphy_activates1)
 		1'd1: begin
-			soc_ddrphy_bankmodel1_activate = (soc_ddrphy_dfi_p0_bank == 1'd1);
+			soc_ddrphy_bankmodel1_activate_row = soc_ddrphy_dfi_p0_address;
 		end
 		2'd2: begin
-			soc_ddrphy_bankmodel1_activate = (soc_ddrphy_dfi_p1_bank == 1'd1);
+			soc_ddrphy_bankmodel1_activate_row = soc_ddrphy_dfi_p1_address;
 		end
 		3'd4: begin
-			soc_ddrphy_bankmodel1_activate = (soc_ddrphy_dfi_p2_bank == 1'd1);
+			soc_ddrphy_bankmodel1_activate_row = soc_ddrphy_dfi_p2_address;
 		end
 		4'd8: begin
-			soc_ddrphy_bankmodel1_activate = (soc_ddrphy_dfi_p3_bank == 1'd1);
+			soc_ddrphy_bankmodel1_activate_row = soc_ddrphy_dfi_p3_address;
 		end
 	endcase
 end
 always @(*) begin
-	soc_ddrphy_bankmodel1_activate_row = 14'd0;
+	soc_ddrphy_bankmodel1_activate = 1'd0;
 	case (soc_ddrphy_activates1)
 		1'd1: begin
-			soc_ddrphy_bankmodel1_activate_row = soc_ddrphy_dfi_p0_address;
+			soc_ddrphy_bankmodel1_activate = (soc_ddrphy_dfi_p0_bank == 1'd1);
 		end
 		2'd2: begin
-			soc_ddrphy_bankmodel1_activate_row = soc_ddrphy_dfi_p1_address;
+			soc_ddrphy_bankmodel1_activate = (soc_ddrphy_dfi_p1_bank == 1'd1);
 		end
 		3'd4: begin
-			soc_ddrphy_bankmodel1_activate_row = soc_ddrphy_dfi_p2_address;
+			soc_ddrphy_bankmodel1_activate = (soc_ddrphy_dfi_p2_bank == 1'd1);
 		end
 		4'd8: begin
-			soc_ddrphy_bankmodel1_activate_row = soc_ddrphy_dfi_p3_address;
+			soc_ddrphy_bankmodel1_activate = (soc_ddrphy_dfi_p3_bank == 1'd1);
 		end
 	endcase
 end
@@ -2838,36 +2838,36 @@ always @(*) begin
 	soc_ddrphy_reads5[3] = soc_ddrphy_dfiphasemodel3_read;
 end
 always @(*) begin
-	soc_ddrphy_bankmodel5_read_col = 10'd0;
+	soc_ddrphy_bankmodel5_read = 1'd0;
 	case (soc_ddrphy_reads5)
 		1'd1: begin
-			soc_ddrphy_bankmodel5_read_col = soc_ddrphy_dfi_p0_address;
+			soc_ddrphy_bankmodel5_read = (soc_ddrphy_dfi_p0_bank == 3'd5);
 		end
 		2'd2: begin
-			soc_ddrphy_bankmodel5_read_col = soc_ddrphy_dfi_p1_address;
+			soc_ddrphy_bankmodel5_read = (soc_ddrphy_dfi_p1_bank == 3'd5);
 		end
 		3'd4: begin
-			soc_ddrphy_bankmodel5_read_col = soc_ddrphy_dfi_p2_address;
+			soc_ddrphy_bankmodel5_read = (soc_ddrphy_dfi_p2_bank == 3'd5);
 		end
 		4'd8: begin
-			soc_ddrphy_bankmodel5_read_col = soc_ddrphy_dfi_p3_address;
+			soc_ddrphy_bankmodel5_read = (soc_ddrphy_dfi_p3_bank == 3'd5);
 		end
 	endcase
 end
 always @(*) begin
-	soc_ddrphy_bankmodel5_read = 1'd0;
+	soc_ddrphy_bankmodel5_read_col = 10'd0;
 	case (soc_ddrphy_reads5)
 		1'd1: begin
-			soc_ddrphy_bankmodel5_read = (soc_ddrphy_dfi_p0_bank == 3'd5);
+			soc_ddrphy_bankmodel5_read_col = soc_ddrphy_dfi_p0_address;
 		end
 		2'd2: begin
-			soc_ddrphy_bankmodel5_read = (soc_ddrphy_dfi_p1_bank == 3'd5);
+			soc_ddrphy_bankmodel5_read_col = soc_ddrphy_dfi_p1_address;
 		end
 		3'd4: begin
-			soc_ddrphy_bankmodel5_read = (soc_ddrphy_dfi_p2_bank == 3'd5);
+			soc_ddrphy_bankmodel5_read_col = soc_ddrphy_dfi_p2_address;
 		end
 		4'd8: begin
-			soc_ddrphy_bankmodel5_read = (soc_ddrphy_dfi_p3_bank == 3'd5);
+			soc_ddrphy_bankmodel5_read_col = soc_ddrphy_dfi_p3_address;
 		end
 	endcase
 end
@@ -3030,36 +3030,36 @@ always @(*) begin
 	soc_ddrphy_activates7[3] = soc_ddrphy_dfiphasemodel3_activate;
 end
 always @(*) begin
-	soc_ddrphy_bankmodel7_activate_row = 14'd0;
+	soc_ddrphy_bankmodel7_activate = 1'd0;
 	case (soc_ddrphy_activates7)
 		1'd1: begin
-			soc_ddrphy_bankmodel7_activate_row = soc_ddrphy_dfi_p0_address;
+			soc_ddrphy_bankmodel7_activate = (soc_ddrphy_dfi_p0_bank == 3'd7);
 		end
 		2'd2: begin
-			soc_ddrphy_bankmodel7_activate_row = soc_ddrphy_dfi_p1_address;
+			soc_ddrphy_bankmodel7_activate = (soc_ddrphy_dfi_p1_bank == 3'd7);
 		end
 		3'd4: begin
-			soc_ddrphy_bankmodel7_activate_row = soc_ddrphy_dfi_p2_address;
+			soc_ddrphy_bankmodel7_activate = (soc_ddrphy_dfi_p2_bank == 3'd7);
 		end
 		4'd8: begin
-			soc_ddrphy_bankmodel7_activate_row = soc_ddrphy_dfi_p3_address;
+			soc_ddrphy_bankmodel7_activate = (soc_ddrphy_dfi_p3_bank == 3'd7);
 		end
 	endcase
 end
 always @(*) begin
-	soc_ddrphy_bankmodel7_activate = 1'd0;
+	soc_ddrphy_bankmodel7_activate_row = 14'd0;
 	case (soc_ddrphy_activates7)
 		1'd1: begin
-			soc_ddrphy_bankmodel7_activate = (soc_ddrphy_dfi_p0_bank == 3'd7);
+			soc_ddrphy_bankmodel7_activate_row = soc_ddrphy_dfi_p0_address;
 		end
 		2'd2: begin
-			soc_ddrphy_bankmodel7_activate = (soc_ddrphy_dfi_p1_bank == 3'd7);
+			soc_ddrphy_bankmodel7_activate_row = soc_ddrphy_dfi_p1_address;
 		end
 		3'd4: begin
-			soc_ddrphy_bankmodel7_activate = (soc_ddrphy_dfi_p2_bank == 3'd7);
+			soc_ddrphy_bankmodel7_activate_row = soc_ddrphy_dfi_p2_address;
 		end
 		4'd8: begin
-			soc_ddrphy_bankmodel7_activate = (soc_ddrphy_dfi_p3_bank == 3'd7);
+			soc_ddrphy_bankmodel7_activate_row = soc_ddrphy_dfi_p3_address;
 		end
 	endcase
 end
@@ -3140,36 +3140,36 @@ always @(*) begin
 	soc_ddrphy_reads7[3] = soc_ddrphy_dfiphasemodel3_read;
 end
 always @(*) begin
-	soc_ddrphy_bankmodel7_read = 1'd0;
+	soc_ddrphy_bankmodel7_read_col = 10'd0;
 	case (soc_ddrphy_reads7)
 		1'd1: begin
-			soc_ddrphy_bankmodel7_read = (soc_ddrphy_dfi_p0_bank == 3'd7);
+			soc_ddrphy_bankmodel7_read_col = soc_ddrphy_dfi_p0_address;
 		end
 		2'd2: begin
-			soc_ddrphy_bankmodel7_read = (soc_ddrphy_dfi_p1_bank == 3'd7);
+			soc_ddrphy_bankmodel7_read_col = soc_ddrphy_dfi_p1_address;
 		end
 		3'd4: begin
-			soc_ddrphy_bankmodel7_read = (soc_ddrphy_dfi_p2_bank == 3'd7);
+			soc_ddrphy_bankmodel7_read_col = soc_ddrphy_dfi_p2_address;
 		end
 		4'd8: begin
-			soc_ddrphy_bankmodel7_read = (soc_ddrphy_dfi_p3_bank == 3'd7);
+			soc_ddrphy_bankmodel7_read_col = soc_ddrphy_dfi_p3_address;
 		end
 	endcase
 end
 always @(*) begin
-	soc_ddrphy_bankmodel7_read_col = 10'd0;
+	soc_ddrphy_bankmodel7_read = 1'd0;
 	case (soc_ddrphy_reads7)
 		1'd1: begin
-			soc_ddrphy_bankmodel7_read_col = soc_ddrphy_dfi_p0_address;
+			soc_ddrphy_bankmodel7_read = (soc_ddrphy_dfi_p0_bank == 3'd7);
 		end
 		2'd2: begin
-			soc_ddrphy_bankmodel7_read_col = soc_ddrphy_dfi_p1_address;
+			soc_ddrphy_bankmodel7_read = (soc_ddrphy_dfi_p1_bank == 3'd7);
 		end
 		3'd4: begin
-			soc_ddrphy_bankmodel7_read_col = soc_ddrphy_dfi_p2_address;
+			soc_ddrphy_bankmodel7_read = (soc_ddrphy_dfi_p2_bank == 3'd7);
 		end
 		4'd8: begin
-			soc_ddrphy_bankmodel7_read_col = soc_ddrphy_dfi_p3_address;
+			soc_ddrphy_bankmodel7_read = (soc_ddrphy_dfi_p3_bank == 3'd7);
 		end
 	endcase
 end
@@ -3321,6 +3321,14 @@ always @(*) begin
 end
 assign soc_ddrphy_bankmodel1_wraddr = slice_proxy2[24:3];
 assign soc_ddrphy_bankmodel1_rdaddr = slice_proxy3[24:3];
+always @(*) begin
+	soc_ddrphy_bankmodel1_read_data = 128'd0;
+	if (soc_ddrphy_bankmodel1_active) begin
+		if (soc_ddrphy_bankmodel1_read) begin
+			soc_ddrphy_bankmodel1_read_data = soc_ddrphy_bankmodel1_read_port_dat_r;
+		end
+	end
+end
 always @(*) begin
 	soc_ddrphy_bankmodel1_write_port_adr = 21'd0;
 	if (soc_ddrphy_bankmodel1_active) begin
@@ -3351,14 +3359,6 @@ always @(*) begin
 		end
 	end
 end
-always @(*) begin
-	soc_ddrphy_bankmodel1_read_data = 128'd0;
-	if (soc_ddrphy_bankmodel1_active) begin
-		if (soc_ddrphy_bankmodel1_read) begin
-			soc_ddrphy_bankmodel1_read_data = soc_ddrphy_bankmodel1_read_port_dat_r;
-		end
-	end
-end
 assign soc_ddrphy_bankmodel2_wraddr = slice_proxy4[24:3];
 assign soc_ddrphy_bankmodel2_rdaddr = slice_proxy5[24:3];
 always @(*) begin
@@ -3441,6 +3441,12 @@ always @(*) begin
 end
 assign soc_ddrphy_bankmodel4_wraddr = slice_proxy8[24:3];
 assign soc_ddrphy_bankmodel4_rdaddr = slice_proxy9[24:3];
+always @(*) begin
+	soc_ddrphy_bankmodel4_write_port_dat_w = 128'd0;
+	if (soc_ddrphy_bankmodel4_active) begin
+		soc_ddrphy_bankmodel4_write_port_dat_w = soc_ddrphy_bankmodel4_write_data;
+	end
+end
 always @(*) begin
 	soc_ddrphy_bankmodel4_read_port_adr = 21'd0;
 	if (soc_ddrphy_bankmodel4_active) begin
@@ -3473,12 +3479,6 @@ always @(*) begin
 		end
 	end
 end
-always @(*) begin
-	soc_ddrphy_bankmodel4_write_port_dat_w = 128'd0;
-	if (soc_ddrphy_bankmodel4_active) begin
-		soc_ddrphy_bankmodel4_write_port_dat_w = soc_ddrphy_bankmodel4_write_data;
-	end
-end
 assign soc_ddrphy_bankmodel5_wraddr = slice_proxy10[24:3];
 assign soc_ddrphy_bankmodel5_rdaddr = slice_proxy11[24:3];
 always @(*) begin
@@ -3944,14 +3944,6 @@ always @(*) begin
 		soc_litedramcore_inti_p2_rddata_valid = soc_litedramcore_master_p2_rddata_valid;
 	end
 end
-always @(*) begin
-	soc_litedramcore_master_p0_ras_n = 1'd1;
-	if (soc_litedramcore_sel) begin
-		soc_litedramcore_master_p0_ras_n = soc_litedramcore_slave_p0_ras_n;
-	end else begin
-		soc_litedramcore_master_p0_ras_n = soc_litedramcore_inti_p0_ras_n;
-	end
-end
 always @(*) begin
 	soc_litedramcore_master_p1_wrdata_mask = 4'd0;
 	if (soc_litedramcore_sel) begin
@@ -3968,6 +3960,14 @@ always @(*) begin
 		soc_litedramcore_master_p1_rddata_en = soc_litedramcore_inti_p1_rddata_en;
 	end
 end
+always @(*) begin
+	soc_litedramcore_master_p0_ras_n = 1'd1;
+	if (soc_litedramcore_sel) begin
+		soc_litedramcore_master_p0_ras_n = soc_litedramcore_slave_p0_ras_n;
+	end else begin
+		soc_litedramcore_master_p0_ras_n = soc_litedramcore_inti_p0_ras_n;
+	end
+end
 always @(*) begin
 	soc_litedramcore_master_p2_address = 14'd0;
 	if (soc_litedramcore_sel) begin
@@ -9670,10 +9670,10 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	soc_litedramcore_en1 = 1'd0;
+	soc_litedramcore_choose_req_want_writes = 1'd0;
 	case (multiplexer_state)
 		1'd1: begin
-			soc_litedramcore_en1 = 1'd1;
+			soc_litedramcore_choose_req_want_writes = 1'd1;
 		end
 		2'd2: begin
 		end
@@ -9698,10 +9698,10 @@ always @(*) begin
 	endcase
 end
 always @(*) begin
-	soc_litedramcore_choose_req_want_writes = 1'd0;
+	soc_litedramcore_en1 = 1'd0;
 	case (multiplexer_state)
 		1'd1: begin
-			soc_litedramcore_choose_req_want_writes = 1'd1;
+			soc_litedramcore_en1 = 1'd1;
 		end
 		2'd2: begin
 		end
@@ -9806,24 +9806,24 @@ assign soc_user_port_cmd_ready = ((((((((1'd0 | (((roundrobin0_grant == 1'd0) &
 assign soc_user_port_wdata_ready = new_master_wdata_ready1;
 assign soc_user_port_rdata_valid = new_master_rdata_valid8;
 always @(*) begin
-	soc_litedramcore_interface_wdata_we = 16'd0;
+	soc_litedramcore_interface_wdata = 128'd0;
 	case ({new_master_wdata_ready1})
 		1'd1: begin
-			soc_litedramcore_interface_wdata_we = soc_user_port_wdata_payload_we;
+			soc_litedramcore_interface_wdata = soc_user_port_wdata_payload_data;
 		end
 		default: begin
-			soc_litedramcore_interface_wdata_we = 1'd0;
+			soc_litedramcore_interface_wdata = 1'd0;
 		end
 	endcase
 end
 always @(*) begin
-	soc_litedramcore_interface_wdata = 128'd0;
+	soc_litedramcore_interface_wdata_we = 16'd0;
 	case ({new_master_wdata_ready1})
 		1'd1: begin
-			soc_litedramcore_interface_wdata = soc_user_port_wdata_payload_data;
+			soc_litedramcore_interface_wdata_we = soc_user_port_wdata_payload_we;
 		end
 		default: begin
-			soc_litedramcore_interface_wdata = 1'd0;
+			soc_litedramcore_interface_wdata_we = 1'd0;
 		end
 	endcase
 end
@@ -9853,6 +9853,21 @@ always @(*) begin
 		end
 	endcase
 end
+always @(*) begin
+	litedramcore_adr_next_value1 = 14'd0;
+	case (state)
+		1'd1: begin
+			litedramcore_adr_next_value1 = 1'd0;
+		end
+		2'd2: begin
+		end
+		default: begin
+			if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
+				litedramcore_adr_next_value1 = litedramcore_wishbone_adr;
+			end
+		end
+	endcase
+end
 always @(*) begin
 	litedramcore_adr_next_value_ce1 = 1'd0;
 	case (state)
@@ -9946,21 +9961,6 @@ always @(*) begin
 		end
 	endcase
 end
-always @(*) begin
-	litedramcore_adr_next_value1 = 14'd0;
-	case (state)
-		1'd1: begin
-			litedramcore_adr_next_value1 = 1'd0;
-		end
-		2'd2: begin
-		end
-		default: begin
-			if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
-				litedramcore_adr_next_value1 = litedramcore_wishbone_adr;
-			end
-		end
-	endcase
-end
 assign litedramcore_wishbone_adr = soc_wb_bus_adr;
 assign litedramcore_wishbone_dat_w = soc_wb_bus_dat_w;
 assign soc_wb_bus_dat_r = litedramcore_wishbone_dat_r;
@@ -9972,7 +9972,7 @@ assign litedramcore_wishbone_we = soc_wb_bus_we;
 assign litedramcore_wishbone_cti = soc_wb_bus_cti;
 assign litedramcore_wishbone_bte = soc_wb_bus_bte;
 assign soc_wb_bus_err = litedramcore_wishbone_err;
-assign csrbank0_sel = (interface0_bank_bus_adr[13:9] == 1'd0);
+assign csrbank0_sel = (interface0_bank_bus_adr[13:9] == 1'd1);
 assign csrbank0_init_done0_r = interface0_bank_bus_dat_w[0];
 always @(*) begin
 	csrbank0_init_done0_we = 1'd0;
@@ -10001,7 +10001,7 @@ always @(*) begin
 end
 assign csrbank0_init_done0_w = soc_init_done_storage;
 assign csrbank0_init_error0_w = soc_init_error_storage;
-assign csrbank1_sel = (interface1_bank_bus_adr[13:9] == 1'd1);
+assign csrbank1_sel = (interface1_bank_bus_adr[13:9] == 1'd0);
 assign csrbank1_dfii_control0_r = interface1_bank_bus_dat_w[3:0];
 always @(*) begin
 	csrbank1_dfii_control0_re = 1'd0;
@@ -10017,15 +10017,15 @@ always @(*) begin
 end
 assign csrbank1_dfii_pi0_command0_r = interface1_bank_bus_dat_w[5:0];
 always @(*) begin
-	csrbank1_dfii_pi0_command0_re = 1'd0;
+	csrbank1_dfii_pi0_command0_we = 1'd0;
 	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd1))) begin
-		csrbank1_dfii_pi0_command0_re = interface1_bank_bus_we;
+		csrbank1_dfii_pi0_command0_we = (~interface1_bank_bus_we);
 	end
 end
 always @(*) begin
-	csrbank1_dfii_pi0_command0_we = 1'd0;
+	csrbank1_dfii_pi0_command0_re = 1'd0;
 	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd1))) begin
-		csrbank1_dfii_pi0_command0_we = (~interface1_bank_bus_we);
+		csrbank1_dfii_pi0_command0_re = interface1_bank_bus_we;
 	end
 end
 assign soc_litedramcore_phaseinjector0_command_issue_r = interface1_bank_bus_dat_w[0];
@@ -10082,15 +10082,15 @@ always @(*) begin
 end
 assign csrbank1_dfii_pi0_wrdata3_r = interface1_bank_bus_dat_w[7:0];
 always @(*) begin
-	csrbank1_dfii_pi0_wrdata3_we = 1'd0;
+	csrbank1_dfii_pi0_wrdata3_re = 1'd0;
 	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd6))) begin
-		csrbank1_dfii_pi0_wrdata3_we = (~interface1_bank_bus_we);
+		csrbank1_dfii_pi0_wrdata3_re = interface1_bank_bus_we;
 	end
 end
 always @(*) begin
-	csrbank1_dfii_pi0_wrdata3_re = 1'd0;
+	csrbank1_dfii_pi0_wrdata3_we = 1'd0;
 	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd6))) begin
-		csrbank1_dfii_pi0_wrdata3_re = interface1_bank_bus_we;
+		csrbank1_dfii_pi0_wrdata3_we = (~interface1_bank_bus_we);
 	end
 end
 assign csrbank1_dfii_pi0_wrdata2_r = interface1_bank_bus_dat_w[7:0];
@@ -10134,15 +10134,15 @@ always @(*) begin
 end
 assign csrbank1_dfii_pi0_rddata3_r = interface1_bank_bus_dat_w[7:0];
 always @(*) begin
-	csrbank1_dfii_pi0_rddata3_re = 1'd0;
+	csrbank1_dfii_pi0_rddata3_we = 1'd0;
 	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd10))) begin
-		csrbank1_dfii_pi0_rddata3_re = interface1_bank_bus_we;
+		csrbank1_dfii_pi0_rddata3_we = (~interface1_bank_bus_we);
 	end
 end
 always @(*) begin
-	csrbank1_dfii_pi0_rddata3_we = 1'd0;
+	csrbank1_dfii_pi0_rddata3_re = 1'd0;
 	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd10))) begin
-		csrbank1_dfii_pi0_rddata3_we = (~interface1_bank_bus_we);
+		csrbank1_dfii_pi0_rddata3_re = interface1_bank_bus_we;
 	end
 end
 assign csrbank1_dfii_pi0_rddata2_r = interface1_bank_bus_dat_w[7:0];
@@ -10160,15 +10160,15 @@ always @(*) begin
 end
 assign csrbank1_dfii_pi0_rddata1_r = interface1_bank_bus_dat_w[7:0];
 always @(*) begin
-	csrbank1_dfii_pi0_rddata1_we = 1'd0;
+	csrbank1_dfii_pi0_rddata1_re = 1'd0;
 	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd12))) begin
-		csrbank1_dfii_pi0_rddata1_we = (~interface1_bank_bus_we);
+		csrbank1_dfii_pi0_rddata1_re = interface1_bank_bus_we;
 	end
 end
 always @(*) begin
-	csrbank1_dfii_pi0_rddata1_re = 1'd0;
+	csrbank1_dfii_pi0_rddata1_we = 1'd0;
 	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd12))) begin
-		csrbank1_dfii_pi0_rddata1_re = interface1_bank_bus_we;
+		csrbank1_dfii_pi0_rddata1_we = (~interface1_bank_bus_we);
 	end
 end
 assign csrbank1_dfii_pi0_rddata0_r = interface1_bank_bus_dat_w[7:0];
@@ -10186,15 +10186,15 @@ always @(*) begin
 end
 assign csrbank1_dfii_pi1_command0_r = interface1_bank_bus_dat_w[5:0];
 always @(*) begin
-	csrbank1_dfii_pi1_command0_re = 1'd0;
+	csrbank1_dfii_pi1_command0_we = 1'd0;
 	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd14))) begin
-		csrbank1_dfii_pi1_command0_re = interface1_bank_bus_we;
+		csrbank1_dfii_pi1_command0_we = (~interface1_bank_bus_we);
 	end
 end
 always @(*) begin
-	csrbank1_dfii_pi1_command0_we = 1'd0;
+	csrbank1_dfii_pi1_command0_re = 1'd0;
 	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd14))) begin
-		csrbank1_dfii_pi1_command0_we = (~interface1_bank_bus_we);
+		csrbank1_dfii_pi1_command0_re = interface1_bank_bus_we;
 	end
 end
 assign soc_litedramcore_phaseinjector1_command_issue_r = interface1_bank_bus_dat_w[0];
@@ -10251,15 +10251,15 @@ always @(*) begin
 end
 assign csrbank1_dfii_pi1_wrdata3_r = interface1_bank_bus_dat_w[7:0];
 always @(*) begin
-	csrbank1_dfii_pi1_wrdata3_we = 1'd0;
+	csrbank1_dfii_pi1_wrdata3_re = 1'd0;
 	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd19))) begin
-		csrbank1_dfii_pi1_wrdata3_we = (~interface1_bank_bus_we);
+		csrbank1_dfii_pi1_wrdata3_re = interface1_bank_bus_we;
 	end
 end
 always @(*) begin
-	csrbank1_dfii_pi1_wrdata3_re = 1'd0;
+	csrbank1_dfii_pi1_wrdata3_we = 1'd0;
 	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd19))) begin
-		csrbank1_dfii_pi1_wrdata3_re = interface1_bank_bus_we;
+		csrbank1_dfii_pi1_wrdata3_we = (~interface1_bank_bus_we);
 	end
 end
 assign csrbank1_dfii_pi1_wrdata2_r = interface1_bank_bus_dat_w[7:0];
@@ -10303,15 +10303,15 @@ always @(*) begin
 end
 assign csrbank1_dfii_pi1_rddata3_r = interface1_bank_bus_dat_w[7:0];
 always @(*) begin
-	csrbank1_dfii_pi1_rddata3_re = 1'd0;
+	csrbank1_dfii_pi1_rddata3_we = 1'd0;
 	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd23))) begin
-		csrbank1_dfii_pi1_rddata3_re = interface1_bank_bus_we;
+		csrbank1_dfii_pi1_rddata3_we = (~interface1_bank_bus_we);
 	end
 end
 always @(*) begin
-	csrbank1_dfii_pi1_rddata3_we = 1'd0;
+	csrbank1_dfii_pi1_rddata3_re = 1'd0;
 	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd23))) begin
-		csrbank1_dfii_pi1_rddata3_we = (~interface1_bank_bus_we);
+		csrbank1_dfii_pi1_rddata3_re = interface1_bank_bus_we;
 	end
 end
 assign csrbank1_dfii_pi1_rddata2_r = interface1_bank_bus_dat_w[7:0];
@@ -10329,15 +10329,15 @@ always @(*) begin
 end
 assign csrbank1_dfii_pi1_rddata1_r = interface1_bank_bus_dat_w[7:0];
 always @(*) begin
-	csrbank1_dfii_pi1_rddata1_we = 1'd0;
+	csrbank1_dfii_pi1_rddata1_re = 1'd0;
 	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd25))) begin
-		csrbank1_dfii_pi1_rddata1_we = (~interface1_bank_bus_we);
+		csrbank1_dfii_pi1_rddata1_re = interface1_bank_bus_we;
 	end
 end
 always @(*) begin
-	csrbank1_dfii_pi1_rddata1_re = 1'd0;
+	csrbank1_dfii_pi1_rddata1_we = 1'd0;
 	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd25))) begin
-		csrbank1_dfii_pi1_rddata1_re = interface1_bank_bus_we;
+		csrbank1_dfii_pi1_rddata1_we = (~interface1_bank_bus_we);
 	end
 end
 assign csrbank1_dfii_pi1_rddata0_r = interface1_bank_bus_dat_w[7:0];
@@ -10355,28 +10355,28 @@ always @(*) begin
 end
 assign csrbank1_dfii_pi2_command0_r = interface1_bank_bus_dat_w[5:0];
 always @(*) begin
-	csrbank1_dfii_pi2_command0_re = 1'd0;
+	csrbank1_dfii_pi2_command0_we = 1'd0;
 	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd27))) begin
-		csrbank1_dfii_pi2_command0_re = interface1_bank_bus_we;
+		csrbank1_dfii_pi2_command0_we = (~interface1_bank_bus_we);
 	end
 end
 always @(*) begin
-	csrbank1_dfii_pi2_command0_we = 1'd0;
+	csrbank1_dfii_pi2_command0_re = 1'd0;
 	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd27))) begin
-		csrbank1_dfii_pi2_command0_we = (~interface1_bank_bus_we);
+		csrbank1_dfii_pi2_command0_re = interface1_bank_bus_we;
 	end
 end
 assign soc_litedramcore_phaseinjector2_command_issue_r = interface1_bank_bus_dat_w[0];
 always @(*) begin
-	soc_litedramcore_phaseinjector2_command_issue_we = 1'd0;
+	soc_litedramcore_phaseinjector2_command_issue_re = 1'd0;
 	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd28))) begin
-		soc_litedramcore_phaseinjector2_command_issue_we = (~interface1_bank_bus_we);
+		soc_litedramcore_phaseinjector2_command_issue_re = interface1_bank_bus_we;
 	end
 end
 always @(*) begin
-	soc_litedramcore_phaseinjector2_command_issue_re = 1'd0;
+	soc_litedramcore_phaseinjector2_command_issue_we = 1'd0;
 	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd28))) begin
-		soc_litedramcore_phaseinjector2_command_issue_re = interface1_bank_bus_we;
+		soc_litedramcore_phaseinjector2_command_issue_we = (~interface1_bank_bus_we);
 	end
 end
 assign csrbank1_dfii_pi2_address1_r = interface1_bank_bus_dat_w[5:0];
@@ -10420,15 +10420,15 @@ always @(*) begin
 end
 assign csrbank1_dfii_pi2_wrdata3_r = interface1_bank_bus_dat_w[7:0];
 always @(*) begin
-	csrbank1_dfii_pi2_wrdata3_we = 1'd0;
+	csrbank1_dfii_pi2_wrdata3_re = 1'd0;
 	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd32))) begin
-		csrbank1_dfii_pi2_wrdata3_we = (~interface1_bank_bus_we);
+		csrbank1_dfii_pi2_wrdata3_re = interface1_bank_bus_we;
 	end
 end
 always @(*) begin
-	csrbank1_dfii_pi2_wrdata3_re = 1'd0;
+	csrbank1_dfii_pi2_wrdata3_we = 1'd0;
 	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd32))) begin
-		csrbank1_dfii_pi2_wrdata3_re = interface1_bank_bus_we;
+		csrbank1_dfii_pi2_wrdata3_we = (~interface1_bank_bus_we);
 	end
 end
 assign csrbank1_dfii_pi2_wrdata2_r = interface1_bank_bus_dat_w[7:0];
@@ -10472,15 +10472,15 @@ always @(*) begin
 end
 assign csrbank1_dfii_pi2_rddata3_r = interface1_bank_bus_dat_w[7:0];
 always @(*) begin
-	csrbank1_dfii_pi2_rddata3_re = 1'd0;
+	csrbank1_dfii_pi2_rddata3_we = 1'd0;
 	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd36))) begin
-		csrbank1_dfii_pi2_rddata3_re = interface1_bank_bus_we;
+		csrbank1_dfii_pi2_rddata3_we = (~interface1_bank_bus_we);
 	end
 end
 always @(*) begin
-	csrbank1_dfii_pi2_rddata3_we = 1'd0;
+	csrbank1_dfii_pi2_rddata3_re = 1'd0;
 	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd36))) begin
-		csrbank1_dfii_pi2_rddata3_we = (~interface1_bank_bus_we);
+		csrbank1_dfii_pi2_rddata3_re = interface1_bank_bus_we;
 	end
 end
 assign csrbank1_dfii_pi2_rddata2_r = interface1_bank_bus_dat_w[7:0];
@@ -10498,15 +10498,15 @@ always @(*) begin
 end
 assign csrbank1_dfii_pi2_rddata1_r = interface1_bank_bus_dat_w[7:0];
 always @(*) begin
-	csrbank1_dfii_pi2_rddata1_we = 1'd0;
+	csrbank1_dfii_pi2_rddata1_re = 1'd0;
 	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd38))) begin
-		csrbank1_dfii_pi2_rddata1_we = (~interface1_bank_bus_we);
+		csrbank1_dfii_pi2_rddata1_re = interface1_bank_bus_we;
 	end
 end
 always @(*) begin
-	csrbank1_dfii_pi2_rddata1_re = 1'd0;
+	csrbank1_dfii_pi2_rddata1_we = 1'd0;
 	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd38))) begin
-		csrbank1_dfii_pi2_rddata1_re = interface1_bank_bus_we;
+		csrbank1_dfii_pi2_rddata1_we = (~interface1_bank_bus_we);
 	end
 end
 assign csrbank1_dfii_pi2_rddata0_r = interface1_bank_bus_dat_w[7:0];
@@ -10524,15 +10524,15 @@ always @(*) begin
 end
 assign csrbank1_dfii_pi3_command0_r = interface1_bank_bus_dat_w[5:0];
 always @(*) begin
-	csrbank1_dfii_pi3_command0_re = 1'd0;
+	csrbank1_dfii_pi3_command0_we = 1'd0;
 	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd40))) begin
-		csrbank1_dfii_pi3_command0_re = interface1_bank_bus_we;
+		csrbank1_dfii_pi3_command0_we = (~interface1_bank_bus_we);
 	end
 end
 always @(*) begin
-	csrbank1_dfii_pi3_command0_we = 1'd0;
+	csrbank1_dfii_pi3_command0_re = 1'd0;
 	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd40))) begin
-		csrbank1_dfii_pi3_command0_we = (~interface1_bank_bus_we);
+		csrbank1_dfii_pi3_command0_re = interface1_bank_bus_we;
 	end
 end
 assign soc_litedramcore_phaseinjector3_command_issue_r = interface1_bank_bus_dat_w[0];
@@ -10589,15 +10589,15 @@ always @(*) begin
 end
 assign csrbank1_dfii_pi3_wrdata3_r = interface1_bank_bus_dat_w[7:0];
 always @(*) begin
-	csrbank1_dfii_pi3_wrdata3_we = 1'd0;
+	csrbank1_dfii_pi3_wrdata3_re = 1'd0;
 	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd45))) begin
-		csrbank1_dfii_pi3_wrdata3_we = (~interface1_bank_bus_we);
+		csrbank1_dfii_pi3_wrdata3_re = interface1_bank_bus_we;
 	end
 end
 always @(*) begin
-	csrbank1_dfii_pi3_wrdata3_re = 1'd0;
+	csrbank1_dfii_pi3_wrdata3_we = 1'd0;
 	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd45))) begin
-		csrbank1_dfii_pi3_wrdata3_re = interface1_bank_bus_we;
+		csrbank1_dfii_pi3_wrdata3_we = (~interface1_bank_bus_we);
 	end
 end
 assign csrbank1_dfii_pi3_wrdata2_r = interface1_bank_bus_dat_w[7:0];
@@ -10641,15 +10641,15 @@ always @(*) begin
 end
 assign csrbank1_dfii_pi3_rddata3_r = interface1_bank_bus_dat_w[7:0];
 always @(*) begin
-	csrbank1_dfii_pi3_rddata3_re = 1'd0;
+	csrbank1_dfii_pi3_rddata3_we = 1'd0;
 	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd49))) begin
-		csrbank1_dfii_pi3_rddata3_re = interface1_bank_bus_we;
+		csrbank1_dfii_pi3_rddata3_we = (~interface1_bank_bus_we);
 	end
 end
 always @(*) begin
-	csrbank1_dfii_pi3_rddata3_we = 1'd0;
+	csrbank1_dfii_pi3_rddata3_re = 1'd0;
 	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd49))) begin
-		csrbank1_dfii_pi3_rddata3_we = (~interface1_bank_bus_we);
+		csrbank1_dfii_pi3_rddata3_re = interface1_bank_bus_we;
 	end
 end
 assign csrbank1_dfii_pi3_rddata2_r = interface1_bank_bus_dat_w[7:0];
@@ -10667,15 +10667,15 @@ always @(*) begin
 end
 assign csrbank1_dfii_pi3_rddata1_r = interface1_bank_bus_dat_w[7:0];
 always @(*) begin
-	csrbank1_dfii_pi3_rddata1_we = 1'd0;
+	csrbank1_dfii_pi3_rddata1_re = 1'd0;
 	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd51))) begin
-		csrbank1_dfii_pi3_rddata1_we = (~interface1_bank_bus_we);
+		csrbank1_dfii_pi3_rddata1_re = interface1_bank_bus_we;
 	end
 end
 always @(*) begin
-	csrbank1_dfii_pi3_rddata1_re = 1'd0;
+	csrbank1_dfii_pi3_rddata1_we = 1'd0;
 	if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 6'd51))) begin
-		csrbank1_dfii_pi3_rddata1_re = interface1_bank_bus_we;
+		csrbank1_dfii_pi3_rddata1_we = (~interface1_bank_bus_we);
 	end
 end
 assign csrbank1_dfii_pi3_rddata0_r = interface1_bank_bus_dat_w[7:0];
diff --git a/litedram/generated/wukong-v2/litedram-initmem.vhdl b/litedram/generated/wukong-v2/litedram-initmem.vhdl
new file mode 100644
index 0000000..395602b
--- /dev/null
+++ b/litedram/generated/wukong-v2/litedram-initmem.vhdl
@@ -0,0 +1,123 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use std.textio.all;
+
+library work;
+use work.wishbone_types.all;
+use work.utils.all;
+
+entity dram_init_mem is
+    generic (
+        EXTRA_PAYLOAD_FILE : string   := "";
+        EXTRA_PAYLOAD_SIZE : integer  := 0
+        );
+    port (
+        clk     : in std_ulogic;
+        wb_in   : in wb_io_master_out;
+        wb_out  : out wb_io_slave_out
+      );
+end entity dram_init_mem;
+
+architecture rtl of dram_init_mem is
+
+    constant INIT_RAM_SIZE    : integer := 24576;
+    constant RND_PAYLOAD_SIZE : integer := round_up(EXTRA_PAYLOAD_SIZE, 8);
+    constant TOTAL_RAM_SIZE   : integer := INIT_RAM_SIZE + RND_PAYLOAD_SIZE;
+    constant INIT_RAM_ABITS   : integer := log2ceil(TOTAL_RAM_SIZE-1);
+    constant INIT_RAM_FILE    : string := "litedram_core.init";
+
+    type ram_t is array(0 to (TOTAL_RAM_SIZE / 4) - 1) of std_logic_vector(31 downto 0);
+
+    -- XXX FIXME: Have a single init function called twice with
+    -- an offset as argument
+    procedure init_load_payload(ram: inout ram_t; filename: string) is
+        file payload_file : text open read_mode is filename;
+        variable ram_line : line;
+        variable temp_word : std_logic_vector(63 downto 0);
+    begin
+        for i in 0 to RND_PAYLOAD_SIZE-1 loop
+            exit when endfile(payload_file);
+            readline(payload_file, ram_line);
+            hread(ram_line, temp_word);
+            ram((INIT_RAM_SIZE/4) + i*2) := temp_word(31 downto 0);
+            ram((INIT_RAM_SIZE/4) + i*2+1) := temp_word(63 downto 32);
+        end loop;
+        assert endfile(payload_file) report "Payload too big !" severity failure;
+    end procedure;
+
+    impure function init_load_ram(name : string) return ram_t is
+        file ram_file : text open read_mode is name;
+        variable temp_word : std_logic_vector(63 downto 0);
+        variable temp_ram : ram_t := (others => (others => '0'));
+        variable ram_line : line;
+    begin
+        report "Payload size:" & integer'image(EXTRA_PAYLOAD_SIZE) &
+            " rounded to:" & integer'image(RND_PAYLOAD_SIZE);
+        report "Total RAM size:" & integer'image(TOTAL_RAM_SIZE) &
+            " bytes using " & integer'image(INIT_RAM_ABITS) &
+            " address bits";
+        for i in 0 to (INIT_RAM_SIZE/8)-1 loop
+            exit when endfile(ram_file);
+            readline(ram_file, ram_line);
+            hread(ram_line, temp_word);
+            temp_ram(i*2) := temp_word(31 downto 0);
+            temp_ram(i*2+1) := temp_word(63 downto 32);
+        end loop;
+        if RND_PAYLOAD_SIZE /= 0 then
+            init_load_payload(temp_ram, EXTRA_PAYLOAD_FILE);
+        end if;
+        return temp_ram;
+    end function;
+
+    impure function init_zero return ram_t is
+        variable temp_ram : ram_t := (others => (others => '0'));
+    begin
+        return temp_ram;
+    end function;
+
+    impure function initialize_ram(filename: string) return ram_t is
+    begin
+        report "Opening file " & filename;
+        if filename'length = 0 then
+            return init_zero;
+        else
+            return init_load_ram(filename);
+        end if;
+    end function;
+    signal init_ram : ram_t := initialize_ram(INIT_RAM_FILE);
+
+    attribute ram_style : string;
+    attribute ram_style of init_ram: signal is "block";
+
+    signal obuf : std_ulogic_vector(31 downto 0);
+    signal oack : std_ulogic;
+begin
+
+    init_ram_0: process(clk)
+        variable adr  : integer;
+    begin
+        if rising_edge(clk) then
+            oack <= '0';
+            if (wb_in.cyc and wb_in.stb) = '1' then
+                adr := to_integer((unsigned(wb_in.adr(INIT_RAM_ABITS-1 downto 2))));
+                if wb_in.we = '0' then
+                   obuf <= init_ram(adr);
+                else
+                    for i in 0 to 3 loop
+                        if wb_in.sel(i) = '1' then
+                            init_ram(adr)(((i + 1) * 8) - 1 downto i * 8) <=
+                                wb_in.dat(((i + 1) * 8) - 1 downto i * 8);
+                        end if;
+                    end loop;
+                end if;
+                oack <= '1';
+            end if;
+            wb_out.ack <= oack;
+            wb_out.dat <= obuf;
+        end if;
+    end process;
+
+    wb_out.stall <= '0';
+
+end architecture rtl;
diff --git a/litedram/generated/wukong-v2/litedram_core.init b/litedram/generated/wukong-v2/litedram_core.init
new file mode 100644
index 0000000..5b1a383
--- /dev/null
+++ b/litedram/generated/wukong-v2/litedram_core.init
@@ -0,0 +1,2073 @@
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diff --git a/litedram/generated/wukong-v2/litedram_core.v b/litedram/generated/wukong-v2/litedram_core.v
new file mode 100644
index 0000000..166195f
--- /dev/null
+++ b/litedram/generated/wukong-v2/litedram_core.v
@@ -0,0 +1,19851 @@
+//--------------------------------------------------------------------------------
+// Auto-generated by Migen (a5bc262) & LiteX (de028765) on 2021-09-24 12:36:40
+//--------------------------------------------------------------------------------
+module litedram_core(
+	input wire clk,
+	input wire rst,
+	output wire pll_locked,
+	output wire [13:0] ddram_a,
+	output wire [2:0] ddram_ba,
+	output wire ddram_ras_n,
+	output wire ddram_cas_n,
+	output wire ddram_we_n,
+	output wire ddram_cs_n,
+	output wire [1:0] ddram_dm,
+	inout wire [15:0] ddram_dq,
+	inout wire [1:0] ddram_dqs_p,
+	inout wire [1:0] ddram_dqs_n,
+	output wire ddram_clk_p,
+	output wire ddram_clk_n,
+	output wire ddram_cke,
+	output wire ddram_odt,
+	output wire ddram_reset_n,
+	output wire init_done,
+	output wire init_error,
+	input wire [29:0] wb_ctrl_adr,
+	input wire [31:0] wb_ctrl_dat_w,
+	output wire [31:0] wb_ctrl_dat_r,
+	input wire [3:0] wb_ctrl_sel,
+	input wire wb_ctrl_cyc,
+	input wire wb_ctrl_stb,
+	output wire wb_ctrl_ack,
+	input wire wb_ctrl_we,
+	input wire [2:0] wb_ctrl_cti,
+	input wire [1:0] wb_ctrl_bte,
+	output wire wb_ctrl_err,
+	output wire user_clk,
+	output wire user_rst,
+	input wire user_port_native_0_cmd_valid,
+	output wire user_port_native_0_cmd_ready,
+	input wire user_port_native_0_cmd_we,
+	input wire [23:0] user_port_native_0_cmd_addr,
+	input wire user_port_native_0_wdata_valid,
+	output wire user_port_native_0_wdata_ready,
+	input wire [15:0] user_port_native_0_wdata_we,
+	input wire [127:0] user_port_native_0_wdata_data,
+	output wire user_port_native_0_rdata_valid,
+	input wire user_port_native_0_rdata_ready,
+	output wire [127:0] user_port_native_0_rdata_data
+);
+
+wire sys_clk;
+wire sys_rst;
+wire sys4x_clk;
+wire sys4x_dqs_clk;
+wire iodelay_clk;
+wire iodelay_rst;
+wire main_reset;
+reg main_power_down = 1'd0;
+wire main_locked;
+wire main_clkin;
+wire main_clkout0;
+wire main_clkout_buf0;
+wire main_clkout1;
+wire main_clkout_buf1;
+wire main_clkout2;
+wire main_clkout_buf2;
+wire main_clkout3;
+wire main_clkout_buf3;
+reg [3:0] main_reset_counter = 4'd15;
+reg main_ic_reset = 1'd1;
+reg main_a7ddrphy_rst_storage = 1'd0;
+reg main_a7ddrphy_rst_re = 1'd0;
+reg [4:0] main_a7ddrphy_half_sys8x_taps_storage = 5'd8;
+reg main_a7ddrphy_half_sys8x_taps_re = 1'd0;
+reg main_a7ddrphy_wlevel_en_storage = 1'd0;
+reg main_a7ddrphy_wlevel_en_re = 1'd0;
+reg main_a7ddrphy_wlevel_strobe_re = 1'd0;
+wire main_a7ddrphy_wlevel_strobe_r;
+reg main_a7ddrphy_wlevel_strobe_we = 1'd0;
+reg main_a7ddrphy_wlevel_strobe_w = 1'd0;
+reg [1:0] main_a7ddrphy_dly_sel_storage = 2'd0;
+reg main_a7ddrphy_dly_sel_re = 1'd0;
+reg main_a7ddrphy_rdly_dq_rst_re = 1'd0;
+wire main_a7ddrphy_rdly_dq_rst_r;
+reg main_a7ddrphy_rdly_dq_rst_we = 1'd0;
+reg main_a7ddrphy_rdly_dq_rst_w = 1'd0;
+reg main_a7ddrphy_rdly_dq_inc_re = 1'd0;
+wire main_a7ddrphy_rdly_dq_inc_r;
+reg main_a7ddrphy_rdly_dq_inc_we = 1'd0;
+reg main_a7ddrphy_rdly_dq_inc_w = 1'd0;
+reg main_a7ddrphy_rdly_dq_bitslip_rst_re = 1'd0;
+wire main_a7ddrphy_rdly_dq_bitslip_rst_r;
+reg main_a7ddrphy_rdly_dq_bitslip_rst_we = 1'd0;
+reg main_a7ddrphy_rdly_dq_bitslip_rst_w = 1'd0;
+reg main_a7ddrphy_rdly_dq_bitslip_re = 1'd0;
+wire main_a7ddrphy_rdly_dq_bitslip_r;
+reg main_a7ddrphy_rdly_dq_bitslip_we = 1'd0;
+reg main_a7ddrphy_rdly_dq_bitslip_w = 1'd0;
+reg main_a7ddrphy_wdly_dq_bitslip_rst_re = 1'd0;
+wire main_a7ddrphy_wdly_dq_bitslip_rst_r;
+reg main_a7ddrphy_wdly_dq_bitslip_rst_we = 1'd0;
+reg main_a7ddrphy_wdly_dq_bitslip_rst_w = 1'd0;
+reg main_a7ddrphy_wdly_dq_bitslip_re = 1'd0;
+wire main_a7ddrphy_wdly_dq_bitslip_r;
+reg main_a7ddrphy_wdly_dq_bitslip_we = 1'd0;
+reg main_a7ddrphy_wdly_dq_bitslip_w = 1'd0;
+reg [1:0] main_a7ddrphy_rdphase_storage = 2'd2;
+reg main_a7ddrphy_rdphase_re = 1'd0;
+reg [1:0] main_a7ddrphy_wrphase_storage = 2'd3;
+reg main_a7ddrphy_wrphase_re = 1'd0;
+wire [13:0] main_a7ddrphy_dfi_p0_address;
+wire [2:0] main_a7ddrphy_dfi_p0_bank;
+wire main_a7ddrphy_dfi_p0_cas_n;
+wire main_a7ddrphy_dfi_p0_cs_n;
+wire main_a7ddrphy_dfi_p0_ras_n;
+wire main_a7ddrphy_dfi_p0_we_n;
+wire main_a7ddrphy_dfi_p0_cke;
+wire main_a7ddrphy_dfi_p0_odt;
+wire main_a7ddrphy_dfi_p0_reset_n;
+wire main_a7ddrphy_dfi_p0_act_n;
+wire [31:0] main_a7ddrphy_dfi_p0_wrdata;
+wire main_a7ddrphy_dfi_p0_wrdata_en;
+wire [3:0] main_a7ddrphy_dfi_p0_wrdata_mask;
+wire main_a7ddrphy_dfi_p0_rddata_en;
+reg [31:0] main_a7ddrphy_dfi_p0_rddata = 32'd0;
+wire main_a7ddrphy_dfi_p0_rddata_valid;
+wire [13:0] main_a7ddrphy_dfi_p1_address;
+wire [2:0] main_a7ddrphy_dfi_p1_bank;
+wire main_a7ddrphy_dfi_p1_cas_n;
+wire main_a7ddrphy_dfi_p1_cs_n;
+wire main_a7ddrphy_dfi_p1_ras_n;
+wire main_a7ddrphy_dfi_p1_we_n;
+wire main_a7ddrphy_dfi_p1_cke;
+wire main_a7ddrphy_dfi_p1_odt;
+wire main_a7ddrphy_dfi_p1_reset_n;
+wire main_a7ddrphy_dfi_p1_act_n;
+wire [31:0] main_a7ddrphy_dfi_p1_wrdata;
+wire main_a7ddrphy_dfi_p1_wrdata_en;
+wire [3:0] main_a7ddrphy_dfi_p1_wrdata_mask;
+wire main_a7ddrphy_dfi_p1_rddata_en;
+reg [31:0] main_a7ddrphy_dfi_p1_rddata = 32'd0;
+wire main_a7ddrphy_dfi_p1_rddata_valid;
+wire [13:0] main_a7ddrphy_dfi_p2_address;
+wire [2:0] main_a7ddrphy_dfi_p2_bank;
+wire main_a7ddrphy_dfi_p2_cas_n;
+wire main_a7ddrphy_dfi_p2_cs_n;
+wire main_a7ddrphy_dfi_p2_ras_n;
+wire main_a7ddrphy_dfi_p2_we_n;
+wire main_a7ddrphy_dfi_p2_cke;
+wire main_a7ddrphy_dfi_p2_odt;
+wire main_a7ddrphy_dfi_p2_reset_n;
+wire main_a7ddrphy_dfi_p2_act_n;
+wire [31:0] main_a7ddrphy_dfi_p2_wrdata;
+wire main_a7ddrphy_dfi_p2_wrdata_en;
+wire [3:0] main_a7ddrphy_dfi_p2_wrdata_mask;
+wire main_a7ddrphy_dfi_p2_rddata_en;
+reg [31:0] main_a7ddrphy_dfi_p2_rddata = 32'd0;
+wire main_a7ddrphy_dfi_p2_rddata_valid;
+wire [13:0] main_a7ddrphy_dfi_p3_address;
+wire [2:0] main_a7ddrphy_dfi_p3_bank;
+wire main_a7ddrphy_dfi_p3_cas_n;
+wire main_a7ddrphy_dfi_p3_cs_n;
+wire main_a7ddrphy_dfi_p3_ras_n;
+wire main_a7ddrphy_dfi_p3_we_n;
+wire main_a7ddrphy_dfi_p3_cke;
+wire main_a7ddrphy_dfi_p3_odt;
+wire main_a7ddrphy_dfi_p3_reset_n;
+wire main_a7ddrphy_dfi_p3_act_n;
+wire [31:0] main_a7ddrphy_dfi_p3_wrdata;
+wire main_a7ddrphy_dfi_p3_wrdata_en;
+wire [3:0] main_a7ddrphy_dfi_p3_wrdata_mask;
+wire main_a7ddrphy_dfi_p3_rddata_en;
+reg [31:0] main_a7ddrphy_dfi_p3_rddata = 32'd0;
+wire main_a7ddrphy_dfi_p3_rddata_valid;
+wire main_a7ddrphy_sd_clk_se_nodelay;
+reg main_a7ddrphy_dqs_oe = 1'd0;
+wire main_a7ddrphy_dqs_preamble;
+wire main_a7ddrphy_dqs_postamble;
+wire main_a7ddrphy_dqs_oe_delay_tappeddelayline;
+reg main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 = 1'd0;
+reg main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 = 1'd0;
+reg main_a7ddrphy_dqspattern0 = 1'd0;
+reg main_a7ddrphy_dqspattern1 = 1'd0;
+reg [7:0] main_a7ddrphy_dqspattern_o0 = 8'd0;
+reg [7:0] main_a7ddrphy_dqspattern_o1 = 8'd0;
+wire main_a7ddrphy_dqs_o_no_delay0;
+wire main_a7ddrphy_dqs_t0;
+reg [7:0] main_a7ddrphy_bitslip00 = 8'd0;
+reg [2:0] main_a7ddrphy_bitslip0_value0 = 3'd7;
+reg [15:0] main_a7ddrphy_bitslip0_r0 = 16'd0;
+wire main_a7ddrphy0;
+wire main_a7ddrphy_dqs_o_no_delay1;
+wire main_a7ddrphy_dqs_t1;
+reg [7:0] main_a7ddrphy_bitslip10 = 8'd0;
+reg [2:0] main_a7ddrphy_bitslip1_value0 = 3'd7;
+reg [15:0] main_a7ddrphy_bitslip1_r0 = 16'd0;
+wire main_a7ddrphy1;
+reg [7:0] main_a7ddrphy_bitslip01 = 8'd0;
+reg [2:0] main_a7ddrphy_bitslip0_value1 = 3'd7;
+reg [15:0] main_a7ddrphy_bitslip0_r1 = 16'd0;
+reg [7:0] main_a7ddrphy_bitslip11 = 8'd0;
+reg [2:0] main_a7ddrphy_bitslip1_value1 = 3'd7;
+reg [15:0] main_a7ddrphy_bitslip1_r1 = 16'd0;
+wire main_a7ddrphy_dq_oe;
+wire main_a7ddrphy_dq_oe_delay_tappeddelayline;
+reg main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 = 1'd0;
+reg main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 = 1'd0;
+wire main_a7ddrphy_dq_o_nodelay0;
+wire main_a7ddrphy_dq_i_nodelay0;
+wire main_a7ddrphy_dq_i_delayed0;
+wire main_a7ddrphy_dq_t0;
+reg [7:0] main_a7ddrphy_bitslip02 = 8'd0;
+reg [2:0] main_a7ddrphy_bitslip0_value2 = 3'd7;
+reg [15:0] main_a7ddrphy_bitslip0_r2 = 16'd0;
+wire [7:0] main_a7ddrphy_bitslip03;
+reg [7:0] main_a7ddrphy_bitslip04 = 8'd0;
+reg [2:0] main_a7ddrphy_bitslip0_value3 = 3'd7;
+reg [15:0] main_a7ddrphy_bitslip0_r3 = 16'd0;
+wire main_a7ddrphy_dq_o_nodelay1;
+wire main_a7ddrphy_dq_i_nodelay1;
+wire main_a7ddrphy_dq_i_delayed1;
+wire main_a7ddrphy_dq_t1;
+reg [7:0] main_a7ddrphy_bitslip12 = 8'd0;
+reg [2:0] main_a7ddrphy_bitslip1_value2 = 3'd7;
+reg [15:0] main_a7ddrphy_bitslip1_r2 = 16'd0;
+wire [7:0] main_a7ddrphy_bitslip13;
+reg [7:0] main_a7ddrphy_bitslip14 = 8'd0;
+reg [2:0] main_a7ddrphy_bitslip1_value3 = 3'd7;
+reg [15:0] main_a7ddrphy_bitslip1_r3 = 16'd0;
+wire main_a7ddrphy_dq_o_nodelay2;
+wire main_a7ddrphy_dq_i_nodelay2;
+wire main_a7ddrphy_dq_i_delayed2;
+wire main_a7ddrphy_dq_t2;
+reg [7:0] main_a7ddrphy_bitslip20 = 8'd0;
+reg [2:0] main_a7ddrphy_bitslip2_value0 = 3'd7;
+reg [15:0] main_a7ddrphy_bitslip2_r0 = 16'd0;
+wire [7:0] main_a7ddrphy_bitslip21;
+reg [7:0] main_a7ddrphy_bitslip22 = 8'd0;
+reg [2:0] main_a7ddrphy_bitslip2_value1 = 3'd7;
+reg [15:0] main_a7ddrphy_bitslip2_r1 = 16'd0;
+wire main_a7ddrphy_dq_o_nodelay3;
+wire main_a7ddrphy_dq_i_nodelay3;
+wire main_a7ddrphy_dq_i_delayed3;
+wire main_a7ddrphy_dq_t3;
+reg [7:0] main_a7ddrphy_bitslip30 = 8'd0;
+reg [2:0] main_a7ddrphy_bitslip3_value0 = 3'd7;
+reg [15:0] main_a7ddrphy_bitslip3_r0 = 16'd0;
+wire [7:0] main_a7ddrphy_bitslip31;
+reg [7:0] main_a7ddrphy_bitslip32 = 8'd0;
+reg [2:0] main_a7ddrphy_bitslip3_value1 = 3'd7;
+reg [15:0] main_a7ddrphy_bitslip3_r1 = 16'd0;
+wire main_a7ddrphy_dq_o_nodelay4;
+wire main_a7ddrphy_dq_i_nodelay4;
+wire main_a7ddrphy_dq_i_delayed4;
+wire main_a7ddrphy_dq_t4;
+reg [7:0] main_a7ddrphy_bitslip40 = 8'd0;
+reg [2:0] main_a7ddrphy_bitslip4_value0 = 3'd7;
+reg [15:0] main_a7ddrphy_bitslip4_r0 = 16'd0;
+wire [7:0] main_a7ddrphy_bitslip41;
+reg [7:0] main_a7ddrphy_bitslip42 = 8'd0;
+reg [2:0] main_a7ddrphy_bitslip4_value1 = 3'd7;
+reg [15:0] main_a7ddrphy_bitslip4_r1 = 16'd0;
+wire main_a7ddrphy_dq_o_nodelay5;
+wire main_a7ddrphy_dq_i_nodelay5;
+wire main_a7ddrphy_dq_i_delayed5;
+wire main_a7ddrphy_dq_t5;
+reg [7:0] main_a7ddrphy_bitslip50 = 8'd0;
+reg [2:0] main_a7ddrphy_bitslip5_value0 = 3'd7;
+reg [15:0] main_a7ddrphy_bitslip5_r0 = 16'd0;
+wire [7:0] main_a7ddrphy_bitslip51;
+reg [7:0] main_a7ddrphy_bitslip52 = 8'd0;
+reg [2:0] main_a7ddrphy_bitslip5_value1 = 3'd7;
+reg [15:0] main_a7ddrphy_bitslip5_r1 = 16'd0;
+wire main_a7ddrphy_dq_o_nodelay6;
+wire main_a7ddrphy_dq_i_nodelay6;
+wire main_a7ddrphy_dq_i_delayed6;
+wire main_a7ddrphy_dq_t6;
+reg [7:0] main_a7ddrphy_bitslip60 = 8'd0;
+reg [2:0] main_a7ddrphy_bitslip6_value0 = 3'd7;
+reg [15:0] main_a7ddrphy_bitslip6_r0 = 16'd0;
+wire [7:0] main_a7ddrphy_bitslip61;
+reg [7:0] main_a7ddrphy_bitslip62 = 8'd0;
+reg [2:0] main_a7ddrphy_bitslip6_value1 = 3'd7;
+reg [15:0] main_a7ddrphy_bitslip6_r1 = 16'd0;
+wire main_a7ddrphy_dq_o_nodelay7;
+wire main_a7ddrphy_dq_i_nodelay7;
+wire main_a7ddrphy_dq_i_delayed7;
+wire main_a7ddrphy_dq_t7;
+reg [7:0] main_a7ddrphy_bitslip70 = 8'd0;
+reg [2:0] main_a7ddrphy_bitslip7_value0 = 3'd7;
+reg [15:0] main_a7ddrphy_bitslip7_r0 = 16'd0;
+wire [7:0] main_a7ddrphy_bitslip71;
+reg [7:0] main_a7ddrphy_bitslip72 = 8'd0;
+reg [2:0] main_a7ddrphy_bitslip7_value1 = 3'd7;
+reg [15:0] main_a7ddrphy_bitslip7_r1 = 16'd0;
+wire main_a7ddrphy_dq_o_nodelay8;
+wire main_a7ddrphy_dq_i_nodelay8;
+wire main_a7ddrphy_dq_i_delayed8;
+wire main_a7ddrphy_dq_t8;
+reg [7:0] main_a7ddrphy_bitslip80 = 8'd0;
+reg [2:0] main_a7ddrphy_bitslip8_value0 = 3'd7;
+reg [15:0] main_a7ddrphy_bitslip8_r0 = 16'd0;
+wire [7:0] main_a7ddrphy_bitslip81;
+reg [7:0] main_a7ddrphy_bitslip82 = 8'd0;
+reg [2:0] main_a7ddrphy_bitslip8_value1 = 3'd7;
+reg [15:0] main_a7ddrphy_bitslip8_r1 = 16'd0;
+wire main_a7ddrphy_dq_o_nodelay9;
+wire main_a7ddrphy_dq_i_nodelay9;
+wire main_a7ddrphy_dq_i_delayed9;
+wire main_a7ddrphy_dq_t9;
+reg [7:0] main_a7ddrphy_bitslip90 = 8'd0;
+reg [2:0] main_a7ddrphy_bitslip9_value0 = 3'd7;
+reg [15:0] main_a7ddrphy_bitslip9_r0 = 16'd0;
+wire [7:0] main_a7ddrphy_bitslip91;
+reg [7:0] main_a7ddrphy_bitslip92 = 8'd0;
+reg [2:0] main_a7ddrphy_bitslip9_value1 = 3'd7;
+reg [15:0] main_a7ddrphy_bitslip9_r1 = 16'd0;
+wire main_a7ddrphy_dq_o_nodelay10;
+wire main_a7ddrphy_dq_i_nodelay10;
+wire main_a7ddrphy_dq_i_delayed10;
+wire main_a7ddrphy_dq_t10;
+reg [7:0] main_a7ddrphy_bitslip100 = 8'd0;
+reg [2:0] main_a7ddrphy_bitslip10_value0 = 3'd7;
+reg [15:0] main_a7ddrphy_bitslip10_r0 = 16'd0;
+wire [7:0] main_a7ddrphy_bitslip101;
+reg [7:0] main_a7ddrphy_bitslip102 = 8'd0;
+reg [2:0] main_a7ddrphy_bitslip10_value1 = 3'd7;
+reg [15:0] main_a7ddrphy_bitslip10_r1 = 16'd0;
+wire main_a7ddrphy_dq_o_nodelay11;
+wire main_a7ddrphy_dq_i_nodelay11;
+wire main_a7ddrphy_dq_i_delayed11;
+wire main_a7ddrphy_dq_t11;
+reg [7:0] main_a7ddrphy_bitslip110 = 8'd0;
+reg [2:0] main_a7ddrphy_bitslip11_value0 = 3'd7;
+reg [15:0] main_a7ddrphy_bitslip11_r0 = 16'd0;
+wire [7:0] main_a7ddrphy_bitslip111;
+reg [7:0] main_a7ddrphy_bitslip112 = 8'd0;
+reg [2:0] main_a7ddrphy_bitslip11_value1 = 3'd7;
+reg [15:0] main_a7ddrphy_bitslip11_r1 = 16'd0;
+wire main_a7ddrphy_dq_o_nodelay12;
+wire main_a7ddrphy_dq_i_nodelay12;
+wire main_a7ddrphy_dq_i_delayed12;
+wire main_a7ddrphy_dq_t12;
+reg [7:0] main_a7ddrphy_bitslip120 = 8'd0;
+reg [2:0] main_a7ddrphy_bitslip12_value0 = 3'd7;
+reg [15:0] main_a7ddrphy_bitslip12_r0 = 16'd0;
+wire [7:0] main_a7ddrphy_bitslip121;
+reg [7:0] main_a7ddrphy_bitslip122 = 8'd0;
+reg [2:0] main_a7ddrphy_bitslip12_value1 = 3'd7;
+reg [15:0] main_a7ddrphy_bitslip12_r1 = 16'd0;
+wire main_a7ddrphy_dq_o_nodelay13;
+wire main_a7ddrphy_dq_i_nodelay13;
+wire main_a7ddrphy_dq_i_delayed13;
+wire main_a7ddrphy_dq_t13;
+reg [7:0] main_a7ddrphy_bitslip130 = 8'd0;
+reg [2:0] main_a7ddrphy_bitslip13_value0 = 3'd7;
+reg [15:0] main_a7ddrphy_bitslip13_r0 = 16'd0;
+wire [7:0] main_a7ddrphy_bitslip131;
+reg [7:0] main_a7ddrphy_bitslip132 = 8'd0;
+reg [2:0] main_a7ddrphy_bitslip13_value1 = 3'd7;
+reg [15:0] main_a7ddrphy_bitslip13_r1 = 16'd0;
+wire main_a7ddrphy_dq_o_nodelay14;
+wire main_a7ddrphy_dq_i_nodelay14;
+wire main_a7ddrphy_dq_i_delayed14;
+wire main_a7ddrphy_dq_t14;
+reg [7:0] main_a7ddrphy_bitslip140 = 8'd0;
+reg [2:0] main_a7ddrphy_bitslip14_value0 = 3'd7;
+reg [15:0] main_a7ddrphy_bitslip14_r0 = 16'd0;
+wire [7:0] main_a7ddrphy_bitslip141;
+reg [7:0] main_a7ddrphy_bitslip142 = 8'd0;
+reg [2:0] main_a7ddrphy_bitslip14_value1 = 3'd7;
+reg [15:0] main_a7ddrphy_bitslip14_r1 = 16'd0;
+wire main_a7ddrphy_dq_o_nodelay15;
+wire main_a7ddrphy_dq_i_nodelay15;
+wire main_a7ddrphy_dq_i_delayed15;
+wire main_a7ddrphy_dq_t15;
+reg [7:0] main_a7ddrphy_bitslip150 = 8'd0;
+reg [2:0] main_a7ddrphy_bitslip15_value0 = 3'd7;
+reg [15:0] main_a7ddrphy_bitslip15_r0 = 16'd0;
+wire [7:0] main_a7ddrphy_bitslip151;
+reg [7:0] main_a7ddrphy_bitslip152 = 8'd0;
+reg [2:0] main_a7ddrphy_bitslip15_value1 = 3'd7;
+reg [15:0] main_a7ddrphy_bitslip15_r1 = 16'd0;
+reg main_a7ddrphy_rddata_en_tappeddelayline0 = 1'd0;
+reg main_a7ddrphy_rddata_en_tappeddelayline1 = 1'd0;
+reg main_a7ddrphy_rddata_en_tappeddelayline2 = 1'd0;
+reg main_a7ddrphy_rddata_en_tappeddelayline3 = 1'd0;
+reg main_a7ddrphy_rddata_en_tappeddelayline4 = 1'd0;
+reg main_a7ddrphy_rddata_en_tappeddelayline5 = 1'd0;
+reg main_a7ddrphy_rddata_en_tappeddelayline6 = 1'd0;
+reg main_a7ddrphy_rddata_en_tappeddelayline7 = 1'd0;
+reg main_a7ddrphy_wrdata_en_tappeddelayline0 = 1'd0;
+reg main_a7ddrphy_wrdata_en_tappeddelayline1 = 1'd0;
+reg main_a7ddrphy_wrdata_en_tappeddelayline2 = 1'd0;
+wire [13:0] main_litedramcore_inti_p0_address;
+wire [2:0] main_litedramcore_inti_p0_bank;
+reg main_litedramcore_inti_p0_cas_n = 1'd1;
+reg main_litedramcore_inti_p0_cs_n = 1'd1;
+reg main_litedramcore_inti_p0_ras_n = 1'd1;
+reg main_litedramcore_inti_p0_we_n = 1'd1;
+wire main_litedramcore_inti_p0_cke;
+wire main_litedramcore_inti_p0_odt;
+wire main_litedramcore_inti_p0_reset_n;
+reg main_litedramcore_inti_p0_act_n = 1'd1;
+wire [31:0] main_litedramcore_inti_p0_wrdata;
+wire main_litedramcore_inti_p0_wrdata_en;
+wire [3:0] main_litedramcore_inti_p0_wrdata_mask;
+wire main_litedramcore_inti_p0_rddata_en;
+reg [31:0] main_litedramcore_inti_p0_rddata = 32'd0;
+reg main_litedramcore_inti_p0_rddata_valid = 1'd0;
+wire [13:0] main_litedramcore_inti_p1_address;
+wire [2:0] main_litedramcore_inti_p1_bank;
+reg main_litedramcore_inti_p1_cas_n = 1'd1;
+reg main_litedramcore_inti_p1_cs_n = 1'd1;
+reg main_litedramcore_inti_p1_ras_n = 1'd1;
+reg main_litedramcore_inti_p1_we_n = 1'd1;
+wire main_litedramcore_inti_p1_cke;
+wire main_litedramcore_inti_p1_odt;
+wire main_litedramcore_inti_p1_reset_n;
+reg main_litedramcore_inti_p1_act_n = 1'd1;
+wire [31:0] main_litedramcore_inti_p1_wrdata;
+wire main_litedramcore_inti_p1_wrdata_en;
+wire [3:0] main_litedramcore_inti_p1_wrdata_mask;
+wire main_litedramcore_inti_p1_rddata_en;
+reg [31:0] main_litedramcore_inti_p1_rddata = 32'd0;
+reg main_litedramcore_inti_p1_rddata_valid = 1'd0;
+wire [13:0] main_litedramcore_inti_p2_address;
+wire [2:0] main_litedramcore_inti_p2_bank;
+reg main_litedramcore_inti_p2_cas_n = 1'd1;
+reg main_litedramcore_inti_p2_cs_n = 1'd1;
+reg main_litedramcore_inti_p2_ras_n = 1'd1;
+reg main_litedramcore_inti_p2_we_n = 1'd1;
+wire main_litedramcore_inti_p2_cke;
+wire main_litedramcore_inti_p2_odt;
+wire main_litedramcore_inti_p2_reset_n;
+reg main_litedramcore_inti_p2_act_n = 1'd1;
+wire [31:0] main_litedramcore_inti_p2_wrdata;
+wire main_litedramcore_inti_p2_wrdata_en;
+wire [3:0] main_litedramcore_inti_p2_wrdata_mask;
+wire main_litedramcore_inti_p2_rddata_en;
+reg [31:0] main_litedramcore_inti_p2_rddata = 32'd0;
+reg main_litedramcore_inti_p2_rddata_valid = 1'd0;
+wire [13:0] main_litedramcore_inti_p3_address;
+wire [2:0] main_litedramcore_inti_p3_bank;
+reg main_litedramcore_inti_p3_cas_n = 1'd1;
+reg main_litedramcore_inti_p3_cs_n = 1'd1;
+reg main_litedramcore_inti_p3_ras_n = 1'd1;
+reg main_litedramcore_inti_p3_we_n = 1'd1;
+wire main_litedramcore_inti_p3_cke;
+wire main_litedramcore_inti_p3_odt;
+wire main_litedramcore_inti_p3_reset_n;
+reg main_litedramcore_inti_p3_act_n = 1'd1;
+wire [31:0] main_litedramcore_inti_p3_wrdata;
+wire main_litedramcore_inti_p3_wrdata_en;
+wire [3:0] main_litedramcore_inti_p3_wrdata_mask;
+wire main_litedramcore_inti_p3_rddata_en;
+reg [31:0] main_litedramcore_inti_p3_rddata = 32'd0;
+reg main_litedramcore_inti_p3_rddata_valid = 1'd0;
+wire [13:0] main_litedramcore_slave_p0_address;
+wire [2:0] main_litedramcore_slave_p0_bank;
+wire main_litedramcore_slave_p0_cas_n;
+wire main_litedramcore_slave_p0_cs_n;
+wire main_litedramcore_slave_p0_ras_n;
+wire main_litedramcore_slave_p0_we_n;
+wire main_litedramcore_slave_p0_cke;
+wire main_litedramcore_slave_p0_odt;
+wire main_litedramcore_slave_p0_reset_n;
+wire main_litedramcore_slave_p0_act_n;
+wire [31:0] main_litedramcore_slave_p0_wrdata;
+wire main_litedramcore_slave_p0_wrdata_en;
+wire [3:0] main_litedramcore_slave_p0_wrdata_mask;
+wire main_litedramcore_slave_p0_rddata_en;
+reg [31:0] main_litedramcore_slave_p0_rddata = 32'd0;
+reg main_litedramcore_slave_p0_rddata_valid = 1'd0;
+wire [13:0] main_litedramcore_slave_p1_address;
+wire [2:0] main_litedramcore_slave_p1_bank;
+wire main_litedramcore_slave_p1_cas_n;
+wire main_litedramcore_slave_p1_cs_n;
+wire main_litedramcore_slave_p1_ras_n;
+wire main_litedramcore_slave_p1_we_n;
+wire main_litedramcore_slave_p1_cke;
+wire main_litedramcore_slave_p1_odt;
+wire main_litedramcore_slave_p1_reset_n;
+wire main_litedramcore_slave_p1_act_n;
+wire [31:0] main_litedramcore_slave_p1_wrdata;
+wire main_litedramcore_slave_p1_wrdata_en;
+wire [3:0] main_litedramcore_slave_p1_wrdata_mask;
+wire main_litedramcore_slave_p1_rddata_en;
+reg [31:0] main_litedramcore_slave_p1_rddata = 32'd0;
+reg main_litedramcore_slave_p1_rddata_valid = 1'd0;
+wire [13:0] main_litedramcore_slave_p2_address;
+wire [2:0] main_litedramcore_slave_p2_bank;
+wire main_litedramcore_slave_p2_cas_n;
+wire main_litedramcore_slave_p2_cs_n;
+wire main_litedramcore_slave_p2_ras_n;
+wire main_litedramcore_slave_p2_we_n;
+wire main_litedramcore_slave_p2_cke;
+wire main_litedramcore_slave_p2_odt;
+wire main_litedramcore_slave_p2_reset_n;
+wire main_litedramcore_slave_p2_act_n;
+wire [31:0] main_litedramcore_slave_p2_wrdata;
+wire main_litedramcore_slave_p2_wrdata_en;
+wire [3:0] main_litedramcore_slave_p2_wrdata_mask;
+wire main_litedramcore_slave_p2_rddata_en;
+reg [31:0] main_litedramcore_slave_p2_rddata = 32'd0;
+reg main_litedramcore_slave_p2_rddata_valid = 1'd0;
+wire [13:0] main_litedramcore_slave_p3_address;
+wire [2:0] main_litedramcore_slave_p3_bank;
+wire main_litedramcore_slave_p3_cas_n;
+wire main_litedramcore_slave_p3_cs_n;
+wire main_litedramcore_slave_p3_ras_n;
+wire main_litedramcore_slave_p3_we_n;
+wire main_litedramcore_slave_p3_cke;
+wire main_litedramcore_slave_p3_odt;
+wire main_litedramcore_slave_p3_reset_n;
+wire main_litedramcore_slave_p3_act_n;
+wire [31:0] main_litedramcore_slave_p3_wrdata;
+wire main_litedramcore_slave_p3_wrdata_en;
+wire [3:0] main_litedramcore_slave_p3_wrdata_mask;
+wire main_litedramcore_slave_p3_rddata_en;
+reg [31:0] main_litedramcore_slave_p3_rddata = 32'd0;
+reg main_litedramcore_slave_p3_rddata_valid = 1'd0;
+reg [13:0] main_litedramcore_master_p0_address = 14'd0;
+reg [2:0] main_litedramcore_master_p0_bank = 3'd0;
+reg main_litedramcore_master_p0_cas_n = 1'd1;
+reg main_litedramcore_master_p0_cs_n = 1'd1;
+reg main_litedramcore_master_p0_ras_n = 1'd1;
+reg main_litedramcore_master_p0_we_n = 1'd1;
+reg main_litedramcore_master_p0_cke = 1'd0;
+reg main_litedramcore_master_p0_odt = 1'd0;
+reg main_litedramcore_master_p0_reset_n = 1'd0;
+reg main_litedramcore_master_p0_act_n = 1'd1;
+reg [31:0] main_litedramcore_master_p0_wrdata = 32'd0;
+reg main_litedramcore_master_p0_wrdata_en = 1'd0;
+reg [3:0] main_litedramcore_master_p0_wrdata_mask = 4'd0;
+reg main_litedramcore_master_p0_rddata_en = 1'd0;
+wire [31:0] main_litedramcore_master_p0_rddata;
+wire main_litedramcore_master_p0_rddata_valid;
+reg [13:0] main_litedramcore_master_p1_address = 14'd0;
+reg [2:0] main_litedramcore_master_p1_bank = 3'd0;
+reg main_litedramcore_master_p1_cas_n = 1'd1;
+reg main_litedramcore_master_p1_cs_n = 1'd1;
+reg main_litedramcore_master_p1_ras_n = 1'd1;
+reg main_litedramcore_master_p1_we_n = 1'd1;
+reg main_litedramcore_master_p1_cke = 1'd0;
+reg main_litedramcore_master_p1_odt = 1'd0;
+reg main_litedramcore_master_p1_reset_n = 1'd0;
+reg main_litedramcore_master_p1_act_n = 1'd1;
+reg [31:0] main_litedramcore_master_p1_wrdata = 32'd0;
+reg main_litedramcore_master_p1_wrdata_en = 1'd0;
+reg [3:0] main_litedramcore_master_p1_wrdata_mask = 4'd0;
+reg main_litedramcore_master_p1_rddata_en = 1'd0;
+wire [31:0] main_litedramcore_master_p1_rddata;
+wire main_litedramcore_master_p1_rddata_valid;
+reg [13:0] main_litedramcore_master_p2_address = 14'd0;
+reg [2:0] main_litedramcore_master_p2_bank = 3'd0;
+reg main_litedramcore_master_p2_cas_n = 1'd1;
+reg main_litedramcore_master_p2_cs_n = 1'd1;
+reg main_litedramcore_master_p2_ras_n = 1'd1;
+reg main_litedramcore_master_p2_we_n = 1'd1;
+reg main_litedramcore_master_p2_cke = 1'd0;
+reg main_litedramcore_master_p2_odt = 1'd0;
+reg main_litedramcore_master_p2_reset_n = 1'd0;
+reg main_litedramcore_master_p2_act_n = 1'd1;
+reg [31:0] main_litedramcore_master_p2_wrdata = 32'd0;
+reg main_litedramcore_master_p2_wrdata_en = 1'd0;
+reg [3:0] main_litedramcore_master_p2_wrdata_mask = 4'd0;
+reg main_litedramcore_master_p2_rddata_en = 1'd0;
+wire [31:0] main_litedramcore_master_p2_rddata;
+wire main_litedramcore_master_p2_rddata_valid;
+reg [13:0] main_litedramcore_master_p3_address = 14'd0;
+reg [2:0] main_litedramcore_master_p3_bank = 3'd0;
+reg main_litedramcore_master_p3_cas_n = 1'd1;
+reg main_litedramcore_master_p3_cs_n = 1'd1;
+reg main_litedramcore_master_p3_ras_n = 1'd1;
+reg main_litedramcore_master_p3_we_n = 1'd1;
+reg main_litedramcore_master_p3_cke = 1'd0;
+reg main_litedramcore_master_p3_odt = 1'd0;
+reg main_litedramcore_master_p3_reset_n = 1'd0;
+reg main_litedramcore_master_p3_act_n = 1'd1;
+reg [31:0] main_litedramcore_master_p3_wrdata = 32'd0;
+reg main_litedramcore_master_p3_wrdata_en = 1'd0;
+reg [3:0] main_litedramcore_master_p3_wrdata_mask = 4'd0;
+reg main_litedramcore_master_p3_rddata_en = 1'd0;
+wire [31:0] main_litedramcore_master_p3_rddata;
+wire main_litedramcore_master_p3_rddata_valid;
+wire main_litedramcore_sel;
+wire main_litedramcore_cke;
+wire main_litedramcore_odt;
+wire main_litedramcore_reset_n;
+reg [3:0] main_litedramcore_storage = 4'd1;
+reg main_litedramcore_re = 1'd0;
+reg [5:0] main_litedramcore_phaseinjector0_command_storage = 6'd0;
+reg main_litedramcore_phaseinjector0_command_re = 1'd0;
+reg main_litedramcore_phaseinjector0_command_issue_re = 1'd0;
+wire main_litedramcore_phaseinjector0_command_issue_r;
+reg main_litedramcore_phaseinjector0_command_issue_we = 1'd0;
+reg main_litedramcore_phaseinjector0_command_issue_w = 1'd0;
+reg [13:0] main_litedramcore_phaseinjector0_address_storage = 14'd0;
+reg main_litedramcore_phaseinjector0_address_re = 1'd0;
+reg [2:0] main_litedramcore_phaseinjector0_baddress_storage = 3'd0;
+reg main_litedramcore_phaseinjector0_baddress_re = 1'd0;
+reg [31:0] main_litedramcore_phaseinjector0_wrdata_storage = 32'd0;
+reg main_litedramcore_phaseinjector0_wrdata_re = 1'd0;
+reg [31:0] main_litedramcore_phaseinjector0_rddata_status = 32'd0;
+wire main_litedramcore_phaseinjector0_rddata_we;
+reg main_litedramcore_phaseinjector0_rddata_re = 1'd0;
+reg [5:0] main_litedramcore_phaseinjector1_command_storage = 6'd0;
+reg main_litedramcore_phaseinjector1_command_re = 1'd0;
+reg main_litedramcore_phaseinjector1_command_issue_re = 1'd0;
+wire main_litedramcore_phaseinjector1_command_issue_r;
+reg main_litedramcore_phaseinjector1_command_issue_we = 1'd0;
+reg main_litedramcore_phaseinjector1_command_issue_w = 1'd0;
+reg [13:0] main_litedramcore_phaseinjector1_address_storage = 14'd0;
+reg main_litedramcore_phaseinjector1_address_re = 1'd0;
+reg [2:0] main_litedramcore_phaseinjector1_baddress_storage = 3'd0;
+reg main_litedramcore_phaseinjector1_baddress_re = 1'd0;
+reg [31:0] main_litedramcore_phaseinjector1_wrdata_storage = 32'd0;
+reg main_litedramcore_phaseinjector1_wrdata_re = 1'd0;
+reg [31:0] main_litedramcore_phaseinjector1_rddata_status = 32'd0;
+wire main_litedramcore_phaseinjector1_rddata_we;
+reg main_litedramcore_phaseinjector1_rddata_re = 1'd0;
+reg [5:0] main_litedramcore_phaseinjector2_command_storage = 6'd0;
+reg main_litedramcore_phaseinjector2_command_re = 1'd0;
+reg main_litedramcore_phaseinjector2_command_issue_re = 1'd0;
+wire main_litedramcore_phaseinjector2_command_issue_r;
+reg main_litedramcore_phaseinjector2_command_issue_we = 1'd0;
+reg main_litedramcore_phaseinjector2_command_issue_w = 1'd0;
+reg [13:0] main_litedramcore_phaseinjector2_address_storage = 14'd0;
+reg main_litedramcore_phaseinjector2_address_re = 1'd0;
+reg [2:0] main_litedramcore_phaseinjector2_baddress_storage = 3'd0;
+reg main_litedramcore_phaseinjector2_baddress_re = 1'd0;
+reg [31:0] main_litedramcore_phaseinjector2_wrdata_storage = 32'd0;
+reg main_litedramcore_phaseinjector2_wrdata_re = 1'd0;
+reg [31:0] main_litedramcore_phaseinjector2_rddata_status = 32'd0;
+wire main_litedramcore_phaseinjector2_rddata_we;
+reg main_litedramcore_phaseinjector2_rddata_re = 1'd0;
+reg [5:0] main_litedramcore_phaseinjector3_command_storage = 6'd0;
+reg main_litedramcore_phaseinjector3_command_re = 1'd0;
+reg main_litedramcore_phaseinjector3_command_issue_re = 1'd0;
+wire main_litedramcore_phaseinjector3_command_issue_r;
+reg main_litedramcore_phaseinjector3_command_issue_we = 1'd0;
+reg main_litedramcore_phaseinjector3_command_issue_w = 1'd0;
+reg [13:0] main_litedramcore_phaseinjector3_address_storage = 14'd0;
+reg main_litedramcore_phaseinjector3_address_re = 1'd0;
+reg [2:0] main_litedramcore_phaseinjector3_baddress_storage = 3'd0;
+reg main_litedramcore_phaseinjector3_baddress_re = 1'd0;
+reg [31:0] main_litedramcore_phaseinjector3_wrdata_storage = 32'd0;
+reg main_litedramcore_phaseinjector3_wrdata_re = 1'd0;
+reg [31:0] main_litedramcore_phaseinjector3_rddata_status = 32'd0;
+wire main_litedramcore_phaseinjector3_rddata_we;
+reg main_litedramcore_phaseinjector3_rddata_re = 1'd0;
+wire main_litedramcore_interface_bank0_valid;
+wire main_litedramcore_interface_bank0_ready;
+wire main_litedramcore_interface_bank0_we;
+wire [20:0] main_litedramcore_interface_bank0_addr;
+wire main_litedramcore_interface_bank0_lock;
+wire main_litedramcore_interface_bank0_wdata_ready;
+wire main_litedramcore_interface_bank0_rdata_valid;
+wire main_litedramcore_interface_bank1_valid;
+wire main_litedramcore_interface_bank1_ready;
+wire main_litedramcore_interface_bank1_we;
+wire [20:0] main_litedramcore_interface_bank1_addr;
+wire main_litedramcore_interface_bank1_lock;
+wire main_litedramcore_interface_bank1_wdata_ready;
+wire main_litedramcore_interface_bank1_rdata_valid;
+wire main_litedramcore_interface_bank2_valid;
+wire main_litedramcore_interface_bank2_ready;
+wire main_litedramcore_interface_bank2_we;
+wire [20:0] main_litedramcore_interface_bank2_addr;
+wire main_litedramcore_interface_bank2_lock;
+wire main_litedramcore_interface_bank2_wdata_ready;
+wire main_litedramcore_interface_bank2_rdata_valid;
+wire main_litedramcore_interface_bank3_valid;
+wire main_litedramcore_interface_bank3_ready;
+wire main_litedramcore_interface_bank3_we;
+wire [20:0] main_litedramcore_interface_bank3_addr;
+wire main_litedramcore_interface_bank3_lock;
+wire main_litedramcore_interface_bank3_wdata_ready;
+wire main_litedramcore_interface_bank3_rdata_valid;
+wire main_litedramcore_interface_bank4_valid;
+wire main_litedramcore_interface_bank4_ready;
+wire main_litedramcore_interface_bank4_we;
+wire [20:0] main_litedramcore_interface_bank4_addr;
+wire main_litedramcore_interface_bank4_lock;
+wire main_litedramcore_interface_bank4_wdata_ready;
+wire main_litedramcore_interface_bank4_rdata_valid;
+wire main_litedramcore_interface_bank5_valid;
+wire main_litedramcore_interface_bank5_ready;
+wire main_litedramcore_interface_bank5_we;
+wire [20:0] main_litedramcore_interface_bank5_addr;
+wire main_litedramcore_interface_bank5_lock;
+wire main_litedramcore_interface_bank5_wdata_ready;
+wire main_litedramcore_interface_bank5_rdata_valid;
+wire main_litedramcore_interface_bank6_valid;
+wire main_litedramcore_interface_bank6_ready;
+wire main_litedramcore_interface_bank6_we;
+wire [20:0] main_litedramcore_interface_bank6_addr;
+wire main_litedramcore_interface_bank6_lock;
+wire main_litedramcore_interface_bank6_wdata_ready;
+wire main_litedramcore_interface_bank6_rdata_valid;
+wire main_litedramcore_interface_bank7_valid;
+wire main_litedramcore_interface_bank7_ready;
+wire main_litedramcore_interface_bank7_we;
+wire [20:0] main_litedramcore_interface_bank7_addr;
+wire main_litedramcore_interface_bank7_lock;
+wire main_litedramcore_interface_bank7_wdata_ready;
+wire main_litedramcore_interface_bank7_rdata_valid;
+reg [127:0] main_litedramcore_interface_wdata = 128'd0;
+reg [15:0] main_litedramcore_interface_wdata_we = 16'd0;
+wire [127:0] main_litedramcore_interface_rdata;
+reg [13:0] main_litedramcore_dfi_p0_address = 14'd0;
+reg [2:0] main_litedramcore_dfi_p0_bank = 3'd0;
+reg main_litedramcore_dfi_p0_cas_n = 1'd1;
+reg main_litedramcore_dfi_p0_cs_n = 1'd1;
+reg main_litedramcore_dfi_p0_ras_n = 1'd1;
+reg main_litedramcore_dfi_p0_we_n = 1'd1;
+wire main_litedramcore_dfi_p0_cke;
+wire main_litedramcore_dfi_p0_odt;
+wire main_litedramcore_dfi_p0_reset_n;
+reg main_litedramcore_dfi_p0_act_n = 1'd1;
+wire [31:0] main_litedramcore_dfi_p0_wrdata;
+reg main_litedramcore_dfi_p0_wrdata_en = 1'd0;
+wire [3:0] main_litedramcore_dfi_p0_wrdata_mask;
+reg main_litedramcore_dfi_p0_rddata_en = 1'd0;
+wire [31:0] main_litedramcore_dfi_p0_rddata;
+wire main_litedramcore_dfi_p0_rddata_valid;
+reg [13:0] main_litedramcore_dfi_p1_address = 14'd0;
+reg [2:0] main_litedramcore_dfi_p1_bank = 3'd0;
+reg main_litedramcore_dfi_p1_cas_n = 1'd1;
+reg main_litedramcore_dfi_p1_cs_n = 1'd1;
+reg main_litedramcore_dfi_p1_ras_n = 1'd1;
+reg main_litedramcore_dfi_p1_we_n = 1'd1;
+wire main_litedramcore_dfi_p1_cke;
+wire main_litedramcore_dfi_p1_odt;
+wire main_litedramcore_dfi_p1_reset_n;
+reg main_litedramcore_dfi_p1_act_n = 1'd1;
+wire [31:0] main_litedramcore_dfi_p1_wrdata;
+reg main_litedramcore_dfi_p1_wrdata_en = 1'd0;
+wire [3:0] main_litedramcore_dfi_p1_wrdata_mask;
+reg main_litedramcore_dfi_p1_rddata_en = 1'd0;
+wire [31:0] main_litedramcore_dfi_p1_rddata;
+wire main_litedramcore_dfi_p1_rddata_valid;
+reg [13:0] main_litedramcore_dfi_p2_address = 14'd0;
+reg [2:0] main_litedramcore_dfi_p2_bank = 3'd0;
+reg main_litedramcore_dfi_p2_cas_n = 1'd1;
+reg main_litedramcore_dfi_p2_cs_n = 1'd1;
+reg main_litedramcore_dfi_p2_ras_n = 1'd1;
+reg main_litedramcore_dfi_p2_we_n = 1'd1;
+wire main_litedramcore_dfi_p2_cke;
+wire main_litedramcore_dfi_p2_odt;
+wire main_litedramcore_dfi_p2_reset_n;
+reg main_litedramcore_dfi_p2_act_n = 1'd1;
+wire [31:0] main_litedramcore_dfi_p2_wrdata;
+reg main_litedramcore_dfi_p2_wrdata_en = 1'd0;
+wire [3:0] main_litedramcore_dfi_p2_wrdata_mask;
+reg main_litedramcore_dfi_p2_rddata_en = 1'd0;
+wire [31:0] main_litedramcore_dfi_p2_rddata;
+wire main_litedramcore_dfi_p2_rddata_valid;
+reg [13:0] main_litedramcore_dfi_p3_address = 14'd0;
+reg [2:0] main_litedramcore_dfi_p3_bank = 3'd0;
+reg main_litedramcore_dfi_p3_cas_n = 1'd1;
+reg main_litedramcore_dfi_p3_cs_n = 1'd1;
+reg main_litedramcore_dfi_p3_ras_n = 1'd1;
+reg main_litedramcore_dfi_p3_we_n = 1'd1;
+wire main_litedramcore_dfi_p3_cke;
+wire main_litedramcore_dfi_p3_odt;
+wire main_litedramcore_dfi_p3_reset_n;
+reg main_litedramcore_dfi_p3_act_n = 1'd1;
+wire [31:0] main_litedramcore_dfi_p3_wrdata;
+reg main_litedramcore_dfi_p3_wrdata_en = 1'd0;
+wire [3:0] main_litedramcore_dfi_p3_wrdata_mask;
+reg main_litedramcore_dfi_p3_rddata_en = 1'd0;
+wire [31:0] main_litedramcore_dfi_p3_rddata;
+wire main_litedramcore_dfi_p3_rddata_valid;
+reg main_litedramcore_cmd_valid = 1'd0;
+reg main_litedramcore_cmd_ready = 1'd0;
+reg main_litedramcore_cmd_last = 1'd0;
+reg [13:0] main_litedramcore_cmd_payload_a = 14'd0;
+reg [2:0] main_litedramcore_cmd_payload_ba = 3'd0;
+reg main_litedramcore_cmd_payload_cas = 1'd0;
+reg main_litedramcore_cmd_payload_ras = 1'd0;
+reg main_litedramcore_cmd_payload_we = 1'd0;
+reg main_litedramcore_cmd_payload_is_read = 1'd0;
+reg main_litedramcore_cmd_payload_is_write = 1'd0;
+wire main_litedramcore_wants_refresh;
+wire main_litedramcore_wants_zqcs;
+wire main_litedramcore_timer_wait;
+wire main_litedramcore_timer_done0;
+wire [9:0] main_litedramcore_timer_count0;
+wire main_litedramcore_timer_done1;
+reg [9:0] main_litedramcore_timer_count1 = 10'd781;
+wire main_litedramcore_postponer_req_i;
+reg main_litedramcore_postponer_req_o = 1'd0;
+reg main_litedramcore_postponer_count = 1'd0;
+reg main_litedramcore_sequencer_start0 = 1'd0;
+wire main_litedramcore_sequencer_done0;
+wire main_litedramcore_sequencer_start1;
+reg main_litedramcore_sequencer_done1 = 1'd0;
+reg [5:0] main_litedramcore_sequencer_counter = 6'd0;
+reg main_litedramcore_sequencer_count = 1'd0;
+wire main_litedramcore_zqcs_timer_wait;
+wire main_litedramcore_zqcs_timer_done0;
+wire [26:0] main_litedramcore_zqcs_timer_count0;
+wire main_litedramcore_zqcs_timer_done1;
+reg [26:0] main_litedramcore_zqcs_timer_count1 = 27'd99999999;
+reg main_litedramcore_zqcs_executer_start = 1'd0;
+reg main_litedramcore_zqcs_executer_done = 1'd0;
+reg [4:0] main_litedramcore_zqcs_executer_counter = 5'd0;
+wire main_litedramcore_bankmachine0_req_valid;
+wire main_litedramcore_bankmachine0_req_ready;
+wire main_litedramcore_bankmachine0_req_we;
+wire [20:0] main_litedramcore_bankmachine0_req_addr;
+wire main_litedramcore_bankmachine0_req_lock;
+reg main_litedramcore_bankmachine0_req_wdata_ready = 1'd0;
+reg main_litedramcore_bankmachine0_req_rdata_valid = 1'd0;
+wire main_litedramcore_bankmachine0_refresh_req;
+reg main_litedramcore_bankmachine0_refresh_gnt = 1'd0;
+reg main_litedramcore_bankmachine0_cmd_valid = 1'd0;
+reg main_litedramcore_bankmachine0_cmd_ready = 1'd0;
+reg [13:0] main_litedramcore_bankmachine0_cmd_payload_a = 14'd0;
+wire [2:0] main_litedramcore_bankmachine0_cmd_payload_ba;
+reg main_litedramcore_bankmachine0_cmd_payload_cas = 1'd0;
+reg main_litedramcore_bankmachine0_cmd_payload_ras = 1'd0;
+reg main_litedramcore_bankmachine0_cmd_payload_we = 1'd0;
+reg main_litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd0;
+reg main_litedramcore_bankmachine0_cmd_payload_is_read = 1'd0;
+reg main_litedramcore_bankmachine0_cmd_payload_is_write = 1'd0;
+reg main_litedramcore_bankmachine0_auto_precharge = 1'd0;
+wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid;
+wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready;
+reg main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_first = 1'd0;
+reg main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_last = 1'd0;
+wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we;
+wire [20:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr;
+wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid;
+wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready;
+wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_first;
+wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_last;
+wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we;
+wire [20:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr;
+wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we;
+wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable;
+wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re;
+wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable;
+wire [23:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din;
+wire [23:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
+reg [4:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_level = 5'd0;
+reg main_litedramcore_bankmachine0_cmd_buffer_lookahead_replace = 1'd0;
+reg [3:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_produce = 4'd0;
+reg [3:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_consume = 4'd0;
+reg [3:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr = 4'd0;
+wire [23:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_r;
+wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we;
+wire [23:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w;
+wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_do_read;
+wire [3:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr;
+wire [23:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r;
+wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we;
+wire [20:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr;
+wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first;
+wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last;
+wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we;
+wire [20:0] main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr;
+wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first;
+wire main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last;
+wire main_litedramcore_bankmachine0_cmd_buffer_sink_valid;
+wire main_litedramcore_bankmachine0_cmd_buffer_sink_ready;
+wire main_litedramcore_bankmachine0_cmd_buffer_sink_first;
+wire main_litedramcore_bankmachine0_cmd_buffer_sink_last;
+wire main_litedramcore_bankmachine0_cmd_buffer_sink_payload_we;
+wire [20:0] main_litedramcore_bankmachine0_cmd_buffer_sink_payload_addr;
+reg main_litedramcore_bankmachine0_cmd_buffer_source_valid = 1'd0;
+wire main_litedramcore_bankmachine0_cmd_buffer_source_ready;
+reg main_litedramcore_bankmachine0_cmd_buffer_source_first = 1'd0;
+reg main_litedramcore_bankmachine0_cmd_buffer_source_last = 1'd0;
+reg main_litedramcore_bankmachine0_cmd_buffer_source_payload_we = 1'd0;
+reg [20:0] main_litedramcore_bankmachine0_cmd_buffer_source_payload_addr = 21'd0;
+reg [13:0] main_litedramcore_bankmachine0_row = 14'd0;
+reg main_litedramcore_bankmachine0_row_opened = 1'd0;
+wire main_litedramcore_bankmachine0_row_hit;
+reg main_litedramcore_bankmachine0_row_open = 1'd0;
+reg main_litedramcore_bankmachine0_row_close = 1'd0;
+reg main_litedramcore_bankmachine0_row_col_n_addr_sel = 1'd0;
+wire main_litedramcore_bankmachine0_twtpcon_valid;
+(* dont_touch = "true" *) reg main_litedramcore_bankmachine0_twtpcon_ready = 1'd0;
+reg [2:0] main_litedramcore_bankmachine0_twtpcon_count = 3'd0;
+wire main_litedramcore_bankmachine0_trccon_valid;
+(* dont_touch = "true" *) reg main_litedramcore_bankmachine0_trccon_ready = 1'd0;
+reg [2:0] main_litedramcore_bankmachine0_trccon_count = 3'd0;
+wire main_litedramcore_bankmachine0_trascon_valid;
+(* dont_touch = "true" *) reg main_litedramcore_bankmachine0_trascon_ready = 1'd0;
+reg [2:0] main_litedramcore_bankmachine0_trascon_count = 3'd0;
+wire main_litedramcore_bankmachine1_req_valid;
+wire main_litedramcore_bankmachine1_req_ready;
+wire main_litedramcore_bankmachine1_req_we;
+wire [20:0] main_litedramcore_bankmachine1_req_addr;
+wire main_litedramcore_bankmachine1_req_lock;
+reg main_litedramcore_bankmachine1_req_wdata_ready = 1'd0;
+reg main_litedramcore_bankmachine1_req_rdata_valid = 1'd0;
+wire main_litedramcore_bankmachine1_refresh_req;
+reg main_litedramcore_bankmachine1_refresh_gnt = 1'd0;
+reg main_litedramcore_bankmachine1_cmd_valid = 1'd0;
+reg main_litedramcore_bankmachine1_cmd_ready = 1'd0;
+reg [13:0] main_litedramcore_bankmachine1_cmd_payload_a = 14'd0;
+wire [2:0] main_litedramcore_bankmachine1_cmd_payload_ba;
+reg main_litedramcore_bankmachine1_cmd_payload_cas = 1'd0;
+reg main_litedramcore_bankmachine1_cmd_payload_ras = 1'd0;
+reg main_litedramcore_bankmachine1_cmd_payload_we = 1'd0;
+reg main_litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd0;
+reg main_litedramcore_bankmachine1_cmd_payload_is_read = 1'd0;
+reg main_litedramcore_bankmachine1_cmd_payload_is_write = 1'd0;
+reg main_litedramcore_bankmachine1_auto_precharge = 1'd0;
+wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid;
+wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready;
+reg main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_first = 1'd0;
+reg main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_last = 1'd0;
+wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we;
+wire [20:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr;
+wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid;
+wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready;
+wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_first;
+wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_last;
+wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we;
+wire [20:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr;
+wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we;
+wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable;
+wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re;
+wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable;
+wire [23:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din;
+wire [23:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
+reg [4:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_level = 5'd0;
+reg main_litedramcore_bankmachine1_cmd_buffer_lookahead_replace = 1'd0;
+reg [3:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_produce = 4'd0;
+reg [3:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_consume = 4'd0;
+reg [3:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr = 4'd0;
+wire [23:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_r;
+wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we;
+wire [23:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w;
+wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_do_read;
+wire [3:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr;
+wire [23:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r;
+wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we;
+wire [20:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr;
+wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first;
+wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last;
+wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we;
+wire [20:0] main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr;
+wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first;
+wire main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last;
+wire main_litedramcore_bankmachine1_cmd_buffer_sink_valid;
+wire main_litedramcore_bankmachine1_cmd_buffer_sink_ready;
+wire main_litedramcore_bankmachine1_cmd_buffer_sink_first;
+wire main_litedramcore_bankmachine1_cmd_buffer_sink_last;
+wire main_litedramcore_bankmachine1_cmd_buffer_sink_payload_we;
+wire [20:0] main_litedramcore_bankmachine1_cmd_buffer_sink_payload_addr;
+reg main_litedramcore_bankmachine1_cmd_buffer_source_valid = 1'd0;
+wire main_litedramcore_bankmachine1_cmd_buffer_source_ready;
+reg main_litedramcore_bankmachine1_cmd_buffer_source_first = 1'd0;
+reg main_litedramcore_bankmachine1_cmd_buffer_source_last = 1'd0;
+reg main_litedramcore_bankmachine1_cmd_buffer_source_payload_we = 1'd0;
+reg [20:0] main_litedramcore_bankmachine1_cmd_buffer_source_payload_addr = 21'd0;
+reg [13:0] main_litedramcore_bankmachine1_row = 14'd0;
+reg main_litedramcore_bankmachine1_row_opened = 1'd0;
+wire main_litedramcore_bankmachine1_row_hit;
+reg main_litedramcore_bankmachine1_row_open = 1'd0;
+reg main_litedramcore_bankmachine1_row_close = 1'd0;
+reg main_litedramcore_bankmachine1_row_col_n_addr_sel = 1'd0;
+wire main_litedramcore_bankmachine1_twtpcon_valid;
+(* dont_touch = "true" *) reg main_litedramcore_bankmachine1_twtpcon_ready = 1'd0;
+reg [2:0] main_litedramcore_bankmachine1_twtpcon_count = 3'd0;
+wire main_litedramcore_bankmachine1_trccon_valid;
+(* dont_touch = "true" *) reg main_litedramcore_bankmachine1_trccon_ready = 1'd0;
+reg [2:0] main_litedramcore_bankmachine1_trccon_count = 3'd0;
+wire main_litedramcore_bankmachine1_trascon_valid;
+(* dont_touch = "true" *) reg main_litedramcore_bankmachine1_trascon_ready = 1'd0;
+reg [2:0] main_litedramcore_bankmachine1_trascon_count = 3'd0;
+wire main_litedramcore_bankmachine2_req_valid;
+wire main_litedramcore_bankmachine2_req_ready;
+wire main_litedramcore_bankmachine2_req_we;
+wire [20:0] main_litedramcore_bankmachine2_req_addr;
+wire main_litedramcore_bankmachine2_req_lock;
+reg main_litedramcore_bankmachine2_req_wdata_ready = 1'd0;
+reg main_litedramcore_bankmachine2_req_rdata_valid = 1'd0;
+wire main_litedramcore_bankmachine2_refresh_req;
+reg main_litedramcore_bankmachine2_refresh_gnt = 1'd0;
+reg main_litedramcore_bankmachine2_cmd_valid = 1'd0;
+reg main_litedramcore_bankmachine2_cmd_ready = 1'd0;
+reg [13:0] main_litedramcore_bankmachine2_cmd_payload_a = 14'd0;
+wire [2:0] main_litedramcore_bankmachine2_cmd_payload_ba;
+reg main_litedramcore_bankmachine2_cmd_payload_cas = 1'd0;
+reg main_litedramcore_bankmachine2_cmd_payload_ras = 1'd0;
+reg main_litedramcore_bankmachine2_cmd_payload_we = 1'd0;
+reg main_litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd0;
+reg main_litedramcore_bankmachine2_cmd_payload_is_read = 1'd0;
+reg main_litedramcore_bankmachine2_cmd_payload_is_write = 1'd0;
+reg main_litedramcore_bankmachine2_auto_precharge = 1'd0;
+wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid;
+wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready;
+reg main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_first = 1'd0;
+reg main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_last = 1'd0;
+wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we;
+wire [20:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr;
+wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid;
+wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready;
+wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_first;
+wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_last;
+wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we;
+wire [20:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr;
+wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we;
+wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable;
+wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re;
+wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable;
+wire [23:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din;
+wire [23:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
+reg [4:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_level = 5'd0;
+reg main_litedramcore_bankmachine2_cmd_buffer_lookahead_replace = 1'd0;
+reg [3:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_produce = 4'd0;
+reg [3:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_consume = 4'd0;
+reg [3:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr = 4'd0;
+wire [23:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_r;
+wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we;
+wire [23:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w;
+wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_do_read;
+wire [3:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr;
+wire [23:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r;
+wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we;
+wire [20:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr;
+wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first;
+wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last;
+wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we;
+wire [20:0] main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr;
+wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first;
+wire main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last;
+wire main_litedramcore_bankmachine2_cmd_buffer_sink_valid;
+wire main_litedramcore_bankmachine2_cmd_buffer_sink_ready;
+wire main_litedramcore_bankmachine2_cmd_buffer_sink_first;
+wire main_litedramcore_bankmachine2_cmd_buffer_sink_last;
+wire main_litedramcore_bankmachine2_cmd_buffer_sink_payload_we;
+wire [20:0] main_litedramcore_bankmachine2_cmd_buffer_sink_payload_addr;
+reg main_litedramcore_bankmachine2_cmd_buffer_source_valid = 1'd0;
+wire main_litedramcore_bankmachine2_cmd_buffer_source_ready;
+reg main_litedramcore_bankmachine2_cmd_buffer_source_first = 1'd0;
+reg main_litedramcore_bankmachine2_cmd_buffer_source_last = 1'd0;
+reg main_litedramcore_bankmachine2_cmd_buffer_source_payload_we = 1'd0;
+reg [20:0] main_litedramcore_bankmachine2_cmd_buffer_source_payload_addr = 21'd0;
+reg [13:0] main_litedramcore_bankmachine2_row = 14'd0;
+reg main_litedramcore_bankmachine2_row_opened = 1'd0;
+wire main_litedramcore_bankmachine2_row_hit;
+reg main_litedramcore_bankmachine2_row_open = 1'd0;
+reg main_litedramcore_bankmachine2_row_close = 1'd0;
+reg main_litedramcore_bankmachine2_row_col_n_addr_sel = 1'd0;
+wire main_litedramcore_bankmachine2_twtpcon_valid;
+(* dont_touch = "true" *) reg main_litedramcore_bankmachine2_twtpcon_ready = 1'd0;
+reg [2:0] main_litedramcore_bankmachine2_twtpcon_count = 3'd0;
+wire main_litedramcore_bankmachine2_trccon_valid;
+(* dont_touch = "true" *) reg main_litedramcore_bankmachine2_trccon_ready = 1'd0;
+reg [2:0] main_litedramcore_bankmachine2_trccon_count = 3'd0;
+wire main_litedramcore_bankmachine2_trascon_valid;
+(* dont_touch = "true" *) reg main_litedramcore_bankmachine2_trascon_ready = 1'd0;
+reg [2:0] main_litedramcore_bankmachine2_trascon_count = 3'd0;
+wire main_litedramcore_bankmachine3_req_valid;
+wire main_litedramcore_bankmachine3_req_ready;
+wire main_litedramcore_bankmachine3_req_we;
+wire [20:0] main_litedramcore_bankmachine3_req_addr;
+wire main_litedramcore_bankmachine3_req_lock;
+reg main_litedramcore_bankmachine3_req_wdata_ready = 1'd0;
+reg main_litedramcore_bankmachine3_req_rdata_valid = 1'd0;
+wire main_litedramcore_bankmachine3_refresh_req;
+reg main_litedramcore_bankmachine3_refresh_gnt = 1'd0;
+reg main_litedramcore_bankmachine3_cmd_valid = 1'd0;
+reg main_litedramcore_bankmachine3_cmd_ready = 1'd0;
+reg [13:0] main_litedramcore_bankmachine3_cmd_payload_a = 14'd0;
+wire [2:0] main_litedramcore_bankmachine3_cmd_payload_ba;
+reg main_litedramcore_bankmachine3_cmd_payload_cas = 1'd0;
+reg main_litedramcore_bankmachine3_cmd_payload_ras = 1'd0;
+reg main_litedramcore_bankmachine3_cmd_payload_we = 1'd0;
+reg main_litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd0;
+reg main_litedramcore_bankmachine3_cmd_payload_is_read = 1'd0;
+reg main_litedramcore_bankmachine3_cmd_payload_is_write = 1'd0;
+reg main_litedramcore_bankmachine3_auto_precharge = 1'd0;
+wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid;
+wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready;
+reg main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_first = 1'd0;
+reg main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_last = 1'd0;
+wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we;
+wire [20:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr;
+wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid;
+wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready;
+wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_first;
+wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_last;
+wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we;
+wire [20:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr;
+wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we;
+wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable;
+wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re;
+wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable;
+wire [23:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din;
+wire [23:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
+reg [4:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_level = 5'd0;
+reg main_litedramcore_bankmachine3_cmd_buffer_lookahead_replace = 1'd0;
+reg [3:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_produce = 4'd0;
+reg [3:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_consume = 4'd0;
+reg [3:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr = 4'd0;
+wire [23:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_r;
+wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we;
+wire [23:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w;
+wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_do_read;
+wire [3:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr;
+wire [23:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r;
+wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we;
+wire [20:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr;
+wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first;
+wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last;
+wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we;
+wire [20:0] main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr;
+wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first;
+wire main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last;
+wire main_litedramcore_bankmachine3_cmd_buffer_sink_valid;
+wire main_litedramcore_bankmachine3_cmd_buffer_sink_ready;
+wire main_litedramcore_bankmachine3_cmd_buffer_sink_first;
+wire main_litedramcore_bankmachine3_cmd_buffer_sink_last;
+wire main_litedramcore_bankmachine3_cmd_buffer_sink_payload_we;
+wire [20:0] main_litedramcore_bankmachine3_cmd_buffer_sink_payload_addr;
+reg main_litedramcore_bankmachine3_cmd_buffer_source_valid = 1'd0;
+wire main_litedramcore_bankmachine3_cmd_buffer_source_ready;
+reg main_litedramcore_bankmachine3_cmd_buffer_source_first = 1'd0;
+reg main_litedramcore_bankmachine3_cmd_buffer_source_last = 1'd0;
+reg main_litedramcore_bankmachine3_cmd_buffer_source_payload_we = 1'd0;
+reg [20:0] main_litedramcore_bankmachine3_cmd_buffer_source_payload_addr = 21'd0;
+reg [13:0] main_litedramcore_bankmachine3_row = 14'd0;
+reg main_litedramcore_bankmachine3_row_opened = 1'd0;
+wire main_litedramcore_bankmachine3_row_hit;
+reg main_litedramcore_bankmachine3_row_open = 1'd0;
+reg main_litedramcore_bankmachine3_row_close = 1'd0;
+reg main_litedramcore_bankmachine3_row_col_n_addr_sel = 1'd0;
+wire main_litedramcore_bankmachine3_twtpcon_valid;
+(* dont_touch = "true" *) reg main_litedramcore_bankmachine3_twtpcon_ready = 1'd0;
+reg [2:0] main_litedramcore_bankmachine3_twtpcon_count = 3'd0;
+wire main_litedramcore_bankmachine3_trccon_valid;
+(* dont_touch = "true" *) reg main_litedramcore_bankmachine3_trccon_ready = 1'd0;
+reg [2:0] main_litedramcore_bankmachine3_trccon_count = 3'd0;
+wire main_litedramcore_bankmachine3_trascon_valid;
+(* dont_touch = "true" *) reg main_litedramcore_bankmachine3_trascon_ready = 1'd0;
+reg [2:0] main_litedramcore_bankmachine3_trascon_count = 3'd0;
+wire main_litedramcore_bankmachine4_req_valid;
+wire main_litedramcore_bankmachine4_req_ready;
+wire main_litedramcore_bankmachine4_req_we;
+wire [20:0] main_litedramcore_bankmachine4_req_addr;
+wire main_litedramcore_bankmachine4_req_lock;
+reg main_litedramcore_bankmachine4_req_wdata_ready = 1'd0;
+reg main_litedramcore_bankmachine4_req_rdata_valid = 1'd0;
+wire main_litedramcore_bankmachine4_refresh_req;
+reg main_litedramcore_bankmachine4_refresh_gnt = 1'd0;
+reg main_litedramcore_bankmachine4_cmd_valid = 1'd0;
+reg main_litedramcore_bankmachine4_cmd_ready = 1'd0;
+reg [13:0] main_litedramcore_bankmachine4_cmd_payload_a = 14'd0;
+wire [2:0] main_litedramcore_bankmachine4_cmd_payload_ba;
+reg main_litedramcore_bankmachine4_cmd_payload_cas = 1'd0;
+reg main_litedramcore_bankmachine4_cmd_payload_ras = 1'd0;
+reg main_litedramcore_bankmachine4_cmd_payload_we = 1'd0;
+reg main_litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd0;
+reg main_litedramcore_bankmachine4_cmd_payload_is_read = 1'd0;
+reg main_litedramcore_bankmachine4_cmd_payload_is_write = 1'd0;
+reg main_litedramcore_bankmachine4_auto_precharge = 1'd0;
+wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid;
+wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready;
+reg main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_first = 1'd0;
+reg main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_last = 1'd0;
+wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we;
+wire [20:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr;
+wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid;
+wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready;
+wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_first;
+wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_last;
+wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we;
+wire [20:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr;
+wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we;
+wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable;
+wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re;
+wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable;
+wire [23:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din;
+wire [23:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
+reg [4:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_level = 5'd0;
+reg main_litedramcore_bankmachine4_cmd_buffer_lookahead_replace = 1'd0;
+reg [3:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_produce = 4'd0;
+reg [3:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_consume = 4'd0;
+reg [3:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr = 4'd0;
+wire [23:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_r;
+wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we;
+wire [23:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w;
+wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_do_read;
+wire [3:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr;
+wire [23:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r;
+wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we;
+wire [20:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr;
+wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first;
+wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last;
+wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we;
+wire [20:0] main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr;
+wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first;
+wire main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last;
+wire main_litedramcore_bankmachine4_cmd_buffer_sink_valid;
+wire main_litedramcore_bankmachine4_cmd_buffer_sink_ready;
+wire main_litedramcore_bankmachine4_cmd_buffer_sink_first;
+wire main_litedramcore_bankmachine4_cmd_buffer_sink_last;
+wire main_litedramcore_bankmachine4_cmd_buffer_sink_payload_we;
+wire [20:0] main_litedramcore_bankmachine4_cmd_buffer_sink_payload_addr;
+reg main_litedramcore_bankmachine4_cmd_buffer_source_valid = 1'd0;
+wire main_litedramcore_bankmachine4_cmd_buffer_source_ready;
+reg main_litedramcore_bankmachine4_cmd_buffer_source_first = 1'd0;
+reg main_litedramcore_bankmachine4_cmd_buffer_source_last = 1'd0;
+reg main_litedramcore_bankmachine4_cmd_buffer_source_payload_we = 1'd0;
+reg [20:0] main_litedramcore_bankmachine4_cmd_buffer_source_payload_addr = 21'd0;
+reg [13:0] main_litedramcore_bankmachine4_row = 14'd0;
+reg main_litedramcore_bankmachine4_row_opened = 1'd0;
+wire main_litedramcore_bankmachine4_row_hit;
+reg main_litedramcore_bankmachine4_row_open = 1'd0;
+reg main_litedramcore_bankmachine4_row_close = 1'd0;
+reg main_litedramcore_bankmachine4_row_col_n_addr_sel = 1'd0;
+wire main_litedramcore_bankmachine4_twtpcon_valid;
+(* dont_touch = "true" *) reg main_litedramcore_bankmachine4_twtpcon_ready = 1'd0;
+reg [2:0] main_litedramcore_bankmachine4_twtpcon_count = 3'd0;
+wire main_litedramcore_bankmachine4_trccon_valid;
+(* dont_touch = "true" *) reg main_litedramcore_bankmachine4_trccon_ready = 1'd0;
+reg [2:0] main_litedramcore_bankmachine4_trccon_count = 3'd0;
+wire main_litedramcore_bankmachine4_trascon_valid;
+(* dont_touch = "true" *) reg main_litedramcore_bankmachine4_trascon_ready = 1'd0;
+reg [2:0] main_litedramcore_bankmachine4_trascon_count = 3'd0;
+wire main_litedramcore_bankmachine5_req_valid;
+wire main_litedramcore_bankmachine5_req_ready;
+wire main_litedramcore_bankmachine5_req_we;
+wire [20:0] main_litedramcore_bankmachine5_req_addr;
+wire main_litedramcore_bankmachine5_req_lock;
+reg main_litedramcore_bankmachine5_req_wdata_ready = 1'd0;
+reg main_litedramcore_bankmachine5_req_rdata_valid = 1'd0;
+wire main_litedramcore_bankmachine5_refresh_req;
+reg main_litedramcore_bankmachine5_refresh_gnt = 1'd0;
+reg main_litedramcore_bankmachine5_cmd_valid = 1'd0;
+reg main_litedramcore_bankmachine5_cmd_ready = 1'd0;
+reg [13:0] main_litedramcore_bankmachine5_cmd_payload_a = 14'd0;
+wire [2:0] main_litedramcore_bankmachine5_cmd_payload_ba;
+reg main_litedramcore_bankmachine5_cmd_payload_cas = 1'd0;
+reg main_litedramcore_bankmachine5_cmd_payload_ras = 1'd0;
+reg main_litedramcore_bankmachine5_cmd_payload_we = 1'd0;
+reg main_litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd0;
+reg main_litedramcore_bankmachine5_cmd_payload_is_read = 1'd0;
+reg main_litedramcore_bankmachine5_cmd_payload_is_write = 1'd0;
+reg main_litedramcore_bankmachine5_auto_precharge = 1'd0;
+wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid;
+wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready;
+reg main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_first = 1'd0;
+reg main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_last = 1'd0;
+wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we;
+wire [20:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr;
+wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid;
+wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready;
+wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_first;
+wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_last;
+wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we;
+wire [20:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr;
+wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we;
+wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable;
+wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re;
+wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable;
+wire [23:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din;
+wire [23:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
+reg [4:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_level = 5'd0;
+reg main_litedramcore_bankmachine5_cmd_buffer_lookahead_replace = 1'd0;
+reg [3:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_produce = 4'd0;
+reg [3:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_consume = 4'd0;
+reg [3:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr = 4'd0;
+wire [23:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_r;
+wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we;
+wire [23:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w;
+wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_do_read;
+wire [3:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr;
+wire [23:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r;
+wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we;
+wire [20:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr;
+wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first;
+wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last;
+wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we;
+wire [20:0] main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr;
+wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first;
+wire main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last;
+wire main_litedramcore_bankmachine5_cmd_buffer_sink_valid;
+wire main_litedramcore_bankmachine5_cmd_buffer_sink_ready;
+wire main_litedramcore_bankmachine5_cmd_buffer_sink_first;
+wire main_litedramcore_bankmachine5_cmd_buffer_sink_last;
+wire main_litedramcore_bankmachine5_cmd_buffer_sink_payload_we;
+wire [20:0] main_litedramcore_bankmachine5_cmd_buffer_sink_payload_addr;
+reg main_litedramcore_bankmachine5_cmd_buffer_source_valid = 1'd0;
+wire main_litedramcore_bankmachine5_cmd_buffer_source_ready;
+reg main_litedramcore_bankmachine5_cmd_buffer_source_first = 1'd0;
+reg main_litedramcore_bankmachine5_cmd_buffer_source_last = 1'd0;
+reg main_litedramcore_bankmachine5_cmd_buffer_source_payload_we = 1'd0;
+reg [20:0] main_litedramcore_bankmachine5_cmd_buffer_source_payload_addr = 21'd0;
+reg [13:0] main_litedramcore_bankmachine5_row = 14'd0;
+reg main_litedramcore_bankmachine5_row_opened = 1'd0;
+wire main_litedramcore_bankmachine5_row_hit;
+reg main_litedramcore_bankmachine5_row_open = 1'd0;
+reg main_litedramcore_bankmachine5_row_close = 1'd0;
+reg main_litedramcore_bankmachine5_row_col_n_addr_sel = 1'd0;
+wire main_litedramcore_bankmachine5_twtpcon_valid;
+(* dont_touch = "true" *) reg main_litedramcore_bankmachine5_twtpcon_ready = 1'd0;
+reg [2:0] main_litedramcore_bankmachine5_twtpcon_count = 3'd0;
+wire main_litedramcore_bankmachine5_trccon_valid;
+(* dont_touch = "true" *) reg main_litedramcore_bankmachine5_trccon_ready = 1'd0;
+reg [2:0] main_litedramcore_bankmachine5_trccon_count = 3'd0;
+wire main_litedramcore_bankmachine5_trascon_valid;
+(* dont_touch = "true" *) reg main_litedramcore_bankmachine5_trascon_ready = 1'd0;
+reg [2:0] main_litedramcore_bankmachine5_trascon_count = 3'd0;
+wire main_litedramcore_bankmachine6_req_valid;
+wire main_litedramcore_bankmachine6_req_ready;
+wire main_litedramcore_bankmachine6_req_we;
+wire [20:0] main_litedramcore_bankmachine6_req_addr;
+wire main_litedramcore_bankmachine6_req_lock;
+reg main_litedramcore_bankmachine6_req_wdata_ready = 1'd0;
+reg main_litedramcore_bankmachine6_req_rdata_valid = 1'd0;
+wire main_litedramcore_bankmachine6_refresh_req;
+reg main_litedramcore_bankmachine6_refresh_gnt = 1'd0;
+reg main_litedramcore_bankmachine6_cmd_valid = 1'd0;
+reg main_litedramcore_bankmachine6_cmd_ready = 1'd0;
+reg [13:0] main_litedramcore_bankmachine6_cmd_payload_a = 14'd0;
+wire [2:0] main_litedramcore_bankmachine6_cmd_payload_ba;
+reg main_litedramcore_bankmachine6_cmd_payload_cas = 1'd0;
+reg main_litedramcore_bankmachine6_cmd_payload_ras = 1'd0;
+reg main_litedramcore_bankmachine6_cmd_payload_we = 1'd0;
+reg main_litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd0;
+reg main_litedramcore_bankmachine6_cmd_payload_is_read = 1'd0;
+reg main_litedramcore_bankmachine6_cmd_payload_is_write = 1'd0;
+reg main_litedramcore_bankmachine6_auto_precharge = 1'd0;
+wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid;
+wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready;
+reg main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_first = 1'd0;
+reg main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_last = 1'd0;
+wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we;
+wire [20:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr;
+wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid;
+wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready;
+wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_first;
+wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_last;
+wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we;
+wire [20:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr;
+wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we;
+wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable;
+wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re;
+wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable;
+wire [23:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din;
+wire [23:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
+reg [4:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_level = 5'd0;
+reg main_litedramcore_bankmachine6_cmd_buffer_lookahead_replace = 1'd0;
+reg [3:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_produce = 4'd0;
+reg [3:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_consume = 4'd0;
+reg [3:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr = 4'd0;
+wire [23:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_r;
+wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we;
+wire [23:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w;
+wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_do_read;
+wire [3:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr;
+wire [23:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r;
+wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we;
+wire [20:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr;
+wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first;
+wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last;
+wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we;
+wire [20:0] main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr;
+wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first;
+wire main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last;
+wire main_litedramcore_bankmachine6_cmd_buffer_sink_valid;
+wire main_litedramcore_bankmachine6_cmd_buffer_sink_ready;
+wire main_litedramcore_bankmachine6_cmd_buffer_sink_first;
+wire main_litedramcore_bankmachine6_cmd_buffer_sink_last;
+wire main_litedramcore_bankmachine6_cmd_buffer_sink_payload_we;
+wire [20:0] main_litedramcore_bankmachine6_cmd_buffer_sink_payload_addr;
+reg main_litedramcore_bankmachine6_cmd_buffer_source_valid = 1'd0;
+wire main_litedramcore_bankmachine6_cmd_buffer_source_ready;
+reg main_litedramcore_bankmachine6_cmd_buffer_source_first = 1'd0;
+reg main_litedramcore_bankmachine6_cmd_buffer_source_last = 1'd0;
+reg main_litedramcore_bankmachine6_cmd_buffer_source_payload_we = 1'd0;
+reg [20:0] main_litedramcore_bankmachine6_cmd_buffer_source_payload_addr = 21'd0;
+reg [13:0] main_litedramcore_bankmachine6_row = 14'd0;
+reg main_litedramcore_bankmachine6_row_opened = 1'd0;
+wire main_litedramcore_bankmachine6_row_hit;
+reg main_litedramcore_bankmachine6_row_open = 1'd0;
+reg main_litedramcore_bankmachine6_row_close = 1'd0;
+reg main_litedramcore_bankmachine6_row_col_n_addr_sel = 1'd0;
+wire main_litedramcore_bankmachine6_twtpcon_valid;
+(* dont_touch = "true" *) reg main_litedramcore_bankmachine6_twtpcon_ready = 1'd0;
+reg [2:0] main_litedramcore_bankmachine6_twtpcon_count = 3'd0;
+wire main_litedramcore_bankmachine6_trccon_valid;
+(* dont_touch = "true" *) reg main_litedramcore_bankmachine6_trccon_ready = 1'd0;
+reg [2:0] main_litedramcore_bankmachine6_trccon_count = 3'd0;
+wire main_litedramcore_bankmachine6_trascon_valid;
+(* dont_touch = "true" *) reg main_litedramcore_bankmachine6_trascon_ready = 1'd0;
+reg [2:0] main_litedramcore_bankmachine6_trascon_count = 3'd0;
+wire main_litedramcore_bankmachine7_req_valid;
+wire main_litedramcore_bankmachine7_req_ready;
+wire main_litedramcore_bankmachine7_req_we;
+wire [20:0] main_litedramcore_bankmachine7_req_addr;
+wire main_litedramcore_bankmachine7_req_lock;
+reg main_litedramcore_bankmachine7_req_wdata_ready = 1'd0;
+reg main_litedramcore_bankmachine7_req_rdata_valid = 1'd0;
+wire main_litedramcore_bankmachine7_refresh_req;
+reg main_litedramcore_bankmachine7_refresh_gnt = 1'd0;
+reg main_litedramcore_bankmachine7_cmd_valid = 1'd0;
+reg main_litedramcore_bankmachine7_cmd_ready = 1'd0;
+reg [13:0] main_litedramcore_bankmachine7_cmd_payload_a = 14'd0;
+wire [2:0] main_litedramcore_bankmachine7_cmd_payload_ba;
+reg main_litedramcore_bankmachine7_cmd_payload_cas = 1'd0;
+reg main_litedramcore_bankmachine7_cmd_payload_ras = 1'd0;
+reg main_litedramcore_bankmachine7_cmd_payload_we = 1'd0;
+reg main_litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd0;
+reg main_litedramcore_bankmachine7_cmd_payload_is_read = 1'd0;
+reg main_litedramcore_bankmachine7_cmd_payload_is_write = 1'd0;
+reg main_litedramcore_bankmachine7_auto_precharge = 1'd0;
+wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid;
+wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready;
+reg main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_first = 1'd0;
+reg main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_last = 1'd0;
+wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we;
+wire [20:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr;
+wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid;
+wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready;
+wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_first;
+wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_last;
+wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we;
+wire [20:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr;
+wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we;
+wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable;
+wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re;
+wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable;
+wire [23:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din;
+wire [23:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
+reg [4:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_level = 5'd0;
+reg main_litedramcore_bankmachine7_cmd_buffer_lookahead_replace = 1'd0;
+reg [3:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_produce = 4'd0;
+reg [3:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_consume = 4'd0;
+reg [3:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr = 4'd0;
+wire [23:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_r;
+wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we;
+wire [23:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w;
+wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_do_read;
+wire [3:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr;
+wire [23:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r;
+wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we;
+wire [20:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr;
+wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first;
+wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last;
+wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we;
+wire [20:0] main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr;
+wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first;
+wire main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last;
+wire main_litedramcore_bankmachine7_cmd_buffer_sink_valid;
+wire main_litedramcore_bankmachine7_cmd_buffer_sink_ready;
+wire main_litedramcore_bankmachine7_cmd_buffer_sink_first;
+wire main_litedramcore_bankmachine7_cmd_buffer_sink_last;
+wire main_litedramcore_bankmachine7_cmd_buffer_sink_payload_we;
+wire [20:0] main_litedramcore_bankmachine7_cmd_buffer_sink_payload_addr;
+reg main_litedramcore_bankmachine7_cmd_buffer_source_valid = 1'd0;
+wire main_litedramcore_bankmachine7_cmd_buffer_source_ready;
+reg main_litedramcore_bankmachine7_cmd_buffer_source_first = 1'd0;
+reg main_litedramcore_bankmachine7_cmd_buffer_source_last = 1'd0;
+reg main_litedramcore_bankmachine7_cmd_buffer_source_payload_we = 1'd0;
+reg [20:0] main_litedramcore_bankmachine7_cmd_buffer_source_payload_addr = 21'd0;
+reg [13:0] main_litedramcore_bankmachine7_row = 14'd0;
+reg main_litedramcore_bankmachine7_row_opened = 1'd0;
+wire main_litedramcore_bankmachine7_row_hit;
+reg main_litedramcore_bankmachine7_row_open = 1'd0;
+reg main_litedramcore_bankmachine7_row_close = 1'd0;
+reg main_litedramcore_bankmachine7_row_col_n_addr_sel = 1'd0;
+wire main_litedramcore_bankmachine7_twtpcon_valid;
+(* dont_touch = "true" *) reg main_litedramcore_bankmachine7_twtpcon_ready = 1'd0;
+reg [2:0] main_litedramcore_bankmachine7_twtpcon_count = 3'd0;
+wire main_litedramcore_bankmachine7_trccon_valid;
+(* dont_touch = "true" *) reg main_litedramcore_bankmachine7_trccon_ready = 1'd0;
+reg [2:0] main_litedramcore_bankmachine7_trccon_count = 3'd0;
+wire main_litedramcore_bankmachine7_trascon_valid;
+(* dont_touch = "true" *) reg main_litedramcore_bankmachine7_trascon_ready = 1'd0;
+reg [2:0] main_litedramcore_bankmachine7_trascon_count = 3'd0;
+wire main_litedramcore_ras_allowed;
+wire main_litedramcore_cas_allowed;
+wire [1:0] main_litedramcore_rdcmdphase;
+wire [1:0] main_litedramcore_wrcmdphase;
+reg main_litedramcore_choose_cmd_want_reads = 1'd0;
+reg main_litedramcore_choose_cmd_want_writes = 1'd0;
+reg main_litedramcore_choose_cmd_want_cmds = 1'd0;
+reg main_litedramcore_choose_cmd_want_activates = 1'd0;
+wire main_litedramcore_choose_cmd_cmd_valid;
+reg main_litedramcore_choose_cmd_cmd_ready = 1'd0;
+wire [13:0] main_litedramcore_choose_cmd_cmd_payload_a;
+wire [2:0] main_litedramcore_choose_cmd_cmd_payload_ba;
+reg main_litedramcore_choose_cmd_cmd_payload_cas = 1'd0;
+reg main_litedramcore_choose_cmd_cmd_payload_ras = 1'd0;
+reg main_litedramcore_choose_cmd_cmd_payload_we = 1'd0;
+wire main_litedramcore_choose_cmd_cmd_payload_is_cmd;
+wire main_litedramcore_choose_cmd_cmd_payload_is_read;
+wire main_litedramcore_choose_cmd_cmd_payload_is_write;
+reg [7:0] main_litedramcore_choose_cmd_valids = 8'd0;
+wire [7:0] main_litedramcore_choose_cmd_request;
+reg [2:0] main_litedramcore_choose_cmd_grant = 3'd0;
+wire main_litedramcore_choose_cmd_ce;
+reg main_litedramcore_choose_req_want_reads = 1'd0;
+reg main_litedramcore_choose_req_want_writes = 1'd0;
+reg main_litedramcore_choose_req_want_cmds = 1'd0;
+reg main_litedramcore_choose_req_want_activates = 1'd0;
+wire main_litedramcore_choose_req_cmd_valid;
+reg main_litedramcore_choose_req_cmd_ready = 1'd0;
+wire [13:0] main_litedramcore_choose_req_cmd_payload_a;
+wire [2:0] main_litedramcore_choose_req_cmd_payload_ba;
+reg main_litedramcore_choose_req_cmd_payload_cas = 1'd0;
+reg main_litedramcore_choose_req_cmd_payload_ras = 1'd0;
+reg main_litedramcore_choose_req_cmd_payload_we = 1'd0;
+wire main_litedramcore_choose_req_cmd_payload_is_cmd;
+wire main_litedramcore_choose_req_cmd_payload_is_read;
+wire main_litedramcore_choose_req_cmd_payload_is_write;
+reg [7:0] main_litedramcore_choose_req_valids = 8'd0;
+wire [7:0] main_litedramcore_choose_req_request;
+reg [2:0] main_litedramcore_choose_req_grant = 3'd0;
+wire main_litedramcore_choose_req_ce;
+reg [13:0] main_litedramcore_nop_a = 14'd0;
+reg [2:0] main_litedramcore_nop_ba = 3'd0;
+reg [1:0] main_litedramcore_steerer_sel0 = 2'd0;
+reg [1:0] main_litedramcore_steerer_sel1 = 2'd0;
+reg [1:0] main_litedramcore_steerer_sel2 = 2'd0;
+reg [1:0] main_litedramcore_steerer_sel3 = 2'd0;
+reg main_litedramcore_steerer0 = 1'd1;
+reg main_litedramcore_steerer1 = 1'd1;
+reg main_litedramcore_steerer2 = 1'd1;
+reg main_litedramcore_steerer3 = 1'd1;
+reg main_litedramcore_steerer4 = 1'd1;
+reg main_litedramcore_steerer5 = 1'd1;
+reg main_litedramcore_steerer6 = 1'd1;
+reg main_litedramcore_steerer7 = 1'd1;
+wire main_litedramcore_trrdcon_valid;
+(* dont_touch = "true" *) reg main_litedramcore_trrdcon_ready = 1'd0;
+reg main_litedramcore_trrdcon_count = 1'd0;
+wire main_litedramcore_tfawcon_valid;
+(* dont_touch = "true" *) reg main_litedramcore_tfawcon_ready = 1'd1;
+wire [2:0] main_litedramcore_tfawcon_count;
+reg [4:0] main_litedramcore_tfawcon_window = 5'd0;
+wire main_litedramcore_tccdcon_valid;
+(* dont_touch = "true" *) reg main_litedramcore_tccdcon_ready = 1'd0;
+reg main_litedramcore_tccdcon_count = 1'd0;
+wire main_litedramcore_twtrcon_valid;
+(* dont_touch = "true" *) reg main_litedramcore_twtrcon_ready = 1'd0;
+reg [2:0] main_litedramcore_twtrcon_count = 3'd0;
+wire main_litedramcore_read_available;
+wire main_litedramcore_write_available;
+reg main_litedramcore_en0 = 1'd0;
+wire main_litedramcore_max_time0;
+reg [4:0] main_litedramcore_time0 = 5'd0;
+reg main_litedramcore_en1 = 1'd0;
+wire main_litedramcore_max_time1;
+reg [3:0] main_litedramcore_time1 = 4'd0;
+wire main_litedramcore_go_to_refresh;
+reg main_init_done_storage = 1'd0;
+reg main_init_done_re = 1'd0;
+reg main_init_error_storage = 1'd0;
+reg main_init_error_re = 1'd0;
+wire [29:0] main_wb_bus_adr;
+wire [31:0] main_wb_bus_dat_w;
+wire [31:0] main_wb_bus_dat_r;
+wire [3:0] main_wb_bus_sel;
+wire main_wb_bus_cyc;
+wire main_wb_bus_stb;
+wire main_wb_bus_ack;
+wire main_wb_bus_we;
+wire [2:0] main_wb_bus_cti;
+wire [1:0] main_wb_bus_bte;
+wire main_wb_bus_err;
+wire main_user_port_cmd_valid;
+wire main_user_port_cmd_ready;
+wire main_user_port_cmd_payload_we;
+wire [23:0] main_user_port_cmd_payload_addr;
+wire main_user_port_wdata_valid;
+wire main_user_port_wdata_ready;
+wire [127:0] main_user_port_wdata_payload_data;
+wire [15:0] main_user_port_wdata_payload_we;
+wire main_user_port_rdata_valid;
+wire main_user_port_rdata_ready;
+wire [127:0] main_user_port_rdata_payload_data;
+wire builder_reset0;
+wire builder_reset1;
+wire builder_reset2;
+wire builder_reset3;
+wire builder_reset4;
+wire builder_reset5;
+wire builder_reset6;
+wire builder_reset7;
+wire builder_pll_fb;
+reg [1:0] builder_refresher_state = 2'd0;
+reg [1:0] builder_refresher_next_state = 2'd0;
+reg [3:0] builder_bankmachine0_state = 4'd0;
+reg [3:0] builder_bankmachine0_next_state = 4'd0;
+reg [3:0] builder_bankmachine1_state = 4'd0;
+reg [3:0] builder_bankmachine1_next_state = 4'd0;
+reg [3:0] builder_bankmachine2_state = 4'd0;
+reg [3:0] builder_bankmachine2_next_state = 4'd0;
+reg [3:0] builder_bankmachine3_state = 4'd0;
+reg [3:0] builder_bankmachine3_next_state = 4'd0;
+reg [3:0] builder_bankmachine4_state = 4'd0;
+reg [3:0] builder_bankmachine4_next_state = 4'd0;
+reg [3:0] builder_bankmachine5_state = 4'd0;
+reg [3:0] builder_bankmachine5_next_state = 4'd0;
+reg [3:0] builder_bankmachine6_state = 4'd0;
+reg [3:0] builder_bankmachine6_next_state = 4'd0;
+reg [3:0] builder_bankmachine7_state = 4'd0;
+reg [3:0] builder_bankmachine7_next_state = 4'd0;
+reg [3:0] builder_multiplexer_state = 4'd0;
+reg [3:0] builder_multiplexer_next_state = 4'd0;
+wire builder_roundrobin0_request;
+wire builder_roundrobin0_grant;
+wire builder_roundrobin0_ce;
+wire builder_roundrobin1_request;
+wire builder_roundrobin1_grant;
+wire builder_roundrobin1_ce;
+wire builder_roundrobin2_request;
+wire builder_roundrobin2_grant;
+wire builder_roundrobin2_ce;
+wire builder_roundrobin3_request;
+wire builder_roundrobin3_grant;
+wire builder_roundrobin3_ce;
+wire builder_roundrobin4_request;
+wire builder_roundrobin4_grant;
+wire builder_roundrobin4_ce;
+wire builder_roundrobin5_request;
+wire builder_roundrobin5_grant;
+wire builder_roundrobin5_ce;
+wire builder_roundrobin6_request;
+wire builder_roundrobin6_grant;
+wire builder_roundrobin6_ce;
+wire builder_roundrobin7_request;
+wire builder_roundrobin7_grant;
+wire builder_roundrobin7_ce;
+reg builder_locked0 = 1'd0;
+reg builder_locked1 = 1'd0;
+reg builder_locked2 = 1'd0;
+reg builder_locked3 = 1'd0;
+reg builder_locked4 = 1'd0;
+reg builder_locked5 = 1'd0;
+reg builder_locked6 = 1'd0;
+reg builder_locked7 = 1'd0;
+reg builder_new_master_wdata_ready0 = 1'd0;
+reg builder_new_master_wdata_ready1 = 1'd0;
+reg builder_new_master_rdata_valid0 = 1'd0;
+reg builder_new_master_rdata_valid1 = 1'd0;
+reg builder_new_master_rdata_valid2 = 1'd0;
+reg builder_new_master_rdata_valid3 = 1'd0;
+reg builder_new_master_rdata_valid4 = 1'd0;
+reg builder_new_master_rdata_valid5 = 1'd0;
+reg builder_new_master_rdata_valid6 = 1'd0;
+reg builder_new_master_rdata_valid7 = 1'd0;
+reg builder_new_master_rdata_valid8 = 1'd0;
+reg [13:0] builder_litedramcore_adr = 14'd0;
+reg builder_litedramcore_we = 1'd0;
+reg [7:0] builder_litedramcore_dat_w = 8'd0;
+wire [7:0] builder_litedramcore_dat_r;
+wire [29:0] builder_litedramcore_wishbone_adr;
+wire [31:0] builder_litedramcore_wishbone_dat_w;
+reg [31:0] builder_litedramcore_wishbone_dat_r = 32'd0;
+wire [3:0] builder_litedramcore_wishbone_sel;
+wire builder_litedramcore_wishbone_cyc;
+wire builder_litedramcore_wishbone_stb;
+reg builder_litedramcore_wishbone_ack = 1'd0;
+wire builder_litedramcore_wishbone_we;
+wire [2:0] builder_litedramcore_wishbone_cti;
+wire [1:0] builder_litedramcore_wishbone_bte;
+reg builder_litedramcore_wishbone_err = 1'd0;
+wire [13:0] builder_interface0_bank_bus_adr;
+wire builder_interface0_bank_bus_we;
+wire [7:0] builder_interface0_bank_bus_dat_w;
+reg [7:0] builder_interface0_bank_bus_dat_r = 8'd0;
+reg builder_csrbank0_init_done0_re = 1'd0;
+wire builder_csrbank0_init_done0_r;
+reg builder_csrbank0_init_done0_we = 1'd0;
+wire builder_csrbank0_init_done0_w;
+reg builder_csrbank0_init_error0_re = 1'd0;
+wire builder_csrbank0_init_error0_r;
+reg builder_csrbank0_init_error0_we = 1'd0;
+wire builder_csrbank0_init_error0_w;
+wire builder_csrbank0_sel;
+wire [13:0] builder_interface1_bank_bus_adr;
+wire builder_interface1_bank_bus_we;
+wire [7:0] builder_interface1_bank_bus_dat_w;
+reg [7:0] builder_interface1_bank_bus_dat_r = 8'd0;
+reg builder_csrbank1_rst0_re = 1'd0;
+wire builder_csrbank1_rst0_r;
+reg builder_csrbank1_rst0_we = 1'd0;
+wire builder_csrbank1_rst0_w;
+reg builder_csrbank1_half_sys8x_taps0_re = 1'd0;
+wire [4:0] builder_csrbank1_half_sys8x_taps0_r;
+reg builder_csrbank1_half_sys8x_taps0_we = 1'd0;
+wire [4:0] builder_csrbank1_half_sys8x_taps0_w;
+reg builder_csrbank1_wlevel_en0_re = 1'd0;
+wire builder_csrbank1_wlevel_en0_r;
+reg builder_csrbank1_wlevel_en0_we = 1'd0;
+wire builder_csrbank1_wlevel_en0_w;
+reg builder_csrbank1_dly_sel0_re = 1'd0;
+wire [1:0] builder_csrbank1_dly_sel0_r;
+reg builder_csrbank1_dly_sel0_we = 1'd0;
+wire [1:0] builder_csrbank1_dly_sel0_w;
+reg builder_csrbank1_rdphase0_re = 1'd0;
+wire [1:0] builder_csrbank1_rdphase0_r;
+reg builder_csrbank1_rdphase0_we = 1'd0;
+wire [1:0] builder_csrbank1_rdphase0_w;
+reg builder_csrbank1_wrphase0_re = 1'd0;
+wire [1:0] builder_csrbank1_wrphase0_r;
+reg builder_csrbank1_wrphase0_we = 1'd0;
+wire [1:0] builder_csrbank1_wrphase0_w;
+wire builder_csrbank1_sel;
+wire [13:0] builder_interface2_bank_bus_adr;
+wire builder_interface2_bank_bus_we;
+wire [7:0] builder_interface2_bank_bus_dat_w;
+reg [7:0] builder_interface2_bank_bus_dat_r = 8'd0;
+reg builder_csrbank2_dfii_control0_re = 1'd0;
+wire [3:0] builder_csrbank2_dfii_control0_r;
+reg builder_csrbank2_dfii_control0_we = 1'd0;
+wire [3:0] builder_csrbank2_dfii_control0_w;
+reg builder_csrbank2_dfii_pi0_command0_re = 1'd0;
+wire [5:0] builder_csrbank2_dfii_pi0_command0_r;
+reg builder_csrbank2_dfii_pi0_command0_we = 1'd0;
+wire [5:0] builder_csrbank2_dfii_pi0_command0_w;
+reg builder_csrbank2_dfii_pi0_address1_re = 1'd0;
+wire [5:0] builder_csrbank2_dfii_pi0_address1_r;
+reg builder_csrbank2_dfii_pi0_address1_we = 1'd0;
+wire [5:0] builder_csrbank2_dfii_pi0_address1_w;
+reg builder_csrbank2_dfii_pi0_address0_re = 1'd0;
+wire [7:0] builder_csrbank2_dfii_pi0_address0_r;
+reg builder_csrbank2_dfii_pi0_address0_we = 1'd0;
+wire [7:0] builder_csrbank2_dfii_pi0_address0_w;
+reg builder_csrbank2_dfii_pi0_baddress0_re = 1'd0;
+wire [2:0] builder_csrbank2_dfii_pi0_baddress0_r;
+reg builder_csrbank2_dfii_pi0_baddress0_we = 1'd0;
+wire [2:0] builder_csrbank2_dfii_pi0_baddress0_w;
+reg builder_csrbank2_dfii_pi0_wrdata3_re = 1'd0;
+wire [7:0] builder_csrbank2_dfii_pi0_wrdata3_r;
+reg builder_csrbank2_dfii_pi0_wrdata3_we = 1'd0;
+wire [7:0] builder_csrbank2_dfii_pi0_wrdata3_w;
+reg builder_csrbank2_dfii_pi0_wrdata2_re = 1'd0;
+wire [7:0] builder_csrbank2_dfii_pi0_wrdata2_r;
+reg builder_csrbank2_dfii_pi0_wrdata2_we = 1'd0;
+wire [7:0] builder_csrbank2_dfii_pi0_wrdata2_w;
+reg builder_csrbank2_dfii_pi0_wrdata1_re = 1'd0;
+wire [7:0] builder_csrbank2_dfii_pi0_wrdata1_r;
+reg builder_csrbank2_dfii_pi0_wrdata1_we = 1'd0;
+wire [7:0] builder_csrbank2_dfii_pi0_wrdata1_w;
+reg builder_csrbank2_dfii_pi0_wrdata0_re = 1'd0;
+wire [7:0] builder_csrbank2_dfii_pi0_wrdata0_r;
+reg builder_csrbank2_dfii_pi0_wrdata0_we = 1'd0;
+wire [7:0] builder_csrbank2_dfii_pi0_wrdata0_w;
+reg builder_csrbank2_dfii_pi0_rddata3_re = 1'd0;
+wire [7:0] builder_csrbank2_dfii_pi0_rddata3_r;
+reg builder_csrbank2_dfii_pi0_rddata3_we = 1'd0;
+wire [7:0] builder_csrbank2_dfii_pi0_rddata3_w;
+reg builder_csrbank2_dfii_pi0_rddata2_re = 1'd0;
+wire [7:0] builder_csrbank2_dfii_pi0_rddata2_r;
+reg builder_csrbank2_dfii_pi0_rddata2_we = 1'd0;
+wire [7:0] builder_csrbank2_dfii_pi0_rddata2_w;
+reg builder_csrbank2_dfii_pi0_rddata1_re = 1'd0;
+wire [7:0] builder_csrbank2_dfii_pi0_rddata1_r;
+reg builder_csrbank2_dfii_pi0_rddata1_we = 1'd0;
+wire [7:0] builder_csrbank2_dfii_pi0_rddata1_w;
+reg builder_csrbank2_dfii_pi0_rddata0_re = 1'd0;
+wire [7:0] builder_csrbank2_dfii_pi0_rddata0_r;
+reg builder_csrbank2_dfii_pi0_rddata0_we = 1'd0;
+wire [7:0] builder_csrbank2_dfii_pi0_rddata0_w;
+reg builder_csrbank2_dfii_pi1_command0_re = 1'd0;
+wire [5:0] builder_csrbank2_dfii_pi1_command0_r;
+reg builder_csrbank2_dfii_pi1_command0_we = 1'd0;
+wire [5:0] builder_csrbank2_dfii_pi1_command0_w;
+reg builder_csrbank2_dfii_pi1_address1_re = 1'd0;
+wire [5:0] builder_csrbank2_dfii_pi1_address1_r;
+reg builder_csrbank2_dfii_pi1_address1_we = 1'd0;
+wire [5:0] builder_csrbank2_dfii_pi1_address1_w;
+reg builder_csrbank2_dfii_pi1_address0_re = 1'd0;
+wire [7:0] builder_csrbank2_dfii_pi1_address0_r;
+reg builder_csrbank2_dfii_pi1_address0_we = 1'd0;
+wire [7:0] builder_csrbank2_dfii_pi1_address0_w;
+reg builder_csrbank2_dfii_pi1_baddress0_re = 1'd0;
+wire [2:0] builder_csrbank2_dfii_pi1_baddress0_r;
+reg builder_csrbank2_dfii_pi1_baddress0_we = 1'd0;
+wire [2:0] builder_csrbank2_dfii_pi1_baddress0_w;
+reg builder_csrbank2_dfii_pi1_wrdata3_re = 1'd0;
+wire [7:0] builder_csrbank2_dfii_pi1_wrdata3_r;
+reg builder_csrbank2_dfii_pi1_wrdata3_we = 1'd0;
+wire [7:0] builder_csrbank2_dfii_pi1_wrdata3_w;
+reg builder_csrbank2_dfii_pi1_wrdata2_re = 1'd0;
+wire [7:0] builder_csrbank2_dfii_pi1_wrdata2_r;
+reg builder_csrbank2_dfii_pi1_wrdata2_we = 1'd0;
+wire [7:0] builder_csrbank2_dfii_pi1_wrdata2_w;
+reg builder_csrbank2_dfii_pi1_wrdata1_re = 1'd0;
+wire [7:0] builder_csrbank2_dfii_pi1_wrdata1_r;
+reg builder_csrbank2_dfii_pi1_wrdata1_we = 1'd0;
+wire [7:0] builder_csrbank2_dfii_pi1_wrdata1_w;
+reg builder_csrbank2_dfii_pi1_wrdata0_re = 1'd0;
+wire [7:0] builder_csrbank2_dfii_pi1_wrdata0_r;
+reg builder_csrbank2_dfii_pi1_wrdata0_we = 1'd0;
+wire [7:0] builder_csrbank2_dfii_pi1_wrdata0_w;
+reg builder_csrbank2_dfii_pi1_rddata3_re = 1'd0;
+wire [7:0] builder_csrbank2_dfii_pi1_rddata3_r;
+reg builder_csrbank2_dfii_pi1_rddata3_we = 1'd0;
+wire [7:0] builder_csrbank2_dfii_pi1_rddata3_w;
+reg builder_csrbank2_dfii_pi1_rddata2_re = 1'd0;
+wire [7:0] builder_csrbank2_dfii_pi1_rddata2_r;
+reg builder_csrbank2_dfii_pi1_rddata2_we = 1'd0;
+wire [7:0] builder_csrbank2_dfii_pi1_rddata2_w;
+reg builder_csrbank2_dfii_pi1_rddata1_re = 1'd0;
+wire [7:0] builder_csrbank2_dfii_pi1_rddata1_r;
+reg builder_csrbank2_dfii_pi1_rddata1_we = 1'd0;
+wire [7:0] builder_csrbank2_dfii_pi1_rddata1_w;
+reg builder_csrbank2_dfii_pi1_rddata0_re = 1'd0;
+wire [7:0] builder_csrbank2_dfii_pi1_rddata0_r;
+reg builder_csrbank2_dfii_pi1_rddata0_we = 1'd0;
+wire [7:0] builder_csrbank2_dfii_pi1_rddata0_w;
+reg builder_csrbank2_dfii_pi2_command0_re = 1'd0;
+wire [5:0] builder_csrbank2_dfii_pi2_command0_r;
+reg builder_csrbank2_dfii_pi2_command0_we = 1'd0;
+wire [5:0] builder_csrbank2_dfii_pi2_command0_w;
+reg builder_csrbank2_dfii_pi2_address1_re = 1'd0;
+wire [5:0] builder_csrbank2_dfii_pi2_address1_r;
+reg builder_csrbank2_dfii_pi2_address1_we = 1'd0;
+wire [5:0] builder_csrbank2_dfii_pi2_address1_w;
+reg builder_csrbank2_dfii_pi2_address0_re = 1'd0;
+wire [7:0] builder_csrbank2_dfii_pi2_address0_r;
+reg builder_csrbank2_dfii_pi2_address0_we = 1'd0;
+wire [7:0] builder_csrbank2_dfii_pi2_address0_w;
+reg builder_csrbank2_dfii_pi2_baddress0_re = 1'd0;
+wire [2:0] builder_csrbank2_dfii_pi2_baddress0_r;
+reg builder_csrbank2_dfii_pi2_baddress0_we = 1'd0;
+wire [2:0] builder_csrbank2_dfii_pi2_baddress0_w;
+reg builder_csrbank2_dfii_pi2_wrdata3_re = 1'd0;
+wire [7:0] builder_csrbank2_dfii_pi2_wrdata3_r;
+reg builder_csrbank2_dfii_pi2_wrdata3_we = 1'd0;
+wire [7:0] builder_csrbank2_dfii_pi2_wrdata3_w;
+reg builder_csrbank2_dfii_pi2_wrdata2_re = 1'd0;
+wire [7:0] builder_csrbank2_dfii_pi2_wrdata2_r;
+reg builder_csrbank2_dfii_pi2_wrdata2_we = 1'd0;
+wire [7:0] builder_csrbank2_dfii_pi2_wrdata2_w;
+reg builder_csrbank2_dfii_pi2_wrdata1_re = 1'd0;
+wire [7:0] builder_csrbank2_dfii_pi2_wrdata1_r;
+reg builder_csrbank2_dfii_pi2_wrdata1_we = 1'd0;
+wire [7:0] builder_csrbank2_dfii_pi2_wrdata1_w;
+reg builder_csrbank2_dfii_pi2_wrdata0_re = 1'd0;
+wire [7:0] builder_csrbank2_dfii_pi2_wrdata0_r;
+reg builder_csrbank2_dfii_pi2_wrdata0_we = 1'd0;
+wire [7:0] builder_csrbank2_dfii_pi2_wrdata0_w;
+reg builder_csrbank2_dfii_pi2_rddata3_re = 1'd0;
+wire [7:0] builder_csrbank2_dfii_pi2_rddata3_r;
+reg builder_csrbank2_dfii_pi2_rddata3_we = 1'd0;
+wire [7:0] builder_csrbank2_dfii_pi2_rddata3_w;
+reg builder_csrbank2_dfii_pi2_rddata2_re = 1'd0;
+wire [7:0] builder_csrbank2_dfii_pi2_rddata2_r;
+reg builder_csrbank2_dfii_pi2_rddata2_we = 1'd0;
+wire [7:0] builder_csrbank2_dfii_pi2_rddata2_w;
+reg builder_csrbank2_dfii_pi2_rddata1_re = 1'd0;
+wire [7:0] builder_csrbank2_dfii_pi2_rddata1_r;
+reg builder_csrbank2_dfii_pi2_rddata1_we = 1'd0;
+wire [7:0] builder_csrbank2_dfii_pi2_rddata1_w;
+reg builder_csrbank2_dfii_pi2_rddata0_re = 1'd0;
+wire [7:0] builder_csrbank2_dfii_pi2_rddata0_r;
+reg builder_csrbank2_dfii_pi2_rddata0_we = 1'd0;
+wire [7:0] builder_csrbank2_dfii_pi2_rddata0_w;
+reg builder_csrbank2_dfii_pi3_command0_re = 1'd0;
+wire [5:0] builder_csrbank2_dfii_pi3_command0_r;
+reg builder_csrbank2_dfii_pi3_command0_we = 1'd0;
+wire [5:0] builder_csrbank2_dfii_pi3_command0_w;
+reg builder_csrbank2_dfii_pi3_address1_re = 1'd0;
+wire [5:0] builder_csrbank2_dfii_pi3_address1_r;
+reg builder_csrbank2_dfii_pi3_address1_we = 1'd0;
+wire [5:0] builder_csrbank2_dfii_pi3_address1_w;
+reg builder_csrbank2_dfii_pi3_address0_re = 1'd0;
+wire [7:0] builder_csrbank2_dfii_pi3_address0_r;
+reg builder_csrbank2_dfii_pi3_address0_we = 1'd0;
+wire [7:0] builder_csrbank2_dfii_pi3_address0_w;
+reg builder_csrbank2_dfii_pi3_baddress0_re = 1'd0;
+wire [2:0] builder_csrbank2_dfii_pi3_baddress0_r;
+reg builder_csrbank2_dfii_pi3_baddress0_we = 1'd0;
+wire [2:0] builder_csrbank2_dfii_pi3_baddress0_w;
+reg builder_csrbank2_dfii_pi3_wrdata3_re = 1'd0;
+wire [7:0] builder_csrbank2_dfii_pi3_wrdata3_r;
+reg builder_csrbank2_dfii_pi3_wrdata3_we = 1'd0;
+wire [7:0] builder_csrbank2_dfii_pi3_wrdata3_w;
+reg builder_csrbank2_dfii_pi3_wrdata2_re = 1'd0;
+wire [7:0] builder_csrbank2_dfii_pi3_wrdata2_r;
+reg builder_csrbank2_dfii_pi3_wrdata2_we = 1'd0;
+wire [7:0] builder_csrbank2_dfii_pi3_wrdata2_w;
+reg builder_csrbank2_dfii_pi3_wrdata1_re = 1'd0;
+wire [7:0] builder_csrbank2_dfii_pi3_wrdata1_r;
+reg builder_csrbank2_dfii_pi3_wrdata1_we = 1'd0;
+wire [7:0] builder_csrbank2_dfii_pi3_wrdata1_w;
+reg builder_csrbank2_dfii_pi3_wrdata0_re = 1'd0;
+wire [7:0] builder_csrbank2_dfii_pi3_wrdata0_r;
+reg builder_csrbank2_dfii_pi3_wrdata0_we = 1'd0;
+wire [7:0] builder_csrbank2_dfii_pi3_wrdata0_w;
+reg builder_csrbank2_dfii_pi3_rddata3_re = 1'd0;
+wire [7:0] builder_csrbank2_dfii_pi3_rddata3_r;
+reg builder_csrbank2_dfii_pi3_rddata3_we = 1'd0;
+wire [7:0] builder_csrbank2_dfii_pi3_rddata3_w;
+reg builder_csrbank2_dfii_pi3_rddata2_re = 1'd0;
+wire [7:0] builder_csrbank2_dfii_pi3_rddata2_r;
+reg builder_csrbank2_dfii_pi3_rddata2_we = 1'd0;
+wire [7:0] builder_csrbank2_dfii_pi3_rddata2_w;
+reg builder_csrbank2_dfii_pi3_rddata1_re = 1'd0;
+wire [7:0] builder_csrbank2_dfii_pi3_rddata1_r;
+reg builder_csrbank2_dfii_pi3_rddata1_we = 1'd0;
+wire [7:0] builder_csrbank2_dfii_pi3_rddata1_w;
+reg builder_csrbank2_dfii_pi3_rddata0_re = 1'd0;
+wire [7:0] builder_csrbank2_dfii_pi3_rddata0_r;
+reg builder_csrbank2_dfii_pi3_rddata0_we = 1'd0;
+wire [7:0] builder_csrbank2_dfii_pi3_rddata0_w;
+wire builder_csrbank2_sel;
+wire [13:0] builder_csr_interconnect_adr;
+wire builder_csr_interconnect_we;
+wire [7:0] builder_csr_interconnect_dat_w;
+wire [7:0] builder_csr_interconnect_dat_r;
+reg [1:0] builder_state = 2'd0;
+reg [1:0] builder_next_state = 2'd0;
+reg [7:0] builder_litedramcore_dat_w_next_value0 = 8'd0;
+reg builder_litedramcore_dat_w_next_value_ce0 = 1'd0;
+reg [13:0] builder_litedramcore_adr_next_value1 = 14'd0;
+reg builder_litedramcore_adr_next_value_ce1 = 1'd0;
+reg builder_litedramcore_we_next_value2 = 1'd0;
+reg builder_litedramcore_we_next_value_ce2 = 1'd0;
+reg builder_rhs_array_muxed0 = 1'd0;
+reg [13:0] builder_rhs_array_muxed1 = 14'd0;
+reg [2:0] builder_rhs_array_muxed2 = 3'd0;
+reg builder_rhs_array_muxed3 = 1'd0;
+reg builder_rhs_array_muxed4 = 1'd0;
+reg builder_rhs_array_muxed5 = 1'd0;
+reg builder_t_array_muxed0 = 1'd0;
+reg builder_t_array_muxed1 = 1'd0;
+reg builder_t_array_muxed2 = 1'd0;
+reg builder_rhs_array_muxed6 = 1'd0;
+reg [13:0] builder_rhs_array_muxed7 = 14'd0;
+reg [2:0] builder_rhs_array_muxed8 = 3'd0;
+reg builder_rhs_array_muxed9 = 1'd0;
+reg builder_rhs_array_muxed10 = 1'd0;
+reg builder_rhs_array_muxed11 = 1'd0;
+reg builder_t_array_muxed3 = 1'd0;
+reg builder_t_array_muxed4 = 1'd0;
+reg builder_t_array_muxed5 = 1'd0;
+reg [20:0] builder_rhs_array_muxed12 = 21'd0;
+reg builder_rhs_array_muxed13 = 1'd0;
+reg builder_rhs_array_muxed14 = 1'd0;
+reg [20:0] builder_rhs_array_muxed15 = 21'd0;
+reg builder_rhs_array_muxed16 = 1'd0;
+reg builder_rhs_array_muxed17 = 1'd0;
+reg [20:0] builder_rhs_array_muxed18 = 21'd0;
+reg builder_rhs_array_muxed19 = 1'd0;
+reg builder_rhs_array_muxed20 = 1'd0;
+reg [20:0] builder_rhs_array_muxed21 = 21'd0;
+reg builder_rhs_array_muxed22 = 1'd0;
+reg builder_rhs_array_muxed23 = 1'd0;
+reg [20:0] builder_rhs_array_muxed24 = 21'd0;
+reg builder_rhs_array_muxed25 = 1'd0;
+reg builder_rhs_array_muxed26 = 1'd0;
+reg [20:0] builder_rhs_array_muxed27 = 21'd0;
+reg builder_rhs_array_muxed28 = 1'd0;
+reg builder_rhs_array_muxed29 = 1'd0;
+reg [20:0] builder_rhs_array_muxed30 = 21'd0;
+reg builder_rhs_array_muxed31 = 1'd0;
+reg builder_rhs_array_muxed32 = 1'd0;
+reg [20:0] builder_rhs_array_muxed33 = 21'd0;
+reg builder_rhs_array_muxed34 = 1'd0;
+reg builder_rhs_array_muxed35 = 1'd0;
+reg [2:0] builder_array_muxed0 = 3'd0;
+reg [13:0] builder_array_muxed1 = 14'd0;
+reg builder_array_muxed2 = 1'd0;
+reg builder_array_muxed3 = 1'd0;
+reg builder_array_muxed4 = 1'd0;
+reg builder_array_muxed5 = 1'd0;
+reg builder_array_muxed6 = 1'd0;
+reg [2:0] builder_array_muxed7 = 3'd0;
+reg [13:0] builder_array_muxed8 = 14'd0;
+reg builder_array_muxed9 = 1'd0;
+reg builder_array_muxed10 = 1'd0;
+reg builder_array_muxed11 = 1'd0;
+reg builder_array_muxed12 = 1'd0;
+reg builder_array_muxed13 = 1'd0;
+reg [2:0] builder_array_muxed14 = 3'd0;
+reg [13:0] builder_array_muxed15 = 14'd0;
+reg builder_array_muxed16 = 1'd0;
+reg builder_array_muxed17 = 1'd0;
+reg builder_array_muxed18 = 1'd0;
+reg builder_array_muxed19 = 1'd0;
+reg builder_array_muxed20 = 1'd0;
+reg [2:0] builder_array_muxed21 = 3'd0;
+reg [13:0] builder_array_muxed22 = 14'd0;
+reg builder_array_muxed23 = 1'd0;
+reg builder_array_muxed24 = 1'd0;
+reg builder_array_muxed25 = 1'd0;
+reg builder_array_muxed26 = 1'd0;
+reg builder_array_muxed27 = 1'd0;
+wire builder_xilinxasyncresetsynchronizerimpl0;
+wire builder_xilinxasyncresetsynchronizerimpl0_rst_meta;
+wire builder_xilinxasyncresetsynchronizerimpl1;
+wire builder_xilinxasyncresetsynchronizerimpl1_rst_meta;
+wire builder_xilinxasyncresetsynchronizerimpl2;
+wire builder_xilinxasyncresetsynchronizerimpl2_rst_meta;
+wire builder_xilinxasyncresetsynchronizerimpl2_expr;
+wire builder_xilinxasyncresetsynchronizerimpl3;
+wire builder_xilinxasyncresetsynchronizerimpl3_rst_meta;
+wire builder_xilinxasyncresetsynchronizerimpl3_expr;
+
+// synthesis translate_off
+reg dummy_s;
+initial dummy_s <= 1'd0;
+// synthesis translate_on
+assign init_done = main_init_done_storage;
+assign init_error = main_init_error_storage;
+assign main_wb_bus_adr = wb_ctrl_adr;
+assign main_wb_bus_dat_w = wb_ctrl_dat_w;
+assign wb_ctrl_dat_r = main_wb_bus_dat_r;
+assign main_wb_bus_sel = wb_ctrl_sel;
+assign main_wb_bus_cyc = wb_ctrl_cyc;
+assign main_wb_bus_stb = wb_ctrl_stb;
+assign wb_ctrl_ack = main_wb_bus_ack;
+assign main_wb_bus_we = wb_ctrl_we;
+assign main_wb_bus_cti = wb_ctrl_cti;
+assign main_wb_bus_bte = wb_ctrl_bte;
+assign wb_ctrl_err = main_wb_bus_err;
+assign user_clk = sys_clk;
+assign user_rst = sys_rst;
+assign main_user_port_cmd_valid = user_port_native_0_cmd_valid;
+assign user_port_native_0_cmd_ready = main_user_port_cmd_ready;
+assign main_user_port_cmd_payload_we = user_port_native_0_cmd_we;
+assign main_user_port_cmd_payload_addr = user_port_native_0_cmd_addr;
+assign main_user_port_wdata_valid = user_port_native_0_wdata_valid;
+assign user_port_native_0_wdata_ready = main_user_port_wdata_ready;
+assign main_user_port_wdata_payload_we = user_port_native_0_wdata_we;
+assign main_user_port_wdata_payload_data = user_port_native_0_wdata_data;
+assign user_port_native_0_rdata_valid = main_user_port_rdata_valid;
+assign main_user_port_rdata_ready = user_port_native_0_rdata_ready;
+assign user_port_native_0_rdata_data = main_user_port_rdata_payload_data;
+assign main_reset = rst;
+assign pll_locked = main_locked;
+assign main_clkin = clk;
+assign iodelay_clk = main_clkout_buf0;
+assign sys_clk = main_clkout_buf1;
+assign sys4x_clk = main_clkout_buf2;
+assign sys4x_dqs_clk = main_clkout_buf3;
+assign main_a7ddrphy_dqs_oe_delay_tappeddelayline = ((main_a7ddrphy_dqs_preamble | main_a7ddrphy_dqs_oe) | main_a7ddrphy_dqs_postamble);
+assign main_a7ddrphy_dq_oe_delay_tappeddelayline = ((main_a7ddrphy_dqs_preamble | main_a7ddrphy_dq_oe) | main_a7ddrphy_dqs_postamble);
+
+// synthesis translate_off
+reg dummy_d;
+// synthesis translate_on
+always @(*) begin
+	main_a7ddrphy_dfi_p0_rddata <= 32'd0;
+	main_a7ddrphy_dfi_p0_rddata[0] <= main_a7ddrphy_bitslip04[0];
+	main_a7ddrphy_dfi_p0_rddata[16] <= main_a7ddrphy_bitslip04[1];
+	main_a7ddrphy_dfi_p0_rddata[1] <= main_a7ddrphy_bitslip14[0];
+	main_a7ddrphy_dfi_p0_rddata[17] <= main_a7ddrphy_bitslip14[1];
+	main_a7ddrphy_dfi_p0_rddata[2] <= main_a7ddrphy_bitslip22[0];
+	main_a7ddrphy_dfi_p0_rddata[18] <= main_a7ddrphy_bitslip22[1];
+	main_a7ddrphy_dfi_p0_rddata[3] <= main_a7ddrphy_bitslip32[0];
+	main_a7ddrphy_dfi_p0_rddata[19] <= main_a7ddrphy_bitslip32[1];
+	main_a7ddrphy_dfi_p0_rddata[4] <= main_a7ddrphy_bitslip42[0];
+	main_a7ddrphy_dfi_p0_rddata[20] <= main_a7ddrphy_bitslip42[1];
+	main_a7ddrphy_dfi_p0_rddata[5] <= main_a7ddrphy_bitslip52[0];
+	main_a7ddrphy_dfi_p0_rddata[21] <= main_a7ddrphy_bitslip52[1];
+	main_a7ddrphy_dfi_p0_rddata[6] <= main_a7ddrphy_bitslip62[0];
+	main_a7ddrphy_dfi_p0_rddata[22] <= main_a7ddrphy_bitslip62[1];
+	main_a7ddrphy_dfi_p0_rddata[7] <= main_a7ddrphy_bitslip72[0];
+	main_a7ddrphy_dfi_p0_rddata[23] <= main_a7ddrphy_bitslip72[1];
+	main_a7ddrphy_dfi_p0_rddata[8] <= main_a7ddrphy_bitslip82[0];
+	main_a7ddrphy_dfi_p0_rddata[24] <= main_a7ddrphy_bitslip82[1];
+	main_a7ddrphy_dfi_p0_rddata[9] <= main_a7ddrphy_bitslip92[0];
+	main_a7ddrphy_dfi_p0_rddata[25] <= main_a7ddrphy_bitslip92[1];
+	main_a7ddrphy_dfi_p0_rddata[10] <= main_a7ddrphy_bitslip102[0];
+	main_a7ddrphy_dfi_p0_rddata[26] <= main_a7ddrphy_bitslip102[1];
+	main_a7ddrphy_dfi_p0_rddata[11] <= main_a7ddrphy_bitslip112[0];
+	main_a7ddrphy_dfi_p0_rddata[27] <= main_a7ddrphy_bitslip112[1];
+	main_a7ddrphy_dfi_p0_rddata[12] <= main_a7ddrphy_bitslip122[0];
+	main_a7ddrphy_dfi_p0_rddata[28] <= main_a7ddrphy_bitslip122[1];
+	main_a7ddrphy_dfi_p0_rddata[13] <= main_a7ddrphy_bitslip132[0];
+	main_a7ddrphy_dfi_p0_rddata[29] <= main_a7ddrphy_bitslip132[1];
+	main_a7ddrphy_dfi_p0_rddata[14] <= main_a7ddrphy_bitslip142[0];
+	main_a7ddrphy_dfi_p0_rddata[30] <= main_a7ddrphy_bitslip142[1];
+	main_a7ddrphy_dfi_p0_rddata[15] <= main_a7ddrphy_bitslip152[0];
+	main_a7ddrphy_dfi_p0_rddata[31] <= main_a7ddrphy_bitslip152[1];
+// synthesis translate_off
+	dummy_d = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_1;
+// synthesis translate_on
+always @(*) begin
+	main_a7ddrphy_dfi_p1_rddata <= 32'd0;
+	main_a7ddrphy_dfi_p1_rddata[0] <= main_a7ddrphy_bitslip04[2];
+	main_a7ddrphy_dfi_p1_rddata[16] <= main_a7ddrphy_bitslip04[3];
+	main_a7ddrphy_dfi_p1_rddata[1] <= main_a7ddrphy_bitslip14[2];
+	main_a7ddrphy_dfi_p1_rddata[17] <= main_a7ddrphy_bitslip14[3];
+	main_a7ddrphy_dfi_p1_rddata[2] <= main_a7ddrphy_bitslip22[2];
+	main_a7ddrphy_dfi_p1_rddata[18] <= main_a7ddrphy_bitslip22[3];
+	main_a7ddrphy_dfi_p1_rddata[3] <= main_a7ddrphy_bitslip32[2];
+	main_a7ddrphy_dfi_p1_rddata[19] <= main_a7ddrphy_bitslip32[3];
+	main_a7ddrphy_dfi_p1_rddata[4] <= main_a7ddrphy_bitslip42[2];
+	main_a7ddrphy_dfi_p1_rddata[20] <= main_a7ddrphy_bitslip42[3];
+	main_a7ddrphy_dfi_p1_rddata[5] <= main_a7ddrphy_bitslip52[2];
+	main_a7ddrphy_dfi_p1_rddata[21] <= main_a7ddrphy_bitslip52[3];
+	main_a7ddrphy_dfi_p1_rddata[6] <= main_a7ddrphy_bitslip62[2];
+	main_a7ddrphy_dfi_p1_rddata[22] <= main_a7ddrphy_bitslip62[3];
+	main_a7ddrphy_dfi_p1_rddata[7] <= main_a7ddrphy_bitslip72[2];
+	main_a7ddrphy_dfi_p1_rddata[23] <= main_a7ddrphy_bitslip72[3];
+	main_a7ddrphy_dfi_p1_rddata[8] <= main_a7ddrphy_bitslip82[2];
+	main_a7ddrphy_dfi_p1_rddata[24] <= main_a7ddrphy_bitslip82[3];
+	main_a7ddrphy_dfi_p1_rddata[9] <= main_a7ddrphy_bitslip92[2];
+	main_a7ddrphy_dfi_p1_rddata[25] <= main_a7ddrphy_bitslip92[3];
+	main_a7ddrphy_dfi_p1_rddata[10] <= main_a7ddrphy_bitslip102[2];
+	main_a7ddrphy_dfi_p1_rddata[26] <= main_a7ddrphy_bitslip102[3];
+	main_a7ddrphy_dfi_p1_rddata[11] <= main_a7ddrphy_bitslip112[2];
+	main_a7ddrphy_dfi_p1_rddata[27] <= main_a7ddrphy_bitslip112[3];
+	main_a7ddrphy_dfi_p1_rddata[12] <= main_a7ddrphy_bitslip122[2];
+	main_a7ddrphy_dfi_p1_rddata[28] <= main_a7ddrphy_bitslip122[3];
+	main_a7ddrphy_dfi_p1_rddata[13] <= main_a7ddrphy_bitslip132[2];
+	main_a7ddrphy_dfi_p1_rddata[29] <= main_a7ddrphy_bitslip132[3];
+	main_a7ddrphy_dfi_p1_rddata[14] <= main_a7ddrphy_bitslip142[2];
+	main_a7ddrphy_dfi_p1_rddata[30] <= main_a7ddrphy_bitslip142[3];
+	main_a7ddrphy_dfi_p1_rddata[15] <= main_a7ddrphy_bitslip152[2];
+	main_a7ddrphy_dfi_p1_rddata[31] <= main_a7ddrphy_bitslip152[3];
+// synthesis translate_off
+	dummy_d_1 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_2;
+// synthesis translate_on
+always @(*) begin
+	main_a7ddrphy_dfi_p2_rddata <= 32'd0;
+	main_a7ddrphy_dfi_p2_rddata[0] <= main_a7ddrphy_bitslip04[4];
+	main_a7ddrphy_dfi_p2_rddata[16] <= main_a7ddrphy_bitslip04[5];
+	main_a7ddrphy_dfi_p2_rddata[1] <= main_a7ddrphy_bitslip14[4];
+	main_a7ddrphy_dfi_p2_rddata[17] <= main_a7ddrphy_bitslip14[5];
+	main_a7ddrphy_dfi_p2_rddata[2] <= main_a7ddrphy_bitslip22[4];
+	main_a7ddrphy_dfi_p2_rddata[18] <= main_a7ddrphy_bitslip22[5];
+	main_a7ddrphy_dfi_p2_rddata[3] <= main_a7ddrphy_bitslip32[4];
+	main_a7ddrphy_dfi_p2_rddata[19] <= main_a7ddrphy_bitslip32[5];
+	main_a7ddrphy_dfi_p2_rddata[4] <= main_a7ddrphy_bitslip42[4];
+	main_a7ddrphy_dfi_p2_rddata[20] <= main_a7ddrphy_bitslip42[5];
+	main_a7ddrphy_dfi_p2_rddata[5] <= main_a7ddrphy_bitslip52[4];
+	main_a7ddrphy_dfi_p2_rddata[21] <= main_a7ddrphy_bitslip52[5];
+	main_a7ddrphy_dfi_p2_rddata[6] <= main_a7ddrphy_bitslip62[4];
+	main_a7ddrphy_dfi_p2_rddata[22] <= main_a7ddrphy_bitslip62[5];
+	main_a7ddrphy_dfi_p2_rddata[7] <= main_a7ddrphy_bitslip72[4];
+	main_a7ddrphy_dfi_p2_rddata[23] <= main_a7ddrphy_bitslip72[5];
+	main_a7ddrphy_dfi_p2_rddata[8] <= main_a7ddrphy_bitslip82[4];
+	main_a7ddrphy_dfi_p2_rddata[24] <= main_a7ddrphy_bitslip82[5];
+	main_a7ddrphy_dfi_p2_rddata[9] <= main_a7ddrphy_bitslip92[4];
+	main_a7ddrphy_dfi_p2_rddata[25] <= main_a7ddrphy_bitslip92[5];
+	main_a7ddrphy_dfi_p2_rddata[10] <= main_a7ddrphy_bitslip102[4];
+	main_a7ddrphy_dfi_p2_rddata[26] <= main_a7ddrphy_bitslip102[5];
+	main_a7ddrphy_dfi_p2_rddata[11] <= main_a7ddrphy_bitslip112[4];
+	main_a7ddrphy_dfi_p2_rddata[27] <= main_a7ddrphy_bitslip112[5];
+	main_a7ddrphy_dfi_p2_rddata[12] <= main_a7ddrphy_bitslip122[4];
+	main_a7ddrphy_dfi_p2_rddata[28] <= main_a7ddrphy_bitslip122[5];
+	main_a7ddrphy_dfi_p2_rddata[13] <= main_a7ddrphy_bitslip132[4];
+	main_a7ddrphy_dfi_p2_rddata[29] <= main_a7ddrphy_bitslip132[5];
+	main_a7ddrphy_dfi_p2_rddata[14] <= main_a7ddrphy_bitslip142[4];
+	main_a7ddrphy_dfi_p2_rddata[30] <= main_a7ddrphy_bitslip142[5];
+	main_a7ddrphy_dfi_p2_rddata[15] <= main_a7ddrphy_bitslip152[4];
+	main_a7ddrphy_dfi_p2_rddata[31] <= main_a7ddrphy_bitslip152[5];
+// synthesis translate_off
+	dummy_d_2 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_3;
+// synthesis translate_on
+always @(*) begin
+	main_a7ddrphy_dfi_p3_rddata <= 32'd0;
+	main_a7ddrphy_dfi_p3_rddata[0] <= main_a7ddrphy_bitslip04[6];
+	main_a7ddrphy_dfi_p3_rddata[16] <= main_a7ddrphy_bitslip04[7];
+	main_a7ddrphy_dfi_p3_rddata[1] <= main_a7ddrphy_bitslip14[6];
+	main_a7ddrphy_dfi_p3_rddata[17] <= main_a7ddrphy_bitslip14[7];
+	main_a7ddrphy_dfi_p3_rddata[2] <= main_a7ddrphy_bitslip22[6];
+	main_a7ddrphy_dfi_p3_rddata[18] <= main_a7ddrphy_bitslip22[7];
+	main_a7ddrphy_dfi_p3_rddata[3] <= main_a7ddrphy_bitslip32[6];
+	main_a7ddrphy_dfi_p3_rddata[19] <= main_a7ddrphy_bitslip32[7];
+	main_a7ddrphy_dfi_p3_rddata[4] <= main_a7ddrphy_bitslip42[6];
+	main_a7ddrphy_dfi_p3_rddata[20] <= main_a7ddrphy_bitslip42[7];
+	main_a7ddrphy_dfi_p3_rddata[5] <= main_a7ddrphy_bitslip52[6];
+	main_a7ddrphy_dfi_p3_rddata[21] <= main_a7ddrphy_bitslip52[7];
+	main_a7ddrphy_dfi_p3_rddata[6] <= main_a7ddrphy_bitslip62[6];
+	main_a7ddrphy_dfi_p3_rddata[22] <= main_a7ddrphy_bitslip62[7];
+	main_a7ddrphy_dfi_p3_rddata[7] <= main_a7ddrphy_bitslip72[6];
+	main_a7ddrphy_dfi_p3_rddata[23] <= main_a7ddrphy_bitslip72[7];
+	main_a7ddrphy_dfi_p3_rddata[8] <= main_a7ddrphy_bitslip82[6];
+	main_a7ddrphy_dfi_p3_rddata[24] <= main_a7ddrphy_bitslip82[7];
+	main_a7ddrphy_dfi_p3_rddata[9] <= main_a7ddrphy_bitslip92[6];
+	main_a7ddrphy_dfi_p3_rddata[25] <= main_a7ddrphy_bitslip92[7];
+	main_a7ddrphy_dfi_p3_rddata[10] <= main_a7ddrphy_bitslip102[6];
+	main_a7ddrphy_dfi_p3_rddata[26] <= main_a7ddrphy_bitslip102[7];
+	main_a7ddrphy_dfi_p3_rddata[11] <= main_a7ddrphy_bitslip112[6];
+	main_a7ddrphy_dfi_p3_rddata[27] <= main_a7ddrphy_bitslip112[7];
+	main_a7ddrphy_dfi_p3_rddata[12] <= main_a7ddrphy_bitslip122[6];
+	main_a7ddrphy_dfi_p3_rddata[28] <= main_a7ddrphy_bitslip122[7];
+	main_a7ddrphy_dfi_p3_rddata[13] <= main_a7ddrphy_bitslip132[6];
+	main_a7ddrphy_dfi_p3_rddata[29] <= main_a7ddrphy_bitslip132[7];
+	main_a7ddrphy_dfi_p3_rddata[14] <= main_a7ddrphy_bitslip142[6];
+	main_a7ddrphy_dfi_p3_rddata[30] <= main_a7ddrphy_bitslip142[7];
+	main_a7ddrphy_dfi_p3_rddata[15] <= main_a7ddrphy_bitslip152[6];
+	main_a7ddrphy_dfi_p3_rddata[31] <= main_a7ddrphy_bitslip152[7];
+// synthesis translate_off
+	dummy_d_3 = dummy_s;
+// synthesis translate_on
+end
+assign main_a7ddrphy_dfi_p0_rddata_valid = (main_a7ddrphy_rddata_en_tappeddelayline7 | main_a7ddrphy_wlevel_en_storage);
+assign main_a7ddrphy_dfi_p1_rddata_valid = (main_a7ddrphy_rddata_en_tappeddelayline7 | main_a7ddrphy_wlevel_en_storage);
+assign main_a7ddrphy_dfi_p2_rddata_valid = (main_a7ddrphy_rddata_en_tappeddelayline7 | main_a7ddrphy_wlevel_en_storage);
+assign main_a7ddrphy_dfi_p3_rddata_valid = (main_a7ddrphy_rddata_en_tappeddelayline7 | main_a7ddrphy_wlevel_en_storage);
+assign main_a7ddrphy_dq_oe = main_a7ddrphy_wrdata_en_tappeddelayline1;
+
+// synthesis translate_off
+reg dummy_d_4;
+// synthesis translate_on
+always @(*) begin
+	main_a7ddrphy_dqs_oe <= 1'd0;
+	if (main_a7ddrphy_wlevel_en_storage) begin
+		main_a7ddrphy_dqs_oe <= 1'd1;
+	end else begin
+		main_a7ddrphy_dqs_oe <= main_a7ddrphy_dq_oe;
+	end
+// synthesis translate_off
+	dummy_d_4 = dummy_s;
+// synthesis translate_on
+end
+assign main_a7ddrphy_dqs_preamble = (main_a7ddrphy_wrdata_en_tappeddelayline0 & (~main_a7ddrphy_wrdata_en_tappeddelayline1));
+assign main_a7ddrphy_dqs_postamble = (main_a7ddrphy_wrdata_en_tappeddelayline2 & (~main_a7ddrphy_wrdata_en_tappeddelayline1));
+
+// synthesis translate_off
+reg dummy_d_5;
+// synthesis translate_on
+always @(*) begin
+	main_a7ddrphy_dqspattern_o0 <= 8'd0;
+	main_a7ddrphy_dqspattern_o0 <= 7'd85;
+	if (main_a7ddrphy_dqspattern0) begin
+		main_a7ddrphy_dqspattern_o0 <= 5'd21;
+	end
+	if (main_a7ddrphy_dqspattern1) begin
+		main_a7ddrphy_dqspattern_o0 <= 7'd84;
+	end
+	if (main_a7ddrphy_wlevel_en_storage) begin
+		main_a7ddrphy_dqspattern_o0 <= 1'd0;
+		if (main_a7ddrphy_wlevel_strobe_re) begin
+			main_a7ddrphy_dqspattern_o0 <= 1'd1;
+		end
+	end
+// synthesis translate_off
+	dummy_d_5 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_6;
+// synthesis translate_on
+always @(*) begin
+	main_a7ddrphy_bitslip00 <= 8'd0;
+	case (main_a7ddrphy_bitslip0_value0)
+		1'd0: begin
+			main_a7ddrphy_bitslip00 <= main_a7ddrphy_bitslip0_r0[8:1];
+		end
+		1'd1: begin
+			main_a7ddrphy_bitslip00 <= main_a7ddrphy_bitslip0_r0[9:2];
+		end
+		2'd2: begin
+			main_a7ddrphy_bitslip00 <= main_a7ddrphy_bitslip0_r0[10:3];
+		end
+		2'd3: begin
+			main_a7ddrphy_bitslip00 <= main_a7ddrphy_bitslip0_r0[11:4];
+		end
+		3'd4: begin
+			main_a7ddrphy_bitslip00 <= main_a7ddrphy_bitslip0_r0[12:5];
+		end
+		3'd5: begin
+			main_a7ddrphy_bitslip00 <= main_a7ddrphy_bitslip0_r0[13:6];
+		end
+		3'd6: begin
+			main_a7ddrphy_bitslip00 <= main_a7ddrphy_bitslip0_r0[14:7];
+		end
+		3'd7: begin
+			main_a7ddrphy_bitslip00 <= main_a7ddrphy_bitslip0_r0[15:8];
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_6 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_7;
+// synthesis translate_on
+always @(*) begin
+	main_a7ddrphy_bitslip10 <= 8'd0;
+	case (main_a7ddrphy_bitslip1_value0)
+		1'd0: begin
+			main_a7ddrphy_bitslip10 <= main_a7ddrphy_bitslip1_r0[8:1];
+		end
+		1'd1: begin
+			main_a7ddrphy_bitslip10 <= main_a7ddrphy_bitslip1_r0[9:2];
+		end
+		2'd2: begin
+			main_a7ddrphy_bitslip10 <= main_a7ddrphy_bitslip1_r0[10:3];
+		end
+		2'd3: begin
+			main_a7ddrphy_bitslip10 <= main_a7ddrphy_bitslip1_r0[11:4];
+		end
+		3'd4: begin
+			main_a7ddrphy_bitslip10 <= main_a7ddrphy_bitslip1_r0[12:5];
+		end
+		3'd5: begin
+			main_a7ddrphy_bitslip10 <= main_a7ddrphy_bitslip1_r0[13:6];
+		end
+		3'd6: begin
+			main_a7ddrphy_bitslip10 <= main_a7ddrphy_bitslip1_r0[14:7];
+		end
+		3'd7: begin
+			main_a7ddrphy_bitslip10 <= main_a7ddrphy_bitslip1_r0[15:8];
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_7 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_8;
+// synthesis translate_on
+always @(*) begin
+	main_a7ddrphy_bitslip01 <= 8'd0;
+	case (main_a7ddrphy_bitslip0_value1)
+		1'd0: begin
+			main_a7ddrphy_bitslip01 <= main_a7ddrphy_bitslip0_r1[8:1];
+		end
+		1'd1: begin
+			main_a7ddrphy_bitslip01 <= main_a7ddrphy_bitslip0_r1[9:2];
+		end
+		2'd2: begin
+			main_a7ddrphy_bitslip01 <= main_a7ddrphy_bitslip0_r1[10:3];
+		end
+		2'd3: begin
+			main_a7ddrphy_bitslip01 <= main_a7ddrphy_bitslip0_r1[11:4];
+		end
+		3'd4: begin
+			main_a7ddrphy_bitslip01 <= main_a7ddrphy_bitslip0_r1[12:5];
+		end
+		3'd5: begin
+			main_a7ddrphy_bitslip01 <= main_a7ddrphy_bitslip0_r1[13:6];
+		end
+		3'd6: begin
+			main_a7ddrphy_bitslip01 <= main_a7ddrphy_bitslip0_r1[14:7];
+		end
+		3'd7: begin
+			main_a7ddrphy_bitslip01 <= main_a7ddrphy_bitslip0_r1[15:8];
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_8 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_9;
+// synthesis translate_on
+always @(*) begin
+	main_a7ddrphy_bitslip11 <= 8'd0;
+	case (main_a7ddrphy_bitslip1_value1)
+		1'd0: begin
+			main_a7ddrphy_bitslip11 <= main_a7ddrphy_bitslip1_r1[8:1];
+		end
+		1'd1: begin
+			main_a7ddrphy_bitslip11 <= main_a7ddrphy_bitslip1_r1[9:2];
+		end
+		2'd2: begin
+			main_a7ddrphy_bitslip11 <= main_a7ddrphy_bitslip1_r1[10:3];
+		end
+		2'd3: begin
+			main_a7ddrphy_bitslip11 <= main_a7ddrphy_bitslip1_r1[11:4];
+		end
+		3'd4: begin
+			main_a7ddrphy_bitslip11 <= main_a7ddrphy_bitslip1_r1[12:5];
+		end
+		3'd5: begin
+			main_a7ddrphy_bitslip11 <= main_a7ddrphy_bitslip1_r1[13:6];
+		end
+		3'd6: begin
+			main_a7ddrphy_bitslip11 <= main_a7ddrphy_bitslip1_r1[14:7];
+		end
+		3'd7: begin
+			main_a7ddrphy_bitslip11 <= main_a7ddrphy_bitslip1_r1[15:8];
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_9 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_10;
+// synthesis translate_on
+always @(*) begin
+	main_a7ddrphy_bitslip02 <= 8'd0;
+	case (main_a7ddrphy_bitslip0_value2)
+		1'd0: begin
+			main_a7ddrphy_bitslip02 <= main_a7ddrphy_bitslip0_r2[8:1];
+		end
+		1'd1: begin
+			main_a7ddrphy_bitslip02 <= main_a7ddrphy_bitslip0_r2[9:2];
+		end
+		2'd2: begin
+			main_a7ddrphy_bitslip02 <= main_a7ddrphy_bitslip0_r2[10:3];
+		end
+		2'd3: begin
+			main_a7ddrphy_bitslip02 <= main_a7ddrphy_bitslip0_r2[11:4];
+		end
+		3'd4: begin
+			main_a7ddrphy_bitslip02 <= main_a7ddrphy_bitslip0_r2[12:5];
+		end
+		3'd5: begin
+			main_a7ddrphy_bitslip02 <= main_a7ddrphy_bitslip0_r2[13:6];
+		end
+		3'd6: begin
+			main_a7ddrphy_bitslip02 <= main_a7ddrphy_bitslip0_r2[14:7];
+		end
+		3'd7: begin
+			main_a7ddrphy_bitslip02 <= main_a7ddrphy_bitslip0_r2[15:8];
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_10 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_11;
+// synthesis translate_on
+always @(*) begin
+	main_a7ddrphy_bitslip04 <= 8'd0;
+	case (main_a7ddrphy_bitslip0_value3)
+		1'd0: begin
+			main_a7ddrphy_bitslip04 <= main_a7ddrphy_bitslip0_r3[8:1];
+		end
+		1'd1: begin
+			main_a7ddrphy_bitslip04 <= main_a7ddrphy_bitslip0_r3[9:2];
+		end
+		2'd2: begin
+			main_a7ddrphy_bitslip04 <= main_a7ddrphy_bitslip0_r3[10:3];
+		end
+		2'd3: begin
+			main_a7ddrphy_bitslip04 <= main_a7ddrphy_bitslip0_r3[11:4];
+		end
+		3'd4: begin
+			main_a7ddrphy_bitslip04 <= main_a7ddrphy_bitslip0_r3[12:5];
+		end
+		3'd5: begin
+			main_a7ddrphy_bitslip04 <= main_a7ddrphy_bitslip0_r3[13:6];
+		end
+		3'd6: begin
+			main_a7ddrphy_bitslip04 <= main_a7ddrphy_bitslip0_r3[14:7];
+		end
+		3'd7: begin
+			main_a7ddrphy_bitslip04 <= main_a7ddrphy_bitslip0_r3[15:8];
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_11 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_12;
+// synthesis translate_on
+always @(*) begin
+	main_a7ddrphy_bitslip12 <= 8'd0;
+	case (main_a7ddrphy_bitslip1_value2)
+		1'd0: begin
+			main_a7ddrphy_bitslip12 <= main_a7ddrphy_bitslip1_r2[8:1];
+		end
+		1'd1: begin
+			main_a7ddrphy_bitslip12 <= main_a7ddrphy_bitslip1_r2[9:2];
+		end
+		2'd2: begin
+			main_a7ddrphy_bitslip12 <= main_a7ddrphy_bitslip1_r2[10:3];
+		end
+		2'd3: begin
+			main_a7ddrphy_bitslip12 <= main_a7ddrphy_bitslip1_r2[11:4];
+		end
+		3'd4: begin
+			main_a7ddrphy_bitslip12 <= main_a7ddrphy_bitslip1_r2[12:5];
+		end
+		3'd5: begin
+			main_a7ddrphy_bitslip12 <= main_a7ddrphy_bitslip1_r2[13:6];
+		end
+		3'd6: begin
+			main_a7ddrphy_bitslip12 <= main_a7ddrphy_bitslip1_r2[14:7];
+		end
+		3'd7: begin
+			main_a7ddrphy_bitslip12 <= main_a7ddrphy_bitslip1_r2[15:8];
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_12 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_13;
+// synthesis translate_on
+always @(*) begin
+	main_a7ddrphy_bitslip14 <= 8'd0;
+	case (main_a7ddrphy_bitslip1_value3)
+		1'd0: begin
+			main_a7ddrphy_bitslip14 <= main_a7ddrphy_bitslip1_r3[8:1];
+		end
+		1'd1: begin
+			main_a7ddrphy_bitslip14 <= main_a7ddrphy_bitslip1_r3[9:2];
+		end
+		2'd2: begin
+			main_a7ddrphy_bitslip14 <= main_a7ddrphy_bitslip1_r3[10:3];
+		end
+		2'd3: begin
+			main_a7ddrphy_bitslip14 <= main_a7ddrphy_bitslip1_r3[11:4];
+		end
+		3'd4: begin
+			main_a7ddrphy_bitslip14 <= main_a7ddrphy_bitslip1_r3[12:5];
+		end
+		3'd5: begin
+			main_a7ddrphy_bitslip14 <= main_a7ddrphy_bitslip1_r3[13:6];
+		end
+		3'd6: begin
+			main_a7ddrphy_bitslip14 <= main_a7ddrphy_bitslip1_r3[14:7];
+		end
+		3'd7: begin
+			main_a7ddrphy_bitslip14 <= main_a7ddrphy_bitslip1_r3[15:8];
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_13 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_14;
+// synthesis translate_on
+always @(*) begin
+	main_a7ddrphy_bitslip20 <= 8'd0;
+	case (main_a7ddrphy_bitslip2_value0)
+		1'd0: begin
+			main_a7ddrphy_bitslip20 <= main_a7ddrphy_bitslip2_r0[8:1];
+		end
+		1'd1: begin
+			main_a7ddrphy_bitslip20 <= main_a7ddrphy_bitslip2_r0[9:2];
+		end
+		2'd2: begin
+			main_a7ddrphy_bitslip20 <= main_a7ddrphy_bitslip2_r0[10:3];
+		end
+		2'd3: begin
+			main_a7ddrphy_bitslip20 <= main_a7ddrphy_bitslip2_r0[11:4];
+		end
+		3'd4: begin
+			main_a7ddrphy_bitslip20 <= main_a7ddrphy_bitslip2_r0[12:5];
+		end
+		3'd5: begin
+			main_a7ddrphy_bitslip20 <= main_a7ddrphy_bitslip2_r0[13:6];
+		end
+		3'd6: begin
+			main_a7ddrphy_bitslip20 <= main_a7ddrphy_bitslip2_r0[14:7];
+		end
+		3'd7: begin
+			main_a7ddrphy_bitslip20 <= main_a7ddrphy_bitslip2_r0[15:8];
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_14 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_15;
+// synthesis translate_on
+always @(*) begin
+	main_a7ddrphy_bitslip22 <= 8'd0;
+	case (main_a7ddrphy_bitslip2_value1)
+		1'd0: begin
+			main_a7ddrphy_bitslip22 <= main_a7ddrphy_bitslip2_r1[8:1];
+		end
+		1'd1: begin
+			main_a7ddrphy_bitslip22 <= main_a7ddrphy_bitslip2_r1[9:2];
+		end
+		2'd2: begin
+			main_a7ddrphy_bitslip22 <= main_a7ddrphy_bitslip2_r1[10:3];
+		end
+		2'd3: begin
+			main_a7ddrphy_bitslip22 <= main_a7ddrphy_bitslip2_r1[11:4];
+		end
+		3'd4: begin
+			main_a7ddrphy_bitslip22 <= main_a7ddrphy_bitslip2_r1[12:5];
+		end
+		3'd5: begin
+			main_a7ddrphy_bitslip22 <= main_a7ddrphy_bitslip2_r1[13:6];
+		end
+		3'd6: begin
+			main_a7ddrphy_bitslip22 <= main_a7ddrphy_bitslip2_r1[14:7];
+		end
+		3'd7: begin
+			main_a7ddrphy_bitslip22 <= main_a7ddrphy_bitslip2_r1[15:8];
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_15 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_16;
+// synthesis translate_on
+always @(*) begin
+	main_a7ddrphy_bitslip30 <= 8'd0;
+	case (main_a7ddrphy_bitslip3_value0)
+		1'd0: begin
+			main_a7ddrphy_bitslip30 <= main_a7ddrphy_bitslip3_r0[8:1];
+		end
+		1'd1: begin
+			main_a7ddrphy_bitslip30 <= main_a7ddrphy_bitslip3_r0[9:2];
+		end
+		2'd2: begin
+			main_a7ddrphy_bitslip30 <= main_a7ddrphy_bitslip3_r0[10:3];
+		end
+		2'd3: begin
+			main_a7ddrphy_bitslip30 <= main_a7ddrphy_bitslip3_r0[11:4];
+		end
+		3'd4: begin
+			main_a7ddrphy_bitslip30 <= main_a7ddrphy_bitslip3_r0[12:5];
+		end
+		3'd5: begin
+			main_a7ddrphy_bitslip30 <= main_a7ddrphy_bitslip3_r0[13:6];
+		end
+		3'd6: begin
+			main_a7ddrphy_bitslip30 <= main_a7ddrphy_bitslip3_r0[14:7];
+		end
+		3'd7: begin
+			main_a7ddrphy_bitslip30 <= main_a7ddrphy_bitslip3_r0[15:8];
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_16 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_17;
+// synthesis translate_on
+always @(*) begin
+	main_a7ddrphy_bitslip32 <= 8'd0;
+	case (main_a7ddrphy_bitslip3_value1)
+		1'd0: begin
+			main_a7ddrphy_bitslip32 <= main_a7ddrphy_bitslip3_r1[8:1];
+		end
+		1'd1: begin
+			main_a7ddrphy_bitslip32 <= main_a7ddrphy_bitslip3_r1[9:2];
+		end
+		2'd2: begin
+			main_a7ddrphy_bitslip32 <= main_a7ddrphy_bitslip3_r1[10:3];
+		end
+		2'd3: begin
+			main_a7ddrphy_bitslip32 <= main_a7ddrphy_bitslip3_r1[11:4];
+		end
+		3'd4: begin
+			main_a7ddrphy_bitslip32 <= main_a7ddrphy_bitslip3_r1[12:5];
+		end
+		3'd5: begin
+			main_a7ddrphy_bitslip32 <= main_a7ddrphy_bitslip3_r1[13:6];
+		end
+		3'd6: begin
+			main_a7ddrphy_bitslip32 <= main_a7ddrphy_bitslip3_r1[14:7];
+		end
+		3'd7: begin
+			main_a7ddrphy_bitslip32 <= main_a7ddrphy_bitslip3_r1[15:8];
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_17 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_18;
+// synthesis translate_on
+always @(*) begin
+	main_a7ddrphy_bitslip40 <= 8'd0;
+	case (main_a7ddrphy_bitslip4_value0)
+		1'd0: begin
+			main_a7ddrphy_bitslip40 <= main_a7ddrphy_bitslip4_r0[8:1];
+		end
+		1'd1: begin
+			main_a7ddrphy_bitslip40 <= main_a7ddrphy_bitslip4_r0[9:2];
+		end
+		2'd2: begin
+			main_a7ddrphy_bitslip40 <= main_a7ddrphy_bitslip4_r0[10:3];
+		end
+		2'd3: begin
+			main_a7ddrphy_bitslip40 <= main_a7ddrphy_bitslip4_r0[11:4];
+		end
+		3'd4: begin
+			main_a7ddrphy_bitslip40 <= main_a7ddrphy_bitslip4_r0[12:5];
+		end
+		3'd5: begin
+			main_a7ddrphy_bitslip40 <= main_a7ddrphy_bitslip4_r0[13:6];
+		end
+		3'd6: begin
+			main_a7ddrphy_bitslip40 <= main_a7ddrphy_bitslip4_r0[14:7];
+		end
+		3'd7: begin
+			main_a7ddrphy_bitslip40 <= main_a7ddrphy_bitslip4_r0[15:8];
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_18 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_19;
+// synthesis translate_on
+always @(*) begin
+	main_a7ddrphy_bitslip42 <= 8'd0;
+	case (main_a7ddrphy_bitslip4_value1)
+		1'd0: begin
+			main_a7ddrphy_bitslip42 <= main_a7ddrphy_bitslip4_r1[8:1];
+		end
+		1'd1: begin
+			main_a7ddrphy_bitslip42 <= main_a7ddrphy_bitslip4_r1[9:2];
+		end
+		2'd2: begin
+			main_a7ddrphy_bitslip42 <= main_a7ddrphy_bitslip4_r1[10:3];
+		end
+		2'd3: begin
+			main_a7ddrphy_bitslip42 <= main_a7ddrphy_bitslip4_r1[11:4];
+		end
+		3'd4: begin
+			main_a7ddrphy_bitslip42 <= main_a7ddrphy_bitslip4_r1[12:5];
+		end
+		3'd5: begin
+			main_a7ddrphy_bitslip42 <= main_a7ddrphy_bitslip4_r1[13:6];
+		end
+		3'd6: begin
+			main_a7ddrphy_bitslip42 <= main_a7ddrphy_bitslip4_r1[14:7];
+		end
+		3'd7: begin
+			main_a7ddrphy_bitslip42 <= main_a7ddrphy_bitslip4_r1[15:8];
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_19 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_20;
+// synthesis translate_on
+always @(*) begin
+	main_a7ddrphy_bitslip50 <= 8'd0;
+	case (main_a7ddrphy_bitslip5_value0)
+		1'd0: begin
+			main_a7ddrphy_bitslip50 <= main_a7ddrphy_bitslip5_r0[8:1];
+		end
+		1'd1: begin
+			main_a7ddrphy_bitslip50 <= main_a7ddrphy_bitslip5_r0[9:2];
+		end
+		2'd2: begin
+			main_a7ddrphy_bitslip50 <= main_a7ddrphy_bitslip5_r0[10:3];
+		end
+		2'd3: begin
+			main_a7ddrphy_bitslip50 <= main_a7ddrphy_bitslip5_r0[11:4];
+		end
+		3'd4: begin
+			main_a7ddrphy_bitslip50 <= main_a7ddrphy_bitslip5_r0[12:5];
+		end
+		3'd5: begin
+			main_a7ddrphy_bitslip50 <= main_a7ddrphy_bitslip5_r0[13:6];
+		end
+		3'd6: begin
+			main_a7ddrphy_bitslip50 <= main_a7ddrphy_bitslip5_r0[14:7];
+		end
+		3'd7: begin
+			main_a7ddrphy_bitslip50 <= main_a7ddrphy_bitslip5_r0[15:8];
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_20 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_21;
+// synthesis translate_on
+always @(*) begin
+	main_a7ddrphy_bitslip52 <= 8'd0;
+	case (main_a7ddrphy_bitslip5_value1)
+		1'd0: begin
+			main_a7ddrphy_bitslip52 <= main_a7ddrphy_bitslip5_r1[8:1];
+		end
+		1'd1: begin
+			main_a7ddrphy_bitslip52 <= main_a7ddrphy_bitslip5_r1[9:2];
+		end
+		2'd2: begin
+			main_a7ddrphy_bitslip52 <= main_a7ddrphy_bitslip5_r1[10:3];
+		end
+		2'd3: begin
+			main_a7ddrphy_bitslip52 <= main_a7ddrphy_bitslip5_r1[11:4];
+		end
+		3'd4: begin
+			main_a7ddrphy_bitslip52 <= main_a7ddrphy_bitslip5_r1[12:5];
+		end
+		3'd5: begin
+			main_a7ddrphy_bitslip52 <= main_a7ddrphy_bitslip5_r1[13:6];
+		end
+		3'd6: begin
+			main_a7ddrphy_bitslip52 <= main_a7ddrphy_bitslip5_r1[14:7];
+		end
+		3'd7: begin
+			main_a7ddrphy_bitslip52 <= main_a7ddrphy_bitslip5_r1[15:8];
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_21 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_22;
+// synthesis translate_on
+always @(*) begin
+	main_a7ddrphy_bitslip60 <= 8'd0;
+	case (main_a7ddrphy_bitslip6_value0)
+		1'd0: begin
+			main_a7ddrphy_bitslip60 <= main_a7ddrphy_bitslip6_r0[8:1];
+		end
+		1'd1: begin
+			main_a7ddrphy_bitslip60 <= main_a7ddrphy_bitslip6_r0[9:2];
+		end
+		2'd2: begin
+			main_a7ddrphy_bitslip60 <= main_a7ddrphy_bitslip6_r0[10:3];
+		end
+		2'd3: begin
+			main_a7ddrphy_bitslip60 <= main_a7ddrphy_bitslip6_r0[11:4];
+		end
+		3'd4: begin
+			main_a7ddrphy_bitslip60 <= main_a7ddrphy_bitslip6_r0[12:5];
+		end
+		3'd5: begin
+			main_a7ddrphy_bitslip60 <= main_a7ddrphy_bitslip6_r0[13:6];
+		end
+		3'd6: begin
+			main_a7ddrphy_bitslip60 <= main_a7ddrphy_bitslip6_r0[14:7];
+		end
+		3'd7: begin
+			main_a7ddrphy_bitslip60 <= main_a7ddrphy_bitslip6_r0[15:8];
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_22 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_23;
+// synthesis translate_on
+always @(*) begin
+	main_a7ddrphy_bitslip62 <= 8'd0;
+	case (main_a7ddrphy_bitslip6_value1)
+		1'd0: begin
+			main_a7ddrphy_bitslip62 <= main_a7ddrphy_bitslip6_r1[8:1];
+		end
+		1'd1: begin
+			main_a7ddrphy_bitslip62 <= main_a7ddrphy_bitslip6_r1[9:2];
+		end
+		2'd2: begin
+			main_a7ddrphy_bitslip62 <= main_a7ddrphy_bitslip6_r1[10:3];
+		end
+		2'd3: begin
+			main_a7ddrphy_bitslip62 <= main_a7ddrphy_bitslip6_r1[11:4];
+		end
+		3'd4: begin
+			main_a7ddrphy_bitslip62 <= main_a7ddrphy_bitslip6_r1[12:5];
+		end
+		3'd5: begin
+			main_a7ddrphy_bitslip62 <= main_a7ddrphy_bitslip6_r1[13:6];
+		end
+		3'd6: begin
+			main_a7ddrphy_bitslip62 <= main_a7ddrphy_bitslip6_r1[14:7];
+		end
+		3'd7: begin
+			main_a7ddrphy_bitslip62 <= main_a7ddrphy_bitslip6_r1[15:8];
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_23 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_24;
+// synthesis translate_on
+always @(*) begin
+	main_a7ddrphy_bitslip70 <= 8'd0;
+	case (main_a7ddrphy_bitslip7_value0)
+		1'd0: begin
+			main_a7ddrphy_bitslip70 <= main_a7ddrphy_bitslip7_r0[8:1];
+		end
+		1'd1: begin
+			main_a7ddrphy_bitslip70 <= main_a7ddrphy_bitslip7_r0[9:2];
+		end
+		2'd2: begin
+			main_a7ddrphy_bitslip70 <= main_a7ddrphy_bitslip7_r0[10:3];
+		end
+		2'd3: begin
+			main_a7ddrphy_bitslip70 <= main_a7ddrphy_bitslip7_r0[11:4];
+		end
+		3'd4: begin
+			main_a7ddrphy_bitslip70 <= main_a7ddrphy_bitslip7_r0[12:5];
+		end
+		3'd5: begin
+			main_a7ddrphy_bitslip70 <= main_a7ddrphy_bitslip7_r0[13:6];
+		end
+		3'd6: begin
+			main_a7ddrphy_bitslip70 <= main_a7ddrphy_bitslip7_r0[14:7];
+		end
+		3'd7: begin
+			main_a7ddrphy_bitslip70 <= main_a7ddrphy_bitslip7_r0[15:8];
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_24 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_25;
+// synthesis translate_on
+always @(*) begin
+	main_a7ddrphy_bitslip72 <= 8'd0;
+	case (main_a7ddrphy_bitslip7_value1)
+		1'd0: begin
+			main_a7ddrphy_bitslip72 <= main_a7ddrphy_bitslip7_r1[8:1];
+		end
+		1'd1: begin
+			main_a7ddrphy_bitslip72 <= main_a7ddrphy_bitslip7_r1[9:2];
+		end
+		2'd2: begin
+			main_a7ddrphy_bitslip72 <= main_a7ddrphy_bitslip7_r1[10:3];
+		end
+		2'd3: begin
+			main_a7ddrphy_bitslip72 <= main_a7ddrphy_bitslip7_r1[11:4];
+		end
+		3'd4: begin
+			main_a7ddrphy_bitslip72 <= main_a7ddrphy_bitslip7_r1[12:5];
+		end
+		3'd5: begin
+			main_a7ddrphy_bitslip72 <= main_a7ddrphy_bitslip7_r1[13:6];
+		end
+		3'd6: begin
+			main_a7ddrphy_bitslip72 <= main_a7ddrphy_bitslip7_r1[14:7];
+		end
+		3'd7: begin
+			main_a7ddrphy_bitslip72 <= main_a7ddrphy_bitslip7_r1[15:8];
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_25 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_26;
+// synthesis translate_on
+always @(*) begin
+	main_a7ddrphy_bitslip80 <= 8'd0;
+	case (main_a7ddrphy_bitslip8_value0)
+		1'd0: begin
+			main_a7ddrphy_bitslip80 <= main_a7ddrphy_bitslip8_r0[8:1];
+		end
+		1'd1: begin
+			main_a7ddrphy_bitslip80 <= main_a7ddrphy_bitslip8_r0[9:2];
+		end
+		2'd2: begin
+			main_a7ddrphy_bitslip80 <= main_a7ddrphy_bitslip8_r0[10:3];
+		end
+		2'd3: begin
+			main_a7ddrphy_bitslip80 <= main_a7ddrphy_bitslip8_r0[11:4];
+		end
+		3'd4: begin
+			main_a7ddrphy_bitslip80 <= main_a7ddrphy_bitslip8_r0[12:5];
+		end
+		3'd5: begin
+			main_a7ddrphy_bitslip80 <= main_a7ddrphy_bitslip8_r0[13:6];
+		end
+		3'd6: begin
+			main_a7ddrphy_bitslip80 <= main_a7ddrphy_bitslip8_r0[14:7];
+		end
+		3'd7: begin
+			main_a7ddrphy_bitslip80 <= main_a7ddrphy_bitslip8_r0[15:8];
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_26 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_27;
+// synthesis translate_on
+always @(*) begin
+	main_a7ddrphy_bitslip82 <= 8'd0;
+	case (main_a7ddrphy_bitslip8_value1)
+		1'd0: begin
+			main_a7ddrphy_bitslip82 <= main_a7ddrphy_bitslip8_r1[8:1];
+		end
+		1'd1: begin
+			main_a7ddrphy_bitslip82 <= main_a7ddrphy_bitslip8_r1[9:2];
+		end
+		2'd2: begin
+			main_a7ddrphy_bitslip82 <= main_a7ddrphy_bitslip8_r1[10:3];
+		end
+		2'd3: begin
+			main_a7ddrphy_bitslip82 <= main_a7ddrphy_bitslip8_r1[11:4];
+		end
+		3'd4: begin
+			main_a7ddrphy_bitslip82 <= main_a7ddrphy_bitslip8_r1[12:5];
+		end
+		3'd5: begin
+			main_a7ddrphy_bitslip82 <= main_a7ddrphy_bitslip8_r1[13:6];
+		end
+		3'd6: begin
+			main_a7ddrphy_bitslip82 <= main_a7ddrphy_bitslip8_r1[14:7];
+		end
+		3'd7: begin
+			main_a7ddrphy_bitslip82 <= main_a7ddrphy_bitslip8_r1[15:8];
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_27 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_28;
+// synthesis translate_on
+always @(*) begin
+	main_a7ddrphy_bitslip90 <= 8'd0;
+	case (main_a7ddrphy_bitslip9_value0)
+		1'd0: begin
+			main_a7ddrphy_bitslip90 <= main_a7ddrphy_bitslip9_r0[8:1];
+		end
+		1'd1: begin
+			main_a7ddrphy_bitslip90 <= main_a7ddrphy_bitslip9_r0[9:2];
+		end
+		2'd2: begin
+			main_a7ddrphy_bitslip90 <= main_a7ddrphy_bitslip9_r0[10:3];
+		end
+		2'd3: begin
+			main_a7ddrphy_bitslip90 <= main_a7ddrphy_bitslip9_r0[11:4];
+		end
+		3'd4: begin
+			main_a7ddrphy_bitslip90 <= main_a7ddrphy_bitslip9_r0[12:5];
+		end
+		3'd5: begin
+			main_a7ddrphy_bitslip90 <= main_a7ddrphy_bitslip9_r0[13:6];
+		end
+		3'd6: begin
+			main_a7ddrphy_bitslip90 <= main_a7ddrphy_bitslip9_r0[14:7];
+		end
+		3'd7: begin
+			main_a7ddrphy_bitslip90 <= main_a7ddrphy_bitslip9_r0[15:8];
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_28 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_29;
+// synthesis translate_on
+always @(*) begin
+	main_a7ddrphy_bitslip92 <= 8'd0;
+	case (main_a7ddrphy_bitslip9_value1)
+		1'd0: begin
+			main_a7ddrphy_bitslip92 <= main_a7ddrphy_bitslip9_r1[8:1];
+		end
+		1'd1: begin
+			main_a7ddrphy_bitslip92 <= main_a7ddrphy_bitslip9_r1[9:2];
+		end
+		2'd2: begin
+			main_a7ddrphy_bitslip92 <= main_a7ddrphy_bitslip9_r1[10:3];
+		end
+		2'd3: begin
+			main_a7ddrphy_bitslip92 <= main_a7ddrphy_bitslip9_r1[11:4];
+		end
+		3'd4: begin
+			main_a7ddrphy_bitslip92 <= main_a7ddrphy_bitslip9_r1[12:5];
+		end
+		3'd5: begin
+			main_a7ddrphy_bitslip92 <= main_a7ddrphy_bitslip9_r1[13:6];
+		end
+		3'd6: begin
+			main_a7ddrphy_bitslip92 <= main_a7ddrphy_bitslip9_r1[14:7];
+		end
+		3'd7: begin
+			main_a7ddrphy_bitslip92 <= main_a7ddrphy_bitslip9_r1[15:8];
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_29 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_30;
+// synthesis translate_on
+always @(*) begin
+	main_a7ddrphy_bitslip100 <= 8'd0;
+	case (main_a7ddrphy_bitslip10_value0)
+		1'd0: begin
+			main_a7ddrphy_bitslip100 <= main_a7ddrphy_bitslip10_r0[8:1];
+		end
+		1'd1: begin
+			main_a7ddrphy_bitslip100 <= main_a7ddrphy_bitslip10_r0[9:2];
+		end
+		2'd2: begin
+			main_a7ddrphy_bitslip100 <= main_a7ddrphy_bitslip10_r0[10:3];
+		end
+		2'd3: begin
+			main_a7ddrphy_bitslip100 <= main_a7ddrphy_bitslip10_r0[11:4];
+		end
+		3'd4: begin
+			main_a7ddrphy_bitslip100 <= main_a7ddrphy_bitslip10_r0[12:5];
+		end
+		3'd5: begin
+			main_a7ddrphy_bitslip100 <= main_a7ddrphy_bitslip10_r0[13:6];
+		end
+		3'd6: begin
+			main_a7ddrphy_bitslip100 <= main_a7ddrphy_bitslip10_r0[14:7];
+		end
+		3'd7: begin
+			main_a7ddrphy_bitslip100 <= main_a7ddrphy_bitslip10_r0[15:8];
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_30 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_31;
+// synthesis translate_on
+always @(*) begin
+	main_a7ddrphy_bitslip102 <= 8'd0;
+	case (main_a7ddrphy_bitslip10_value1)
+		1'd0: begin
+			main_a7ddrphy_bitslip102 <= main_a7ddrphy_bitslip10_r1[8:1];
+		end
+		1'd1: begin
+			main_a7ddrphy_bitslip102 <= main_a7ddrphy_bitslip10_r1[9:2];
+		end
+		2'd2: begin
+			main_a7ddrphy_bitslip102 <= main_a7ddrphy_bitslip10_r1[10:3];
+		end
+		2'd3: begin
+			main_a7ddrphy_bitslip102 <= main_a7ddrphy_bitslip10_r1[11:4];
+		end
+		3'd4: begin
+			main_a7ddrphy_bitslip102 <= main_a7ddrphy_bitslip10_r1[12:5];
+		end
+		3'd5: begin
+			main_a7ddrphy_bitslip102 <= main_a7ddrphy_bitslip10_r1[13:6];
+		end
+		3'd6: begin
+			main_a7ddrphy_bitslip102 <= main_a7ddrphy_bitslip10_r1[14:7];
+		end
+		3'd7: begin
+			main_a7ddrphy_bitslip102 <= main_a7ddrphy_bitslip10_r1[15:8];
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_31 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_32;
+// synthesis translate_on
+always @(*) begin
+	main_a7ddrphy_bitslip110 <= 8'd0;
+	case (main_a7ddrphy_bitslip11_value0)
+		1'd0: begin
+			main_a7ddrphy_bitslip110 <= main_a7ddrphy_bitslip11_r0[8:1];
+		end
+		1'd1: begin
+			main_a7ddrphy_bitslip110 <= main_a7ddrphy_bitslip11_r0[9:2];
+		end
+		2'd2: begin
+			main_a7ddrphy_bitslip110 <= main_a7ddrphy_bitslip11_r0[10:3];
+		end
+		2'd3: begin
+			main_a7ddrphy_bitslip110 <= main_a7ddrphy_bitslip11_r0[11:4];
+		end
+		3'd4: begin
+			main_a7ddrphy_bitslip110 <= main_a7ddrphy_bitslip11_r0[12:5];
+		end
+		3'd5: begin
+			main_a7ddrphy_bitslip110 <= main_a7ddrphy_bitslip11_r0[13:6];
+		end
+		3'd6: begin
+			main_a7ddrphy_bitslip110 <= main_a7ddrphy_bitslip11_r0[14:7];
+		end
+		3'd7: begin
+			main_a7ddrphy_bitslip110 <= main_a7ddrphy_bitslip11_r0[15:8];
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_32 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_33;
+// synthesis translate_on
+always @(*) begin
+	main_a7ddrphy_bitslip112 <= 8'd0;
+	case (main_a7ddrphy_bitslip11_value1)
+		1'd0: begin
+			main_a7ddrphy_bitslip112 <= main_a7ddrphy_bitslip11_r1[8:1];
+		end
+		1'd1: begin
+			main_a7ddrphy_bitslip112 <= main_a7ddrphy_bitslip11_r1[9:2];
+		end
+		2'd2: begin
+			main_a7ddrphy_bitslip112 <= main_a7ddrphy_bitslip11_r1[10:3];
+		end
+		2'd3: begin
+			main_a7ddrphy_bitslip112 <= main_a7ddrphy_bitslip11_r1[11:4];
+		end
+		3'd4: begin
+			main_a7ddrphy_bitslip112 <= main_a7ddrphy_bitslip11_r1[12:5];
+		end
+		3'd5: begin
+			main_a7ddrphy_bitslip112 <= main_a7ddrphy_bitslip11_r1[13:6];
+		end
+		3'd6: begin
+			main_a7ddrphy_bitslip112 <= main_a7ddrphy_bitslip11_r1[14:7];
+		end
+		3'd7: begin
+			main_a7ddrphy_bitslip112 <= main_a7ddrphy_bitslip11_r1[15:8];
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_33 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_34;
+// synthesis translate_on
+always @(*) begin
+	main_a7ddrphy_bitslip120 <= 8'd0;
+	case (main_a7ddrphy_bitslip12_value0)
+		1'd0: begin
+			main_a7ddrphy_bitslip120 <= main_a7ddrphy_bitslip12_r0[8:1];
+		end
+		1'd1: begin
+			main_a7ddrphy_bitslip120 <= main_a7ddrphy_bitslip12_r0[9:2];
+		end
+		2'd2: begin
+			main_a7ddrphy_bitslip120 <= main_a7ddrphy_bitslip12_r0[10:3];
+		end
+		2'd3: begin
+			main_a7ddrphy_bitslip120 <= main_a7ddrphy_bitslip12_r0[11:4];
+		end
+		3'd4: begin
+			main_a7ddrphy_bitslip120 <= main_a7ddrphy_bitslip12_r0[12:5];
+		end
+		3'd5: begin
+			main_a7ddrphy_bitslip120 <= main_a7ddrphy_bitslip12_r0[13:6];
+		end
+		3'd6: begin
+			main_a7ddrphy_bitslip120 <= main_a7ddrphy_bitslip12_r0[14:7];
+		end
+		3'd7: begin
+			main_a7ddrphy_bitslip120 <= main_a7ddrphy_bitslip12_r0[15:8];
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_34 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_35;
+// synthesis translate_on
+always @(*) begin
+	main_a7ddrphy_bitslip122 <= 8'd0;
+	case (main_a7ddrphy_bitslip12_value1)
+		1'd0: begin
+			main_a7ddrphy_bitslip122 <= main_a7ddrphy_bitslip12_r1[8:1];
+		end
+		1'd1: begin
+			main_a7ddrphy_bitslip122 <= main_a7ddrphy_bitslip12_r1[9:2];
+		end
+		2'd2: begin
+			main_a7ddrphy_bitslip122 <= main_a7ddrphy_bitslip12_r1[10:3];
+		end
+		2'd3: begin
+			main_a7ddrphy_bitslip122 <= main_a7ddrphy_bitslip12_r1[11:4];
+		end
+		3'd4: begin
+			main_a7ddrphy_bitslip122 <= main_a7ddrphy_bitslip12_r1[12:5];
+		end
+		3'd5: begin
+			main_a7ddrphy_bitslip122 <= main_a7ddrphy_bitslip12_r1[13:6];
+		end
+		3'd6: begin
+			main_a7ddrphy_bitslip122 <= main_a7ddrphy_bitslip12_r1[14:7];
+		end
+		3'd7: begin
+			main_a7ddrphy_bitslip122 <= main_a7ddrphy_bitslip12_r1[15:8];
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_35 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_36;
+// synthesis translate_on
+always @(*) begin
+	main_a7ddrphy_bitslip130 <= 8'd0;
+	case (main_a7ddrphy_bitslip13_value0)
+		1'd0: begin
+			main_a7ddrphy_bitslip130 <= main_a7ddrphy_bitslip13_r0[8:1];
+		end
+		1'd1: begin
+			main_a7ddrphy_bitslip130 <= main_a7ddrphy_bitslip13_r0[9:2];
+		end
+		2'd2: begin
+			main_a7ddrphy_bitslip130 <= main_a7ddrphy_bitslip13_r0[10:3];
+		end
+		2'd3: begin
+			main_a7ddrphy_bitslip130 <= main_a7ddrphy_bitslip13_r0[11:4];
+		end
+		3'd4: begin
+			main_a7ddrphy_bitslip130 <= main_a7ddrphy_bitslip13_r0[12:5];
+		end
+		3'd5: begin
+			main_a7ddrphy_bitslip130 <= main_a7ddrphy_bitslip13_r0[13:6];
+		end
+		3'd6: begin
+			main_a7ddrphy_bitslip130 <= main_a7ddrphy_bitslip13_r0[14:7];
+		end
+		3'd7: begin
+			main_a7ddrphy_bitslip130 <= main_a7ddrphy_bitslip13_r0[15:8];
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_36 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_37;
+// synthesis translate_on
+always @(*) begin
+	main_a7ddrphy_bitslip132 <= 8'd0;
+	case (main_a7ddrphy_bitslip13_value1)
+		1'd0: begin
+			main_a7ddrphy_bitslip132 <= main_a7ddrphy_bitslip13_r1[8:1];
+		end
+		1'd1: begin
+			main_a7ddrphy_bitslip132 <= main_a7ddrphy_bitslip13_r1[9:2];
+		end
+		2'd2: begin
+			main_a7ddrphy_bitslip132 <= main_a7ddrphy_bitslip13_r1[10:3];
+		end
+		2'd3: begin
+			main_a7ddrphy_bitslip132 <= main_a7ddrphy_bitslip13_r1[11:4];
+		end
+		3'd4: begin
+			main_a7ddrphy_bitslip132 <= main_a7ddrphy_bitslip13_r1[12:5];
+		end
+		3'd5: begin
+			main_a7ddrphy_bitslip132 <= main_a7ddrphy_bitslip13_r1[13:6];
+		end
+		3'd6: begin
+			main_a7ddrphy_bitslip132 <= main_a7ddrphy_bitslip13_r1[14:7];
+		end
+		3'd7: begin
+			main_a7ddrphy_bitslip132 <= main_a7ddrphy_bitslip13_r1[15:8];
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_37 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_38;
+// synthesis translate_on
+always @(*) begin
+	main_a7ddrphy_bitslip140 <= 8'd0;
+	case (main_a7ddrphy_bitslip14_value0)
+		1'd0: begin
+			main_a7ddrphy_bitslip140 <= main_a7ddrphy_bitslip14_r0[8:1];
+		end
+		1'd1: begin
+			main_a7ddrphy_bitslip140 <= main_a7ddrphy_bitslip14_r0[9:2];
+		end
+		2'd2: begin
+			main_a7ddrphy_bitslip140 <= main_a7ddrphy_bitslip14_r0[10:3];
+		end
+		2'd3: begin
+			main_a7ddrphy_bitslip140 <= main_a7ddrphy_bitslip14_r0[11:4];
+		end
+		3'd4: begin
+			main_a7ddrphy_bitslip140 <= main_a7ddrphy_bitslip14_r0[12:5];
+		end
+		3'd5: begin
+			main_a7ddrphy_bitslip140 <= main_a7ddrphy_bitslip14_r0[13:6];
+		end
+		3'd6: begin
+			main_a7ddrphy_bitslip140 <= main_a7ddrphy_bitslip14_r0[14:7];
+		end
+		3'd7: begin
+			main_a7ddrphy_bitslip140 <= main_a7ddrphy_bitslip14_r0[15:8];
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_38 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_39;
+// synthesis translate_on
+always @(*) begin
+	main_a7ddrphy_bitslip142 <= 8'd0;
+	case (main_a7ddrphy_bitslip14_value1)
+		1'd0: begin
+			main_a7ddrphy_bitslip142 <= main_a7ddrphy_bitslip14_r1[8:1];
+		end
+		1'd1: begin
+			main_a7ddrphy_bitslip142 <= main_a7ddrphy_bitslip14_r1[9:2];
+		end
+		2'd2: begin
+			main_a7ddrphy_bitslip142 <= main_a7ddrphy_bitslip14_r1[10:3];
+		end
+		2'd3: begin
+			main_a7ddrphy_bitslip142 <= main_a7ddrphy_bitslip14_r1[11:4];
+		end
+		3'd4: begin
+			main_a7ddrphy_bitslip142 <= main_a7ddrphy_bitslip14_r1[12:5];
+		end
+		3'd5: begin
+			main_a7ddrphy_bitslip142 <= main_a7ddrphy_bitslip14_r1[13:6];
+		end
+		3'd6: begin
+			main_a7ddrphy_bitslip142 <= main_a7ddrphy_bitslip14_r1[14:7];
+		end
+		3'd7: begin
+			main_a7ddrphy_bitslip142 <= main_a7ddrphy_bitslip14_r1[15:8];
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_39 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_40;
+// synthesis translate_on
+always @(*) begin
+	main_a7ddrphy_bitslip150 <= 8'd0;
+	case (main_a7ddrphy_bitslip15_value0)
+		1'd0: begin
+			main_a7ddrphy_bitslip150 <= main_a7ddrphy_bitslip15_r0[8:1];
+		end
+		1'd1: begin
+			main_a7ddrphy_bitslip150 <= main_a7ddrphy_bitslip15_r0[9:2];
+		end
+		2'd2: begin
+			main_a7ddrphy_bitslip150 <= main_a7ddrphy_bitslip15_r0[10:3];
+		end
+		2'd3: begin
+			main_a7ddrphy_bitslip150 <= main_a7ddrphy_bitslip15_r0[11:4];
+		end
+		3'd4: begin
+			main_a7ddrphy_bitslip150 <= main_a7ddrphy_bitslip15_r0[12:5];
+		end
+		3'd5: begin
+			main_a7ddrphy_bitslip150 <= main_a7ddrphy_bitslip15_r0[13:6];
+		end
+		3'd6: begin
+			main_a7ddrphy_bitslip150 <= main_a7ddrphy_bitslip15_r0[14:7];
+		end
+		3'd7: begin
+			main_a7ddrphy_bitslip150 <= main_a7ddrphy_bitslip15_r0[15:8];
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_40 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_41;
+// synthesis translate_on
+always @(*) begin
+	main_a7ddrphy_bitslip152 <= 8'd0;
+	case (main_a7ddrphy_bitslip15_value1)
+		1'd0: begin
+			main_a7ddrphy_bitslip152 <= main_a7ddrphy_bitslip15_r1[8:1];
+		end
+		1'd1: begin
+			main_a7ddrphy_bitslip152 <= main_a7ddrphy_bitslip15_r1[9:2];
+		end
+		2'd2: begin
+			main_a7ddrphy_bitslip152 <= main_a7ddrphy_bitslip15_r1[10:3];
+		end
+		2'd3: begin
+			main_a7ddrphy_bitslip152 <= main_a7ddrphy_bitslip15_r1[11:4];
+		end
+		3'd4: begin
+			main_a7ddrphy_bitslip152 <= main_a7ddrphy_bitslip15_r1[12:5];
+		end
+		3'd5: begin
+			main_a7ddrphy_bitslip152 <= main_a7ddrphy_bitslip15_r1[13:6];
+		end
+		3'd6: begin
+			main_a7ddrphy_bitslip152 <= main_a7ddrphy_bitslip15_r1[14:7];
+		end
+		3'd7: begin
+			main_a7ddrphy_bitslip152 <= main_a7ddrphy_bitslip15_r1[15:8];
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_41 = dummy_s;
+// synthesis translate_on
+end
+assign main_a7ddrphy_dfi_p0_address = main_litedramcore_master_p0_address;
+assign main_a7ddrphy_dfi_p0_bank = main_litedramcore_master_p0_bank;
+assign main_a7ddrphy_dfi_p0_cas_n = main_litedramcore_master_p0_cas_n;
+assign main_a7ddrphy_dfi_p0_cs_n = main_litedramcore_master_p0_cs_n;
+assign main_a7ddrphy_dfi_p0_ras_n = main_litedramcore_master_p0_ras_n;
+assign main_a7ddrphy_dfi_p0_we_n = main_litedramcore_master_p0_we_n;
+assign main_a7ddrphy_dfi_p0_cke = main_litedramcore_master_p0_cke;
+assign main_a7ddrphy_dfi_p0_odt = main_litedramcore_master_p0_odt;
+assign main_a7ddrphy_dfi_p0_reset_n = main_litedramcore_master_p0_reset_n;
+assign main_a7ddrphy_dfi_p0_act_n = main_litedramcore_master_p0_act_n;
+assign main_a7ddrphy_dfi_p0_wrdata = main_litedramcore_master_p0_wrdata;
+assign main_a7ddrphy_dfi_p0_wrdata_en = main_litedramcore_master_p0_wrdata_en;
+assign main_a7ddrphy_dfi_p0_wrdata_mask = main_litedramcore_master_p0_wrdata_mask;
+assign main_a7ddrphy_dfi_p0_rddata_en = main_litedramcore_master_p0_rddata_en;
+assign main_litedramcore_master_p0_rddata = main_a7ddrphy_dfi_p0_rddata;
+assign main_litedramcore_master_p0_rddata_valid = main_a7ddrphy_dfi_p0_rddata_valid;
+assign main_a7ddrphy_dfi_p1_address = main_litedramcore_master_p1_address;
+assign main_a7ddrphy_dfi_p1_bank = main_litedramcore_master_p1_bank;
+assign main_a7ddrphy_dfi_p1_cas_n = main_litedramcore_master_p1_cas_n;
+assign main_a7ddrphy_dfi_p1_cs_n = main_litedramcore_master_p1_cs_n;
+assign main_a7ddrphy_dfi_p1_ras_n = main_litedramcore_master_p1_ras_n;
+assign main_a7ddrphy_dfi_p1_we_n = main_litedramcore_master_p1_we_n;
+assign main_a7ddrphy_dfi_p1_cke = main_litedramcore_master_p1_cke;
+assign main_a7ddrphy_dfi_p1_odt = main_litedramcore_master_p1_odt;
+assign main_a7ddrphy_dfi_p1_reset_n = main_litedramcore_master_p1_reset_n;
+assign main_a7ddrphy_dfi_p1_act_n = main_litedramcore_master_p1_act_n;
+assign main_a7ddrphy_dfi_p1_wrdata = main_litedramcore_master_p1_wrdata;
+assign main_a7ddrphy_dfi_p1_wrdata_en = main_litedramcore_master_p1_wrdata_en;
+assign main_a7ddrphy_dfi_p1_wrdata_mask = main_litedramcore_master_p1_wrdata_mask;
+assign main_a7ddrphy_dfi_p1_rddata_en = main_litedramcore_master_p1_rddata_en;
+assign main_litedramcore_master_p1_rddata = main_a7ddrphy_dfi_p1_rddata;
+assign main_litedramcore_master_p1_rddata_valid = main_a7ddrphy_dfi_p1_rddata_valid;
+assign main_a7ddrphy_dfi_p2_address = main_litedramcore_master_p2_address;
+assign main_a7ddrphy_dfi_p2_bank = main_litedramcore_master_p2_bank;
+assign main_a7ddrphy_dfi_p2_cas_n = main_litedramcore_master_p2_cas_n;
+assign main_a7ddrphy_dfi_p2_cs_n = main_litedramcore_master_p2_cs_n;
+assign main_a7ddrphy_dfi_p2_ras_n = main_litedramcore_master_p2_ras_n;
+assign main_a7ddrphy_dfi_p2_we_n = main_litedramcore_master_p2_we_n;
+assign main_a7ddrphy_dfi_p2_cke = main_litedramcore_master_p2_cke;
+assign main_a7ddrphy_dfi_p2_odt = main_litedramcore_master_p2_odt;
+assign main_a7ddrphy_dfi_p2_reset_n = main_litedramcore_master_p2_reset_n;
+assign main_a7ddrphy_dfi_p2_act_n = main_litedramcore_master_p2_act_n;
+assign main_a7ddrphy_dfi_p2_wrdata = main_litedramcore_master_p2_wrdata;
+assign main_a7ddrphy_dfi_p2_wrdata_en = main_litedramcore_master_p2_wrdata_en;
+assign main_a7ddrphy_dfi_p2_wrdata_mask = main_litedramcore_master_p2_wrdata_mask;
+assign main_a7ddrphy_dfi_p2_rddata_en = main_litedramcore_master_p2_rddata_en;
+assign main_litedramcore_master_p2_rddata = main_a7ddrphy_dfi_p2_rddata;
+assign main_litedramcore_master_p2_rddata_valid = main_a7ddrphy_dfi_p2_rddata_valid;
+assign main_a7ddrphy_dfi_p3_address = main_litedramcore_master_p3_address;
+assign main_a7ddrphy_dfi_p3_bank = main_litedramcore_master_p3_bank;
+assign main_a7ddrphy_dfi_p3_cas_n = main_litedramcore_master_p3_cas_n;
+assign main_a7ddrphy_dfi_p3_cs_n = main_litedramcore_master_p3_cs_n;
+assign main_a7ddrphy_dfi_p3_ras_n = main_litedramcore_master_p3_ras_n;
+assign main_a7ddrphy_dfi_p3_we_n = main_litedramcore_master_p3_we_n;
+assign main_a7ddrphy_dfi_p3_cke = main_litedramcore_master_p3_cke;
+assign main_a7ddrphy_dfi_p3_odt = main_litedramcore_master_p3_odt;
+assign main_a7ddrphy_dfi_p3_reset_n = main_litedramcore_master_p3_reset_n;
+assign main_a7ddrphy_dfi_p3_act_n = main_litedramcore_master_p3_act_n;
+assign main_a7ddrphy_dfi_p3_wrdata = main_litedramcore_master_p3_wrdata;
+assign main_a7ddrphy_dfi_p3_wrdata_en = main_litedramcore_master_p3_wrdata_en;
+assign main_a7ddrphy_dfi_p3_wrdata_mask = main_litedramcore_master_p3_wrdata_mask;
+assign main_a7ddrphy_dfi_p3_rddata_en = main_litedramcore_master_p3_rddata_en;
+assign main_litedramcore_master_p3_rddata = main_a7ddrphy_dfi_p3_rddata;
+assign main_litedramcore_master_p3_rddata_valid = main_a7ddrphy_dfi_p3_rddata_valid;
+assign main_litedramcore_slave_p0_address = main_litedramcore_dfi_p0_address;
+assign main_litedramcore_slave_p0_bank = main_litedramcore_dfi_p0_bank;
+assign main_litedramcore_slave_p0_cas_n = main_litedramcore_dfi_p0_cas_n;
+assign main_litedramcore_slave_p0_cs_n = main_litedramcore_dfi_p0_cs_n;
+assign main_litedramcore_slave_p0_ras_n = main_litedramcore_dfi_p0_ras_n;
+assign main_litedramcore_slave_p0_we_n = main_litedramcore_dfi_p0_we_n;
+assign main_litedramcore_slave_p0_cke = main_litedramcore_dfi_p0_cke;
+assign main_litedramcore_slave_p0_odt = main_litedramcore_dfi_p0_odt;
+assign main_litedramcore_slave_p0_reset_n = main_litedramcore_dfi_p0_reset_n;
+assign main_litedramcore_slave_p0_act_n = main_litedramcore_dfi_p0_act_n;
+assign main_litedramcore_slave_p0_wrdata = main_litedramcore_dfi_p0_wrdata;
+assign main_litedramcore_slave_p0_wrdata_en = main_litedramcore_dfi_p0_wrdata_en;
+assign main_litedramcore_slave_p0_wrdata_mask = main_litedramcore_dfi_p0_wrdata_mask;
+assign main_litedramcore_slave_p0_rddata_en = main_litedramcore_dfi_p0_rddata_en;
+assign main_litedramcore_dfi_p0_rddata = main_litedramcore_slave_p0_rddata;
+assign main_litedramcore_dfi_p0_rddata_valid = main_litedramcore_slave_p0_rddata_valid;
+assign main_litedramcore_slave_p1_address = main_litedramcore_dfi_p1_address;
+assign main_litedramcore_slave_p1_bank = main_litedramcore_dfi_p1_bank;
+assign main_litedramcore_slave_p1_cas_n = main_litedramcore_dfi_p1_cas_n;
+assign main_litedramcore_slave_p1_cs_n = main_litedramcore_dfi_p1_cs_n;
+assign main_litedramcore_slave_p1_ras_n = main_litedramcore_dfi_p1_ras_n;
+assign main_litedramcore_slave_p1_we_n = main_litedramcore_dfi_p1_we_n;
+assign main_litedramcore_slave_p1_cke = main_litedramcore_dfi_p1_cke;
+assign main_litedramcore_slave_p1_odt = main_litedramcore_dfi_p1_odt;
+assign main_litedramcore_slave_p1_reset_n = main_litedramcore_dfi_p1_reset_n;
+assign main_litedramcore_slave_p1_act_n = main_litedramcore_dfi_p1_act_n;
+assign main_litedramcore_slave_p1_wrdata = main_litedramcore_dfi_p1_wrdata;
+assign main_litedramcore_slave_p1_wrdata_en = main_litedramcore_dfi_p1_wrdata_en;
+assign main_litedramcore_slave_p1_wrdata_mask = main_litedramcore_dfi_p1_wrdata_mask;
+assign main_litedramcore_slave_p1_rddata_en = main_litedramcore_dfi_p1_rddata_en;
+assign main_litedramcore_dfi_p1_rddata = main_litedramcore_slave_p1_rddata;
+assign main_litedramcore_dfi_p1_rddata_valid = main_litedramcore_slave_p1_rddata_valid;
+assign main_litedramcore_slave_p2_address = main_litedramcore_dfi_p2_address;
+assign main_litedramcore_slave_p2_bank = main_litedramcore_dfi_p2_bank;
+assign main_litedramcore_slave_p2_cas_n = main_litedramcore_dfi_p2_cas_n;
+assign main_litedramcore_slave_p2_cs_n = main_litedramcore_dfi_p2_cs_n;
+assign main_litedramcore_slave_p2_ras_n = main_litedramcore_dfi_p2_ras_n;
+assign main_litedramcore_slave_p2_we_n = main_litedramcore_dfi_p2_we_n;
+assign main_litedramcore_slave_p2_cke = main_litedramcore_dfi_p2_cke;
+assign main_litedramcore_slave_p2_odt = main_litedramcore_dfi_p2_odt;
+assign main_litedramcore_slave_p2_reset_n = main_litedramcore_dfi_p2_reset_n;
+assign main_litedramcore_slave_p2_act_n = main_litedramcore_dfi_p2_act_n;
+assign main_litedramcore_slave_p2_wrdata = main_litedramcore_dfi_p2_wrdata;
+assign main_litedramcore_slave_p2_wrdata_en = main_litedramcore_dfi_p2_wrdata_en;
+assign main_litedramcore_slave_p2_wrdata_mask = main_litedramcore_dfi_p2_wrdata_mask;
+assign main_litedramcore_slave_p2_rddata_en = main_litedramcore_dfi_p2_rddata_en;
+assign main_litedramcore_dfi_p2_rddata = main_litedramcore_slave_p2_rddata;
+assign main_litedramcore_dfi_p2_rddata_valid = main_litedramcore_slave_p2_rddata_valid;
+assign main_litedramcore_slave_p3_address = main_litedramcore_dfi_p3_address;
+assign main_litedramcore_slave_p3_bank = main_litedramcore_dfi_p3_bank;
+assign main_litedramcore_slave_p3_cas_n = main_litedramcore_dfi_p3_cas_n;
+assign main_litedramcore_slave_p3_cs_n = main_litedramcore_dfi_p3_cs_n;
+assign main_litedramcore_slave_p3_ras_n = main_litedramcore_dfi_p3_ras_n;
+assign main_litedramcore_slave_p3_we_n = main_litedramcore_dfi_p3_we_n;
+assign main_litedramcore_slave_p3_cke = main_litedramcore_dfi_p3_cke;
+assign main_litedramcore_slave_p3_odt = main_litedramcore_dfi_p3_odt;
+assign main_litedramcore_slave_p3_reset_n = main_litedramcore_dfi_p3_reset_n;
+assign main_litedramcore_slave_p3_act_n = main_litedramcore_dfi_p3_act_n;
+assign main_litedramcore_slave_p3_wrdata = main_litedramcore_dfi_p3_wrdata;
+assign main_litedramcore_slave_p3_wrdata_en = main_litedramcore_dfi_p3_wrdata_en;
+assign main_litedramcore_slave_p3_wrdata_mask = main_litedramcore_dfi_p3_wrdata_mask;
+assign main_litedramcore_slave_p3_rddata_en = main_litedramcore_dfi_p3_rddata_en;
+assign main_litedramcore_dfi_p3_rddata = main_litedramcore_slave_p3_rddata;
+assign main_litedramcore_dfi_p3_rddata_valid = main_litedramcore_slave_p3_rddata_valid;
+
+// synthesis translate_off
+reg dummy_d_42;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_master_p0_address <= 14'd0;
+	if (main_litedramcore_sel) begin
+		main_litedramcore_master_p0_address <= main_litedramcore_slave_p0_address;
+	end else begin
+		main_litedramcore_master_p0_address <= main_litedramcore_inti_p0_address;
+	end
+// synthesis translate_off
+	dummy_d_42 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_43;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_master_p0_bank <= 3'd0;
+	if (main_litedramcore_sel) begin
+		main_litedramcore_master_p0_bank <= main_litedramcore_slave_p0_bank;
+	end else begin
+		main_litedramcore_master_p0_bank <= main_litedramcore_inti_p0_bank;
+	end
+// synthesis translate_off
+	dummy_d_43 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_44;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_master_p0_cas_n <= 1'd1;
+	if (main_litedramcore_sel) begin
+		main_litedramcore_master_p0_cas_n <= main_litedramcore_slave_p0_cas_n;
+	end else begin
+		main_litedramcore_master_p0_cas_n <= main_litedramcore_inti_p0_cas_n;
+	end
+// synthesis translate_off
+	dummy_d_44 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_45;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_master_p0_cs_n <= 1'd1;
+	if (main_litedramcore_sel) begin
+		main_litedramcore_master_p0_cs_n <= main_litedramcore_slave_p0_cs_n;
+	end else begin
+		main_litedramcore_master_p0_cs_n <= main_litedramcore_inti_p0_cs_n;
+	end
+// synthesis translate_off
+	dummy_d_45 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_46;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_master_p0_ras_n <= 1'd1;
+	if (main_litedramcore_sel) begin
+		main_litedramcore_master_p0_ras_n <= main_litedramcore_slave_p0_ras_n;
+	end else begin
+		main_litedramcore_master_p0_ras_n <= main_litedramcore_inti_p0_ras_n;
+	end
+// synthesis translate_off
+	dummy_d_46 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_47;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_slave_p0_rddata <= 32'd0;
+	if (main_litedramcore_sel) begin
+		main_litedramcore_slave_p0_rddata <= main_litedramcore_master_p0_rddata;
+	end else begin
+	end
+// synthesis translate_off
+	dummy_d_47 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_48;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_master_p0_we_n <= 1'd1;
+	if (main_litedramcore_sel) begin
+		main_litedramcore_master_p0_we_n <= main_litedramcore_slave_p0_we_n;
+	end else begin
+		main_litedramcore_master_p0_we_n <= main_litedramcore_inti_p0_we_n;
+	end
+// synthesis translate_off
+	dummy_d_48 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_49;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_slave_p0_rddata_valid <= 1'd0;
+	if (main_litedramcore_sel) begin
+		main_litedramcore_slave_p0_rddata_valid <= main_litedramcore_master_p0_rddata_valid;
+	end else begin
+	end
+// synthesis translate_off
+	dummy_d_49 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_50;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_master_p0_cke <= 1'd0;
+	if (main_litedramcore_sel) begin
+		main_litedramcore_master_p0_cke <= main_litedramcore_slave_p0_cke;
+	end else begin
+		main_litedramcore_master_p0_cke <= main_litedramcore_inti_p0_cke;
+	end
+// synthesis translate_off
+	dummy_d_50 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_51;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_master_p0_odt <= 1'd0;
+	if (main_litedramcore_sel) begin
+		main_litedramcore_master_p0_odt <= main_litedramcore_slave_p0_odt;
+	end else begin
+		main_litedramcore_master_p0_odt <= main_litedramcore_inti_p0_odt;
+	end
+// synthesis translate_off
+	dummy_d_51 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_52;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_master_p0_reset_n <= 1'd0;
+	if (main_litedramcore_sel) begin
+		main_litedramcore_master_p0_reset_n <= main_litedramcore_slave_p0_reset_n;
+	end else begin
+		main_litedramcore_master_p0_reset_n <= main_litedramcore_inti_p0_reset_n;
+	end
+// synthesis translate_off
+	dummy_d_52 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_53;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_master_p0_act_n <= 1'd1;
+	if (main_litedramcore_sel) begin
+		main_litedramcore_master_p0_act_n <= main_litedramcore_slave_p0_act_n;
+	end else begin
+		main_litedramcore_master_p0_act_n <= main_litedramcore_inti_p0_act_n;
+	end
+// synthesis translate_off
+	dummy_d_53 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_54;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_master_p0_wrdata <= 32'd0;
+	if (main_litedramcore_sel) begin
+		main_litedramcore_master_p0_wrdata <= main_litedramcore_slave_p0_wrdata;
+	end else begin
+		main_litedramcore_master_p0_wrdata <= main_litedramcore_inti_p0_wrdata;
+	end
+// synthesis translate_off
+	dummy_d_54 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_55;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_inti_p1_rddata <= 32'd0;
+	if (main_litedramcore_sel) begin
+	end else begin
+		main_litedramcore_inti_p1_rddata <= main_litedramcore_master_p1_rddata;
+	end
+// synthesis translate_off
+	dummy_d_55 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_56;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_master_p0_wrdata_en <= 1'd0;
+	if (main_litedramcore_sel) begin
+		main_litedramcore_master_p0_wrdata_en <= main_litedramcore_slave_p0_wrdata_en;
+	end else begin
+		main_litedramcore_master_p0_wrdata_en <= main_litedramcore_inti_p0_wrdata_en;
+	end
+// synthesis translate_off
+	dummy_d_56 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_57;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_inti_p1_rddata_valid <= 1'd0;
+	if (main_litedramcore_sel) begin
+	end else begin
+		main_litedramcore_inti_p1_rddata_valid <= main_litedramcore_master_p1_rddata_valid;
+	end
+// synthesis translate_off
+	dummy_d_57 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_58;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_master_p0_wrdata_mask <= 4'd0;
+	if (main_litedramcore_sel) begin
+		main_litedramcore_master_p0_wrdata_mask <= main_litedramcore_slave_p0_wrdata_mask;
+	end else begin
+		main_litedramcore_master_p0_wrdata_mask <= main_litedramcore_inti_p0_wrdata_mask;
+	end
+// synthesis translate_off
+	dummy_d_58 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_59;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_master_p0_rddata_en <= 1'd0;
+	if (main_litedramcore_sel) begin
+		main_litedramcore_master_p0_rddata_en <= main_litedramcore_slave_p0_rddata_en;
+	end else begin
+		main_litedramcore_master_p0_rddata_en <= main_litedramcore_inti_p0_rddata_en;
+	end
+// synthesis translate_off
+	dummy_d_59 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_60;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_master_p1_address <= 14'd0;
+	if (main_litedramcore_sel) begin
+		main_litedramcore_master_p1_address <= main_litedramcore_slave_p1_address;
+	end else begin
+		main_litedramcore_master_p1_address <= main_litedramcore_inti_p1_address;
+	end
+// synthesis translate_off
+	dummy_d_60 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_61;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_master_p1_bank <= 3'd0;
+	if (main_litedramcore_sel) begin
+		main_litedramcore_master_p1_bank <= main_litedramcore_slave_p1_bank;
+	end else begin
+		main_litedramcore_master_p1_bank <= main_litedramcore_inti_p1_bank;
+	end
+// synthesis translate_off
+	dummy_d_61 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_62;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_master_p1_cas_n <= 1'd1;
+	if (main_litedramcore_sel) begin
+		main_litedramcore_master_p1_cas_n <= main_litedramcore_slave_p1_cas_n;
+	end else begin
+		main_litedramcore_master_p1_cas_n <= main_litedramcore_inti_p1_cas_n;
+	end
+// synthesis translate_off
+	dummy_d_62 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_63;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_master_p1_cs_n <= 1'd1;
+	if (main_litedramcore_sel) begin
+		main_litedramcore_master_p1_cs_n <= main_litedramcore_slave_p1_cs_n;
+	end else begin
+		main_litedramcore_master_p1_cs_n <= main_litedramcore_inti_p1_cs_n;
+	end
+// synthesis translate_off
+	dummy_d_63 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_64;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_master_p1_ras_n <= 1'd1;
+	if (main_litedramcore_sel) begin
+		main_litedramcore_master_p1_ras_n <= main_litedramcore_slave_p1_ras_n;
+	end else begin
+		main_litedramcore_master_p1_ras_n <= main_litedramcore_inti_p1_ras_n;
+	end
+// synthesis translate_off
+	dummy_d_64 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_65;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_slave_p1_rddata <= 32'd0;
+	if (main_litedramcore_sel) begin
+		main_litedramcore_slave_p1_rddata <= main_litedramcore_master_p1_rddata;
+	end else begin
+	end
+// synthesis translate_off
+	dummy_d_65 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_66;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_master_p1_we_n <= 1'd1;
+	if (main_litedramcore_sel) begin
+		main_litedramcore_master_p1_we_n <= main_litedramcore_slave_p1_we_n;
+	end else begin
+		main_litedramcore_master_p1_we_n <= main_litedramcore_inti_p1_we_n;
+	end
+// synthesis translate_off
+	dummy_d_66 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_67;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_slave_p1_rddata_valid <= 1'd0;
+	if (main_litedramcore_sel) begin
+		main_litedramcore_slave_p1_rddata_valid <= main_litedramcore_master_p1_rddata_valid;
+	end else begin
+	end
+// synthesis translate_off
+	dummy_d_67 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_68;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_master_p1_cke <= 1'd0;
+	if (main_litedramcore_sel) begin
+		main_litedramcore_master_p1_cke <= main_litedramcore_slave_p1_cke;
+	end else begin
+		main_litedramcore_master_p1_cke <= main_litedramcore_inti_p1_cke;
+	end
+// synthesis translate_off
+	dummy_d_68 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_69;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_master_p1_odt <= 1'd0;
+	if (main_litedramcore_sel) begin
+		main_litedramcore_master_p1_odt <= main_litedramcore_slave_p1_odt;
+	end else begin
+		main_litedramcore_master_p1_odt <= main_litedramcore_inti_p1_odt;
+	end
+// synthesis translate_off
+	dummy_d_69 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_70;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_master_p1_reset_n <= 1'd0;
+	if (main_litedramcore_sel) begin
+		main_litedramcore_master_p1_reset_n <= main_litedramcore_slave_p1_reset_n;
+	end else begin
+		main_litedramcore_master_p1_reset_n <= main_litedramcore_inti_p1_reset_n;
+	end
+// synthesis translate_off
+	dummy_d_70 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_71;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_master_p1_act_n <= 1'd1;
+	if (main_litedramcore_sel) begin
+		main_litedramcore_master_p1_act_n <= main_litedramcore_slave_p1_act_n;
+	end else begin
+		main_litedramcore_master_p1_act_n <= main_litedramcore_inti_p1_act_n;
+	end
+// synthesis translate_off
+	dummy_d_71 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_72;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_master_p1_wrdata <= 32'd0;
+	if (main_litedramcore_sel) begin
+		main_litedramcore_master_p1_wrdata <= main_litedramcore_slave_p1_wrdata;
+	end else begin
+		main_litedramcore_master_p1_wrdata <= main_litedramcore_inti_p1_wrdata;
+	end
+// synthesis translate_off
+	dummy_d_72 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_73;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_inti_p2_rddata <= 32'd0;
+	if (main_litedramcore_sel) begin
+	end else begin
+		main_litedramcore_inti_p2_rddata <= main_litedramcore_master_p2_rddata;
+	end
+// synthesis translate_off
+	dummy_d_73 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_74;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_master_p1_wrdata_en <= 1'd0;
+	if (main_litedramcore_sel) begin
+		main_litedramcore_master_p1_wrdata_en <= main_litedramcore_slave_p1_wrdata_en;
+	end else begin
+		main_litedramcore_master_p1_wrdata_en <= main_litedramcore_inti_p1_wrdata_en;
+	end
+// synthesis translate_off
+	dummy_d_74 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_75;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_inti_p2_rddata_valid <= 1'd0;
+	if (main_litedramcore_sel) begin
+	end else begin
+		main_litedramcore_inti_p2_rddata_valid <= main_litedramcore_master_p2_rddata_valid;
+	end
+// synthesis translate_off
+	dummy_d_75 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_76;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_master_p1_wrdata_mask <= 4'd0;
+	if (main_litedramcore_sel) begin
+		main_litedramcore_master_p1_wrdata_mask <= main_litedramcore_slave_p1_wrdata_mask;
+	end else begin
+		main_litedramcore_master_p1_wrdata_mask <= main_litedramcore_inti_p1_wrdata_mask;
+	end
+// synthesis translate_off
+	dummy_d_76 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_77;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_master_p1_rddata_en <= 1'd0;
+	if (main_litedramcore_sel) begin
+		main_litedramcore_master_p1_rddata_en <= main_litedramcore_slave_p1_rddata_en;
+	end else begin
+		main_litedramcore_master_p1_rddata_en <= main_litedramcore_inti_p1_rddata_en;
+	end
+// synthesis translate_off
+	dummy_d_77 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_78;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_master_p2_address <= 14'd0;
+	if (main_litedramcore_sel) begin
+		main_litedramcore_master_p2_address <= main_litedramcore_slave_p2_address;
+	end else begin
+		main_litedramcore_master_p2_address <= main_litedramcore_inti_p2_address;
+	end
+// synthesis translate_off
+	dummy_d_78 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_79;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_master_p2_bank <= 3'd0;
+	if (main_litedramcore_sel) begin
+		main_litedramcore_master_p2_bank <= main_litedramcore_slave_p2_bank;
+	end else begin
+		main_litedramcore_master_p2_bank <= main_litedramcore_inti_p2_bank;
+	end
+// synthesis translate_off
+	dummy_d_79 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_80;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_master_p2_cas_n <= 1'd1;
+	if (main_litedramcore_sel) begin
+		main_litedramcore_master_p2_cas_n <= main_litedramcore_slave_p2_cas_n;
+	end else begin
+		main_litedramcore_master_p2_cas_n <= main_litedramcore_inti_p2_cas_n;
+	end
+// synthesis translate_off
+	dummy_d_80 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_81;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_master_p2_cs_n <= 1'd1;
+	if (main_litedramcore_sel) begin
+		main_litedramcore_master_p2_cs_n <= main_litedramcore_slave_p2_cs_n;
+	end else begin
+		main_litedramcore_master_p2_cs_n <= main_litedramcore_inti_p2_cs_n;
+	end
+// synthesis translate_off
+	dummy_d_81 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_82;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_master_p2_ras_n <= 1'd1;
+	if (main_litedramcore_sel) begin
+		main_litedramcore_master_p2_ras_n <= main_litedramcore_slave_p2_ras_n;
+	end else begin
+		main_litedramcore_master_p2_ras_n <= main_litedramcore_inti_p2_ras_n;
+	end
+// synthesis translate_off
+	dummy_d_82 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_83;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_slave_p2_rddata <= 32'd0;
+	if (main_litedramcore_sel) begin
+		main_litedramcore_slave_p2_rddata <= main_litedramcore_master_p2_rddata;
+	end else begin
+	end
+// synthesis translate_off
+	dummy_d_83 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_84;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_master_p2_we_n <= 1'd1;
+	if (main_litedramcore_sel) begin
+		main_litedramcore_master_p2_we_n <= main_litedramcore_slave_p2_we_n;
+	end else begin
+		main_litedramcore_master_p2_we_n <= main_litedramcore_inti_p2_we_n;
+	end
+// synthesis translate_off
+	dummy_d_84 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_85;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_slave_p2_rddata_valid <= 1'd0;
+	if (main_litedramcore_sel) begin
+		main_litedramcore_slave_p2_rddata_valid <= main_litedramcore_master_p2_rddata_valid;
+	end else begin
+	end
+// synthesis translate_off
+	dummy_d_85 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_86;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_master_p2_cke <= 1'd0;
+	if (main_litedramcore_sel) begin
+		main_litedramcore_master_p2_cke <= main_litedramcore_slave_p2_cke;
+	end else begin
+		main_litedramcore_master_p2_cke <= main_litedramcore_inti_p2_cke;
+	end
+// synthesis translate_off
+	dummy_d_86 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_87;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_inti_p0_rddata <= 32'd0;
+	if (main_litedramcore_sel) begin
+	end else begin
+		main_litedramcore_inti_p0_rddata <= main_litedramcore_master_p0_rddata;
+	end
+// synthesis translate_off
+	dummy_d_87 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_88;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_master_p2_odt <= 1'd0;
+	if (main_litedramcore_sel) begin
+		main_litedramcore_master_p2_odt <= main_litedramcore_slave_p2_odt;
+	end else begin
+		main_litedramcore_master_p2_odt <= main_litedramcore_inti_p2_odt;
+	end
+// synthesis translate_off
+	dummy_d_88 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_89;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_master_p2_reset_n <= 1'd0;
+	if (main_litedramcore_sel) begin
+		main_litedramcore_master_p2_reset_n <= main_litedramcore_slave_p2_reset_n;
+	end else begin
+		main_litedramcore_master_p2_reset_n <= main_litedramcore_inti_p2_reset_n;
+	end
+// synthesis translate_off
+	dummy_d_89 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_90;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_master_p2_act_n <= 1'd1;
+	if (main_litedramcore_sel) begin
+		main_litedramcore_master_p2_act_n <= main_litedramcore_slave_p2_act_n;
+	end else begin
+		main_litedramcore_master_p2_act_n <= main_litedramcore_inti_p2_act_n;
+	end
+// synthesis translate_off
+	dummy_d_90 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_91;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_master_p2_wrdata <= 32'd0;
+	if (main_litedramcore_sel) begin
+		main_litedramcore_master_p2_wrdata <= main_litedramcore_slave_p2_wrdata;
+	end else begin
+		main_litedramcore_master_p2_wrdata <= main_litedramcore_inti_p2_wrdata;
+	end
+// synthesis translate_off
+	dummy_d_91 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_92;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_inti_p3_rddata <= 32'd0;
+	if (main_litedramcore_sel) begin
+	end else begin
+		main_litedramcore_inti_p3_rddata <= main_litedramcore_master_p3_rddata;
+	end
+// synthesis translate_off
+	dummy_d_92 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_93;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_master_p2_wrdata_en <= 1'd0;
+	if (main_litedramcore_sel) begin
+		main_litedramcore_master_p2_wrdata_en <= main_litedramcore_slave_p2_wrdata_en;
+	end else begin
+		main_litedramcore_master_p2_wrdata_en <= main_litedramcore_inti_p2_wrdata_en;
+	end
+// synthesis translate_off
+	dummy_d_93 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_94;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_inti_p0_rddata_valid <= 1'd0;
+	if (main_litedramcore_sel) begin
+	end else begin
+		main_litedramcore_inti_p0_rddata_valid <= main_litedramcore_master_p0_rddata_valid;
+	end
+// synthesis translate_off
+	dummy_d_94 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_95;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_master_p2_wrdata_mask <= 4'd0;
+	if (main_litedramcore_sel) begin
+		main_litedramcore_master_p2_wrdata_mask <= main_litedramcore_slave_p2_wrdata_mask;
+	end else begin
+		main_litedramcore_master_p2_wrdata_mask <= main_litedramcore_inti_p2_wrdata_mask;
+	end
+// synthesis translate_off
+	dummy_d_95 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_96;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_inti_p3_rddata_valid <= 1'd0;
+	if (main_litedramcore_sel) begin
+	end else begin
+		main_litedramcore_inti_p3_rddata_valid <= main_litedramcore_master_p3_rddata_valid;
+	end
+// synthesis translate_off
+	dummy_d_96 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_97;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_master_p2_rddata_en <= 1'd0;
+	if (main_litedramcore_sel) begin
+		main_litedramcore_master_p2_rddata_en <= main_litedramcore_slave_p2_rddata_en;
+	end else begin
+		main_litedramcore_master_p2_rddata_en <= main_litedramcore_inti_p2_rddata_en;
+	end
+// synthesis translate_off
+	dummy_d_97 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_98;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_master_p3_address <= 14'd0;
+	if (main_litedramcore_sel) begin
+		main_litedramcore_master_p3_address <= main_litedramcore_slave_p3_address;
+	end else begin
+		main_litedramcore_master_p3_address <= main_litedramcore_inti_p3_address;
+	end
+// synthesis translate_off
+	dummy_d_98 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_99;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_master_p3_bank <= 3'd0;
+	if (main_litedramcore_sel) begin
+		main_litedramcore_master_p3_bank <= main_litedramcore_slave_p3_bank;
+	end else begin
+		main_litedramcore_master_p3_bank <= main_litedramcore_inti_p3_bank;
+	end
+// synthesis translate_off
+	dummy_d_99 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_100;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_master_p3_cas_n <= 1'd1;
+	if (main_litedramcore_sel) begin
+		main_litedramcore_master_p3_cas_n <= main_litedramcore_slave_p3_cas_n;
+	end else begin
+		main_litedramcore_master_p3_cas_n <= main_litedramcore_inti_p3_cas_n;
+	end
+// synthesis translate_off
+	dummy_d_100 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_101;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_master_p3_cs_n <= 1'd1;
+	if (main_litedramcore_sel) begin
+		main_litedramcore_master_p3_cs_n <= main_litedramcore_slave_p3_cs_n;
+	end else begin
+		main_litedramcore_master_p3_cs_n <= main_litedramcore_inti_p3_cs_n;
+	end
+// synthesis translate_off
+	dummy_d_101 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_102;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_master_p3_ras_n <= 1'd1;
+	if (main_litedramcore_sel) begin
+		main_litedramcore_master_p3_ras_n <= main_litedramcore_slave_p3_ras_n;
+	end else begin
+		main_litedramcore_master_p3_ras_n <= main_litedramcore_inti_p3_ras_n;
+	end
+// synthesis translate_off
+	dummy_d_102 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_103;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_slave_p3_rddata <= 32'd0;
+	if (main_litedramcore_sel) begin
+		main_litedramcore_slave_p3_rddata <= main_litedramcore_master_p3_rddata;
+	end else begin
+	end
+// synthesis translate_off
+	dummy_d_103 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_104;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_master_p3_we_n <= 1'd1;
+	if (main_litedramcore_sel) begin
+		main_litedramcore_master_p3_we_n <= main_litedramcore_slave_p3_we_n;
+	end else begin
+		main_litedramcore_master_p3_we_n <= main_litedramcore_inti_p3_we_n;
+	end
+// synthesis translate_off
+	dummy_d_104 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_105;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_slave_p3_rddata_valid <= 1'd0;
+	if (main_litedramcore_sel) begin
+		main_litedramcore_slave_p3_rddata_valid <= main_litedramcore_master_p3_rddata_valid;
+	end else begin
+	end
+// synthesis translate_off
+	dummy_d_105 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_106;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_master_p3_cke <= 1'd0;
+	if (main_litedramcore_sel) begin
+		main_litedramcore_master_p3_cke <= main_litedramcore_slave_p3_cke;
+	end else begin
+		main_litedramcore_master_p3_cke <= main_litedramcore_inti_p3_cke;
+	end
+// synthesis translate_off
+	dummy_d_106 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_107;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_master_p3_odt <= 1'd0;
+	if (main_litedramcore_sel) begin
+		main_litedramcore_master_p3_odt <= main_litedramcore_slave_p3_odt;
+	end else begin
+		main_litedramcore_master_p3_odt <= main_litedramcore_inti_p3_odt;
+	end
+// synthesis translate_off
+	dummy_d_107 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_108;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_master_p3_reset_n <= 1'd0;
+	if (main_litedramcore_sel) begin
+		main_litedramcore_master_p3_reset_n <= main_litedramcore_slave_p3_reset_n;
+	end else begin
+		main_litedramcore_master_p3_reset_n <= main_litedramcore_inti_p3_reset_n;
+	end
+// synthesis translate_off
+	dummy_d_108 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_109;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_master_p3_act_n <= 1'd1;
+	if (main_litedramcore_sel) begin
+		main_litedramcore_master_p3_act_n <= main_litedramcore_slave_p3_act_n;
+	end else begin
+		main_litedramcore_master_p3_act_n <= main_litedramcore_inti_p3_act_n;
+	end
+// synthesis translate_off
+	dummy_d_109 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_110;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_master_p3_wrdata <= 32'd0;
+	if (main_litedramcore_sel) begin
+		main_litedramcore_master_p3_wrdata <= main_litedramcore_slave_p3_wrdata;
+	end else begin
+		main_litedramcore_master_p3_wrdata <= main_litedramcore_inti_p3_wrdata;
+	end
+// synthesis translate_off
+	dummy_d_110 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_111;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_master_p3_wrdata_en <= 1'd0;
+	if (main_litedramcore_sel) begin
+		main_litedramcore_master_p3_wrdata_en <= main_litedramcore_slave_p3_wrdata_en;
+	end else begin
+		main_litedramcore_master_p3_wrdata_en <= main_litedramcore_inti_p3_wrdata_en;
+	end
+// synthesis translate_off
+	dummy_d_111 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_112;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_master_p3_wrdata_mask <= 4'd0;
+	if (main_litedramcore_sel) begin
+		main_litedramcore_master_p3_wrdata_mask <= main_litedramcore_slave_p3_wrdata_mask;
+	end else begin
+		main_litedramcore_master_p3_wrdata_mask <= main_litedramcore_inti_p3_wrdata_mask;
+	end
+// synthesis translate_off
+	dummy_d_112 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_113;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_master_p3_rddata_en <= 1'd0;
+	if (main_litedramcore_sel) begin
+		main_litedramcore_master_p3_rddata_en <= main_litedramcore_slave_p3_rddata_en;
+	end else begin
+		main_litedramcore_master_p3_rddata_en <= main_litedramcore_inti_p3_rddata_en;
+	end
+// synthesis translate_off
+	dummy_d_113 = dummy_s;
+// synthesis translate_on
+end
+assign main_litedramcore_inti_p0_cke = main_litedramcore_cke;
+assign main_litedramcore_inti_p1_cke = main_litedramcore_cke;
+assign main_litedramcore_inti_p2_cke = main_litedramcore_cke;
+assign main_litedramcore_inti_p3_cke = main_litedramcore_cke;
+assign main_litedramcore_inti_p0_odt = main_litedramcore_odt;
+assign main_litedramcore_inti_p1_odt = main_litedramcore_odt;
+assign main_litedramcore_inti_p2_odt = main_litedramcore_odt;
+assign main_litedramcore_inti_p3_odt = main_litedramcore_odt;
+assign main_litedramcore_inti_p0_reset_n = main_litedramcore_reset_n;
+assign main_litedramcore_inti_p1_reset_n = main_litedramcore_reset_n;
+assign main_litedramcore_inti_p2_reset_n = main_litedramcore_reset_n;
+assign main_litedramcore_inti_p3_reset_n = main_litedramcore_reset_n;
+
+// synthesis translate_off
+reg dummy_d_114;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_inti_p0_cas_n <= 1'd1;
+	if (main_litedramcore_phaseinjector0_command_issue_re) begin
+		main_litedramcore_inti_p0_cas_n <= (~main_litedramcore_phaseinjector0_command_storage[2]);
+	end else begin
+		main_litedramcore_inti_p0_cas_n <= 1'd1;
+	end
+// synthesis translate_off
+	dummy_d_114 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_115;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_inti_p0_cs_n <= 1'd1;
+	if (main_litedramcore_phaseinjector0_command_issue_re) begin
+		main_litedramcore_inti_p0_cs_n <= {1{(~main_litedramcore_phaseinjector0_command_storage[0])}};
+	end else begin
+		main_litedramcore_inti_p0_cs_n <= {1{1'd1}};
+	end
+// synthesis translate_off
+	dummy_d_115 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_116;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_inti_p0_ras_n <= 1'd1;
+	if (main_litedramcore_phaseinjector0_command_issue_re) begin
+		main_litedramcore_inti_p0_ras_n <= (~main_litedramcore_phaseinjector0_command_storage[3]);
+	end else begin
+		main_litedramcore_inti_p0_ras_n <= 1'd1;
+	end
+// synthesis translate_off
+	dummy_d_116 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_117;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_inti_p0_we_n <= 1'd1;
+	if (main_litedramcore_phaseinjector0_command_issue_re) begin
+		main_litedramcore_inti_p0_we_n <= (~main_litedramcore_phaseinjector0_command_storage[1]);
+	end else begin
+		main_litedramcore_inti_p0_we_n <= 1'd1;
+	end
+// synthesis translate_off
+	dummy_d_117 = dummy_s;
+// synthesis translate_on
+end
+assign main_litedramcore_inti_p0_address = main_litedramcore_phaseinjector0_address_storage;
+assign main_litedramcore_inti_p0_bank = main_litedramcore_phaseinjector0_baddress_storage;
+assign main_litedramcore_inti_p0_wrdata_en = (main_litedramcore_phaseinjector0_command_issue_re & main_litedramcore_phaseinjector0_command_storage[4]);
+assign main_litedramcore_inti_p0_rddata_en = (main_litedramcore_phaseinjector0_command_issue_re & main_litedramcore_phaseinjector0_command_storage[5]);
+assign main_litedramcore_inti_p0_wrdata = main_litedramcore_phaseinjector0_wrdata_storage;
+assign main_litedramcore_inti_p0_wrdata_mask = 1'd0;
+
+// synthesis translate_off
+reg dummy_d_118;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_inti_p1_cas_n <= 1'd1;
+	if (main_litedramcore_phaseinjector1_command_issue_re) begin
+		main_litedramcore_inti_p1_cas_n <= (~main_litedramcore_phaseinjector1_command_storage[2]);
+	end else begin
+		main_litedramcore_inti_p1_cas_n <= 1'd1;
+	end
+// synthesis translate_off
+	dummy_d_118 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_119;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_inti_p1_cs_n <= 1'd1;
+	if (main_litedramcore_phaseinjector1_command_issue_re) begin
+		main_litedramcore_inti_p1_cs_n <= {1{(~main_litedramcore_phaseinjector1_command_storage[0])}};
+	end else begin
+		main_litedramcore_inti_p1_cs_n <= {1{1'd1}};
+	end
+// synthesis translate_off
+	dummy_d_119 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_120;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_inti_p1_ras_n <= 1'd1;
+	if (main_litedramcore_phaseinjector1_command_issue_re) begin
+		main_litedramcore_inti_p1_ras_n <= (~main_litedramcore_phaseinjector1_command_storage[3]);
+	end else begin
+		main_litedramcore_inti_p1_ras_n <= 1'd1;
+	end
+// synthesis translate_off
+	dummy_d_120 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_121;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_inti_p1_we_n <= 1'd1;
+	if (main_litedramcore_phaseinjector1_command_issue_re) begin
+		main_litedramcore_inti_p1_we_n <= (~main_litedramcore_phaseinjector1_command_storage[1]);
+	end else begin
+		main_litedramcore_inti_p1_we_n <= 1'd1;
+	end
+// synthesis translate_off
+	dummy_d_121 = dummy_s;
+// synthesis translate_on
+end
+assign main_litedramcore_inti_p1_address = main_litedramcore_phaseinjector1_address_storage;
+assign main_litedramcore_inti_p1_bank = main_litedramcore_phaseinjector1_baddress_storage;
+assign main_litedramcore_inti_p1_wrdata_en = (main_litedramcore_phaseinjector1_command_issue_re & main_litedramcore_phaseinjector1_command_storage[4]);
+assign main_litedramcore_inti_p1_rddata_en = (main_litedramcore_phaseinjector1_command_issue_re & main_litedramcore_phaseinjector1_command_storage[5]);
+assign main_litedramcore_inti_p1_wrdata = main_litedramcore_phaseinjector1_wrdata_storage;
+assign main_litedramcore_inti_p1_wrdata_mask = 1'd0;
+
+// synthesis translate_off
+reg dummy_d_122;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_inti_p2_cas_n <= 1'd1;
+	if (main_litedramcore_phaseinjector2_command_issue_re) begin
+		main_litedramcore_inti_p2_cas_n <= (~main_litedramcore_phaseinjector2_command_storage[2]);
+	end else begin
+		main_litedramcore_inti_p2_cas_n <= 1'd1;
+	end
+// synthesis translate_off
+	dummy_d_122 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_123;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_inti_p2_cs_n <= 1'd1;
+	if (main_litedramcore_phaseinjector2_command_issue_re) begin
+		main_litedramcore_inti_p2_cs_n <= {1{(~main_litedramcore_phaseinjector2_command_storage[0])}};
+	end else begin
+		main_litedramcore_inti_p2_cs_n <= {1{1'd1}};
+	end
+// synthesis translate_off
+	dummy_d_123 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_124;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_inti_p2_ras_n <= 1'd1;
+	if (main_litedramcore_phaseinjector2_command_issue_re) begin
+		main_litedramcore_inti_p2_ras_n <= (~main_litedramcore_phaseinjector2_command_storage[3]);
+	end else begin
+		main_litedramcore_inti_p2_ras_n <= 1'd1;
+	end
+// synthesis translate_off
+	dummy_d_124 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_125;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_inti_p2_we_n <= 1'd1;
+	if (main_litedramcore_phaseinjector2_command_issue_re) begin
+		main_litedramcore_inti_p2_we_n <= (~main_litedramcore_phaseinjector2_command_storage[1]);
+	end else begin
+		main_litedramcore_inti_p2_we_n <= 1'd1;
+	end
+// synthesis translate_off
+	dummy_d_125 = dummy_s;
+// synthesis translate_on
+end
+assign main_litedramcore_inti_p2_address = main_litedramcore_phaseinjector2_address_storage;
+assign main_litedramcore_inti_p2_bank = main_litedramcore_phaseinjector2_baddress_storage;
+assign main_litedramcore_inti_p2_wrdata_en = (main_litedramcore_phaseinjector2_command_issue_re & main_litedramcore_phaseinjector2_command_storage[4]);
+assign main_litedramcore_inti_p2_rddata_en = (main_litedramcore_phaseinjector2_command_issue_re & main_litedramcore_phaseinjector2_command_storage[5]);
+assign main_litedramcore_inti_p2_wrdata = main_litedramcore_phaseinjector2_wrdata_storage;
+assign main_litedramcore_inti_p2_wrdata_mask = 1'd0;
+
+// synthesis translate_off
+reg dummy_d_126;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_inti_p3_cas_n <= 1'd1;
+	if (main_litedramcore_phaseinjector3_command_issue_re) begin
+		main_litedramcore_inti_p3_cas_n <= (~main_litedramcore_phaseinjector3_command_storage[2]);
+	end else begin
+		main_litedramcore_inti_p3_cas_n <= 1'd1;
+	end
+// synthesis translate_off
+	dummy_d_126 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_127;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_inti_p3_cs_n <= 1'd1;
+	if (main_litedramcore_phaseinjector3_command_issue_re) begin
+		main_litedramcore_inti_p3_cs_n <= {1{(~main_litedramcore_phaseinjector3_command_storage[0])}};
+	end else begin
+		main_litedramcore_inti_p3_cs_n <= {1{1'd1}};
+	end
+// synthesis translate_off
+	dummy_d_127 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_128;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_inti_p3_ras_n <= 1'd1;
+	if (main_litedramcore_phaseinjector3_command_issue_re) begin
+		main_litedramcore_inti_p3_ras_n <= (~main_litedramcore_phaseinjector3_command_storage[3]);
+	end else begin
+		main_litedramcore_inti_p3_ras_n <= 1'd1;
+	end
+// synthesis translate_off
+	dummy_d_128 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_129;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_inti_p3_we_n <= 1'd1;
+	if (main_litedramcore_phaseinjector3_command_issue_re) begin
+		main_litedramcore_inti_p3_we_n <= (~main_litedramcore_phaseinjector3_command_storage[1]);
+	end else begin
+		main_litedramcore_inti_p3_we_n <= 1'd1;
+	end
+// synthesis translate_off
+	dummy_d_129 = dummy_s;
+// synthesis translate_on
+end
+assign main_litedramcore_inti_p3_address = main_litedramcore_phaseinjector3_address_storage;
+assign main_litedramcore_inti_p3_bank = main_litedramcore_phaseinjector3_baddress_storage;
+assign main_litedramcore_inti_p3_wrdata_en = (main_litedramcore_phaseinjector3_command_issue_re & main_litedramcore_phaseinjector3_command_storage[4]);
+assign main_litedramcore_inti_p3_rddata_en = (main_litedramcore_phaseinjector3_command_issue_re & main_litedramcore_phaseinjector3_command_storage[5]);
+assign main_litedramcore_inti_p3_wrdata = main_litedramcore_phaseinjector3_wrdata_storage;
+assign main_litedramcore_inti_p3_wrdata_mask = 1'd0;
+assign main_litedramcore_bankmachine0_req_valid = main_litedramcore_interface_bank0_valid;
+assign main_litedramcore_interface_bank0_ready = main_litedramcore_bankmachine0_req_ready;
+assign main_litedramcore_bankmachine0_req_we = main_litedramcore_interface_bank0_we;
+assign main_litedramcore_bankmachine0_req_addr = main_litedramcore_interface_bank0_addr;
+assign main_litedramcore_interface_bank0_lock = main_litedramcore_bankmachine0_req_lock;
+assign main_litedramcore_interface_bank0_wdata_ready = main_litedramcore_bankmachine0_req_wdata_ready;
+assign main_litedramcore_interface_bank0_rdata_valid = main_litedramcore_bankmachine0_req_rdata_valid;
+assign main_litedramcore_bankmachine1_req_valid = main_litedramcore_interface_bank1_valid;
+assign main_litedramcore_interface_bank1_ready = main_litedramcore_bankmachine1_req_ready;
+assign main_litedramcore_bankmachine1_req_we = main_litedramcore_interface_bank1_we;
+assign main_litedramcore_bankmachine1_req_addr = main_litedramcore_interface_bank1_addr;
+assign main_litedramcore_interface_bank1_lock = main_litedramcore_bankmachine1_req_lock;
+assign main_litedramcore_interface_bank1_wdata_ready = main_litedramcore_bankmachine1_req_wdata_ready;
+assign main_litedramcore_interface_bank1_rdata_valid = main_litedramcore_bankmachine1_req_rdata_valid;
+assign main_litedramcore_bankmachine2_req_valid = main_litedramcore_interface_bank2_valid;
+assign main_litedramcore_interface_bank2_ready = main_litedramcore_bankmachine2_req_ready;
+assign main_litedramcore_bankmachine2_req_we = main_litedramcore_interface_bank2_we;
+assign main_litedramcore_bankmachine2_req_addr = main_litedramcore_interface_bank2_addr;
+assign main_litedramcore_interface_bank2_lock = main_litedramcore_bankmachine2_req_lock;
+assign main_litedramcore_interface_bank2_wdata_ready = main_litedramcore_bankmachine2_req_wdata_ready;
+assign main_litedramcore_interface_bank2_rdata_valid = main_litedramcore_bankmachine2_req_rdata_valid;
+assign main_litedramcore_bankmachine3_req_valid = main_litedramcore_interface_bank3_valid;
+assign main_litedramcore_interface_bank3_ready = main_litedramcore_bankmachine3_req_ready;
+assign main_litedramcore_bankmachine3_req_we = main_litedramcore_interface_bank3_we;
+assign main_litedramcore_bankmachine3_req_addr = main_litedramcore_interface_bank3_addr;
+assign main_litedramcore_interface_bank3_lock = main_litedramcore_bankmachine3_req_lock;
+assign main_litedramcore_interface_bank3_wdata_ready = main_litedramcore_bankmachine3_req_wdata_ready;
+assign main_litedramcore_interface_bank3_rdata_valid = main_litedramcore_bankmachine3_req_rdata_valid;
+assign main_litedramcore_bankmachine4_req_valid = main_litedramcore_interface_bank4_valid;
+assign main_litedramcore_interface_bank4_ready = main_litedramcore_bankmachine4_req_ready;
+assign main_litedramcore_bankmachine4_req_we = main_litedramcore_interface_bank4_we;
+assign main_litedramcore_bankmachine4_req_addr = main_litedramcore_interface_bank4_addr;
+assign main_litedramcore_interface_bank4_lock = main_litedramcore_bankmachine4_req_lock;
+assign main_litedramcore_interface_bank4_wdata_ready = main_litedramcore_bankmachine4_req_wdata_ready;
+assign main_litedramcore_interface_bank4_rdata_valid = main_litedramcore_bankmachine4_req_rdata_valid;
+assign main_litedramcore_bankmachine5_req_valid = main_litedramcore_interface_bank5_valid;
+assign main_litedramcore_interface_bank5_ready = main_litedramcore_bankmachine5_req_ready;
+assign main_litedramcore_bankmachine5_req_we = main_litedramcore_interface_bank5_we;
+assign main_litedramcore_bankmachine5_req_addr = main_litedramcore_interface_bank5_addr;
+assign main_litedramcore_interface_bank5_lock = main_litedramcore_bankmachine5_req_lock;
+assign main_litedramcore_interface_bank5_wdata_ready = main_litedramcore_bankmachine5_req_wdata_ready;
+assign main_litedramcore_interface_bank5_rdata_valid = main_litedramcore_bankmachine5_req_rdata_valid;
+assign main_litedramcore_bankmachine6_req_valid = main_litedramcore_interface_bank6_valid;
+assign main_litedramcore_interface_bank6_ready = main_litedramcore_bankmachine6_req_ready;
+assign main_litedramcore_bankmachine6_req_we = main_litedramcore_interface_bank6_we;
+assign main_litedramcore_bankmachine6_req_addr = main_litedramcore_interface_bank6_addr;
+assign main_litedramcore_interface_bank6_lock = main_litedramcore_bankmachine6_req_lock;
+assign main_litedramcore_interface_bank6_wdata_ready = main_litedramcore_bankmachine6_req_wdata_ready;
+assign main_litedramcore_interface_bank6_rdata_valid = main_litedramcore_bankmachine6_req_rdata_valid;
+assign main_litedramcore_bankmachine7_req_valid = main_litedramcore_interface_bank7_valid;
+assign main_litedramcore_interface_bank7_ready = main_litedramcore_bankmachine7_req_ready;
+assign main_litedramcore_bankmachine7_req_we = main_litedramcore_interface_bank7_we;
+assign main_litedramcore_bankmachine7_req_addr = main_litedramcore_interface_bank7_addr;
+assign main_litedramcore_interface_bank7_lock = main_litedramcore_bankmachine7_req_lock;
+assign main_litedramcore_interface_bank7_wdata_ready = main_litedramcore_bankmachine7_req_wdata_ready;
+assign main_litedramcore_interface_bank7_rdata_valid = main_litedramcore_bankmachine7_req_rdata_valid;
+assign main_litedramcore_timer_wait = (~main_litedramcore_timer_done0);
+assign main_litedramcore_postponer_req_i = main_litedramcore_timer_done0;
+assign main_litedramcore_wants_refresh = main_litedramcore_postponer_req_o;
+assign main_litedramcore_wants_zqcs = main_litedramcore_zqcs_timer_done0;
+assign main_litedramcore_zqcs_timer_wait = (~main_litedramcore_zqcs_executer_done);
+assign main_litedramcore_timer_done1 = (main_litedramcore_timer_count1 == 1'd0);
+assign main_litedramcore_timer_done0 = main_litedramcore_timer_done1;
+assign main_litedramcore_timer_count0 = main_litedramcore_timer_count1;
+assign main_litedramcore_sequencer_start1 = (main_litedramcore_sequencer_start0 | (main_litedramcore_sequencer_count != 1'd0));
+assign main_litedramcore_sequencer_done0 = (main_litedramcore_sequencer_done1 & (main_litedramcore_sequencer_count == 1'd0));
+assign main_litedramcore_zqcs_timer_done1 = (main_litedramcore_zqcs_timer_count1 == 1'd0);
+assign main_litedramcore_zqcs_timer_done0 = main_litedramcore_zqcs_timer_done1;
+assign main_litedramcore_zqcs_timer_count0 = main_litedramcore_zqcs_timer_count1;
+
+// synthesis translate_off
+reg dummy_d_130;
+// synthesis translate_on
+always @(*) begin
+	builder_refresher_next_state <= 2'd0;
+	builder_refresher_next_state <= builder_refresher_state;
+	case (builder_refresher_state)
+		1'd1: begin
+			if (main_litedramcore_cmd_ready) begin
+				builder_refresher_next_state <= 2'd2;
+			end
+		end
+		2'd2: begin
+			if (main_litedramcore_sequencer_done0) begin
+				if (main_litedramcore_wants_zqcs) begin
+					builder_refresher_next_state <= 2'd3;
+				end else begin
+					builder_refresher_next_state <= 1'd0;
+				end
+			end
+		end
+		2'd3: begin
+			if (main_litedramcore_zqcs_executer_done) begin
+				builder_refresher_next_state <= 1'd0;
+			end
+		end
+		default: begin
+			if (1'd1) begin
+				if (main_litedramcore_wants_refresh) begin
+					builder_refresher_next_state <= 1'd1;
+				end
+			end
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_130 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_131;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_sequencer_start0 <= 1'd0;
+	case (builder_refresher_state)
+		1'd1: begin
+			if (main_litedramcore_cmd_ready) begin
+				main_litedramcore_sequencer_start0 <= 1'd1;
+			end
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+		end
+		default: begin
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_131 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_132;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_cmd_valid <= 1'd0;
+	case (builder_refresher_state)
+		1'd1: begin
+			main_litedramcore_cmd_valid <= 1'd1;
+		end
+		2'd2: begin
+			main_litedramcore_cmd_valid <= 1'd1;
+			if (main_litedramcore_sequencer_done0) begin
+				if (main_litedramcore_wants_zqcs) begin
+				end else begin
+					main_litedramcore_cmd_valid <= 1'd0;
+				end
+			end
+		end
+		2'd3: begin
+			main_litedramcore_cmd_valid <= 1'd1;
+			if (main_litedramcore_zqcs_executer_done) begin
+				main_litedramcore_cmd_valid <= 1'd0;
+			end
+		end
+		default: begin
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_132 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_133;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_zqcs_executer_start <= 1'd0;
+	case (builder_refresher_state)
+		1'd1: begin
+		end
+		2'd2: begin
+			if (main_litedramcore_sequencer_done0) begin
+				if (main_litedramcore_wants_zqcs) begin
+					main_litedramcore_zqcs_executer_start <= 1'd1;
+				end else begin
+				end
+			end
+		end
+		2'd3: begin
+		end
+		default: begin
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_133 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_134;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_cmd_last <= 1'd0;
+	case (builder_refresher_state)
+		1'd1: begin
+		end
+		2'd2: begin
+			if (main_litedramcore_sequencer_done0) begin
+				if (main_litedramcore_wants_zqcs) begin
+				end else begin
+					main_litedramcore_cmd_last <= 1'd1;
+				end
+			end
+		end
+		2'd3: begin
+			if (main_litedramcore_zqcs_executer_done) begin
+				main_litedramcore_cmd_last <= 1'd1;
+			end
+		end
+		default: begin
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_134 = dummy_s;
+// synthesis translate_on
+end
+assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine0_req_valid;
+assign main_litedramcore_bankmachine0_req_ready = main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready;
+assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we = main_litedramcore_bankmachine0_req_we;
+assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr = main_litedramcore_bankmachine0_req_addr;
+assign main_litedramcore_bankmachine0_cmd_buffer_sink_valid = main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid;
+assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready = main_litedramcore_bankmachine0_cmd_buffer_sink_ready;
+assign main_litedramcore_bankmachine0_cmd_buffer_sink_first = main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_first;
+assign main_litedramcore_bankmachine0_cmd_buffer_sink_last = main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_last;
+assign main_litedramcore_bankmachine0_cmd_buffer_sink_payload_we = main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we;
+assign main_litedramcore_bankmachine0_cmd_buffer_sink_payload_addr = main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr;
+assign main_litedramcore_bankmachine0_cmd_buffer_source_ready = (main_litedramcore_bankmachine0_req_wdata_ready | main_litedramcore_bankmachine0_req_rdata_valid);
+assign main_litedramcore_bankmachine0_req_lock = (main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid | main_litedramcore_bankmachine0_cmd_buffer_source_valid);
+assign main_litedramcore_bankmachine0_row_hit = (main_litedramcore_bankmachine0_row == main_litedramcore_bankmachine0_cmd_buffer_source_payload_addr[20:7]);
+assign main_litedramcore_bankmachine0_cmd_payload_ba = 1'd0;
+
+// synthesis translate_off
+reg dummy_d_135;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine0_cmd_payload_a <= 14'd0;
+	if (main_litedramcore_bankmachine0_row_col_n_addr_sel) begin
+		main_litedramcore_bankmachine0_cmd_payload_a <= main_litedramcore_bankmachine0_cmd_buffer_source_payload_addr[20:7];
+	end else begin
+		main_litedramcore_bankmachine0_cmd_payload_a <= ((main_litedramcore_bankmachine0_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine0_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
+	end
+// synthesis translate_off
+	dummy_d_135 = dummy_s;
+// synthesis translate_on
+end
+assign main_litedramcore_bankmachine0_twtpcon_valid = ((main_litedramcore_bankmachine0_cmd_valid & main_litedramcore_bankmachine0_cmd_ready) & main_litedramcore_bankmachine0_cmd_payload_is_write);
+assign main_litedramcore_bankmachine0_trccon_valid = ((main_litedramcore_bankmachine0_cmd_valid & main_litedramcore_bankmachine0_cmd_ready) & main_litedramcore_bankmachine0_row_open);
+assign main_litedramcore_bankmachine0_trascon_valid = ((main_litedramcore_bankmachine0_cmd_valid & main_litedramcore_bankmachine0_cmd_ready) & main_litedramcore_bankmachine0_row_open);
+
+// synthesis translate_off
+reg dummy_d_136;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine0_auto_precharge <= 1'd0;
+	if ((main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid & main_litedramcore_bankmachine0_cmd_buffer_source_valid)) begin
+		if ((main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr[20:7] != main_litedramcore_bankmachine0_cmd_buffer_source_payload_addr[20:7])) begin
+			main_litedramcore_bankmachine0_auto_precharge <= (main_litedramcore_bankmachine0_row_close == 1'd0);
+		end
+	end
+// synthesis translate_off
+	dummy_d_136 = dummy_s;
+// synthesis translate_on
+end
+assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din = {main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we};
+assign {main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
+assign {main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
+assign {main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
+assign {main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
+assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready = main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable;
+assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we = main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid;
+assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first = main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_first;
+assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last = main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_last;
+assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we = main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we;
+assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr = main_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr;
+assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid = main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable;
+assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_first = main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first;
+assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_last = main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last;
+assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we = main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we;
+assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr = main_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr;
+assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re = main_litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready;
+
+// synthesis translate_off
+reg dummy_d_137;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= 4'd0;
+	if (main_litedramcore_bankmachine0_cmd_buffer_lookahead_replace) begin
+		main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= (main_litedramcore_bankmachine0_cmd_buffer_lookahead_produce - 1'd1);
+	end else begin
+		main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= main_litedramcore_bankmachine0_cmd_buffer_lookahead_produce;
+	end
+// synthesis translate_off
+	dummy_d_137 = dummy_s;
+// synthesis translate_on
+end
+assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w = main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din;
+assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we = (main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & (main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable | main_litedramcore_bankmachine0_cmd_buffer_lookahead_replace));
+assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_do_read = (main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable & main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re);
+assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr = main_litedramcore_bankmachine0_cmd_buffer_lookahead_consume;
+assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout = main_litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r;
+assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable = (main_litedramcore_bankmachine0_cmd_buffer_lookahead_level != 5'd16);
+assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable = (main_litedramcore_bankmachine0_cmd_buffer_lookahead_level != 1'd0);
+assign main_litedramcore_bankmachine0_cmd_buffer_sink_ready = ((~main_litedramcore_bankmachine0_cmd_buffer_source_valid) | main_litedramcore_bankmachine0_cmd_buffer_source_ready);
+
+// synthesis translate_off
+reg dummy_d_138;
+// synthesis translate_on
+always @(*) begin
+	builder_bankmachine0_next_state <= 4'd0;
+	builder_bankmachine0_next_state <= builder_bankmachine0_state;
+	case (builder_bankmachine0_state)
+		1'd1: begin
+			if ((main_litedramcore_bankmachine0_twtpcon_ready & main_litedramcore_bankmachine0_trascon_ready)) begin
+				if (main_litedramcore_bankmachine0_cmd_ready) begin
+					builder_bankmachine0_next_state <= 3'd5;
+				end
+			end
+		end
+		2'd2: begin
+			if ((main_litedramcore_bankmachine0_twtpcon_ready & main_litedramcore_bankmachine0_trascon_ready)) begin
+				builder_bankmachine0_next_state <= 3'd5;
+			end
+		end
+		2'd3: begin
+			if (main_litedramcore_bankmachine0_trccon_ready) begin
+				if (main_litedramcore_bankmachine0_cmd_ready) begin
+					builder_bankmachine0_next_state <= 3'd7;
+				end
+			end
+		end
+		3'd4: begin
+			if ((~main_litedramcore_bankmachine0_refresh_req)) begin
+				builder_bankmachine0_next_state <= 1'd0;
+			end
+		end
+		3'd5: begin
+			builder_bankmachine0_next_state <= 3'd6;
+		end
+		3'd6: begin
+			builder_bankmachine0_next_state <= 2'd3;
+		end
+		3'd7: begin
+			builder_bankmachine0_next_state <= 4'd8;
+		end
+		4'd8: begin
+			builder_bankmachine0_next_state <= 1'd0;
+		end
+		default: begin
+			if (main_litedramcore_bankmachine0_refresh_req) begin
+				builder_bankmachine0_next_state <= 3'd4;
+			end else begin
+				if (main_litedramcore_bankmachine0_cmd_buffer_source_valid) begin
+					if (main_litedramcore_bankmachine0_row_opened) begin
+						if (main_litedramcore_bankmachine0_row_hit) begin
+							if ((main_litedramcore_bankmachine0_cmd_ready & main_litedramcore_bankmachine0_auto_precharge)) begin
+								builder_bankmachine0_next_state <= 2'd2;
+							end
+						end else begin
+							builder_bankmachine0_next_state <= 1'd1;
+						end
+					end else begin
+						builder_bankmachine0_next_state <= 2'd3;
+					end
+				end
+			end
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_138 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_139;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine0_row_open <= 1'd0;
+	case (builder_bankmachine0_state)
+		1'd1: begin
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+			if (main_litedramcore_bankmachine0_trccon_ready) begin
+				main_litedramcore_bankmachine0_row_open <= 1'd1;
+			end
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_139 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_140;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine0_row_close <= 1'd0;
+	case (builder_bankmachine0_state)
+		1'd1: begin
+			main_litedramcore_bankmachine0_row_close <= 1'd1;
+		end
+		2'd2: begin
+			main_litedramcore_bankmachine0_row_close <= 1'd1;
+		end
+		2'd3: begin
+		end
+		3'd4: begin
+			main_litedramcore_bankmachine0_row_close <= 1'd1;
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_140 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_141;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine0_cmd_payload_cas <= 1'd0;
+	case (builder_bankmachine0_state)
+		1'd1: begin
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+			if (main_litedramcore_bankmachine0_refresh_req) begin
+			end else begin
+				if (main_litedramcore_bankmachine0_cmd_buffer_source_valid) begin
+					if (main_litedramcore_bankmachine0_row_opened) begin
+						if (main_litedramcore_bankmachine0_row_hit) begin
+							main_litedramcore_bankmachine0_cmd_payload_cas <= 1'd1;
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_141 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_142;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine0_cmd_payload_ras <= 1'd0;
+	case (builder_bankmachine0_state)
+		1'd1: begin
+			if ((main_litedramcore_bankmachine0_twtpcon_ready & main_litedramcore_bankmachine0_trascon_ready)) begin
+				main_litedramcore_bankmachine0_cmd_payload_ras <= 1'd1;
+			end
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+			if (main_litedramcore_bankmachine0_trccon_ready) begin
+				main_litedramcore_bankmachine0_cmd_payload_ras <= 1'd1;
+			end
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_142 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_143;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine0_cmd_payload_we <= 1'd0;
+	case (builder_bankmachine0_state)
+		1'd1: begin
+			if ((main_litedramcore_bankmachine0_twtpcon_ready & main_litedramcore_bankmachine0_trascon_ready)) begin
+				main_litedramcore_bankmachine0_cmd_payload_we <= 1'd1;
+			end
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+			if (main_litedramcore_bankmachine0_refresh_req) begin
+			end else begin
+				if (main_litedramcore_bankmachine0_cmd_buffer_source_valid) begin
+					if (main_litedramcore_bankmachine0_row_opened) begin
+						if (main_litedramcore_bankmachine0_row_hit) begin
+							if (main_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
+								main_litedramcore_bankmachine0_cmd_payload_we <= 1'd1;
+							end else begin
+							end
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_143 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_144;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd0;
+	case (builder_bankmachine0_state)
+		1'd1: begin
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+			if (main_litedramcore_bankmachine0_trccon_ready) begin
+				main_litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd1;
+			end
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_144 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_145;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd0;
+	case (builder_bankmachine0_state)
+		1'd1: begin
+			if ((main_litedramcore_bankmachine0_twtpcon_ready & main_litedramcore_bankmachine0_trascon_ready)) begin
+				main_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
+			end
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+			if (main_litedramcore_bankmachine0_trccon_ready) begin
+				main_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
+			end
+		end
+		3'd4: begin
+			main_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_145 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_146;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine0_cmd_payload_is_read <= 1'd0;
+	case (builder_bankmachine0_state)
+		1'd1: begin
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+			if (main_litedramcore_bankmachine0_refresh_req) begin
+			end else begin
+				if (main_litedramcore_bankmachine0_cmd_buffer_source_valid) begin
+					if (main_litedramcore_bankmachine0_row_opened) begin
+						if (main_litedramcore_bankmachine0_row_hit) begin
+							if (main_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
+							end else begin
+								main_litedramcore_bankmachine0_cmd_payload_is_read <= 1'd1;
+							end
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_146 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_147;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine0_req_rdata_valid <= 1'd0;
+	case (builder_bankmachine0_state)
+		1'd1: begin
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+			if (main_litedramcore_bankmachine0_refresh_req) begin
+			end else begin
+				if (main_litedramcore_bankmachine0_cmd_buffer_source_valid) begin
+					if (main_litedramcore_bankmachine0_row_opened) begin
+						if (main_litedramcore_bankmachine0_row_hit) begin
+							if (main_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
+							end else begin
+								main_litedramcore_bankmachine0_req_rdata_valid <= main_litedramcore_bankmachine0_cmd_ready;
+							end
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_147 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_148;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine0_cmd_payload_is_write <= 1'd0;
+	case (builder_bankmachine0_state)
+		1'd1: begin
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+			if (main_litedramcore_bankmachine0_refresh_req) begin
+			end else begin
+				if (main_litedramcore_bankmachine0_cmd_buffer_source_valid) begin
+					if (main_litedramcore_bankmachine0_row_opened) begin
+						if (main_litedramcore_bankmachine0_row_hit) begin
+							if (main_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
+								main_litedramcore_bankmachine0_cmd_payload_is_write <= 1'd1;
+							end else begin
+							end
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_148 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_149;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine0_req_wdata_ready <= 1'd0;
+	case (builder_bankmachine0_state)
+		1'd1: begin
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+			if (main_litedramcore_bankmachine0_refresh_req) begin
+			end else begin
+				if (main_litedramcore_bankmachine0_cmd_buffer_source_valid) begin
+					if (main_litedramcore_bankmachine0_row_opened) begin
+						if (main_litedramcore_bankmachine0_row_hit) begin
+							if (main_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
+								main_litedramcore_bankmachine0_req_wdata_ready <= main_litedramcore_bankmachine0_cmd_ready;
+							end else begin
+							end
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_149 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_150;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine0_refresh_gnt <= 1'd0;
+	case (builder_bankmachine0_state)
+		1'd1: begin
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+		end
+		3'd4: begin
+			if (main_litedramcore_bankmachine0_twtpcon_ready) begin
+				main_litedramcore_bankmachine0_refresh_gnt <= 1'd1;
+			end
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_150 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_151;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine0_cmd_valid <= 1'd0;
+	case (builder_bankmachine0_state)
+		1'd1: begin
+			if ((main_litedramcore_bankmachine0_twtpcon_ready & main_litedramcore_bankmachine0_trascon_ready)) begin
+				main_litedramcore_bankmachine0_cmd_valid <= 1'd1;
+			end
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+			if (main_litedramcore_bankmachine0_trccon_ready) begin
+				main_litedramcore_bankmachine0_cmd_valid <= 1'd1;
+			end
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+			if (main_litedramcore_bankmachine0_refresh_req) begin
+			end else begin
+				if (main_litedramcore_bankmachine0_cmd_buffer_source_valid) begin
+					if (main_litedramcore_bankmachine0_row_opened) begin
+						if (main_litedramcore_bankmachine0_row_hit) begin
+							main_litedramcore_bankmachine0_cmd_valid <= 1'd1;
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_151 = dummy_s;
+// synthesis translate_on
+end
+assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine1_req_valid;
+assign main_litedramcore_bankmachine1_req_ready = main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready;
+assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we = main_litedramcore_bankmachine1_req_we;
+assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr = main_litedramcore_bankmachine1_req_addr;
+assign main_litedramcore_bankmachine1_cmd_buffer_sink_valid = main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid;
+assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready = main_litedramcore_bankmachine1_cmd_buffer_sink_ready;
+assign main_litedramcore_bankmachine1_cmd_buffer_sink_first = main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_first;
+assign main_litedramcore_bankmachine1_cmd_buffer_sink_last = main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_last;
+assign main_litedramcore_bankmachine1_cmd_buffer_sink_payload_we = main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we;
+assign main_litedramcore_bankmachine1_cmd_buffer_sink_payload_addr = main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr;
+assign main_litedramcore_bankmachine1_cmd_buffer_source_ready = (main_litedramcore_bankmachine1_req_wdata_ready | main_litedramcore_bankmachine1_req_rdata_valid);
+assign main_litedramcore_bankmachine1_req_lock = (main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid | main_litedramcore_bankmachine1_cmd_buffer_source_valid);
+assign main_litedramcore_bankmachine1_row_hit = (main_litedramcore_bankmachine1_row == main_litedramcore_bankmachine1_cmd_buffer_source_payload_addr[20:7]);
+assign main_litedramcore_bankmachine1_cmd_payload_ba = 1'd1;
+
+// synthesis translate_off
+reg dummy_d_152;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine1_cmd_payload_a <= 14'd0;
+	if (main_litedramcore_bankmachine1_row_col_n_addr_sel) begin
+		main_litedramcore_bankmachine1_cmd_payload_a <= main_litedramcore_bankmachine1_cmd_buffer_source_payload_addr[20:7];
+	end else begin
+		main_litedramcore_bankmachine1_cmd_payload_a <= ((main_litedramcore_bankmachine1_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine1_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
+	end
+// synthesis translate_off
+	dummy_d_152 = dummy_s;
+// synthesis translate_on
+end
+assign main_litedramcore_bankmachine1_twtpcon_valid = ((main_litedramcore_bankmachine1_cmd_valid & main_litedramcore_bankmachine1_cmd_ready) & main_litedramcore_bankmachine1_cmd_payload_is_write);
+assign main_litedramcore_bankmachine1_trccon_valid = ((main_litedramcore_bankmachine1_cmd_valid & main_litedramcore_bankmachine1_cmd_ready) & main_litedramcore_bankmachine1_row_open);
+assign main_litedramcore_bankmachine1_trascon_valid = ((main_litedramcore_bankmachine1_cmd_valid & main_litedramcore_bankmachine1_cmd_ready) & main_litedramcore_bankmachine1_row_open);
+
+// synthesis translate_off
+reg dummy_d_153;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine1_auto_precharge <= 1'd0;
+	if ((main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid & main_litedramcore_bankmachine1_cmd_buffer_source_valid)) begin
+		if ((main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr[20:7] != main_litedramcore_bankmachine1_cmd_buffer_source_payload_addr[20:7])) begin
+			main_litedramcore_bankmachine1_auto_precharge <= (main_litedramcore_bankmachine1_row_close == 1'd0);
+		end
+	end
+// synthesis translate_off
+	dummy_d_153 = dummy_s;
+// synthesis translate_on
+end
+assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din = {main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we};
+assign {main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
+assign {main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
+assign {main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
+assign {main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
+assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready = main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable;
+assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we = main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid;
+assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first = main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_first;
+assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last = main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_last;
+assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we = main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we;
+assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr = main_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr;
+assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid = main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable;
+assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_first = main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first;
+assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_last = main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last;
+assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we = main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we;
+assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr = main_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr;
+assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re = main_litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready;
+
+// synthesis translate_off
+reg dummy_d_154;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= 4'd0;
+	if (main_litedramcore_bankmachine1_cmd_buffer_lookahead_replace) begin
+		main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= (main_litedramcore_bankmachine1_cmd_buffer_lookahead_produce - 1'd1);
+	end else begin
+		main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= main_litedramcore_bankmachine1_cmd_buffer_lookahead_produce;
+	end
+// synthesis translate_off
+	dummy_d_154 = dummy_s;
+// synthesis translate_on
+end
+assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w = main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din;
+assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we = (main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & (main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable | main_litedramcore_bankmachine1_cmd_buffer_lookahead_replace));
+assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_do_read = (main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable & main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re);
+assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr = main_litedramcore_bankmachine1_cmd_buffer_lookahead_consume;
+assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout = main_litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r;
+assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable = (main_litedramcore_bankmachine1_cmd_buffer_lookahead_level != 5'd16);
+assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable = (main_litedramcore_bankmachine1_cmd_buffer_lookahead_level != 1'd0);
+assign main_litedramcore_bankmachine1_cmd_buffer_sink_ready = ((~main_litedramcore_bankmachine1_cmd_buffer_source_valid) | main_litedramcore_bankmachine1_cmd_buffer_source_ready);
+
+// synthesis translate_off
+reg dummy_d_155;
+// synthesis translate_on
+always @(*) begin
+	builder_bankmachine1_next_state <= 4'd0;
+	builder_bankmachine1_next_state <= builder_bankmachine1_state;
+	case (builder_bankmachine1_state)
+		1'd1: begin
+			if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin
+				if (main_litedramcore_bankmachine1_cmd_ready) begin
+					builder_bankmachine1_next_state <= 3'd5;
+				end
+			end
+		end
+		2'd2: begin
+			if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin
+				builder_bankmachine1_next_state <= 3'd5;
+			end
+		end
+		2'd3: begin
+			if (main_litedramcore_bankmachine1_trccon_ready) begin
+				if (main_litedramcore_bankmachine1_cmd_ready) begin
+					builder_bankmachine1_next_state <= 3'd7;
+				end
+			end
+		end
+		3'd4: begin
+			if ((~main_litedramcore_bankmachine1_refresh_req)) begin
+				builder_bankmachine1_next_state <= 1'd0;
+			end
+		end
+		3'd5: begin
+			builder_bankmachine1_next_state <= 3'd6;
+		end
+		3'd6: begin
+			builder_bankmachine1_next_state <= 2'd3;
+		end
+		3'd7: begin
+			builder_bankmachine1_next_state <= 4'd8;
+		end
+		4'd8: begin
+			builder_bankmachine1_next_state <= 1'd0;
+		end
+		default: begin
+			if (main_litedramcore_bankmachine1_refresh_req) begin
+				builder_bankmachine1_next_state <= 3'd4;
+			end else begin
+				if (main_litedramcore_bankmachine1_cmd_buffer_source_valid) begin
+					if (main_litedramcore_bankmachine1_row_opened) begin
+						if (main_litedramcore_bankmachine1_row_hit) begin
+							if ((main_litedramcore_bankmachine1_cmd_ready & main_litedramcore_bankmachine1_auto_precharge)) begin
+								builder_bankmachine1_next_state <= 2'd2;
+							end
+						end else begin
+							builder_bankmachine1_next_state <= 1'd1;
+						end
+					end else begin
+						builder_bankmachine1_next_state <= 2'd3;
+					end
+				end
+			end
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_155 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_156;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine1_row_open <= 1'd0;
+	case (builder_bankmachine1_state)
+		1'd1: begin
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+			if (main_litedramcore_bankmachine1_trccon_ready) begin
+				main_litedramcore_bankmachine1_row_open <= 1'd1;
+			end
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_156 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_157;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine1_row_close <= 1'd0;
+	case (builder_bankmachine1_state)
+		1'd1: begin
+			main_litedramcore_bankmachine1_row_close <= 1'd1;
+		end
+		2'd2: begin
+			main_litedramcore_bankmachine1_row_close <= 1'd1;
+		end
+		2'd3: begin
+		end
+		3'd4: begin
+			main_litedramcore_bankmachine1_row_close <= 1'd1;
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_157 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_158;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine1_cmd_payload_cas <= 1'd0;
+	case (builder_bankmachine1_state)
+		1'd1: begin
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+			if (main_litedramcore_bankmachine1_refresh_req) begin
+			end else begin
+				if (main_litedramcore_bankmachine1_cmd_buffer_source_valid) begin
+					if (main_litedramcore_bankmachine1_row_opened) begin
+						if (main_litedramcore_bankmachine1_row_hit) begin
+							main_litedramcore_bankmachine1_cmd_payload_cas <= 1'd1;
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_158 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_159;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine1_cmd_payload_ras <= 1'd0;
+	case (builder_bankmachine1_state)
+		1'd1: begin
+			if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin
+				main_litedramcore_bankmachine1_cmd_payload_ras <= 1'd1;
+			end
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+			if (main_litedramcore_bankmachine1_trccon_ready) begin
+				main_litedramcore_bankmachine1_cmd_payload_ras <= 1'd1;
+			end
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_159 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_160;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine1_cmd_payload_we <= 1'd0;
+	case (builder_bankmachine1_state)
+		1'd1: begin
+			if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin
+				main_litedramcore_bankmachine1_cmd_payload_we <= 1'd1;
+			end
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+			if (main_litedramcore_bankmachine1_refresh_req) begin
+			end else begin
+				if (main_litedramcore_bankmachine1_cmd_buffer_source_valid) begin
+					if (main_litedramcore_bankmachine1_row_opened) begin
+						if (main_litedramcore_bankmachine1_row_hit) begin
+							if (main_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
+								main_litedramcore_bankmachine1_cmd_payload_we <= 1'd1;
+							end else begin
+							end
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_160 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_161;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd0;
+	case (builder_bankmachine1_state)
+		1'd1: begin
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+			if (main_litedramcore_bankmachine1_trccon_ready) begin
+				main_litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd1;
+			end
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_161 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_162;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd0;
+	case (builder_bankmachine1_state)
+		1'd1: begin
+			if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin
+				main_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
+			end
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+			if (main_litedramcore_bankmachine1_trccon_ready) begin
+				main_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
+			end
+		end
+		3'd4: begin
+			main_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_162 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_163;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine1_refresh_gnt <= 1'd0;
+	case (builder_bankmachine1_state)
+		1'd1: begin
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+		end
+		3'd4: begin
+			if (main_litedramcore_bankmachine1_twtpcon_ready) begin
+				main_litedramcore_bankmachine1_refresh_gnt <= 1'd1;
+			end
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_163 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_164;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine1_cmd_payload_is_read <= 1'd0;
+	case (builder_bankmachine1_state)
+		1'd1: begin
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+			if (main_litedramcore_bankmachine1_refresh_req) begin
+			end else begin
+				if (main_litedramcore_bankmachine1_cmd_buffer_source_valid) begin
+					if (main_litedramcore_bankmachine1_row_opened) begin
+						if (main_litedramcore_bankmachine1_row_hit) begin
+							if (main_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
+							end else begin
+								main_litedramcore_bankmachine1_cmd_payload_is_read <= 1'd1;
+							end
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_164 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_165;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine1_cmd_payload_is_write <= 1'd0;
+	case (builder_bankmachine1_state)
+		1'd1: begin
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+			if (main_litedramcore_bankmachine1_refresh_req) begin
+			end else begin
+				if (main_litedramcore_bankmachine1_cmd_buffer_source_valid) begin
+					if (main_litedramcore_bankmachine1_row_opened) begin
+						if (main_litedramcore_bankmachine1_row_hit) begin
+							if (main_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
+								main_litedramcore_bankmachine1_cmd_payload_is_write <= 1'd1;
+							end else begin
+							end
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_165 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_166;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine1_req_wdata_ready <= 1'd0;
+	case (builder_bankmachine1_state)
+		1'd1: begin
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+			if (main_litedramcore_bankmachine1_refresh_req) begin
+			end else begin
+				if (main_litedramcore_bankmachine1_cmd_buffer_source_valid) begin
+					if (main_litedramcore_bankmachine1_row_opened) begin
+						if (main_litedramcore_bankmachine1_row_hit) begin
+							if (main_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
+								main_litedramcore_bankmachine1_req_wdata_ready <= main_litedramcore_bankmachine1_cmd_ready;
+							end else begin
+							end
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_166 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_167;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine1_req_rdata_valid <= 1'd0;
+	case (builder_bankmachine1_state)
+		1'd1: begin
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+			if (main_litedramcore_bankmachine1_refresh_req) begin
+			end else begin
+				if (main_litedramcore_bankmachine1_cmd_buffer_source_valid) begin
+					if (main_litedramcore_bankmachine1_row_opened) begin
+						if (main_litedramcore_bankmachine1_row_hit) begin
+							if (main_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
+							end else begin
+								main_litedramcore_bankmachine1_req_rdata_valid <= main_litedramcore_bankmachine1_cmd_ready;
+							end
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_167 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_168;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine1_cmd_valid <= 1'd0;
+	case (builder_bankmachine1_state)
+		1'd1: begin
+			if ((main_litedramcore_bankmachine1_twtpcon_ready & main_litedramcore_bankmachine1_trascon_ready)) begin
+				main_litedramcore_bankmachine1_cmd_valid <= 1'd1;
+			end
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+			if (main_litedramcore_bankmachine1_trccon_ready) begin
+				main_litedramcore_bankmachine1_cmd_valid <= 1'd1;
+			end
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+			if (main_litedramcore_bankmachine1_refresh_req) begin
+			end else begin
+				if (main_litedramcore_bankmachine1_cmd_buffer_source_valid) begin
+					if (main_litedramcore_bankmachine1_row_opened) begin
+						if (main_litedramcore_bankmachine1_row_hit) begin
+							main_litedramcore_bankmachine1_cmd_valid <= 1'd1;
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_168 = dummy_s;
+// synthesis translate_on
+end
+assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine2_req_valid;
+assign main_litedramcore_bankmachine2_req_ready = main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready;
+assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we = main_litedramcore_bankmachine2_req_we;
+assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr = main_litedramcore_bankmachine2_req_addr;
+assign main_litedramcore_bankmachine2_cmd_buffer_sink_valid = main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid;
+assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready = main_litedramcore_bankmachine2_cmd_buffer_sink_ready;
+assign main_litedramcore_bankmachine2_cmd_buffer_sink_first = main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_first;
+assign main_litedramcore_bankmachine2_cmd_buffer_sink_last = main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_last;
+assign main_litedramcore_bankmachine2_cmd_buffer_sink_payload_we = main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we;
+assign main_litedramcore_bankmachine2_cmd_buffer_sink_payload_addr = main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr;
+assign main_litedramcore_bankmachine2_cmd_buffer_source_ready = (main_litedramcore_bankmachine2_req_wdata_ready | main_litedramcore_bankmachine2_req_rdata_valid);
+assign main_litedramcore_bankmachine2_req_lock = (main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid | main_litedramcore_bankmachine2_cmd_buffer_source_valid);
+assign main_litedramcore_bankmachine2_row_hit = (main_litedramcore_bankmachine2_row == main_litedramcore_bankmachine2_cmd_buffer_source_payload_addr[20:7]);
+assign main_litedramcore_bankmachine2_cmd_payload_ba = 2'd2;
+
+// synthesis translate_off
+reg dummy_d_169;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine2_cmd_payload_a <= 14'd0;
+	if (main_litedramcore_bankmachine2_row_col_n_addr_sel) begin
+		main_litedramcore_bankmachine2_cmd_payload_a <= main_litedramcore_bankmachine2_cmd_buffer_source_payload_addr[20:7];
+	end else begin
+		main_litedramcore_bankmachine2_cmd_payload_a <= ((main_litedramcore_bankmachine2_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine2_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
+	end
+// synthesis translate_off
+	dummy_d_169 = dummy_s;
+// synthesis translate_on
+end
+assign main_litedramcore_bankmachine2_twtpcon_valid = ((main_litedramcore_bankmachine2_cmd_valid & main_litedramcore_bankmachine2_cmd_ready) & main_litedramcore_bankmachine2_cmd_payload_is_write);
+assign main_litedramcore_bankmachine2_trccon_valid = ((main_litedramcore_bankmachine2_cmd_valid & main_litedramcore_bankmachine2_cmd_ready) & main_litedramcore_bankmachine2_row_open);
+assign main_litedramcore_bankmachine2_trascon_valid = ((main_litedramcore_bankmachine2_cmd_valid & main_litedramcore_bankmachine2_cmd_ready) & main_litedramcore_bankmachine2_row_open);
+
+// synthesis translate_off
+reg dummy_d_170;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine2_auto_precharge <= 1'd0;
+	if ((main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid & main_litedramcore_bankmachine2_cmd_buffer_source_valid)) begin
+		if ((main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr[20:7] != main_litedramcore_bankmachine2_cmd_buffer_source_payload_addr[20:7])) begin
+			main_litedramcore_bankmachine2_auto_precharge <= (main_litedramcore_bankmachine2_row_close == 1'd0);
+		end
+	end
+// synthesis translate_off
+	dummy_d_170 = dummy_s;
+// synthesis translate_on
+end
+assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din = {main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we};
+assign {main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
+assign {main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
+assign {main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
+assign {main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
+assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready = main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable;
+assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we = main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid;
+assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first = main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_first;
+assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last = main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_last;
+assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we = main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we;
+assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr = main_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr;
+assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid = main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable;
+assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_first = main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first;
+assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_last = main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last;
+assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we = main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we;
+assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr = main_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr;
+assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re = main_litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready;
+
+// synthesis translate_off
+reg dummy_d_171;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= 4'd0;
+	if (main_litedramcore_bankmachine2_cmd_buffer_lookahead_replace) begin
+		main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= (main_litedramcore_bankmachine2_cmd_buffer_lookahead_produce - 1'd1);
+	end else begin
+		main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= main_litedramcore_bankmachine2_cmd_buffer_lookahead_produce;
+	end
+// synthesis translate_off
+	dummy_d_171 = dummy_s;
+// synthesis translate_on
+end
+assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w = main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din;
+assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we = (main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & (main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable | main_litedramcore_bankmachine2_cmd_buffer_lookahead_replace));
+assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_do_read = (main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable & main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re);
+assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr = main_litedramcore_bankmachine2_cmd_buffer_lookahead_consume;
+assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout = main_litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r;
+assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable = (main_litedramcore_bankmachine2_cmd_buffer_lookahead_level != 5'd16);
+assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable = (main_litedramcore_bankmachine2_cmd_buffer_lookahead_level != 1'd0);
+assign main_litedramcore_bankmachine2_cmd_buffer_sink_ready = ((~main_litedramcore_bankmachine2_cmd_buffer_source_valid) | main_litedramcore_bankmachine2_cmd_buffer_source_ready);
+
+// synthesis translate_off
+reg dummy_d_172;
+// synthesis translate_on
+always @(*) begin
+	builder_bankmachine2_next_state <= 4'd0;
+	builder_bankmachine2_next_state <= builder_bankmachine2_state;
+	case (builder_bankmachine2_state)
+		1'd1: begin
+			if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin
+				if (main_litedramcore_bankmachine2_cmd_ready) begin
+					builder_bankmachine2_next_state <= 3'd5;
+				end
+			end
+		end
+		2'd2: begin
+			if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin
+				builder_bankmachine2_next_state <= 3'd5;
+			end
+		end
+		2'd3: begin
+			if (main_litedramcore_bankmachine2_trccon_ready) begin
+				if (main_litedramcore_bankmachine2_cmd_ready) begin
+					builder_bankmachine2_next_state <= 3'd7;
+				end
+			end
+		end
+		3'd4: begin
+			if ((~main_litedramcore_bankmachine2_refresh_req)) begin
+				builder_bankmachine2_next_state <= 1'd0;
+			end
+		end
+		3'd5: begin
+			builder_bankmachine2_next_state <= 3'd6;
+		end
+		3'd6: begin
+			builder_bankmachine2_next_state <= 2'd3;
+		end
+		3'd7: begin
+			builder_bankmachine2_next_state <= 4'd8;
+		end
+		4'd8: begin
+			builder_bankmachine2_next_state <= 1'd0;
+		end
+		default: begin
+			if (main_litedramcore_bankmachine2_refresh_req) begin
+				builder_bankmachine2_next_state <= 3'd4;
+			end else begin
+				if (main_litedramcore_bankmachine2_cmd_buffer_source_valid) begin
+					if (main_litedramcore_bankmachine2_row_opened) begin
+						if (main_litedramcore_bankmachine2_row_hit) begin
+							if ((main_litedramcore_bankmachine2_cmd_ready & main_litedramcore_bankmachine2_auto_precharge)) begin
+								builder_bankmachine2_next_state <= 2'd2;
+							end
+						end else begin
+							builder_bankmachine2_next_state <= 1'd1;
+						end
+					end else begin
+						builder_bankmachine2_next_state <= 2'd3;
+					end
+				end
+			end
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_172 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_173;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine2_req_rdata_valid <= 1'd0;
+	case (builder_bankmachine2_state)
+		1'd1: begin
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+			if (main_litedramcore_bankmachine2_refresh_req) begin
+			end else begin
+				if (main_litedramcore_bankmachine2_cmd_buffer_source_valid) begin
+					if (main_litedramcore_bankmachine2_row_opened) begin
+						if (main_litedramcore_bankmachine2_row_hit) begin
+							if (main_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
+							end else begin
+								main_litedramcore_bankmachine2_req_rdata_valid <= main_litedramcore_bankmachine2_cmd_ready;
+							end
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_173 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_174;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine2_row_open <= 1'd0;
+	case (builder_bankmachine2_state)
+		1'd1: begin
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+			if (main_litedramcore_bankmachine2_trccon_ready) begin
+				main_litedramcore_bankmachine2_row_open <= 1'd1;
+			end
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_174 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_175;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine2_row_close <= 1'd0;
+	case (builder_bankmachine2_state)
+		1'd1: begin
+			main_litedramcore_bankmachine2_row_close <= 1'd1;
+		end
+		2'd2: begin
+			main_litedramcore_bankmachine2_row_close <= 1'd1;
+		end
+		2'd3: begin
+		end
+		3'd4: begin
+			main_litedramcore_bankmachine2_row_close <= 1'd1;
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_175 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_176;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine2_cmd_payload_cas <= 1'd0;
+	case (builder_bankmachine2_state)
+		1'd1: begin
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+			if (main_litedramcore_bankmachine2_refresh_req) begin
+			end else begin
+				if (main_litedramcore_bankmachine2_cmd_buffer_source_valid) begin
+					if (main_litedramcore_bankmachine2_row_opened) begin
+						if (main_litedramcore_bankmachine2_row_hit) begin
+							main_litedramcore_bankmachine2_cmd_payload_cas <= 1'd1;
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_176 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_177;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine2_cmd_payload_ras <= 1'd0;
+	case (builder_bankmachine2_state)
+		1'd1: begin
+			if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin
+				main_litedramcore_bankmachine2_cmd_payload_ras <= 1'd1;
+			end
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+			if (main_litedramcore_bankmachine2_trccon_ready) begin
+				main_litedramcore_bankmachine2_cmd_payload_ras <= 1'd1;
+			end
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_177 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_178;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine2_cmd_payload_we <= 1'd0;
+	case (builder_bankmachine2_state)
+		1'd1: begin
+			if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin
+				main_litedramcore_bankmachine2_cmd_payload_we <= 1'd1;
+			end
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+			if (main_litedramcore_bankmachine2_refresh_req) begin
+			end else begin
+				if (main_litedramcore_bankmachine2_cmd_buffer_source_valid) begin
+					if (main_litedramcore_bankmachine2_row_opened) begin
+						if (main_litedramcore_bankmachine2_row_hit) begin
+							if (main_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
+								main_litedramcore_bankmachine2_cmd_payload_we <= 1'd1;
+							end else begin
+							end
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_178 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_179;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd0;
+	case (builder_bankmachine2_state)
+		1'd1: begin
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+			if (main_litedramcore_bankmachine2_trccon_ready) begin
+				main_litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd1;
+			end
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_179 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_180;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd0;
+	case (builder_bankmachine2_state)
+		1'd1: begin
+			if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin
+				main_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
+			end
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+			if (main_litedramcore_bankmachine2_trccon_ready) begin
+				main_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
+			end
+		end
+		3'd4: begin
+			main_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_180 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_181;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine2_cmd_payload_is_read <= 1'd0;
+	case (builder_bankmachine2_state)
+		1'd1: begin
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+			if (main_litedramcore_bankmachine2_refresh_req) begin
+			end else begin
+				if (main_litedramcore_bankmachine2_cmd_buffer_source_valid) begin
+					if (main_litedramcore_bankmachine2_row_opened) begin
+						if (main_litedramcore_bankmachine2_row_hit) begin
+							if (main_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
+							end else begin
+								main_litedramcore_bankmachine2_cmd_payload_is_read <= 1'd1;
+							end
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_181 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_182;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine2_cmd_payload_is_write <= 1'd0;
+	case (builder_bankmachine2_state)
+		1'd1: begin
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+			if (main_litedramcore_bankmachine2_refresh_req) begin
+			end else begin
+				if (main_litedramcore_bankmachine2_cmd_buffer_source_valid) begin
+					if (main_litedramcore_bankmachine2_row_opened) begin
+						if (main_litedramcore_bankmachine2_row_hit) begin
+							if (main_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
+								main_litedramcore_bankmachine2_cmd_payload_is_write <= 1'd1;
+							end else begin
+							end
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_182 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_183;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine2_req_wdata_ready <= 1'd0;
+	case (builder_bankmachine2_state)
+		1'd1: begin
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+			if (main_litedramcore_bankmachine2_refresh_req) begin
+			end else begin
+				if (main_litedramcore_bankmachine2_cmd_buffer_source_valid) begin
+					if (main_litedramcore_bankmachine2_row_opened) begin
+						if (main_litedramcore_bankmachine2_row_hit) begin
+							if (main_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
+								main_litedramcore_bankmachine2_req_wdata_ready <= main_litedramcore_bankmachine2_cmd_ready;
+							end else begin
+							end
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_183 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_184;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine2_refresh_gnt <= 1'd0;
+	case (builder_bankmachine2_state)
+		1'd1: begin
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+		end
+		3'd4: begin
+			if (main_litedramcore_bankmachine2_twtpcon_ready) begin
+				main_litedramcore_bankmachine2_refresh_gnt <= 1'd1;
+			end
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_184 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_185;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine2_cmd_valid <= 1'd0;
+	case (builder_bankmachine2_state)
+		1'd1: begin
+			if ((main_litedramcore_bankmachine2_twtpcon_ready & main_litedramcore_bankmachine2_trascon_ready)) begin
+				main_litedramcore_bankmachine2_cmd_valid <= 1'd1;
+			end
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+			if (main_litedramcore_bankmachine2_trccon_ready) begin
+				main_litedramcore_bankmachine2_cmd_valid <= 1'd1;
+			end
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+			if (main_litedramcore_bankmachine2_refresh_req) begin
+			end else begin
+				if (main_litedramcore_bankmachine2_cmd_buffer_source_valid) begin
+					if (main_litedramcore_bankmachine2_row_opened) begin
+						if (main_litedramcore_bankmachine2_row_hit) begin
+							main_litedramcore_bankmachine2_cmd_valid <= 1'd1;
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_185 = dummy_s;
+// synthesis translate_on
+end
+assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine3_req_valid;
+assign main_litedramcore_bankmachine3_req_ready = main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready;
+assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we = main_litedramcore_bankmachine3_req_we;
+assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr = main_litedramcore_bankmachine3_req_addr;
+assign main_litedramcore_bankmachine3_cmd_buffer_sink_valid = main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid;
+assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready = main_litedramcore_bankmachine3_cmd_buffer_sink_ready;
+assign main_litedramcore_bankmachine3_cmd_buffer_sink_first = main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_first;
+assign main_litedramcore_bankmachine3_cmd_buffer_sink_last = main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_last;
+assign main_litedramcore_bankmachine3_cmd_buffer_sink_payload_we = main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we;
+assign main_litedramcore_bankmachine3_cmd_buffer_sink_payload_addr = main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr;
+assign main_litedramcore_bankmachine3_cmd_buffer_source_ready = (main_litedramcore_bankmachine3_req_wdata_ready | main_litedramcore_bankmachine3_req_rdata_valid);
+assign main_litedramcore_bankmachine3_req_lock = (main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid | main_litedramcore_bankmachine3_cmd_buffer_source_valid);
+assign main_litedramcore_bankmachine3_row_hit = (main_litedramcore_bankmachine3_row == main_litedramcore_bankmachine3_cmd_buffer_source_payload_addr[20:7]);
+assign main_litedramcore_bankmachine3_cmd_payload_ba = 2'd3;
+
+// synthesis translate_off
+reg dummy_d_186;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine3_cmd_payload_a <= 14'd0;
+	if (main_litedramcore_bankmachine3_row_col_n_addr_sel) begin
+		main_litedramcore_bankmachine3_cmd_payload_a <= main_litedramcore_bankmachine3_cmd_buffer_source_payload_addr[20:7];
+	end else begin
+		main_litedramcore_bankmachine3_cmd_payload_a <= ((main_litedramcore_bankmachine3_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine3_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
+	end
+// synthesis translate_off
+	dummy_d_186 = dummy_s;
+// synthesis translate_on
+end
+assign main_litedramcore_bankmachine3_twtpcon_valid = ((main_litedramcore_bankmachine3_cmd_valid & main_litedramcore_bankmachine3_cmd_ready) & main_litedramcore_bankmachine3_cmd_payload_is_write);
+assign main_litedramcore_bankmachine3_trccon_valid = ((main_litedramcore_bankmachine3_cmd_valid & main_litedramcore_bankmachine3_cmd_ready) & main_litedramcore_bankmachine3_row_open);
+assign main_litedramcore_bankmachine3_trascon_valid = ((main_litedramcore_bankmachine3_cmd_valid & main_litedramcore_bankmachine3_cmd_ready) & main_litedramcore_bankmachine3_row_open);
+
+// synthesis translate_off
+reg dummy_d_187;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine3_auto_precharge <= 1'd0;
+	if ((main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid & main_litedramcore_bankmachine3_cmd_buffer_source_valid)) begin
+		if ((main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr[20:7] != main_litedramcore_bankmachine3_cmd_buffer_source_payload_addr[20:7])) begin
+			main_litedramcore_bankmachine3_auto_precharge <= (main_litedramcore_bankmachine3_row_close == 1'd0);
+		end
+	end
+// synthesis translate_off
+	dummy_d_187 = dummy_s;
+// synthesis translate_on
+end
+assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din = {main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we};
+assign {main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
+assign {main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
+assign {main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
+assign {main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
+assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready = main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable;
+assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we = main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid;
+assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first = main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_first;
+assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last = main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_last;
+assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we = main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we;
+assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr = main_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr;
+assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid = main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable;
+assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_first = main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first;
+assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_last = main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last;
+assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we = main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we;
+assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr = main_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr;
+assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re = main_litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready;
+
+// synthesis translate_off
+reg dummy_d_188;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= 4'd0;
+	if (main_litedramcore_bankmachine3_cmd_buffer_lookahead_replace) begin
+		main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= (main_litedramcore_bankmachine3_cmd_buffer_lookahead_produce - 1'd1);
+	end else begin
+		main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= main_litedramcore_bankmachine3_cmd_buffer_lookahead_produce;
+	end
+// synthesis translate_off
+	dummy_d_188 = dummy_s;
+// synthesis translate_on
+end
+assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w = main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din;
+assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we = (main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & (main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable | main_litedramcore_bankmachine3_cmd_buffer_lookahead_replace));
+assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_do_read = (main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable & main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re);
+assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr = main_litedramcore_bankmachine3_cmd_buffer_lookahead_consume;
+assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout = main_litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r;
+assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable = (main_litedramcore_bankmachine3_cmd_buffer_lookahead_level != 5'd16);
+assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable = (main_litedramcore_bankmachine3_cmd_buffer_lookahead_level != 1'd0);
+assign main_litedramcore_bankmachine3_cmd_buffer_sink_ready = ((~main_litedramcore_bankmachine3_cmd_buffer_source_valid) | main_litedramcore_bankmachine3_cmd_buffer_source_ready);
+
+// synthesis translate_off
+reg dummy_d_189;
+// synthesis translate_on
+always @(*) begin
+	builder_bankmachine3_next_state <= 4'd0;
+	builder_bankmachine3_next_state <= builder_bankmachine3_state;
+	case (builder_bankmachine3_state)
+		1'd1: begin
+			if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin
+				if (main_litedramcore_bankmachine3_cmd_ready) begin
+					builder_bankmachine3_next_state <= 3'd5;
+				end
+			end
+		end
+		2'd2: begin
+			if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin
+				builder_bankmachine3_next_state <= 3'd5;
+			end
+		end
+		2'd3: begin
+			if (main_litedramcore_bankmachine3_trccon_ready) begin
+				if (main_litedramcore_bankmachine3_cmd_ready) begin
+					builder_bankmachine3_next_state <= 3'd7;
+				end
+			end
+		end
+		3'd4: begin
+			if ((~main_litedramcore_bankmachine3_refresh_req)) begin
+				builder_bankmachine3_next_state <= 1'd0;
+			end
+		end
+		3'd5: begin
+			builder_bankmachine3_next_state <= 3'd6;
+		end
+		3'd6: begin
+			builder_bankmachine3_next_state <= 2'd3;
+		end
+		3'd7: begin
+			builder_bankmachine3_next_state <= 4'd8;
+		end
+		4'd8: begin
+			builder_bankmachine3_next_state <= 1'd0;
+		end
+		default: begin
+			if (main_litedramcore_bankmachine3_refresh_req) begin
+				builder_bankmachine3_next_state <= 3'd4;
+			end else begin
+				if (main_litedramcore_bankmachine3_cmd_buffer_source_valid) begin
+					if (main_litedramcore_bankmachine3_row_opened) begin
+						if (main_litedramcore_bankmachine3_row_hit) begin
+							if ((main_litedramcore_bankmachine3_cmd_ready & main_litedramcore_bankmachine3_auto_precharge)) begin
+								builder_bankmachine3_next_state <= 2'd2;
+							end
+						end else begin
+							builder_bankmachine3_next_state <= 1'd1;
+						end
+					end else begin
+						builder_bankmachine3_next_state <= 2'd3;
+					end
+				end
+			end
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_189 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_190;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine3_row_open <= 1'd0;
+	case (builder_bankmachine3_state)
+		1'd1: begin
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+			if (main_litedramcore_bankmachine3_trccon_ready) begin
+				main_litedramcore_bankmachine3_row_open <= 1'd1;
+			end
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_190 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_191;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine3_row_close <= 1'd0;
+	case (builder_bankmachine3_state)
+		1'd1: begin
+			main_litedramcore_bankmachine3_row_close <= 1'd1;
+		end
+		2'd2: begin
+			main_litedramcore_bankmachine3_row_close <= 1'd1;
+		end
+		2'd3: begin
+		end
+		3'd4: begin
+			main_litedramcore_bankmachine3_row_close <= 1'd1;
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_191 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_192;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine3_cmd_payload_cas <= 1'd0;
+	case (builder_bankmachine3_state)
+		1'd1: begin
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+			if (main_litedramcore_bankmachine3_refresh_req) begin
+			end else begin
+				if (main_litedramcore_bankmachine3_cmd_buffer_source_valid) begin
+					if (main_litedramcore_bankmachine3_row_opened) begin
+						if (main_litedramcore_bankmachine3_row_hit) begin
+							main_litedramcore_bankmachine3_cmd_payload_cas <= 1'd1;
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_192 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_193;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine3_cmd_payload_ras <= 1'd0;
+	case (builder_bankmachine3_state)
+		1'd1: begin
+			if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin
+				main_litedramcore_bankmachine3_cmd_payload_ras <= 1'd1;
+			end
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+			if (main_litedramcore_bankmachine3_trccon_ready) begin
+				main_litedramcore_bankmachine3_cmd_payload_ras <= 1'd1;
+			end
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_193 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_194;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine3_cmd_payload_we <= 1'd0;
+	case (builder_bankmachine3_state)
+		1'd1: begin
+			if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin
+				main_litedramcore_bankmachine3_cmd_payload_we <= 1'd1;
+			end
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+			if (main_litedramcore_bankmachine3_refresh_req) begin
+			end else begin
+				if (main_litedramcore_bankmachine3_cmd_buffer_source_valid) begin
+					if (main_litedramcore_bankmachine3_row_opened) begin
+						if (main_litedramcore_bankmachine3_row_hit) begin
+							if (main_litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
+								main_litedramcore_bankmachine3_cmd_payload_we <= 1'd1;
+							end else begin
+							end
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_194 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_195;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine3_req_rdata_valid <= 1'd0;
+	case (builder_bankmachine3_state)
+		1'd1: begin
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+			if (main_litedramcore_bankmachine3_refresh_req) begin
+			end else begin
+				if (main_litedramcore_bankmachine3_cmd_buffer_source_valid) begin
+					if (main_litedramcore_bankmachine3_row_opened) begin
+						if (main_litedramcore_bankmachine3_row_hit) begin
+							if (main_litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
+							end else begin
+								main_litedramcore_bankmachine3_req_rdata_valid <= main_litedramcore_bankmachine3_cmd_ready;
+							end
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_195 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_196;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd0;
+	case (builder_bankmachine3_state)
+		1'd1: begin
+			if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin
+				main_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
+			end
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+			if (main_litedramcore_bankmachine3_trccon_ready) begin
+				main_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
+			end
+		end
+		3'd4: begin
+			main_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_196 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_197;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd0;
+	case (builder_bankmachine3_state)
+		1'd1: begin
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+			if (main_litedramcore_bankmachine3_trccon_ready) begin
+				main_litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd1;
+			end
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_197 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_198;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine3_cmd_payload_is_read <= 1'd0;
+	case (builder_bankmachine3_state)
+		1'd1: begin
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+			if (main_litedramcore_bankmachine3_refresh_req) begin
+			end else begin
+				if (main_litedramcore_bankmachine3_cmd_buffer_source_valid) begin
+					if (main_litedramcore_bankmachine3_row_opened) begin
+						if (main_litedramcore_bankmachine3_row_hit) begin
+							if (main_litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
+							end else begin
+								main_litedramcore_bankmachine3_cmd_payload_is_read <= 1'd1;
+							end
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_198 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_199;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine3_cmd_payload_is_write <= 1'd0;
+	case (builder_bankmachine3_state)
+		1'd1: begin
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+			if (main_litedramcore_bankmachine3_refresh_req) begin
+			end else begin
+				if (main_litedramcore_bankmachine3_cmd_buffer_source_valid) begin
+					if (main_litedramcore_bankmachine3_row_opened) begin
+						if (main_litedramcore_bankmachine3_row_hit) begin
+							if (main_litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
+								main_litedramcore_bankmachine3_cmd_payload_is_write <= 1'd1;
+							end else begin
+							end
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_199 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_200;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine3_req_wdata_ready <= 1'd0;
+	case (builder_bankmachine3_state)
+		1'd1: begin
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+			if (main_litedramcore_bankmachine3_refresh_req) begin
+			end else begin
+				if (main_litedramcore_bankmachine3_cmd_buffer_source_valid) begin
+					if (main_litedramcore_bankmachine3_row_opened) begin
+						if (main_litedramcore_bankmachine3_row_hit) begin
+							if (main_litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
+								main_litedramcore_bankmachine3_req_wdata_ready <= main_litedramcore_bankmachine3_cmd_ready;
+							end else begin
+							end
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_200 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_201;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine3_refresh_gnt <= 1'd0;
+	case (builder_bankmachine3_state)
+		1'd1: begin
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+		end
+		3'd4: begin
+			if (main_litedramcore_bankmachine3_twtpcon_ready) begin
+				main_litedramcore_bankmachine3_refresh_gnt <= 1'd1;
+			end
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_201 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_202;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine3_cmd_valid <= 1'd0;
+	case (builder_bankmachine3_state)
+		1'd1: begin
+			if ((main_litedramcore_bankmachine3_twtpcon_ready & main_litedramcore_bankmachine3_trascon_ready)) begin
+				main_litedramcore_bankmachine3_cmd_valid <= 1'd1;
+			end
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+			if (main_litedramcore_bankmachine3_trccon_ready) begin
+				main_litedramcore_bankmachine3_cmd_valid <= 1'd1;
+			end
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+			if (main_litedramcore_bankmachine3_refresh_req) begin
+			end else begin
+				if (main_litedramcore_bankmachine3_cmd_buffer_source_valid) begin
+					if (main_litedramcore_bankmachine3_row_opened) begin
+						if (main_litedramcore_bankmachine3_row_hit) begin
+							main_litedramcore_bankmachine3_cmd_valid <= 1'd1;
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_202 = dummy_s;
+// synthesis translate_on
+end
+assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine4_req_valid;
+assign main_litedramcore_bankmachine4_req_ready = main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready;
+assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we = main_litedramcore_bankmachine4_req_we;
+assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr = main_litedramcore_bankmachine4_req_addr;
+assign main_litedramcore_bankmachine4_cmd_buffer_sink_valid = main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid;
+assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready = main_litedramcore_bankmachine4_cmd_buffer_sink_ready;
+assign main_litedramcore_bankmachine4_cmd_buffer_sink_first = main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_first;
+assign main_litedramcore_bankmachine4_cmd_buffer_sink_last = main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_last;
+assign main_litedramcore_bankmachine4_cmd_buffer_sink_payload_we = main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we;
+assign main_litedramcore_bankmachine4_cmd_buffer_sink_payload_addr = main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr;
+assign main_litedramcore_bankmachine4_cmd_buffer_source_ready = (main_litedramcore_bankmachine4_req_wdata_ready | main_litedramcore_bankmachine4_req_rdata_valid);
+assign main_litedramcore_bankmachine4_req_lock = (main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid | main_litedramcore_bankmachine4_cmd_buffer_source_valid);
+assign main_litedramcore_bankmachine4_row_hit = (main_litedramcore_bankmachine4_row == main_litedramcore_bankmachine4_cmd_buffer_source_payload_addr[20:7]);
+assign main_litedramcore_bankmachine4_cmd_payload_ba = 3'd4;
+
+// synthesis translate_off
+reg dummy_d_203;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine4_cmd_payload_a <= 14'd0;
+	if (main_litedramcore_bankmachine4_row_col_n_addr_sel) begin
+		main_litedramcore_bankmachine4_cmd_payload_a <= main_litedramcore_bankmachine4_cmd_buffer_source_payload_addr[20:7];
+	end else begin
+		main_litedramcore_bankmachine4_cmd_payload_a <= ((main_litedramcore_bankmachine4_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine4_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
+	end
+// synthesis translate_off
+	dummy_d_203 = dummy_s;
+// synthesis translate_on
+end
+assign main_litedramcore_bankmachine4_twtpcon_valid = ((main_litedramcore_bankmachine4_cmd_valid & main_litedramcore_bankmachine4_cmd_ready) & main_litedramcore_bankmachine4_cmd_payload_is_write);
+assign main_litedramcore_bankmachine4_trccon_valid = ((main_litedramcore_bankmachine4_cmd_valid & main_litedramcore_bankmachine4_cmd_ready) & main_litedramcore_bankmachine4_row_open);
+assign main_litedramcore_bankmachine4_trascon_valid = ((main_litedramcore_bankmachine4_cmd_valid & main_litedramcore_bankmachine4_cmd_ready) & main_litedramcore_bankmachine4_row_open);
+
+// synthesis translate_off
+reg dummy_d_204;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine4_auto_precharge <= 1'd0;
+	if ((main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid & main_litedramcore_bankmachine4_cmd_buffer_source_valid)) begin
+		if ((main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr[20:7] != main_litedramcore_bankmachine4_cmd_buffer_source_payload_addr[20:7])) begin
+			main_litedramcore_bankmachine4_auto_precharge <= (main_litedramcore_bankmachine4_row_close == 1'd0);
+		end
+	end
+// synthesis translate_off
+	dummy_d_204 = dummy_s;
+// synthesis translate_on
+end
+assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din = {main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we};
+assign {main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
+assign {main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
+assign {main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
+assign {main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
+assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready = main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable;
+assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we = main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid;
+assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first = main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_first;
+assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last = main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_last;
+assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we = main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we;
+assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr = main_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr;
+assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid = main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable;
+assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_first = main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first;
+assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_last = main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last;
+assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we = main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we;
+assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr = main_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr;
+assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re = main_litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready;
+
+// synthesis translate_off
+reg dummy_d_205;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= 4'd0;
+	if (main_litedramcore_bankmachine4_cmd_buffer_lookahead_replace) begin
+		main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= (main_litedramcore_bankmachine4_cmd_buffer_lookahead_produce - 1'd1);
+	end else begin
+		main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= main_litedramcore_bankmachine4_cmd_buffer_lookahead_produce;
+	end
+// synthesis translate_off
+	dummy_d_205 = dummy_s;
+// synthesis translate_on
+end
+assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w = main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din;
+assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we = (main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & (main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable | main_litedramcore_bankmachine4_cmd_buffer_lookahead_replace));
+assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_do_read = (main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable & main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re);
+assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr = main_litedramcore_bankmachine4_cmd_buffer_lookahead_consume;
+assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout = main_litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r;
+assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable = (main_litedramcore_bankmachine4_cmd_buffer_lookahead_level != 5'd16);
+assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable = (main_litedramcore_bankmachine4_cmd_buffer_lookahead_level != 1'd0);
+assign main_litedramcore_bankmachine4_cmd_buffer_sink_ready = ((~main_litedramcore_bankmachine4_cmd_buffer_source_valid) | main_litedramcore_bankmachine4_cmd_buffer_source_ready);
+
+// synthesis translate_off
+reg dummy_d_206;
+// synthesis translate_on
+always @(*) begin
+	builder_bankmachine4_next_state <= 4'd0;
+	builder_bankmachine4_next_state <= builder_bankmachine4_state;
+	case (builder_bankmachine4_state)
+		1'd1: begin
+			if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin
+				if (main_litedramcore_bankmachine4_cmd_ready) begin
+					builder_bankmachine4_next_state <= 3'd5;
+				end
+			end
+		end
+		2'd2: begin
+			if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin
+				builder_bankmachine4_next_state <= 3'd5;
+			end
+		end
+		2'd3: begin
+			if (main_litedramcore_bankmachine4_trccon_ready) begin
+				if (main_litedramcore_bankmachine4_cmd_ready) begin
+					builder_bankmachine4_next_state <= 3'd7;
+				end
+			end
+		end
+		3'd4: begin
+			if ((~main_litedramcore_bankmachine4_refresh_req)) begin
+				builder_bankmachine4_next_state <= 1'd0;
+			end
+		end
+		3'd5: begin
+			builder_bankmachine4_next_state <= 3'd6;
+		end
+		3'd6: begin
+			builder_bankmachine4_next_state <= 2'd3;
+		end
+		3'd7: begin
+			builder_bankmachine4_next_state <= 4'd8;
+		end
+		4'd8: begin
+			builder_bankmachine4_next_state <= 1'd0;
+		end
+		default: begin
+			if (main_litedramcore_bankmachine4_refresh_req) begin
+				builder_bankmachine4_next_state <= 3'd4;
+			end else begin
+				if (main_litedramcore_bankmachine4_cmd_buffer_source_valid) begin
+					if (main_litedramcore_bankmachine4_row_opened) begin
+						if (main_litedramcore_bankmachine4_row_hit) begin
+							if ((main_litedramcore_bankmachine4_cmd_ready & main_litedramcore_bankmachine4_auto_precharge)) begin
+								builder_bankmachine4_next_state <= 2'd2;
+							end
+						end else begin
+							builder_bankmachine4_next_state <= 1'd1;
+						end
+					end else begin
+						builder_bankmachine4_next_state <= 2'd3;
+					end
+				end
+			end
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_206 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_207;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine4_row_open <= 1'd0;
+	case (builder_bankmachine4_state)
+		1'd1: begin
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+			if (main_litedramcore_bankmachine4_trccon_ready) begin
+				main_litedramcore_bankmachine4_row_open <= 1'd1;
+			end
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_207 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_208;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine4_row_close <= 1'd0;
+	case (builder_bankmachine4_state)
+		1'd1: begin
+			main_litedramcore_bankmachine4_row_close <= 1'd1;
+		end
+		2'd2: begin
+			main_litedramcore_bankmachine4_row_close <= 1'd1;
+		end
+		2'd3: begin
+		end
+		3'd4: begin
+			main_litedramcore_bankmachine4_row_close <= 1'd1;
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_208 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_209;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine4_cmd_payload_cas <= 1'd0;
+	case (builder_bankmachine4_state)
+		1'd1: begin
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+			if (main_litedramcore_bankmachine4_refresh_req) begin
+			end else begin
+				if (main_litedramcore_bankmachine4_cmd_buffer_source_valid) begin
+					if (main_litedramcore_bankmachine4_row_opened) begin
+						if (main_litedramcore_bankmachine4_row_hit) begin
+							main_litedramcore_bankmachine4_cmd_payload_cas <= 1'd1;
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_209 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_210;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine4_cmd_payload_ras <= 1'd0;
+	case (builder_bankmachine4_state)
+		1'd1: begin
+			if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin
+				main_litedramcore_bankmachine4_cmd_payload_ras <= 1'd1;
+			end
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+			if (main_litedramcore_bankmachine4_trccon_ready) begin
+				main_litedramcore_bankmachine4_cmd_payload_ras <= 1'd1;
+			end
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_210 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_211;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine4_cmd_payload_we <= 1'd0;
+	case (builder_bankmachine4_state)
+		1'd1: begin
+			if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin
+				main_litedramcore_bankmachine4_cmd_payload_we <= 1'd1;
+			end
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+			if (main_litedramcore_bankmachine4_refresh_req) begin
+			end else begin
+				if (main_litedramcore_bankmachine4_cmd_buffer_source_valid) begin
+					if (main_litedramcore_bankmachine4_row_opened) begin
+						if (main_litedramcore_bankmachine4_row_hit) begin
+							if (main_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
+								main_litedramcore_bankmachine4_cmd_payload_we <= 1'd1;
+							end else begin
+							end
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_211 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_212;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd0;
+	case (builder_bankmachine4_state)
+		1'd1: begin
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+			if (main_litedramcore_bankmachine4_trccon_ready) begin
+				main_litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd1;
+			end
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_212 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_213;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd0;
+	case (builder_bankmachine4_state)
+		1'd1: begin
+			if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin
+				main_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
+			end
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+			if (main_litedramcore_bankmachine4_trccon_ready) begin
+				main_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
+			end
+		end
+		3'd4: begin
+			main_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_213 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_214;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine4_cmd_payload_is_read <= 1'd0;
+	case (builder_bankmachine4_state)
+		1'd1: begin
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+			if (main_litedramcore_bankmachine4_refresh_req) begin
+			end else begin
+				if (main_litedramcore_bankmachine4_cmd_buffer_source_valid) begin
+					if (main_litedramcore_bankmachine4_row_opened) begin
+						if (main_litedramcore_bankmachine4_row_hit) begin
+							if (main_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
+							end else begin
+								main_litedramcore_bankmachine4_cmd_payload_is_read <= 1'd1;
+							end
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_214 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_215;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine4_cmd_payload_is_write <= 1'd0;
+	case (builder_bankmachine4_state)
+		1'd1: begin
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+			if (main_litedramcore_bankmachine4_refresh_req) begin
+			end else begin
+				if (main_litedramcore_bankmachine4_cmd_buffer_source_valid) begin
+					if (main_litedramcore_bankmachine4_row_opened) begin
+						if (main_litedramcore_bankmachine4_row_hit) begin
+							if (main_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
+								main_litedramcore_bankmachine4_cmd_payload_is_write <= 1'd1;
+							end else begin
+							end
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_215 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_216;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine4_req_wdata_ready <= 1'd0;
+	case (builder_bankmachine4_state)
+		1'd1: begin
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+			if (main_litedramcore_bankmachine4_refresh_req) begin
+			end else begin
+				if (main_litedramcore_bankmachine4_cmd_buffer_source_valid) begin
+					if (main_litedramcore_bankmachine4_row_opened) begin
+						if (main_litedramcore_bankmachine4_row_hit) begin
+							if (main_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
+								main_litedramcore_bankmachine4_req_wdata_ready <= main_litedramcore_bankmachine4_cmd_ready;
+							end else begin
+							end
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_216 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_217;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine4_req_rdata_valid <= 1'd0;
+	case (builder_bankmachine4_state)
+		1'd1: begin
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+			if (main_litedramcore_bankmachine4_refresh_req) begin
+			end else begin
+				if (main_litedramcore_bankmachine4_cmd_buffer_source_valid) begin
+					if (main_litedramcore_bankmachine4_row_opened) begin
+						if (main_litedramcore_bankmachine4_row_hit) begin
+							if (main_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
+							end else begin
+								main_litedramcore_bankmachine4_req_rdata_valid <= main_litedramcore_bankmachine4_cmd_ready;
+							end
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_217 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_218;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine4_refresh_gnt <= 1'd0;
+	case (builder_bankmachine4_state)
+		1'd1: begin
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+		end
+		3'd4: begin
+			if (main_litedramcore_bankmachine4_twtpcon_ready) begin
+				main_litedramcore_bankmachine4_refresh_gnt <= 1'd1;
+			end
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_218 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_219;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine4_cmd_valid <= 1'd0;
+	case (builder_bankmachine4_state)
+		1'd1: begin
+			if ((main_litedramcore_bankmachine4_twtpcon_ready & main_litedramcore_bankmachine4_trascon_ready)) begin
+				main_litedramcore_bankmachine4_cmd_valid <= 1'd1;
+			end
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+			if (main_litedramcore_bankmachine4_trccon_ready) begin
+				main_litedramcore_bankmachine4_cmd_valid <= 1'd1;
+			end
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+			if (main_litedramcore_bankmachine4_refresh_req) begin
+			end else begin
+				if (main_litedramcore_bankmachine4_cmd_buffer_source_valid) begin
+					if (main_litedramcore_bankmachine4_row_opened) begin
+						if (main_litedramcore_bankmachine4_row_hit) begin
+							main_litedramcore_bankmachine4_cmd_valid <= 1'd1;
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_219 = dummy_s;
+// synthesis translate_on
+end
+assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine5_req_valid;
+assign main_litedramcore_bankmachine5_req_ready = main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready;
+assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we = main_litedramcore_bankmachine5_req_we;
+assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr = main_litedramcore_bankmachine5_req_addr;
+assign main_litedramcore_bankmachine5_cmd_buffer_sink_valid = main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid;
+assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready = main_litedramcore_bankmachine5_cmd_buffer_sink_ready;
+assign main_litedramcore_bankmachine5_cmd_buffer_sink_first = main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_first;
+assign main_litedramcore_bankmachine5_cmd_buffer_sink_last = main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_last;
+assign main_litedramcore_bankmachine5_cmd_buffer_sink_payload_we = main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we;
+assign main_litedramcore_bankmachine5_cmd_buffer_sink_payload_addr = main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr;
+assign main_litedramcore_bankmachine5_cmd_buffer_source_ready = (main_litedramcore_bankmachine5_req_wdata_ready | main_litedramcore_bankmachine5_req_rdata_valid);
+assign main_litedramcore_bankmachine5_req_lock = (main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid | main_litedramcore_bankmachine5_cmd_buffer_source_valid);
+assign main_litedramcore_bankmachine5_row_hit = (main_litedramcore_bankmachine5_row == main_litedramcore_bankmachine5_cmd_buffer_source_payload_addr[20:7]);
+assign main_litedramcore_bankmachine5_cmd_payload_ba = 3'd5;
+
+// synthesis translate_off
+reg dummy_d_220;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine5_cmd_payload_a <= 14'd0;
+	if (main_litedramcore_bankmachine5_row_col_n_addr_sel) begin
+		main_litedramcore_bankmachine5_cmd_payload_a <= main_litedramcore_bankmachine5_cmd_buffer_source_payload_addr[20:7];
+	end else begin
+		main_litedramcore_bankmachine5_cmd_payload_a <= ((main_litedramcore_bankmachine5_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine5_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
+	end
+// synthesis translate_off
+	dummy_d_220 = dummy_s;
+// synthesis translate_on
+end
+assign main_litedramcore_bankmachine5_twtpcon_valid = ((main_litedramcore_bankmachine5_cmd_valid & main_litedramcore_bankmachine5_cmd_ready) & main_litedramcore_bankmachine5_cmd_payload_is_write);
+assign main_litedramcore_bankmachine5_trccon_valid = ((main_litedramcore_bankmachine5_cmd_valid & main_litedramcore_bankmachine5_cmd_ready) & main_litedramcore_bankmachine5_row_open);
+assign main_litedramcore_bankmachine5_trascon_valid = ((main_litedramcore_bankmachine5_cmd_valid & main_litedramcore_bankmachine5_cmd_ready) & main_litedramcore_bankmachine5_row_open);
+
+// synthesis translate_off
+reg dummy_d_221;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine5_auto_precharge <= 1'd0;
+	if ((main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid & main_litedramcore_bankmachine5_cmd_buffer_source_valid)) begin
+		if ((main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr[20:7] != main_litedramcore_bankmachine5_cmd_buffer_source_payload_addr[20:7])) begin
+			main_litedramcore_bankmachine5_auto_precharge <= (main_litedramcore_bankmachine5_row_close == 1'd0);
+		end
+	end
+// synthesis translate_off
+	dummy_d_221 = dummy_s;
+// synthesis translate_on
+end
+assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din = {main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we};
+assign {main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
+assign {main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
+assign {main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
+assign {main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
+assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready = main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable;
+assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we = main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid;
+assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first = main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_first;
+assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last = main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_last;
+assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we = main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we;
+assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr = main_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr;
+assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid = main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable;
+assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_first = main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first;
+assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_last = main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last;
+assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we = main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we;
+assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr = main_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr;
+assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re = main_litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready;
+
+// synthesis translate_off
+reg dummy_d_222;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= 4'd0;
+	if (main_litedramcore_bankmachine5_cmd_buffer_lookahead_replace) begin
+		main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= (main_litedramcore_bankmachine5_cmd_buffer_lookahead_produce - 1'd1);
+	end else begin
+		main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= main_litedramcore_bankmachine5_cmd_buffer_lookahead_produce;
+	end
+// synthesis translate_off
+	dummy_d_222 = dummy_s;
+// synthesis translate_on
+end
+assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w = main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din;
+assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we = (main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & (main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable | main_litedramcore_bankmachine5_cmd_buffer_lookahead_replace));
+assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_do_read = (main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable & main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re);
+assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr = main_litedramcore_bankmachine5_cmd_buffer_lookahead_consume;
+assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout = main_litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r;
+assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable = (main_litedramcore_bankmachine5_cmd_buffer_lookahead_level != 5'd16);
+assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable = (main_litedramcore_bankmachine5_cmd_buffer_lookahead_level != 1'd0);
+assign main_litedramcore_bankmachine5_cmd_buffer_sink_ready = ((~main_litedramcore_bankmachine5_cmd_buffer_source_valid) | main_litedramcore_bankmachine5_cmd_buffer_source_ready);
+
+// synthesis translate_off
+reg dummy_d_223;
+// synthesis translate_on
+always @(*) begin
+	builder_bankmachine5_next_state <= 4'd0;
+	builder_bankmachine5_next_state <= builder_bankmachine5_state;
+	case (builder_bankmachine5_state)
+		1'd1: begin
+			if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin
+				if (main_litedramcore_bankmachine5_cmd_ready) begin
+					builder_bankmachine5_next_state <= 3'd5;
+				end
+			end
+		end
+		2'd2: begin
+			if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin
+				builder_bankmachine5_next_state <= 3'd5;
+			end
+		end
+		2'd3: begin
+			if (main_litedramcore_bankmachine5_trccon_ready) begin
+				if (main_litedramcore_bankmachine5_cmd_ready) begin
+					builder_bankmachine5_next_state <= 3'd7;
+				end
+			end
+		end
+		3'd4: begin
+			if ((~main_litedramcore_bankmachine5_refresh_req)) begin
+				builder_bankmachine5_next_state <= 1'd0;
+			end
+		end
+		3'd5: begin
+			builder_bankmachine5_next_state <= 3'd6;
+		end
+		3'd6: begin
+			builder_bankmachine5_next_state <= 2'd3;
+		end
+		3'd7: begin
+			builder_bankmachine5_next_state <= 4'd8;
+		end
+		4'd8: begin
+			builder_bankmachine5_next_state <= 1'd0;
+		end
+		default: begin
+			if (main_litedramcore_bankmachine5_refresh_req) begin
+				builder_bankmachine5_next_state <= 3'd4;
+			end else begin
+				if (main_litedramcore_bankmachine5_cmd_buffer_source_valid) begin
+					if (main_litedramcore_bankmachine5_row_opened) begin
+						if (main_litedramcore_bankmachine5_row_hit) begin
+							if ((main_litedramcore_bankmachine5_cmd_ready & main_litedramcore_bankmachine5_auto_precharge)) begin
+								builder_bankmachine5_next_state <= 2'd2;
+							end
+						end else begin
+							builder_bankmachine5_next_state <= 1'd1;
+						end
+					end else begin
+						builder_bankmachine5_next_state <= 2'd3;
+					end
+				end
+			end
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_223 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_224;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine5_req_rdata_valid <= 1'd0;
+	case (builder_bankmachine5_state)
+		1'd1: begin
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+			if (main_litedramcore_bankmachine5_refresh_req) begin
+			end else begin
+				if (main_litedramcore_bankmachine5_cmd_buffer_source_valid) begin
+					if (main_litedramcore_bankmachine5_row_opened) begin
+						if (main_litedramcore_bankmachine5_row_hit) begin
+							if (main_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
+							end else begin
+								main_litedramcore_bankmachine5_req_rdata_valid <= main_litedramcore_bankmachine5_cmd_ready;
+							end
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_224 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_225;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine5_row_open <= 1'd0;
+	case (builder_bankmachine5_state)
+		1'd1: begin
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+			if (main_litedramcore_bankmachine5_trccon_ready) begin
+				main_litedramcore_bankmachine5_row_open <= 1'd1;
+			end
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_225 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_226;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine5_row_close <= 1'd0;
+	case (builder_bankmachine5_state)
+		1'd1: begin
+			main_litedramcore_bankmachine5_row_close <= 1'd1;
+		end
+		2'd2: begin
+			main_litedramcore_bankmachine5_row_close <= 1'd1;
+		end
+		2'd3: begin
+		end
+		3'd4: begin
+			main_litedramcore_bankmachine5_row_close <= 1'd1;
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_226 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_227;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine5_cmd_payload_cas <= 1'd0;
+	case (builder_bankmachine5_state)
+		1'd1: begin
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+			if (main_litedramcore_bankmachine5_refresh_req) begin
+			end else begin
+				if (main_litedramcore_bankmachine5_cmd_buffer_source_valid) begin
+					if (main_litedramcore_bankmachine5_row_opened) begin
+						if (main_litedramcore_bankmachine5_row_hit) begin
+							main_litedramcore_bankmachine5_cmd_payload_cas <= 1'd1;
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_227 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_228;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine5_cmd_payload_ras <= 1'd0;
+	case (builder_bankmachine5_state)
+		1'd1: begin
+			if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin
+				main_litedramcore_bankmachine5_cmd_payload_ras <= 1'd1;
+			end
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+			if (main_litedramcore_bankmachine5_trccon_ready) begin
+				main_litedramcore_bankmachine5_cmd_payload_ras <= 1'd1;
+			end
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_228 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_229;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine5_cmd_payload_we <= 1'd0;
+	case (builder_bankmachine5_state)
+		1'd1: begin
+			if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin
+				main_litedramcore_bankmachine5_cmd_payload_we <= 1'd1;
+			end
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+			if (main_litedramcore_bankmachine5_refresh_req) begin
+			end else begin
+				if (main_litedramcore_bankmachine5_cmd_buffer_source_valid) begin
+					if (main_litedramcore_bankmachine5_row_opened) begin
+						if (main_litedramcore_bankmachine5_row_hit) begin
+							if (main_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
+								main_litedramcore_bankmachine5_cmd_payload_we <= 1'd1;
+							end else begin
+							end
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_229 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_230;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd0;
+	case (builder_bankmachine5_state)
+		1'd1: begin
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+			if (main_litedramcore_bankmachine5_trccon_ready) begin
+				main_litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd1;
+			end
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_230 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_231;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd0;
+	case (builder_bankmachine5_state)
+		1'd1: begin
+			if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin
+				main_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
+			end
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+			if (main_litedramcore_bankmachine5_trccon_ready) begin
+				main_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
+			end
+		end
+		3'd4: begin
+			main_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_231 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_232;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine5_cmd_payload_is_read <= 1'd0;
+	case (builder_bankmachine5_state)
+		1'd1: begin
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+			if (main_litedramcore_bankmachine5_refresh_req) begin
+			end else begin
+				if (main_litedramcore_bankmachine5_cmd_buffer_source_valid) begin
+					if (main_litedramcore_bankmachine5_row_opened) begin
+						if (main_litedramcore_bankmachine5_row_hit) begin
+							if (main_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
+							end else begin
+								main_litedramcore_bankmachine5_cmd_payload_is_read <= 1'd1;
+							end
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_232 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_233;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine5_cmd_payload_is_write <= 1'd0;
+	case (builder_bankmachine5_state)
+		1'd1: begin
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+			if (main_litedramcore_bankmachine5_refresh_req) begin
+			end else begin
+				if (main_litedramcore_bankmachine5_cmd_buffer_source_valid) begin
+					if (main_litedramcore_bankmachine5_row_opened) begin
+						if (main_litedramcore_bankmachine5_row_hit) begin
+							if (main_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
+								main_litedramcore_bankmachine5_cmd_payload_is_write <= 1'd1;
+							end else begin
+							end
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_233 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_234;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine5_req_wdata_ready <= 1'd0;
+	case (builder_bankmachine5_state)
+		1'd1: begin
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+			if (main_litedramcore_bankmachine5_refresh_req) begin
+			end else begin
+				if (main_litedramcore_bankmachine5_cmd_buffer_source_valid) begin
+					if (main_litedramcore_bankmachine5_row_opened) begin
+						if (main_litedramcore_bankmachine5_row_hit) begin
+							if (main_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
+								main_litedramcore_bankmachine5_req_wdata_ready <= main_litedramcore_bankmachine5_cmd_ready;
+							end else begin
+							end
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_234 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_235;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine5_refresh_gnt <= 1'd0;
+	case (builder_bankmachine5_state)
+		1'd1: begin
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+		end
+		3'd4: begin
+			if (main_litedramcore_bankmachine5_twtpcon_ready) begin
+				main_litedramcore_bankmachine5_refresh_gnt <= 1'd1;
+			end
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_235 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_236;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine5_cmd_valid <= 1'd0;
+	case (builder_bankmachine5_state)
+		1'd1: begin
+			if ((main_litedramcore_bankmachine5_twtpcon_ready & main_litedramcore_bankmachine5_trascon_ready)) begin
+				main_litedramcore_bankmachine5_cmd_valid <= 1'd1;
+			end
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+			if (main_litedramcore_bankmachine5_trccon_ready) begin
+				main_litedramcore_bankmachine5_cmd_valid <= 1'd1;
+			end
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+			if (main_litedramcore_bankmachine5_refresh_req) begin
+			end else begin
+				if (main_litedramcore_bankmachine5_cmd_buffer_source_valid) begin
+					if (main_litedramcore_bankmachine5_row_opened) begin
+						if (main_litedramcore_bankmachine5_row_hit) begin
+							main_litedramcore_bankmachine5_cmd_valid <= 1'd1;
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_236 = dummy_s;
+// synthesis translate_on
+end
+assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine6_req_valid;
+assign main_litedramcore_bankmachine6_req_ready = main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready;
+assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we = main_litedramcore_bankmachine6_req_we;
+assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr = main_litedramcore_bankmachine6_req_addr;
+assign main_litedramcore_bankmachine6_cmd_buffer_sink_valid = main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid;
+assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready = main_litedramcore_bankmachine6_cmd_buffer_sink_ready;
+assign main_litedramcore_bankmachine6_cmd_buffer_sink_first = main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_first;
+assign main_litedramcore_bankmachine6_cmd_buffer_sink_last = main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_last;
+assign main_litedramcore_bankmachine6_cmd_buffer_sink_payload_we = main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we;
+assign main_litedramcore_bankmachine6_cmd_buffer_sink_payload_addr = main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr;
+assign main_litedramcore_bankmachine6_cmd_buffer_source_ready = (main_litedramcore_bankmachine6_req_wdata_ready | main_litedramcore_bankmachine6_req_rdata_valid);
+assign main_litedramcore_bankmachine6_req_lock = (main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid | main_litedramcore_bankmachine6_cmd_buffer_source_valid);
+assign main_litedramcore_bankmachine6_row_hit = (main_litedramcore_bankmachine6_row == main_litedramcore_bankmachine6_cmd_buffer_source_payload_addr[20:7]);
+assign main_litedramcore_bankmachine6_cmd_payload_ba = 3'd6;
+
+// synthesis translate_off
+reg dummy_d_237;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine6_cmd_payload_a <= 14'd0;
+	if (main_litedramcore_bankmachine6_row_col_n_addr_sel) begin
+		main_litedramcore_bankmachine6_cmd_payload_a <= main_litedramcore_bankmachine6_cmd_buffer_source_payload_addr[20:7];
+	end else begin
+		main_litedramcore_bankmachine6_cmd_payload_a <= ((main_litedramcore_bankmachine6_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine6_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
+	end
+// synthesis translate_off
+	dummy_d_237 = dummy_s;
+// synthesis translate_on
+end
+assign main_litedramcore_bankmachine6_twtpcon_valid = ((main_litedramcore_bankmachine6_cmd_valid & main_litedramcore_bankmachine6_cmd_ready) & main_litedramcore_bankmachine6_cmd_payload_is_write);
+assign main_litedramcore_bankmachine6_trccon_valid = ((main_litedramcore_bankmachine6_cmd_valid & main_litedramcore_bankmachine6_cmd_ready) & main_litedramcore_bankmachine6_row_open);
+assign main_litedramcore_bankmachine6_trascon_valid = ((main_litedramcore_bankmachine6_cmd_valid & main_litedramcore_bankmachine6_cmd_ready) & main_litedramcore_bankmachine6_row_open);
+
+// synthesis translate_off
+reg dummy_d_238;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine6_auto_precharge <= 1'd0;
+	if ((main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid & main_litedramcore_bankmachine6_cmd_buffer_source_valid)) begin
+		if ((main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr[20:7] != main_litedramcore_bankmachine6_cmd_buffer_source_payload_addr[20:7])) begin
+			main_litedramcore_bankmachine6_auto_precharge <= (main_litedramcore_bankmachine6_row_close == 1'd0);
+		end
+	end
+// synthesis translate_off
+	dummy_d_238 = dummy_s;
+// synthesis translate_on
+end
+assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din = {main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we};
+assign {main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
+assign {main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
+assign {main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
+assign {main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
+assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready = main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable;
+assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we = main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid;
+assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first = main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_first;
+assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last = main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_last;
+assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we = main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we;
+assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr = main_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr;
+assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid = main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable;
+assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_first = main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first;
+assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_last = main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last;
+assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we = main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we;
+assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr = main_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr;
+assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re = main_litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready;
+
+// synthesis translate_off
+reg dummy_d_239;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= 4'd0;
+	if (main_litedramcore_bankmachine6_cmd_buffer_lookahead_replace) begin
+		main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= (main_litedramcore_bankmachine6_cmd_buffer_lookahead_produce - 1'd1);
+	end else begin
+		main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= main_litedramcore_bankmachine6_cmd_buffer_lookahead_produce;
+	end
+// synthesis translate_off
+	dummy_d_239 = dummy_s;
+// synthesis translate_on
+end
+assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w = main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din;
+assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we = (main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & (main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable | main_litedramcore_bankmachine6_cmd_buffer_lookahead_replace));
+assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_do_read = (main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable & main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re);
+assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr = main_litedramcore_bankmachine6_cmd_buffer_lookahead_consume;
+assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout = main_litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r;
+assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable = (main_litedramcore_bankmachine6_cmd_buffer_lookahead_level != 5'd16);
+assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable = (main_litedramcore_bankmachine6_cmd_buffer_lookahead_level != 1'd0);
+assign main_litedramcore_bankmachine6_cmd_buffer_sink_ready = ((~main_litedramcore_bankmachine6_cmd_buffer_source_valid) | main_litedramcore_bankmachine6_cmd_buffer_source_ready);
+
+// synthesis translate_off
+reg dummy_d_240;
+// synthesis translate_on
+always @(*) begin
+	builder_bankmachine6_next_state <= 4'd0;
+	builder_bankmachine6_next_state <= builder_bankmachine6_state;
+	case (builder_bankmachine6_state)
+		1'd1: begin
+			if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin
+				if (main_litedramcore_bankmachine6_cmd_ready) begin
+					builder_bankmachine6_next_state <= 3'd5;
+				end
+			end
+		end
+		2'd2: begin
+			if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin
+				builder_bankmachine6_next_state <= 3'd5;
+			end
+		end
+		2'd3: begin
+			if (main_litedramcore_bankmachine6_trccon_ready) begin
+				if (main_litedramcore_bankmachine6_cmd_ready) begin
+					builder_bankmachine6_next_state <= 3'd7;
+				end
+			end
+		end
+		3'd4: begin
+			if ((~main_litedramcore_bankmachine6_refresh_req)) begin
+				builder_bankmachine6_next_state <= 1'd0;
+			end
+		end
+		3'd5: begin
+			builder_bankmachine6_next_state <= 3'd6;
+		end
+		3'd6: begin
+			builder_bankmachine6_next_state <= 2'd3;
+		end
+		3'd7: begin
+			builder_bankmachine6_next_state <= 4'd8;
+		end
+		4'd8: begin
+			builder_bankmachine6_next_state <= 1'd0;
+		end
+		default: begin
+			if (main_litedramcore_bankmachine6_refresh_req) begin
+				builder_bankmachine6_next_state <= 3'd4;
+			end else begin
+				if (main_litedramcore_bankmachine6_cmd_buffer_source_valid) begin
+					if (main_litedramcore_bankmachine6_row_opened) begin
+						if (main_litedramcore_bankmachine6_row_hit) begin
+							if ((main_litedramcore_bankmachine6_cmd_ready & main_litedramcore_bankmachine6_auto_precharge)) begin
+								builder_bankmachine6_next_state <= 2'd2;
+							end
+						end else begin
+							builder_bankmachine6_next_state <= 1'd1;
+						end
+					end else begin
+						builder_bankmachine6_next_state <= 2'd3;
+					end
+				end
+			end
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_240 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_241;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine6_row_open <= 1'd0;
+	case (builder_bankmachine6_state)
+		1'd1: begin
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+			if (main_litedramcore_bankmachine6_trccon_ready) begin
+				main_litedramcore_bankmachine6_row_open <= 1'd1;
+			end
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_241 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_242;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine6_row_close <= 1'd0;
+	case (builder_bankmachine6_state)
+		1'd1: begin
+			main_litedramcore_bankmachine6_row_close <= 1'd1;
+		end
+		2'd2: begin
+			main_litedramcore_bankmachine6_row_close <= 1'd1;
+		end
+		2'd3: begin
+		end
+		3'd4: begin
+			main_litedramcore_bankmachine6_row_close <= 1'd1;
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_242 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_243;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine6_req_rdata_valid <= 1'd0;
+	case (builder_bankmachine6_state)
+		1'd1: begin
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+			if (main_litedramcore_bankmachine6_refresh_req) begin
+			end else begin
+				if (main_litedramcore_bankmachine6_cmd_buffer_source_valid) begin
+					if (main_litedramcore_bankmachine6_row_opened) begin
+						if (main_litedramcore_bankmachine6_row_hit) begin
+							if (main_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
+							end else begin
+								main_litedramcore_bankmachine6_req_rdata_valid <= main_litedramcore_bankmachine6_cmd_ready;
+							end
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_243 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_244;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine6_cmd_payload_cas <= 1'd0;
+	case (builder_bankmachine6_state)
+		1'd1: begin
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+			if (main_litedramcore_bankmachine6_refresh_req) begin
+			end else begin
+				if (main_litedramcore_bankmachine6_cmd_buffer_source_valid) begin
+					if (main_litedramcore_bankmachine6_row_opened) begin
+						if (main_litedramcore_bankmachine6_row_hit) begin
+							main_litedramcore_bankmachine6_cmd_payload_cas <= 1'd1;
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_244 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_245;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine6_cmd_payload_ras <= 1'd0;
+	case (builder_bankmachine6_state)
+		1'd1: begin
+			if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin
+				main_litedramcore_bankmachine6_cmd_payload_ras <= 1'd1;
+			end
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+			if (main_litedramcore_bankmachine6_trccon_ready) begin
+				main_litedramcore_bankmachine6_cmd_payload_ras <= 1'd1;
+			end
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_245 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_246;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine6_cmd_payload_we <= 1'd0;
+	case (builder_bankmachine6_state)
+		1'd1: begin
+			if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin
+				main_litedramcore_bankmachine6_cmd_payload_we <= 1'd1;
+			end
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+			if (main_litedramcore_bankmachine6_refresh_req) begin
+			end else begin
+				if (main_litedramcore_bankmachine6_cmd_buffer_source_valid) begin
+					if (main_litedramcore_bankmachine6_row_opened) begin
+						if (main_litedramcore_bankmachine6_row_hit) begin
+							if (main_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
+								main_litedramcore_bankmachine6_cmd_payload_we <= 1'd1;
+							end else begin
+							end
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_246 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_247;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd0;
+	case (builder_bankmachine6_state)
+		1'd1: begin
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+			if (main_litedramcore_bankmachine6_trccon_ready) begin
+				main_litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd1;
+			end
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_247 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_248;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd0;
+	case (builder_bankmachine6_state)
+		1'd1: begin
+			if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin
+				main_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
+			end
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+			if (main_litedramcore_bankmachine6_trccon_ready) begin
+				main_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
+			end
+		end
+		3'd4: begin
+			main_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_248 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_249;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine6_cmd_payload_is_read <= 1'd0;
+	case (builder_bankmachine6_state)
+		1'd1: begin
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+			if (main_litedramcore_bankmachine6_refresh_req) begin
+			end else begin
+				if (main_litedramcore_bankmachine6_cmd_buffer_source_valid) begin
+					if (main_litedramcore_bankmachine6_row_opened) begin
+						if (main_litedramcore_bankmachine6_row_hit) begin
+							if (main_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
+							end else begin
+								main_litedramcore_bankmachine6_cmd_payload_is_read <= 1'd1;
+							end
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_249 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_250;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine6_cmd_payload_is_write <= 1'd0;
+	case (builder_bankmachine6_state)
+		1'd1: begin
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+			if (main_litedramcore_bankmachine6_refresh_req) begin
+			end else begin
+				if (main_litedramcore_bankmachine6_cmd_buffer_source_valid) begin
+					if (main_litedramcore_bankmachine6_row_opened) begin
+						if (main_litedramcore_bankmachine6_row_hit) begin
+							if (main_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
+								main_litedramcore_bankmachine6_cmd_payload_is_write <= 1'd1;
+							end else begin
+							end
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_250 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_251;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine6_req_wdata_ready <= 1'd0;
+	case (builder_bankmachine6_state)
+		1'd1: begin
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+			if (main_litedramcore_bankmachine6_refresh_req) begin
+			end else begin
+				if (main_litedramcore_bankmachine6_cmd_buffer_source_valid) begin
+					if (main_litedramcore_bankmachine6_row_opened) begin
+						if (main_litedramcore_bankmachine6_row_hit) begin
+							if (main_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
+								main_litedramcore_bankmachine6_req_wdata_ready <= main_litedramcore_bankmachine6_cmd_ready;
+							end else begin
+							end
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_251 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_252;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine6_refresh_gnt <= 1'd0;
+	case (builder_bankmachine6_state)
+		1'd1: begin
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+		end
+		3'd4: begin
+			if (main_litedramcore_bankmachine6_twtpcon_ready) begin
+				main_litedramcore_bankmachine6_refresh_gnt <= 1'd1;
+			end
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_252 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_253;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine6_cmd_valid <= 1'd0;
+	case (builder_bankmachine6_state)
+		1'd1: begin
+			if ((main_litedramcore_bankmachine6_twtpcon_ready & main_litedramcore_bankmachine6_trascon_ready)) begin
+				main_litedramcore_bankmachine6_cmd_valid <= 1'd1;
+			end
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+			if (main_litedramcore_bankmachine6_trccon_ready) begin
+				main_litedramcore_bankmachine6_cmd_valid <= 1'd1;
+			end
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+			if (main_litedramcore_bankmachine6_refresh_req) begin
+			end else begin
+				if (main_litedramcore_bankmachine6_cmd_buffer_source_valid) begin
+					if (main_litedramcore_bankmachine6_row_opened) begin
+						if (main_litedramcore_bankmachine6_row_hit) begin
+							main_litedramcore_bankmachine6_cmd_valid <= 1'd1;
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_253 = dummy_s;
+// synthesis translate_on
+end
+assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid = main_litedramcore_bankmachine7_req_valid;
+assign main_litedramcore_bankmachine7_req_ready = main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready;
+assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we = main_litedramcore_bankmachine7_req_we;
+assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr = main_litedramcore_bankmachine7_req_addr;
+assign main_litedramcore_bankmachine7_cmd_buffer_sink_valid = main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid;
+assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready = main_litedramcore_bankmachine7_cmd_buffer_sink_ready;
+assign main_litedramcore_bankmachine7_cmd_buffer_sink_first = main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_first;
+assign main_litedramcore_bankmachine7_cmd_buffer_sink_last = main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_last;
+assign main_litedramcore_bankmachine7_cmd_buffer_sink_payload_we = main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we;
+assign main_litedramcore_bankmachine7_cmd_buffer_sink_payload_addr = main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr;
+assign main_litedramcore_bankmachine7_cmd_buffer_source_ready = (main_litedramcore_bankmachine7_req_wdata_ready | main_litedramcore_bankmachine7_req_rdata_valid);
+assign main_litedramcore_bankmachine7_req_lock = (main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid | main_litedramcore_bankmachine7_cmd_buffer_source_valid);
+assign main_litedramcore_bankmachine7_row_hit = (main_litedramcore_bankmachine7_row == main_litedramcore_bankmachine7_cmd_buffer_source_payload_addr[20:7]);
+assign main_litedramcore_bankmachine7_cmd_payload_ba = 3'd7;
+
+// synthesis translate_off
+reg dummy_d_254;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine7_cmd_payload_a <= 14'd0;
+	if (main_litedramcore_bankmachine7_row_col_n_addr_sel) begin
+		main_litedramcore_bankmachine7_cmd_payload_a <= main_litedramcore_bankmachine7_cmd_buffer_source_payload_addr[20:7];
+	end else begin
+		main_litedramcore_bankmachine7_cmd_payload_a <= ((main_litedramcore_bankmachine7_auto_precharge <<< 4'd10) | {main_litedramcore_bankmachine7_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
+	end
+// synthesis translate_off
+	dummy_d_254 = dummy_s;
+// synthesis translate_on
+end
+assign main_litedramcore_bankmachine7_twtpcon_valid = ((main_litedramcore_bankmachine7_cmd_valid & main_litedramcore_bankmachine7_cmd_ready) & main_litedramcore_bankmachine7_cmd_payload_is_write);
+assign main_litedramcore_bankmachine7_trccon_valid = ((main_litedramcore_bankmachine7_cmd_valid & main_litedramcore_bankmachine7_cmd_ready) & main_litedramcore_bankmachine7_row_open);
+assign main_litedramcore_bankmachine7_trascon_valid = ((main_litedramcore_bankmachine7_cmd_valid & main_litedramcore_bankmachine7_cmd_ready) & main_litedramcore_bankmachine7_row_open);
+
+// synthesis translate_off
+reg dummy_d_255;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine7_auto_precharge <= 1'd0;
+	if ((main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid & main_litedramcore_bankmachine7_cmd_buffer_source_valid)) begin
+		if ((main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr[20:7] != main_litedramcore_bankmachine7_cmd_buffer_source_payload_addr[20:7])) begin
+			main_litedramcore_bankmachine7_auto_precharge <= (main_litedramcore_bankmachine7_row_close == 1'd0);
+		end
+	end
+// synthesis translate_off
+	dummy_d_255 = dummy_s;
+// synthesis translate_on
+end
+assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din = {main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we};
+assign {main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
+assign {main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
+assign {main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
+assign {main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
+assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready = main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable;
+assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we = main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid;
+assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first = main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_first;
+assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last = main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_last;
+assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we = main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we;
+assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr = main_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr;
+assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid = main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable;
+assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_first = main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first;
+assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_last = main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last;
+assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we = main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we;
+assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr = main_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr;
+assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re = main_litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready;
+
+// synthesis translate_off
+reg dummy_d_256;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= 4'd0;
+	if (main_litedramcore_bankmachine7_cmd_buffer_lookahead_replace) begin
+		main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= (main_litedramcore_bankmachine7_cmd_buffer_lookahead_produce - 1'd1);
+	end else begin
+		main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= main_litedramcore_bankmachine7_cmd_buffer_lookahead_produce;
+	end
+// synthesis translate_off
+	dummy_d_256 = dummy_s;
+// synthesis translate_on
+end
+assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w = main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din;
+assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we = (main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & (main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable | main_litedramcore_bankmachine7_cmd_buffer_lookahead_replace));
+assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_do_read = (main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable & main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re);
+assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr = main_litedramcore_bankmachine7_cmd_buffer_lookahead_consume;
+assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout = main_litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r;
+assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable = (main_litedramcore_bankmachine7_cmd_buffer_lookahead_level != 5'd16);
+assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable = (main_litedramcore_bankmachine7_cmd_buffer_lookahead_level != 1'd0);
+assign main_litedramcore_bankmachine7_cmd_buffer_sink_ready = ((~main_litedramcore_bankmachine7_cmd_buffer_source_valid) | main_litedramcore_bankmachine7_cmd_buffer_source_ready);
+
+// synthesis translate_off
+reg dummy_d_257;
+// synthesis translate_on
+always @(*) begin
+	builder_bankmachine7_next_state <= 4'd0;
+	builder_bankmachine7_next_state <= builder_bankmachine7_state;
+	case (builder_bankmachine7_state)
+		1'd1: begin
+			if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin
+				if (main_litedramcore_bankmachine7_cmd_ready) begin
+					builder_bankmachine7_next_state <= 3'd5;
+				end
+			end
+		end
+		2'd2: begin
+			if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin
+				builder_bankmachine7_next_state <= 3'd5;
+			end
+		end
+		2'd3: begin
+			if (main_litedramcore_bankmachine7_trccon_ready) begin
+				if (main_litedramcore_bankmachine7_cmd_ready) begin
+					builder_bankmachine7_next_state <= 3'd7;
+				end
+			end
+		end
+		3'd4: begin
+			if ((~main_litedramcore_bankmachine7_refresh_req)) begin
+				builder_bankmachine7_next_state <= 1'd0;
+			end
+		end
+		3'd5: begin
+			builder_bankmachine7_next_state <= 3'd6;
+		end
+		3'd6: begin
+			builder_bankmachine7_next_state <= 2'd3;
+		end
+		3'd7: begin
+			builder_bankmachine7_next_state <= 4'd8;
+		end
+		4'd8: begin
+			builder_bankmachine7_next_state <= 1'd0;
+		end
+		default: begin
+			if (main_litedramcore_bankmachine7_refresh_req) begin
+				builder_bankmachine7_next_state <= 3'd4;
+			end else begin
+				if (main_litedramcore_bankmachine7_cmd_buffer_source_valid) begin
+					if (main_litedramcore_bankmachine7_row_opened) begin
+						if (main_litedramcore_bankmachine7_row_hit) begin
+							if ((main_litedramcore_bankmachine7_cmd_ready & main_litedramcore_bankmachine7_auto_precharge)) begin
+								builder_bankmachine7_next_state <= 2'd2;
+							end
+						end else begin
+							builder_bankmachine7_next_state <= 1'd1;
+						end
+					end else begin
+						builder_bankmachine7_next_state <= 2'd3;
+					end
+				end
+			end
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_257 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_258;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine7_row_open <= 1'd0;
+	case (builder_bankmachine7_state)
+		1'd1: begin
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+			if (main_litedramcore_bankmachine7_trccon_ready) begin
+				main_litedramcore_bankmachine7_row_open <= 1'd1;
+			end
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_258 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_259;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine7_row_close <= 1'd0;
+	case (builder_bankmachine7_state)
+		1'd1: begin
+			main_litedramcore_bankmachine7_row_close <= 1'd1;
+		end
+		2'd2: begin
+			main_litedramcore_bankmachine7_row_close <= 1'd1;
+		end
+		2'd3: begin
+		end
+		3'd4: begin
+			main_litedramcore_bankmachine7_row_close <= 1'd1;
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_259 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_260;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine7_cmd_payload_cas <= 1'd0;
+	case (builder_bankmachine7_state)
+		1'd1: begin
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+			if (main_litedramcore_bankmachine7_refresh_req) begin
+			end else begin
+				if (main_litedramcore_bankmachine7_cmd_buffer_source_valid) begin
+					if (main_litedramcore_bankmachine7_row_opened) begin
+						if (main_litedramcore_bankmachine7_row_hit) begin
+							main_litedramcore_bankmachine7_cmd_payload_cas <= 1'd1;
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_260 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_261;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine7_cmd_payload_ras <= 1'd0;
+	case (builder_bankmachine7_state)
+		1'd1: begin
+			if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin
+				main_litedramcore_bankmachine7_cmd_payload_ras <= 1'd1;
+			end
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+			if (main_litedramcore_bankmachine7_trccon_ready) begin
+				main_litedramcore_bankmachine7_cmd_payload_ras <= 1'd1;
+			end
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_261 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_262;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine7_cmd_payload_we <= 1'd0;
+	case (builder_bankmachine7_state)
+		1'd1: begin
+			if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin
+				main_litedramcore_bankmachine7_cmd_payload_we <= 1'd1;
+			end
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+			if (main_litedramcore_bankmachine7_refresh_req) begin
+			end else begin
+				if (main_litedramcore_bankmachine7_cmd_buffer_source_valid) begin
+					if (main_litedramcore_bankmachine7_row_opened) begin
+						if (main_litedramcore_bankmachine7_row_hit) begin
+							if (main_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
+								main_litedramcore_bankmachine7_cmd_payload_we <= 1'd1;
+							end else begin
+							end
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_262 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_263;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd0;
+	case (builder_bankmachine7_state)
+		1'd1: begin
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+			if (main_litedramcore_bankmachine7_trccon_ready) begin
+				main_litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd1;
+			end
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_263 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_264;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd0;
+	case (builder_bankmachine7_state)
+		1'd1: begin
+			if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin
+				main_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
+			end
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+			if (main_litedramcore_bankmachine7_trccon_ready) begin
+				main_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
+			end
+		end
+		3'd4: begin
+			main_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_264 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_265;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine7_req_rdata_valid <= 1'd0;
+	case (builder_bankmachine7_state)
+		1'd1: begin
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+			if (main_litedramcore_bankmachine7_refresh_req) begin
+			end else begin
+				if (main_litedramcore_bankmachine7_cmd_buffer_source_valid) begin
+					if (main_litedramcore_bankmachine7_row_opened) begin
+						if (main_litedramcore_bankmachine7_row_hit) begin
+							if (main_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
+							end else begin
+								main_litedramcore_bankmachine7_req_rdata_valid <= main_litedramcore_bankmachine7_cmd_ready;
+							end
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_265 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_266;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine7_cmd_payload_is_read <= 1'd0;
+	case (builder_bankmachine7_state)
+		1'd1: begin
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+			if (main_litedramcore_bankmachine7_refresh_req) begin
+			end else begin
+				if (main_litedramcore_bankmachine7_cmd_buffer_source_valid) begin
+					if (main_litedramcore_bankmachine7_row_opened) begin
+						if (main_litedramcore_bankmachine7_row_hit) begin
+							if (main_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
+							end else begin
+								main_litedramcore_bankmachine7_cmd_payload_is_read <= 1'd1;
+							end
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_266 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_267;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine7_cmd_payload_is_write <= 1'd0;
+	case (builder_bankmachine7_state)
+		1'd1: begin
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+			if (main_litedramcore_bankmachine7_refresh_req) begin
+			end else begin
+				if (main_litedramcore_bankmachine7_cmd_buffer_source_valid) begin
+					if (main_litedramcore_bankmachine7_row_opened) begin
+						if (main_litedramcore_bankmachine7_row_hit) begin
+							if (main_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
+								main_litedramcore_bankmachine7_cmd_payload_is_write <= 1'd1;
+							end else begin
+							end
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_267 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_268;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine7_req_wdata_ready <= 1'd0;
+	case (builder_bankmachine7_state)
+		1'd1: begin
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+			if (main_litedramcore_bankmachine7_refresh_req) begin
+			end else begin
+				if (main_litedramcore_bankmachine7_cmd_buffer_source_valid) begin
+					if (main_litedramcore_bankmachine7_row_opened) begin
+						if (main_litedramcore_bankmachine7_row_hit) begin
+							if (main_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
+								main_litedramcore_bankmachine7_req_wdata_ready <= main_litedramcore_bankmachine7_cmd_ready;
+							end else begin
+							end
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_268 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_269;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine7_refresh_gnt <= 1'd0;
+	case (builder_bankmachine7_state)
+		1'd1: begin
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+		end
+		3'd4: begin
+			if (main_litedramcore_bankmachine7_twtpcon_ready) begin
+				main_litedramcore_bankmachine7_refresh_gnt <= 1'd1;
+			end
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_269 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_270;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine7_cmd_valid <= 1'd0;
+	case (builder_bankmachine7_state)
+		1'd1: begin
+			if ((main_litedramcore_bankmachine7_twtpcon_ready & main_litedramcore_bankmachine7_trascon_ready)) begin
+				main_litedramcore_bankmachine7_cmd_valid <= 1'd1;
+			end
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+			if (main_litedramcore_bankmachine7_trccon_ready) begin
+				main_litedramcore_bankmachine7_cmd_valid <= 1'd1;
+			end
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		default: begin
+			if (main_litedramcore_bankmachine7_refresh_req) begin
+			end else begin
+				if (main_litedramcore_bankmachine7_cmd_buffer_source_valid) begin
+					if (main_litedramcore_bankmachine7_row_opened) begin
+						if (main_litedramcore_bankmachine7_row_hit) begin
+							main_litedramcore_bankmachine7_cmd_valid <= 1'd1;
+						end else begin
+						end
+					end else begin
+					end
+				end
+			end
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_270 = dummy_s;
+// synthesis translate_on
+end
+assign main_litedramcore_rdcmdphase = (main_a7ddrphy_rdphase_storage - 1'd1);
+assign main_litedramcore_wrcmdphase = (main_a7ddrphy_wrphase_storage - 1'd1);
+assign main_litedramcore_trrdcon_valid = ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & ((main_litedramcore_choose_cmd_cmd_payload_ras & (~main_litedramcore_choose_cmd_cmd_payload_cas)) & (~main_litedramcore_choose_cmd_cmd_payload_we)));
+assign main_litedramcore_tfawcon_valid = ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & ((main_litedramcore_choose_cmd_cmd_payload_ras & (~main_litedramcore_choose_cmd_cmd_payload_cas)) & (~main_litedramcore_choose_cmd_cmd_payload_we)));
+assign main_litedramcore_ras_allowed = (main_litedramcore_trrdcon_ready & main_litedramcore_tfawcon_ready);
+assign main_litedramcore_tccdcon_valid = ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_cmd_payload_is_write | main_litedramcore_choose_req_cmd_payload_is_read));
+assign main_litedramcore_cas_allowed = main_litedramcore_tccdcon_ready;
+assign main_litedramcore_twtrcon_valid = ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_write);
+assign main_litedramcore_read_available = ((((((((main_litedramcore_bankmachine0_cmd_valid & main_litedramcore_bankmachine0_cmd_payload_is_read) | (main_litedramcore_bankmachine1_cmd_valid & main_litedramcore_bankmachine1_cmd_payload_is_read)) | (main_litedramcore_bankmachine2_cmd_valid & main_litedramcore_bankmachine2_cmd_payload_is_read)) | (main_litedramcore_bankmachine3_cmd_valid & main_litedramcore_bankmachine3_cmd_payload_is_read)) | (main_litedramcore_bankmachine4_cmd_valid & main_litedramcore_bankmachine4_cmd_payload_is_read)) | (main_litedramcore_bankmachine5_cmd_valid & main_litedramcore_bankmachine5_cmd_payload_is_read)) | (main_litedramcore_bankmachine6_cmd_valid & main_litedramcore_bankmachine6_cmd_payload_is_read)) | (main_litedramcore_bankmachine7_cmd_valid & main_litedramcore_bankmachine7_cmd_payload_is_read));
+assign main_litedramcore_write_available = ((((((((main_litedramcore_bankmachine0_cmd_valid & main_litedramcore_bankmachine0_cmd_payload_is_write) | (main_litedramcore_bankmachine1_cmd_valid & main_litedramcore_bankmachine1_cmd_payload_is_write)) | (main_litedramcore_bankmachine2_cmd_valid & main_litedramcore_bankmachine2_cmd_payload_is_write)) | (main_litedramcore_bankmachine3_cmd_valid & main_litedramcore_bankmachine3_cmd_payload_is_write)) | (main_litedramcore_bankmachine4_cmd_valid & main_litedramcore_bankmachine4_cmd_payload_is_write)) | (main_litedramcore_bankmachine5_cmd_valid & main_litedramcore_bankmachine5_cmd_payload_is_write)) | (main_litedramcore_bankmachine6_cmd_valid & main_litedramcore_bankmachine6_cmd_payload_is_write)) | (main_litedramcore_bankmachine7_cmd_valid & main_litedramcore_bankmachine7_cmd_payload_is_write));
+assign main_litedramcore_max_time0 = (main_litedramcore_time0 == 1'd0);
+assign main_litedramcore_max_time1 = (main_litedramcore_time1 == 1'd0);
+assign main_litedramcore_bankmachine0_refresh_req = main_litedramcore_cmd_valid;
+assign main_litedramcore_bankmachine1_refresh_req = main_litedramcore_cmd_valid;
+assign main_litedramcore_bankmachine2_refresh_req = main_litedramcore_cmd_valid;
+assign main_litedramcore_bankmachine3_refresh_req = main_litedramcore_cmd_valid;
+assign main_litedramcore_bankmachine4_refresh_req = main_litedramcore_cmd_valid;
+assign main_litedramcore_bankmachine5_refresh_req = main_litedramcore_cmd_valid;
+assign main_litedramcore_bankmachine6_refresh_req = main_litedramcore_cmd_valid;
+assign main_litedramcore_bankmachine7_refresh_req = main_litedramcore_cmd_valid;
+assign main_litedramcore_go_to_refresh = (((((((main_litedramcore_bankmachine0_refresh_gnt & main_litedramcore_bankmachine1_refresh_gnt) & main_litedramcore_bankmachine2_refresh_gnt) & main_litedramcore_bankmachine3_refresh_gnt) & main_litedramcore_bankmachine4_refresh_gnt) & main_litedramcore_bankmachine5_refresh_gnt) & main_litedramcore_bankmachine6_refresh_gnt) & main_litedramcore_bankmachine7_refresh_gnt);
+assign main_litedramcore_interface_rdata = {main_litedramcore_dfi_p3_rddata, main_litedramcore_dfi_p2_rddata, main_litedramcore_dfi_p1_rddata, main_litedramcore_dfi_p0_rddata};
+assign {main_litedramcore_dfi_p3_wrdata, main_litedramcore_dfi_p2_wrdata, main_litedramcore_dfi_p1_wrdata, main_litedramcore_dfi_p0_wrdata} = main_litedramcore_interface_wdata;
+assign {main_litedramcore_dfi_p3_wrdata, main_litedramcore_dfi_p2_wrdata, main_litedramcore_dfi_p1_wrdata, main_litedramcore_dfi_p0_wrdata} = main_litedramcore_interface_wdata;
+assign {main_litedramcore_dfi_p3_wrdata, main_litedramcore_dfi_p2_wrdata, main_litedramcore_dfi_p1_wrdata, main_litedramcore_dfi_p0_wrdata} = main_litedramcore_interface_wdata;
+assign {main_litedramcore_dfi_p3_wrdata, main_litedramcore_dfi_p2_wrdata, main_litedramcore_dfi_p1_wrdata, main_litedramcore_dfi_p0_wrdata} = main_litedramcore_interface_wdata;
+assign {main_litedramcore_dfi_p3_wrdata_mask, main_litedramcore_dfi_p2_wrdata_mask, main_litedramcore_dfi_p1_wrdata_mask, main_litedramcore_dfi_p0_wrdata_mask} = (~main_litedramcore_interface_wdata_we);
+assign {main_litedramcore_dfi_p3_wrdata_mask, main_litedramcore_dfi_p2_wrdata_mask, main_litedramcore_dfi_p1_wrdata_mask, main_litedramcore_dfi_p0_wrdata_mask} = (~main_litedramcore_interface_wdata_we);
+assign {main_litedramcore_dfi_p3_wrdata_mask, main_litedramcore_dfi_p2_wrdata_mask, main_litedramcore_dfi_p1_wrdata_mask, main_litedramcore_dfi_p0_wrdata_mask} = (~main_litedramcore_interface_wdata_we);
+assign {main_litedramcore_dfi_p3_wrdata_mask, main_litedramcore_dfi_p2_wrdata_mask, main_litedramcore_dfi_p1_wrdata_mask, main_litedramcore_dfi_p0_wrdata_mask} = (~main_litedramcore_interface_wdata_we);
+
+// synthesis translate_off
+reg dummy_d_271;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_choose_cmd_valids <= 8'd0;
+	main_litedramcore_choose_cmd_valids[0] <= (main_litedramcore_bankmachine0_cmd_valid & (((main_litedramcore_bankmachine0_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine0_cmd_payload_ras & (~main_litedramcore_bankmachine0_cmd_payload_cas)) & (~main_litedramcore_bankmachine0_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine0_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine0_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes))));
+	main_litedramcore_choose_cmd_valids[1] <= (main_litedramcore_bankmachine1_cmd_valid & (((main_litedramcore_bankmachine1_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine1_cmd_payload_ras & (~main_litedramcore_bankmachine1_cmd_payload_cas)) & (~main_litedramcore_bankmachine1_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine1_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine1_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes))));
+	main_litedramcore_choose_cmd_valids[2] <= (main_litedramcore_bankmachine2_cmd_valid & (((main_litedramcore_bankmachine2_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine2_cmd_payload_ras & (~main_litedramcore_bankmachine2_cmd_payload_cas)) & (~main_litedramcore_bankmachine2_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine2_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine2_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes))));
+	main_litedramcore_choose_cmd_valids[3] <= (main_litedramcore_bankmachine3_cmd_valid & (((main_litedramcore_bankmachine3_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine3_cmd_payload_ras & (~main_litedramcore_bankmachine3_cmd_payload_cas)) & (~main_litedramcore_bankmachine3_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine3_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine3_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes))));
+	main_litedramcore_choose_cmd_valids[4] <= (main_litedramcore_bankmachine4_cmd_valid & (((main_litedramcore_bankmachine4_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine4_cmd_payload_ras & (~main_litedramcore_bankmachine4_cmd_payload_cas)) & (~main_litedramcore_bankmachine4_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine4_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine4_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes))));
+	main_litedramcore_choose_cmd_valids[5] <= (main_litedramcore_bankmachine5_cmd_valid & (((main_litedramcore_bankmachine5_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine5_cmd_payload_ras & (~main_litedramcore_bankmachine5_cmd_payload_cas)) & (~main_litedramcore_bankmachine5_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine5_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine5_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes))));
+	main_litedramcore_choose_cmd_valids[6] <= (main_litedramcore_bankmachine6_cmd_valid & (((main_litedramcore_bankmachine6_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine6_cmd_payload_ras & (~main_litedramcore_bankmachine6_cmd_payload_cas)) & (~main_litedramcore_bankmachine6_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine6_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine6_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes))));
+	main_litedramcore_choose_cmd_valids[7] <= (main_litedramcore_bankmachine7_cmd_valid & (((main_litedramcore_bankmachine7_cmd_payload_is_cmd & main_litedramcore_choose_cmd_want_cmds) & ((~((main_litedramcore_bankmachine7_cmd_payload_ras & (~main_litedramcore_bankmachine7_cmd_payload_cas)) & (~main_litedramcore_bankmachine7_cmd_payload_we))) | main_litedramcore_choose_cmd_want_activates)) | ((main_litedramcore_bankmachine7_cmd_payload_is_read == main_litedramcore_choose_cmd_want_reads) & (main_litedramcore_bankmachine7_cmd_payload_is_write == main_litedramcore_choose_cmd_want_writes))));
+// synthesis translate_off
+	dummy_d_271 = dummy_s;
+// synthesis translate_on
+end
+assign main_litedramcore_choose_cmd_request = main_litedramcore_choose_cmd_valids;
+assign main_litedramcore_choose_cmd_cmd_valid = builder_rhs_array_muxed0;
+assign main_litedramcore_choose_cmd_cmd_payload_a = builder_rhs_array_muxed1;
+assign main_litedramcore_choose_cmd_cmd_payload_ba = builder_rhs_array_muxed2;
+assign main_litedramcore_choose_cmd_cmd_payload_is_read = builder_rhs_array_muxed3;
+assign main_litedramcore_choose_cmd_cmd_payload_is_write = builder_rhs_array_muxed4;
+assign main_litedramcore_choose_cmd_cmd_payload_is_cmd = builder_rhs_array_muxed5;
+
+// synthesis translate_off
+reg dummy_d_272;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_choose_cmd_cmd_payload_cas <= 1'd0;
+	if (main_litedramcore_choose_cmd_cmd_valid) begin
+		main_litedramcore_choose_cmd_cmd_payload_cas <= builder_t_array_muxed0;
+	end
+// synthesis translate_off
+	dummy_d_272 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_273;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_choose_cmd_cmd_payload_ras <= 1'd0;
+	if (main_litedramcore_choose_cmd_cmd_valid) begin
+		main_litedramcore_choose_cmd_cmd_payload_ras <= builder_t_array_muxed1;
+	end
+// synthesis translate_off
+	dummy_d_273 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_274;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_choose_cmd_cmd_payload_we <= 1'd0;
+	if (main_litedramcore_choose_cmd_cmd_valid) begin
+		main_litedramcore_choose_cmd_cmd_payload_we <= builder_t_array_muxed2;
+	end
+// synthesis translate_off
+	dummy_d_274 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_275;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine0_cmd_ready <= 1'd0;
+	if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 1'd0))) begin
+		main_litedramcore_bankmachine0_cmd_ready <= 1'd1;
+	end
+	if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 1'd0))) begin
+		main_litedramcore_bankmachine0_cmd_ready <= 1'd1;
+	end
+// synthesis translate_off
+	dummy_d_275 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_276;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine1_cmd_ready <= 1'd0;
+	if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 1'd1))) begin
+		main_litedramcore_bankmachine1_cmd_ready <= 1'd1;
+	end
+	if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 1'd1))) begin
+		main_litedramcore_bankmachine1_cmd_ready <= 1'd1;
+	end
+// synthesis translate_off
+	dummy_d_276 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_277;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine2_cmd_ready <= 1'd0;
+	if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 2'd2))) begin
+		main_litedramcore_bankmachine2_cmd_ready <= 1'd1;
+	end
+	if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 2'd2))) begin
+		main_litedramcore_bankmachine2_cmd_ready <= 1'd1;
+	end
+// synthesis translate_off
+	dummy_d_277 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_278;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine3_cmd_ready <= 1'd0;
+	if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 2'd3))) begin
+		main_litedramcore_bankmachine3_cmd_ready <= 1'd1;
+	end
+	if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 2'd3))) begin
+		main_litedramcore_bankmachine3_cmd_ready <= 1'd1;
+	end
+// synthesis translate_off
+	dummy_d_278 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_279;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine4_cmd_ready <= 1'd0;
+	if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 3'd4))) begin
+		main_litedramcore_bankmachine4_cmd_ready <= 1'd1;
+	end
+	if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 3'd4))) begin
+		main_litedramcore_bankmachine4_cmd_ready <= 1'd1;
+	end
+// synthesis translate_off
+	dummy_d_279 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_280;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine5_cmd_ready <= 1'd0;
+	if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 3'd5))) begin
+		main_litedramcore_bankmachine5_cmd_ready <= 1'd1;
+	end
+	if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 3'd5))) begin
+		main_litedramcore_bankmachine5_cmd_ready <= 1'd1;
+	end
+// synthesis translate_off
+	dummy_d_280 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_281;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine6_cmd_ready <= 1'd0;
+	if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 3'd6))) begin
+		main_litedramcore_bankmachine6_cmd_ready <= 1'd1;
+	end
+	if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 3'd6))) begin
+		main_litedramcore_bankmachine6_cmd_ready <= 1'd1;
+	end
+// synthesis translate_off
+	dummy_d_281 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_282;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_bankmachine7_cmd_ready <= 1'd0;
+	if (((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & (main_litedramcore_choose_cmd_grant == 3'd7))) begin
+		main_litedramcore_bankmachine7_cmd_ready <= 1'd1;
+	end
+	if (((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & (main_litedramcore_choose_req_grant == 3'd7))) begin
+		main_litedramcore_bankmachine7_cmd_ready <= 1'd1;
+	end
+// synthesis translate_off
+	dummy_d_282 = dummy_s;
+// synthesis translate_on
+end
+assign main_litedramcore_choose_cmd_ce = (main_litedramcore_choose_cmd_cmd_ready | (~main_litedramcore_choose_cmd_cmd_valid));
+
+// synthesis translate_off
+reg dummy_d_283;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_choose_req_valids <= 8'd0;
+	main_litedramcore_choose_req_valids[0] <= (main_litedramcore_bankmachine0_cmd_valid & (((main_litedramcore_bankmachine0_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine0_cmd_payload_ras & (~main_litedramcore_bankmachine0_cmd_payload_cas)) & (~main_litedramcore_bankmachine0_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine0_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine0_cmd_payload_is_write == main_litedramcore_choose_req_want_writes))));
+	main_litedramcore_choose_req_valids[1] <= (main_litedramcore_bankmachine1_cmd_valid & (((main_litedramcore_bankmachine1_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine1_cmd_payload_ras & (~main_litedramcore_bankmachine1_cmd_payload_cas)) & (~main_litedramcore_bankmachine1_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine1_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine1_cmd_payload_is_write == main_litedramcore_choose_req_want_writes))));
+	main_litedramcore_choose_req_valids[2] <= (main_litedramcore_bankmachine2_cmd_valid & (((main_litedramcore_bankmachine2_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine2_cmd_payload_ras & (~main_litedramcore_bankmachine2_cmd_payload_cas)) & (~main_litedramcore_bankmachine2_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine2_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine2_cmd_payload_is_write == main_litedramcore_choose_req_want_writes))));
+	main_litedramcore_choose_req_valids[3] <= (main_litedramcore_bankmachine3_cmd_valid & (((main_litedramcore_bankmachine3_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine3_cmd_payload_ras & (~main_litedramcore_bankmachine3_cmd_payload_cas)) & (~main_litedramcore_bankmachine3_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine3_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine3_cmd_payload_is_write == main_litedramcore_choose_req_want_writes))));
+	main_litedramcore_choose_req_valids[4] <= (main_litedramcore_bankmachine4_cmd_valid & (((main_litedramcore_bankmachine4_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine4_cmd_payload_ras & (~main_litedramcore_bankmachine4_cmd_payload_cas)) & (~main_litedramcore_bankmachine4_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine4_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine4_cmd_payload_is_write == main_litedramcore_choose_req_want_writes))));
+	main_litedramcore_choose_req_valids[5] <= (main_litedramcore_bankmachine5_cmd_valid & (((main_litedramcore_bankmachine5_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine5_cmd_payload_ras & (~main_litedramcore_bankmachine5_cmd_payload_cas)) & (~main_litedramcore_bankmachine5_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine5_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine5_cmd_payload_is_write == main_litedramcore_choose_req_want_writes))));
+	main_litedramcore_choose_req_valids[6] <= (main_litedramcore_bankmachine6_cmd_valid & (((main_litedramcore_bankmachine6_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine6_cmd_payload_ras & (~main_litedramcore_bankmachine6_cmd_payload_cas)) & (~main_litedramcore_bankmachine6_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine6_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine6_cmd_payload_is_write == main_litedramcore_choose_req_want_writes))));
+	main_litedramcore_choose_req_valids[7] <= (main_litedramcore_bankmachine7_cmd_valid & (((main_litedramcore_bankmachine7_cmd_payload_is_cmd & main_litedramcore_choose_req_want_cmds) & ((~((main_litedramcore_bankmachine7_cmd_payload_ras & (~main_litedramcore_bankmachine7_cmd_payload_cas)) & (~main_litedramcore_bankmachine7_cmd_payload_we))) | main_litedramcore_choose_req_want_activates)) | ((main_litedramcore_bankmachine7_cmd_payload_is_read == main_litedramcore_choose_req_want_reads) & (main_litedramcore_bankmachine7_cmd_payload_is_write == main_litedramcore_choose_req_want_writes))));
+// synthesis translate_off
+	dummy_d_283 = dummy_s;
+// synthesis translate_on
+end
+assign main_litedramcore_choose_req_request = main_litedramcore_choose_req_valids;
+assign main_litedramcore_choose_req_cmd_valid = builder_rhs_array_muxed6;
+assign main_litedramcore_choose_req_cmd_payload_a = builder_rhs_array_muxed7;
+assign main_litedramcore_choose_req_cmd_payload_ba = builder_rhs_array_muxed8;
+assign main_litedramcore_choose_req_cmd_payload_is_read = builder_rhs_array_muxed9;
+assign main_litedramcore_choose_req_cmd_payload_is_write = builder_rhs_array_muxed10;
+assign main_litedramcore_choose_req_cmd_payload_is_cmd = builder_rhs_array_muxed11;
+
+// synthesis translate_off
+reg dummy_d_284;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_choose_req_cmd_payload_cas <= 1'd0;
+	if (main_litedramcore_choose_req_cmd_valid) begin
+		main_litedramcore_choose_req_cmd_payload_cas <= builder_t_array_muxed3;
+	end
+// synthesis translate_off
+	dummy_d_284 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_285;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_choose_req_cmd_payload_ras <= 1'd0;
+	if (main_litedramcore_choose_req_cmd_valid) begin
+		main_litedramcore_choose_req_cmd_payload_ras <= builder_t_array_muxed4;
+	end
+// synthesis translate_off
+	dummy_d_285 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_286;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_choose_req_cmd_payload_we <= 1'd0;
+	if (main_litedramcore_choose_req_cmd_valid) begin
+		main_litedramcore_choose_req_cmd_payload_we <= builder_t_array_muxed5;
+	end
+// synthesis translate_off
+	dummy_d_286 = dummy_s;
+// synthesis translate_on
+end
+assign main_litedramcore_choose_req_ce = (main_litedramcore_choose_req_cmd_ready | (~main_litedramcore_choose_req_cmd_valid));
+assign main_litedramcore_dfi_p0_reset_n = 1'd1;
+assign main_litedramcore_dfi_p0_cke = {1{main_litedramcore_steerer0}};
+assign main_litedramcore_dfi_p0_odt = {1{main_litedramcore_steerer1}};
+assign main_litedramcore_dfi_p1_reset_n = 1'd1;
+assign main_litedramcore_dfi_p1_cke = {1{main_litedramcore_steerer2}};
+assign main_litedramcore_dfi_p1_odt = {1{main_litedramcore_steerer3}};
+assign main_litedramcore_dfi_p2_reset_n = 1'd1;
+assign main_litedramcore_dfi_p2_cke = {1{main_litedramcore_steerer4}};
+assign main_litedramcore_dfi_p2_odt = {1{main_litedramcore_steerer5}};
+assign main_litedramcore_dfi_p3_reset_n = 1'd1;
+assign main_litedramcore_dfi_p3_cke = {1{main_litedramcore_steerer6}};
+assign main_litedramcore_dfi_p3_odt = {1{main_litedramcore_steerer7}};
+assign main_litedramcore_tfawcon_count = ((((main_litedramcore_tfawcon_window[0] + main_litedramcore_tfawcon_window[1]) + main_litedramcore_tfawcon_window[2]) + main_litedramcore_tfawcon_window[3]) + main_litedramcore_tfawcon_window[4]);
+
+// synthesis translate_off
+reg dummy_d_287;
+// synthesis translate_on
+always @(*) begin
+	builder_multiplexer_next_state <= 4'd0;
+	builder_multiplexer_next_state <= builder_multiplexer_state;
+	case (builder_multiplexer_state)
+		1'd1: begin
+			if (main_litedramcore_read_available) begin
+				if (((~main_litedramcore_write_available) | main_litedramcore_max_time1)) begin
+					builder_multiplexer_next_state <= 2'd3;
+				end
+			end
+			if (main_litedramcore_go_to_refresh) begin
+				builder_multiplexer_next_state <= 2'd2;
+			end
+		end
+		2'd2: begin
+			if (main_litedramcore_cmd_last) begin
+				builder_multiplexer_next_state <= 1'd0;
+			end
+		end
+		2'd3: begin
+			if (main_litedramcore_twtrcon_ready) begin
+				builder_multiplexer_next_state <= 1'd0;
+			end
+		end
+		3'd4: begin
+			builder_multiplexer_next_state <= 3'd5;
+		end
+		3'd5: begin
+			builder_multiplexer_next_state <= 3'd6;
+		end
+		3'd6: begin
+			builder_multiplexer_next_state <= 3'd7;
+		end
+		3'd7: begin
+			builder_multiplexer_next_state <= 4'd8;
+		end
+		4'd8: begin
+			builder_multiplexer_next_state <= 4'd9;
+		end
+		4'd9: begin
+			builder_multiplexer_next_state <= 4'd10;
+		end
+		4'd10: begin
+			builder_multiplexer_next_state <= 1'd1;
+		end
+		default: begin
+			if (main_litedramcore_write_available) begin
+				if (((~main_litedramcore_read_available) | main_litedramcore_max_time0)) begin
+					builder_multiplexer_next_state <= 3'd4;
+				end
+			end
+			if (main_litedramcore_go_to_refresh) begin
+				builder_multiplexer_next_state <= 2'd2;
+			end
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_287 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_288;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_en0 <= 1'd0;
+	case (builder_multiplexer_state)
+		1'd1: begin
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		4'd9: begin
+		end
+		4'd10: begin
+		end
+		default: begin
+			main_litedramcore_en0 <= 1'd1;
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_288 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_289;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_choose_cmd_cmd_ready <= 1'd0;
+	case (builder_multiplexer_state)
+		1'd1: begin
+			if (1'd0) begin
+			end else begin
+				main_litedramcore_choose_cmd_cmd_ready <= ((~((main_litedramcore_choose_cmd_cmd_payload_ras & (~main_litedramcore_choose_cmd_cmd_payload_cas)) & (~main_litedramcore_choose_cmd_cmd_payload_we))) | main_litedramcore_ras_allowed);
+			end
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		4'd9: begin
+		end
+		4'd10: begin
+		end
+		default: begin
+			if (1'd0) begin
+			end else begin
+				main_litedramcore_choose_cmd_cmd_ready <= ((~((main_litedramcore_choose_cmd_cmd_payload_ras & (~main_litedramcore_choose_cmd_cmd_payload_cas)) & (~main_litedramcore_choose_cmd_cmd_payload_we))) | main_litedramcore_ras_allowed);
+			end
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_289 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_290;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_choose_req_want_reads <= 1'd0;
+	case (builder_multiplexer_state)
+		1'd1: begin
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		4'd9: begin
+		end
+		4'd10: begin
+		end
+		default: begin
+			main_litedramcore_choose_req_want_reads <= 1'd1;
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_290 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_291;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_choose_req_want_writes <= 1'd0;
+	case (builder_multiplexer_state)
+		1'd1: begin
+			main_litedramcore_choose_req_want_writes <= 1'd1;
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		4'd9: begin
+		end
+		4'd10: begin
+		end
+		default: begin
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_291 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_292;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_choose_req_cmd_ready <= 1'd0;
+	case (builder_multiplexer_state)
+		1'd1: begin
+			if (1'd0) begin
+				main_litedramcore_choose_req_cmd_ready <= (main_litedramcore_cas_allowed & ((~((main_litedramcore_choose_req_cmd_payload_ras & (~main_litedramcore_choose_req_cmd_payload_cas)) & (~main_litedramcore_choose_req_cmd_payload_we))) | main_litedramcore_ras_allowed));
+			end else begin
+				main_litedramcore_choose_req_cmd_ready <= main_litedramcore_cas_allowed;
+			end
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		4'd9: begin
+		end
+		4'd10: begin
+		end
+		default: begin
+			if (1'd0) begin
+				main_litedramcore_choose_req_cmd_ready <= (main_litedramcore_cas_allowed & ((~((main_litedramcore_choose_req_cmd_payload_ras & (~main_litedramcore_choose_req_cmd_payload_cas)) & (~main_litedramcore_choose_req_cmd_payload_we))) | main_litedramcore_ras_allowed));
+			end else begin
+				main_litedramcore_choose_req_cmd_ready <= main_litedramcore_cas_allowed;
+			end
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_292 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_293;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_steerer_sel3 <= 2'd0;
+	case (builder_multiplexer_state)
+		1'd1: begin
+			main_litedramcore_steerer_sel3 <= 1'd0;
+			if ((main_a7ddrphy_wrphase_storage == 2'd3)) begin
+				main_litedramcore_steerer_sel3 <= 2'd2;
+			end
+			if ((main_litedramcore_wrcmdphase == 2'd3)) begin
+				main_litedramcore_steerer_sel3 <= 1'd1;
+			end
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		4'd9: begin
+		end
+		4'd10: begin
+		end
+		default: begin
+			main_litedramcore_steerer_sel3 <= 1'd0;
+			if ((main_a7ddrphy_rdphase_storage == 2'd3)) begin
+				main_litedramcore_steerer_sel3 <= 2'd2;
+			end
+			if ((main_litedramcore_rdcmdphase == 2'd3)) begin
+				main_litedramcore_steerer_sel3 <= 1'd1;
+			end
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_293 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_294;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_en1 <= 1'd0;
+	case (builder_multiplexer_state)
+		1'd1: begin
+			main_litedramcore_en1 <= 1'd1;
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		4'd9: begin
+		end
+		4'd10: begin
+		end
+		default: begin
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_294 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_295;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_steerer_sel0 <= 2'd0;
+	case (builder_multiplexer_state)
+		1'd1: begin
+			main_litedramcore_steerer_sel0 <= 1'd0;
+			if ((main_a7ddrphy_wrphase_storage == 1'd0)) begin
+				main_litedramcore_steerer_sel0 <= 2'd2;
+			end
+			if ((main_litedramcore_wrcmdphase == 1'd0)) begin
+				main_litedramcore_steerer_sel0 <= 1'd1;
+			end
+		end
+		2'd2: begin
+			main_litedramcore_steerer_sel0 <= 2'd3;
+		end
+		2'd3: begin
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		4'd9: begin
+		end
+		4'd10: begin
+		end
+		default: begin
+			main_litedramcore_steerer_sel0 <= 1'd0;
+			if ((main_a7ddrphy_rdphase_storage == 1'd0)) begin
+				main_litedramcore_steerer_sel0 <= 2'd2;
+			end
+			if ((main_litedramcore_rdcmdphase == 1'd0)) begin
+				main_litedramcore_steerer_sel0 <= 1'd1;
+			end
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_295 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_296;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_cmd_ready <= 1'd0;
+	case (builder_multiplexer_state)
+		1'd1: begin
+		end
+		2'd2: begin
+			main_litedramcore_cmd_ready <= 1'd1;
+		end
+		2'd3: begin
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		4'd9: begin
+		end
+		4'd10: begin
+		end
+		default: begin
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_296 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_297;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_steerer_sel1 <= 2'd0;
+	case (builder_multiplexer_state)
+		1'd1: begin
+			main_litedramcore_steerer_sel1 <= 1'd0;
+			if ((main_a7ddrphy_wrphase_storage == 1'd1)) begin
+				main_litedramcore_steerer_sel1 <= 2'd2;
+			end
+			if ((main_litedramcore_wrcmdphase == 1'd1)) begin
+				main_litedramcore_steerer_sel1 <= 1'd1;
+			end
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		4'd9: begin
+		end
+		4'd10: begin
+		end
+		default: begin
+			main_litedramcore_steerer_sel1 <= 1'd0;
+			if ((main_a7ddrphy_rdphase_storage == 1'd1)) begin
+				main_litedramcore_steerer_sel1 <= 2'd2;
+			end
+			if ((main_litedramcore_rdcmdphase == 1'd1)) begin
+				main_litedramcore_steerer_sel1 <= 1'd1;
+			end
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_297 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_298;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_steerer_sel2 <= 2'd0;
+	case (builder_multiplexer_state)
+		1'd1: begin
+			main_litedramcore_steerer_sel2 <= 1'd0;
+			if ((main_a7ddrphy_wrphase_storage == 2'd2)) begin
+				main_litedramcore_steerer_sel2 <= 2'd2;
+			end
+			if ((main_litedramcore_wrcmdphase == 2'd2)) begin
+				main_litedramcore_steerer_sel2 <= 1'd1;
+			end
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		4'd9: begin
+		end
+		4'd10: begin
+		end
+		default: begin
+			main_litedramcore_steerer_sel2 <= 1'd0;
+			if ((main_a7ddrphy_rdphase_storage == 2'd2)) begin
+				main_litedramcore_steerer_sel2 <= 2'd2;
+			end
+			if ((main_litedramcore_rdcmdphase == 2'd2)) begin
+				main_litedramcore_steerer_sel2 <= 1'd1;
+			end
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_298 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_299;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_choose_cmd_want_activates <= 1'd0;
+	case (builder_multiplexer_state)
+		1'd1: begin
+			if (1'd0) begin
+			end else begin
+				main_litedramcore_choose_cmd_want_activates <= main_litedramcore_ras_allowed;
+			end
+		end
+		2'd2: begin
+		end
+		2'd3: begin
+		end
+		3'd4: begin
+		end
+		3'd5: begin
+		end
+		3'd6: begin
+		end
+		3'd7: begin
+		end
+		4'd8: begin
+		end
+		4'd9: begin
+		end
+		4'd10: begin
+		end
+		default: begin
+			if (1'd0) begin
+			end else begin
+				main_litedramcore_choose_cmd_want_activates <= main_litedramcore_ras_allowed;
+			end
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_299 = dummy_s;
+// synthesis translate_on
+end
+assign builder_roundrobin0_request = {(((main_user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((builder_locked0 | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid)};
+assign builder_roundrobin0_ce = ((~main_litedramcore_interface_bank0_valid) & (~main_litedramcore_interface_bank0_lock));
+assign main_litedramcore_interface_bank0_addr = builder_rhs_array_muxed12;
+assign main_litedramcore_interface_bank0_we = builder_rhs_array_muxed13;
+assign main_litedramcore_interface_bank0_valid = builder_rhs_array_muxed14;
+assign builder_roundrobin1_request = {(((main_user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((builder_locked1 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid)};
+assign builder_roundrobin1_ce = ((~main_litedramcore_interface_bank1_valid) & (~main_litedramcore_interface_bank1_lock));
+assign main_litedramcore_interface_bank1_addr = builder_rhs_array_muxed15;
+assign main_litedramcore_interface_bank1_we = builder_rhs_array_muxed16;
+assign main_litedramcore_interface_bank1_valid = builder_rhs_array_muxed17;
+assign builder_roundrobin2_request = {(((main_user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((builder_locked2 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid)};
+assign builder_roundrobin2_ce = ((~main_litedramcore_interface_bank2_valid) & (~main_litedramcore_interface_bank2_lock));
+assign main_litedramcore_interface_bank2_addr = builder_rhs_array_muxed18;
+assign main_litedramcore_interface_bank2_we = builder_rhs_array_muxed19;
+assign main_litedramcore_interface_bank2_valid = builder_rhs_array_muxed20;
+assign builder_roundrobin3_request = {(((main_user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((builder_locked3 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid)};
+assign builder_roundrobin3_ce = ((~main_litedramcore_interface_bank3_valid) & (~main_litedramcore_interface_bank3_lock));
+assign main_litedramcore_interface_bank3_addr = builder_rhs_array_muxed21;
+assign main_litedramcore_interface_bank3_we = builder_rhs_array_muxed22;
+assign main_litedramcore_interface_bank3_valid = builder_rhs_array_muxed23;
+assign builder_roundrobin4_request = {(((main_user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((builder_locked4 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid)};
+assign builder_roundrobin4_ce = ((~main_litedramcore_interface_bank4_valid) & (~main_litedramcore_interface_bank4_lock));
+assign main_litedramcore_interface_bank4_addr = builder_rhs_array_muxed24;
+assign main_litedramcore_interface_bank4_we = builder_rhs_array_muxed25;
+assign main_litedramcore_interface_bank4_valid = builder_rhs_array_muxed26;
+assign builder_roundrobin5_request = {(((main_user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((builder_locked5 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid)};
+assign builder_roundrobin5_ce = ((~main_litedramcore_interface_bank5_valid) & (~main_litedramcore_interface_bank5_lock));
+assign main_litedramcore_interface_bank5_addr = builder_rhs_array_muxed27;
+assign main_litedramcore_interface_bank5_we = builder_rhs_array_muxed28;
+assign main_litedramcore_interface_bank5_valid = builder_rhs_array_muxed29;
+assign builder_roundrobin6_request = {(((main_user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((builder_locked6 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid)};
+assign builder_roundrobin6_ce = ((~main_litedramcore_interface_bank6_valid) & (~main_litedramcore_interface_bank6_lock));
+assign main_litedramcore_interface_bank6_addr = builder_rhs_array_muxed30;
+assign main_litedramcore_interface_bank6_we = builder_rhs_array_muxed31;
+assign main_litedramcore_interface_bank6_valid = builder_rhs_array_muxed32;
+assign builder_roundrobin7_request = {(((main_user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((builder_locked7 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))))) & main_user_port_cmd_valid)};
+assign builder_roundrobin7_ce = ((~main_litedramcore_interface_bank7_valid) & (~main_litedramcore_interface_bank7_lock));
+assign main_litedramcore_interface_bank7_addr = builder_rhs_array_muxed33;
+assign main_litedramcore_interface_bank7_we = builder_rhs_array_muxed34;
+assign main_litedramcore_interface_bank7_valid = builder_rhs_array_muxed35;
+assign main_user_port_cmd_ready = ((((((((1'd0 | (((builder_roundrobin0_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((builder_locked0 | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank0_ready)) | (((builder_roundrobin1_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((builder_locked1 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank1_ready)) | (((builder_roundrobin2_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((builder_locked2 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank2_ready)) | (((builder_roundrobin3_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((builder_locked3 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank3_ready)) | (((builder_roundrobin4_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((builder_locked4 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank4_ready)) | (((builder_roundrobin5_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((builder_locked5 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank5_ready)) | (((builder_roundrobin6_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((builder_locked6 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_litedramcore_interface_bank6_ready)) | (((builder_roundrobin7_grant == 1'd0) & ((main_user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((builder_locked7 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0)))))) & main_litedramcore_interface_bank7_ready));
+assign main_user_port_wdata_ready = builder_new_master_wdata_ready1;
+assign main_user_port_rdata_valid = builder_new_master_rdata_valid8;
+
+// synthesis translate_off
+reg dummy_d_300;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_interface_wdata <= 128'd0;
+	case ({builder_new_master_wdata_ready1})
+		1'd1: begin
+			main_litedramcore_interface_wdata <= main_user_port_wdata_payload_data;
+		end
+		default: begin
+			main_litedramcore_interface_wdata <= 1'd0;
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_300 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_301;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_interface_wdata_we <= 16'd0;
+	case ({builder_new_master_wdata_ready1})
+		1'd1: begin
+			main_litedramcore_interface_wdata_we <= main_user_port_wdata_payload_we;
+		end
+		default: begin
+			main_litedramcore_interface_wdata_we <= 1'd0;
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_301 = dummy_s;
+// synthesis translate_on
+end
+assign main_user_port_rdata_payload_data = main_litedramcore_interface_rdata;
+assign builder_roundrobin0_grant = 1'd0;
+assign builder_roundrobin1_grant = 1'd0;
+assign builder_roundrobin2_grant = 1'd0;
+assign builder_roundrobin3_grant = 1'd0;
+assign builder_roundrobin4_grant = 1'd0;
+assign builder_roundrobin5_grant = 1'd0;
+assign builder_roundrobin6_grant = 1'd0;
+assign builder_roundrobin7_grant = 1'd0;
+
+// synthesis translate_off
+reg dummy_d_302;
+// synthesis translate_on
+always @(*) begin
+	builder_next_state <= 2'd0;
+	builder_next_state <= builder_state;
+	case (builder_state)
+		1'd1: begin
+			builder_next_state <= 2'd2;
+		end
+		2'd2: begin
+			builder_next_state <= 1'd0;
+		end
+		default: begin
+			if ((builder_litedramcore_wishbone_cyc & builder_litedramcore_wishbone_stb)) begin
+				builder_next_state <= 1'd1;
+			end
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_302 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_303;
+// synthesis translate_on
+always @(*) begin
+	builder_litedramcore_dat_w_next_value0 <= 8'd0;
+	case (builder_state)
+		1'd1: begin
+		end
+		2'd2: begin
+		end
+		default: begin
+			builder_litedramcore_dat_w_next_value0 <= builder_litedramcore_wishbone_dat_w;
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_303 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_304;
+// synthesis translate_on
+always @(*) begin
+	builder_litedramcore_dat_w_next_value_ce0 <= 1'd0;
+	case (builder_state)
+		1'd1: begin
+		end
+		2'd2: begin
+		end
+		default: begin
+			builder_litedramcore_dat_w_next_value_ce0 <= 1'd1;
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_304 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_305;
+// synthesis translate_on
+always @(*) begin
+	builder_litedramcore_adr_next_value1 <= 14'd0;
+	case (builder_state)
+		1'd1: begin
+			builder_litedramcore_adr_next_value1 <= 1'd0;
+		end
+		2'd2: begin
+		end
+		default: begin
+			if ((builder_litedramcore_wishbone_cyc & builder_litedramcore_wishbone_stb)) begin
+				builder_litedramcore_adr_next_value1 <= builder_litedramcore_wishbone_adr;
+			end
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_305 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_306;
+// synthesis translate_on
+always @(*) begin
+	builder_litedramcore_adr_next_value_ce1 <= 1'd0;
+	case (builder_state)
+		1'd1: begin
+			builder_litedramcore_adr_next_value_ce1 <= 1'd1;
+		end
+		2'd2: begin
+		end
+		default: begin
+			if ((builder_litedramcore_wishbone_cyc & builder_litedramcore_wishbone_stb)) begin
+				builder_litedramcore_adr_next_value_ce1 <= 1'd1;
+			end
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_306 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_307;
+// synthesis translate_on
+always @(*) begin
+	builder_litedramcore_we_next_value2 <= 1'd0;
+	case (builder_state)
+		1'd1: begin
+			builder_litedramcore_we_next_value2 <= 1'd0;
+		end
+		2'd2: begin
+		end
+		default: begin
+			if ((builder_litedramcore_wishbone_cyc & builder_litedramcore_wishbone_stb)) begin
+				builder_litedramcore_we_next_value2 <= (builder_litedramcore_wishbone_we & (builder_litedramcore_wishbone_sel != 1'd0));
+			end
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_307 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_308;
+// synthesis translate_on
+always @(*) begin
+	builder_litedramcore_we_next_value_ce2 <= 1'd0;
+	case (builder_state)
+		1'd1: begin
+			builder_litedramcore_we_next_value_ce2 <= 1'd1;
+		end
+		2'd2: begin
+		end
+		default: begin
+			if ((builder_litedramcore_wishbone_cyc & builder_litedramcore_wishbone_stb)) begin
+				builder_litedramcore_we_next_value_ce2 <= 1'd1;
+			end
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_308 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_309;
+// synthesis translate_on
+always @(*) begin
+	builder_litedramcore_wishbone_dat_r <= 32'd0;
+	case (builder_state)
+		1'd1: begin
+		end
+		2'd2: begin
+			builder_litedramcore_wishbone_dat_r <= builder_litedramcore_dat_r;
+		end
+		default: begin
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_309 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_310;
+// synthesis translate_on
+always @(*) begin
+	builder_litedramcore_wishbone_ack <= 1'd0;
+	case (builder_state)
+		1'd1: begin
+		end
+		2'd2: begin
+			builder_litedramcore_wishbone_ack <= 1'd1;
+		end
+		default: begin
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_310 = dummy_s;
+// synthesis translate_on
+end
+assign builder_litedramcore_wishbone_adr = main_wb_bus_adr;
+assign builder_litedramcore_wishbone_dat_w = main_wb_bus_dat_w;
+assign main_wb_bus_dat_r = builder_litedramcore_wishbone_dat_r;
+assign builder_litedramcore_wishbone_sel = main_wb_bus_sel;
+assign builder_litedramcore_wishbone_cyc = main_wb_bus_cyc;
+assign builder_litedramcore_wishbone_stb = main_wb_bus_stb;
+assign main_wb_bus_ack = builder_litedramcore_wishbone_ack;
+assign builder_litedramcore_wishbone_we = main_wb_bus_we;
+assign builder_litedramcore_wishbone_cti = main_wb_bus_cti;
+assign builder_litedramcore_wishbone_bte = main_wb_bus_bte;
+assign main_wb_bus_err = builder_litedramcore_wishbone_err;
+assign builder_csrbank0_sel = (builder_interface0_bank_bus_adr[13:9] == 1'd1);
+assign builder_csrbank0_init_done0_r = builder_interface0_bank_bus_dat_w[0];
+
+// synthesis translate_off
+reg dummy_d_311;
+// synthesis translate_on
+always @(*) begin
+	builder_csrbank0_init_done0_re <= 1'd0;
+	if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd0))) begin
+		builder_csrbank0_init_done0_re <= builder_interface0_bank_bus_we;
+	end
+// synthesis translate_off
+	dummy_d_311 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_312;
+// synthesis translate_on
+always @(*) begin
+	builder_csrbank0_init_done0_we <= 1'd0;
+	if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd0))) begin
+		builder_csrbank0_init_done0_we <= (~builder_interface0_bank_bus_we);
+	end
+// synthesis translate_off
+	dummy_d_312 = dummy_s;
+// synthesis translate_on
+end
+assign builder_csrbank0_init_error0_r = builder_interface0_bank_bus_dat_w[0];
+
+// synthesis translate_off
+reg dummy_d_313;
+// synthesis translate_on
+always @(*) begin
+	builder_csrbank0_init_error0_re <= 1'd0;
+	if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd1))) begin
+		builder_csrbank0_init_error0_re <= builder_interface0_bank_bus_we;
+	end
+// synthesis translate_off
+	dummy_d_313 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_314;
+// synthesis translate_on
+always @(*) begin
+	builder_csrbank0_init_error0_we <= 1'd0;
+	if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd1))) begin
+		builder_csrbank0_init_error0_we <= (~builder_interface0_bank_bus_we);
+	end
+// synthesis translate_off
+	dummy_d_314 = dummy_s;
+// synthesis translate_on
+end
+assign builder_csrbank0_init_done0_w = main_init_done_storage;
+assign builder_csrbank0_init_error0_w = main_init_error_storage;
+assign builder_csrbank1_sel = (builder_interface1_bank_bus_adr[13:9] == 2'd2);
+assign builder_csrbank1_rst0_r = builder_interface1_bank_bus_dat_w[0];
+
+// synthesis translate_off
+reg dummy_d_315;
+// synthesis translate_on
+always @(*) begin
+	builder_csrbank1_rst0_re <= 1'd0;
+	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd0))) begin
+		builder_csrbank1_rst0_re <= builder_interface1_bank_bus_we;
+	end
+// synthesis translate_off
+	dummy_d_315 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_316;
+// synthesis translate_on
+always @(*) begin
+	builder_csrbank1_rst0_we <= 1'd0;
+	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd0))) begin
+		builder_csrbank1_rst0_we <= (~builder_interface1_bank_bus_we);
+	end
+// synthesis translate_off
+	dummy_d_316 = dummy_s;
+// synthesis translate_on
+end
+assign builder_csrbank1_half_sys8x_taps0_r = builder_interface1_bank_bus_dat_w[4:0];
+
+// synthesis translate_off
+reg dummy_d_317;
+// synthesis translate_on
+always @(*) begin
+	builder_csrbank1_half_sys8x_taps0_we <= 1'd0;
+	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd1))) begin
+		builder_csrbank1_half_sys8x_taps0_we <= (~builder_interface1_bank_bus_we);
+	end
+// synthesis translate_off
+	dummy_d_317 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_318;
+// synthesis translate_on
+always @(*) begin
+	builder_csrbank1_half_sys8x_taps0_re <= 1'd0;
+	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd1))) begin
+		builder_csrbank1_half_sys8x_taps0_re <= builder_interface1_bank_bus_we;
+	end
+// synthesis translate_off
+	dummy_d_318 = dummy_s;
+// synthesis translate_on
+end
+assign builder_csrbank1_wlevel_en0_r = builder_interface1_bank_bus_dat_w[0];
+
+// synthesis translate_off
+reg dummy_d_319;
+// synthesis translate_on
+always @(*) begin
+	builder_csrbank1_wlevel_en0_re <= 1'd0;
+	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd2))) begin
+		builder_csrbank1_wlevel_en0_re <= builder_interface1_bank_bus_we;
+	end
+// synthesis translate_off
+	dummy_d_319 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_320;
+// synthesis translate_on
+always @(*) begin
+	builder_csrbank1_wlevel_en0_we <= 1'd0;
+	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd2))) begin
+		builder_csrbank1_wlevel_en0_we <= (~builder_interface1_bank_bus_we);
+	end
+// synthesis translate_off
+	dummy_d_320 = dummy_s;
+// synthesis translate_on
+end
+assign main_a7ddrphy_wlevel_strobe_r = builder_interface1_bank_bus_dat_w[0];
+
+// synthesis translate_off
+reg dummy_d_321;
+// synthesis translate_on
+always @(*) begin
+	main_a7ddrphy_wlevel_strobe_we <= 1'd0;
+	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd3))) begin
+		main_a7ddrphy_wlevel_strobe_we <= (~builder_interface1_bank_bus_we);
+	end
+// synthesis translate_off
+	dummy_d_321 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_322;
+// synthesis translate_on
+always @(*) begin
+	main_a7ddrphy_wlevel_strobe_re <= 1'd0;
+	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd3))) begin
+		main_a7ddrphy_wlevel_strobe_re <= builder_interface1_bank_bus_we;
+	end
+// synthesis translate_off
+	dummy_d_322 = dummy_s;
+// synthesis translate_on
+end
+assign builder_csrbank1_dly_sel0_r = builder_interface1_bank_bus_dat_w[1:0];
+
+// synthesis translate_off
+reg dummy_d_323;
+// synthesis translate_on
+always @(*) begin
+	builder_csrbank1_dly_sel0_we <= 1'd0;
+	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd4))) begin
+		builder_csrbank1_dly_sel0_we <= (~builder_interface1_bank_bus_we);
+	end
+// synthesis translate_off
+	dummy_d_323 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_324;
+// synthesis translate_on
+always @(*) begin
+	builder_csrbank1_dly_sel0_re <= 1'd0;
+	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd4))) begin
+		builder_csrbank1_dly_sel0_re <= builder_interface1_bank_bus_we;
+	end
+// synthesis translate_off
+	dummy_d_324 = dummy_s;
+// synthesis translate_on
+end
+assign main_a7ddrphy_rdly_dq_rst_r = builder_interface1_bank_bus_dat_w[0];
+
+// synthesis translate_off
+reg dummy_d_325;
+// synthesis translate_on
+always @(*) begin
+	main_a7ddrphy_rdly_dq_rst_re <= 1'd0;
+	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd5))) begin
+		main_a7ddrphy_rdly_dq_rst_re <= builder_interface1_bank_bus_we;
+	end
+// synthesis translate_off
+	dummy_d_325 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_326;
+// synthesis translate_on
+always @(*) begin
+	main_a7ddrphy_rdly_dq_rst_we <= 1'd0;
+	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd5))) begin
+		main_a7ddrphy_rdly_dq_rst_we <= (~builder_interface1_bank_bus_we);
+	end
+// synthesis translate_off
+	dummy_d_326 = dummy_s;
+// synthesis translate_on
+end
+assign main_a7ddrphy_rdly_dq_inc_r = builder_interface1_bank_bus_dat_w[0];
+
+// synthesis translate_off
+reg dummy_d_327;
+// synthesis translate_on
+always @(*) begin
+	main_a7ddrphy_rdly_dq_inc_re <= 1'd0;
+	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd6))) begin
+		main_a7ddrphy_rdly_dq_inc_re <= builder_interface1_bank_bus_we;
+	end
+// synthesis translate_off
+	dummy_d_327 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_328;
+// synthesis translate_on
+always @(*) begin
+	main_a7ddrphy_rdly_dq_inc_we <= 1'd0;
+	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd6))) begin
+		main_a7ddrphy_rdly_dq_inc_we <= (~builder_interface1_bank_bus_we);
+	end
+// synthesis translate_off
+	dummy_d_328 = dummy_s;
+// synthesis translate_on
+end
+assign main_a7ddrphy_rdly_dq_bitslip_rst_r = builder_interface1_bank_bus_dat_w[0];
+
+// synthesis translate_off
+reg dummy_d_329;
+// synthesis translate_on
+always @(*) begin
+	main_a7ddrphy_rdly_dq_bitslip_rst_we <= 1'd0;
+	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd7))) begin
+		main_a7ddrphy_rdly_dq_bitslip_rst_we <= (~builder_interface1_bank_bus_we);
+	end
+// synthesis translate_off
+	dummy_d_329 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_330;
+// synthesis translate_on
+always @(*) begin
+	main_a7ddrphy_rdly_dq_bitslip_rst_re <= 1'd0;
+	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd7))) begin
+		main_a7ddrphy_rdly_dq_bitslip_rst_re <= builder_interface1_bank_bus_we;
+	end
+// synthesis translate_off
+	dummy_d_330 = dummy_s;
+// synthesis translate_on
+end
+assign main_a7ddrphy_rdly_dq_bitslip_r = builder_interface1_bank_bus_dat_w[0];
+
+// synthesis translate_off
+reg dummy_d_331;
+// synthesis translate_on
+always @(*) begin
+	main_a7ddrphy_rdly_dq_bitslip_we <= 1'd0;
+	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd8))) begin
+		main_a7ddrphy_rdly_dq_bitslip_we <= (~builder_interface1_bank_bus_we);
+	end
+// synthesis translate_off
+	dummy_d_331 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_332;
+// synthesis translate_on
+always @(*) begin
+	main_a7ddrphy_rdly_dq_bitslip_re <= 1'd0;
+	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd8))) begin
+		main_a7ddrphy_rdly_dq_bitslip_re <= builder_interface1_bank_bus_we;
+	end
+// synthesis translate_off
+	dummy_d_332 = dummy_s;
+// synthesis translate_on
+end
+assign main_a7ddrphy_wdly_dq_bitslip_rst_r = builder_interface1_bank_bus_dat_w[0];
+
+// synthesis translate_off
+reg dummy_d_333;
+// synthesis translate_on
+always @(*) begin
+	main_a7ddrphy_wdly_dq_bitslip_rst_we <= 1'd0;
+	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd9))) begin
+		main_a7ddrphy_wdly_dq_bitslip_rst_we <= (~builder_interface1_bank_bus_we);
+	end
+// synthesis translate_off
+	dummy_d_333 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_334;
+// synthesis translate_on
+always @(*) begin
+	main_a7ddrphy_wdly_dq_bitslip_rst_re <= 1'd0;
+	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd9))) begin
+		main_a7ddrphy_wdly_dq_bitslip_rst_re <= builder_interface1_bank_bus_we;
+	end
+// synthesis translate_off
+	dummy_d_334 = dummy_s;
+// synthesis translate_on
+end
+assign main_a7ddrphy_wdly_dq_bitslip_r = builder_interface1_bank_bus_dat_w[0];
+
+// synthesis translate_off
+reg dummy_d_335;
+// synthesis translate_on
+always @(*) begin
+	main_a7ddrphy_wdly_dq_bitslip_we <= 1'd0;
+	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd10))) begin
+		main_a7ddrphy_wdly_dq_bitslip_we <= (~builder_interface1_bank_bus_we);
+	end
+// synthesis translate_off
+	dummy_d_335 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_336;
+// synthesis translate_on
+always @(*) begin
+	main_a7ddrphy_wdly_dq_bitslip_re <= 1'd0;
+	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd10))) begin
+		main_a7ddrphy_wdly_dq_bitslip_re <= builder_interface1_bank_bus_we;
+	end
+// synthesis translate_off
+	dummy_d_336 = dummy_s;
+// synthesis translate_on
+end
+assign builder_csrbank1_rdphase0_r = builder_interface1_bank_bus_dat_w[1:0];
+
+// synthesis translate_off
+reg dummy_d_337;
+// synthesis translate_on
+always @(*) begin
+	builder_csrbank1_rdphase0_we <= 1'd0;
+	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd11))) begin
+		builder_csrbank1_rdphase0_we <= (~builder_interface1_bank_bus_we);
+	end
+// synthesis translate_off
+	dummy_d_337 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_338;
+// synthesis translate_on
+always @(*) begin
+	builder_csrbank1_rdphase0_re <= 1'd0;
+	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd11))) begin
+		builder_csrbank1_rdphase0_re <= builder_interface1_bank_bus_we;
+	end
+// synthesis translate_off
+	dummy_d_338 = dummy_s;
+// synthesis translate_on
+end
+assign builder_csrbank1_wrphase0_r = builder_interface1_bank_bus_dat_w[1:0];
+
+// synthesis translate_off
+reg dummy_d_339;
+// synthesis translate_on
+always @(*) begin
+	builder_csrbank1_wrphase0_re <= 1'd0;
+	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd12))) begin
+		builder_csrbank1_wrphase0_re <= builder_interface1_bank_bus_we;
+	end
+// synthesis translate_off
+	dummy_d_339 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_340;
+// synthesis translate_on
+always @(*) begin
+	builder_csrbank1_wrphase0_we <= 1'd0;
+	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd12))) begin
+		builder_csrbank1_wrphase0_we <= (~builder_interface1_bank_bus_we);
+	end
+// synthesis translate_off
+	dummy_d_340 = dummy_s;
+// synthesis translate_on
+end
+assign builder_csrbank1_rst0_w = main_a7ddrphy_rst_storage;
+assign builder_csrbank1_half_sys8x_taps0_w = main_a7ddrphy_half_sys8x_taps_storage[4:0];
+assign builder_csrbank1_wlevel_en0_w = main_a7ddrphy_wlevel_en_storage;
+assign builder_csrbank1_dly_sel0_w = main_a7ddrphy_dly_sel_storage[1:0];
+assign builder_csrbank1_rdphase0_w = main_a7ddrphy_rdphase_storage[1:0];
+assign builder_csrbank1_wrphase0_w = main_a7ddrphy_wrphase_storage[1:0];
+assign builder_csrbank2_sel = (builder_interface2_bank_bus_adr[13:9] == 1'd0);
+assign builder_csrbank2_dfii_control0_r = builder_interface2_bank_bus_dat_w[3:0];
+
+// synthesis translate_off
+reg dummy_d_341;
+// synthesis translate_on
+always @(*) begin
+	builder_csrbank2_dfii_control0_we <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd0))) begin
+		builder_csrbank2_dfii_control0_we <= (~builder_interface2_bank_bus_we);
+	end
+// synthesis translate_off
+	dummy_d_341 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_342;
+// synthesis translate_on
+always @(*) begin
+	builder_csrbank2_dfii_control0_re <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd0))) begin
+		builder_csrbank2_dfii_control0_re <= builder_interface2_bank_bus_we;
+	end
+// synthesis translate_off
+	dummy_d_342 = dummy_s;
+// synthesis translate_on
+end
+assign builder_csrbank2_dfii_pi0_command0_r = builder_interface2_bank_bus_dat_w[5:0];
+
+// synthesis translate_off
+reg dummy_d_343;
+// synthesis translate_on
+always @(*) begin
+	builder_csrbank2_dfii_pi0_command0_re <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd1))) begin
+		builder_csrbank2_dfii_pi0_command0_re <= builder_interface2_bank_bus_we;
+	end
+// synthesis translate_off
+	dummy_d_343 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_344;
+// synthesis translate_on
+always @(*) begin
+	builder_csrbank2_dfii_pi0_command0_we <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd1))) begin
+		builder_csrbank2_dfii_pi0_command0_we <= (~builder_interface2_bank_bus_we);
+	end
+// synthesis translate_off
+	dummy_d_344 = dummy_s;
+// synthesis translate_on
+end
+assign main_litedramcore_phaseinjector0_command_issue_r = builder_interface2_bank_bus_dat_w[0];
+
+// synthesis translate_off
+reg dummy_d_345;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_phaseinjector0_command_issue_we <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd2))) begin
+		main_litedramcore_phaseinjector0_command_issue_we <= (~builder_interface2_bank_bus_we);
+	end
+// synthesis translate_off
+	dummy_d_345 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_346;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_phaseinjector0_command_issue_re <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd2))) begin
+		main_litedramcore_phaseinjector0_command_issue_re <= builder_interface2_bank_bus_we;
+	end
+// synthesis translate_off
+	dummy_d_346 = dummy_s;
+// synthesis translate_on
+end
+assign builder_csrbank2_dfii_pi0_address1_r = builder_interface2_bank_bus_dat_w[5:0];
+
+// synthesis translate_off
+reg dummy_d_347;
+// synthesis translate_on
+always @(*) begin
+	builder_csrbank2_dfii_pi0_address1_we <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd3))) begin
+		builder_csrbank2_dfii_pi0_address1_we <= (~builder_interface2_bank_bus_we);
+	end
+// synthesis translate_off
+	dummy_d_347 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_348;
+// synthesis translate_on
+always @(*) begin
+	builder_csrbank2_dfii_pi0_address1_re <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd3))) begin
+		builder_csrbank2_dfii_pi0_address1_re <= builder_interface2_bank_bus_we;
+	end
+// synthesis translate_off
+	dummy_d_348 = dummy_s;
+// synthesis translate_on
+end
+assign builder_csrbank2_dfii_pi0_address0_r = builder_interface2_bank_bus_dat_w[7:0];
+
+// synthesis translate_off
+reg dummy_d_349;
+// synthesis translate_on
+always @(*) begin
+	builder_csrbank2_dfii_pi0_address0_re <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd4))) begin
+		builder_csrbank2_dfii_pi0_address0_re <= builder_interface2_bank_bus_we;
+	end
+// synthesis translate_off
+	dummy_d_349 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_350;
+// synthesis translate_on
+always @(*) begin
+	builder_csrbank2_dfii_pi0_address0_we <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd4))) begin
+		builder_csrbank2_dfii_pi0_address0_we <= (~builder_interface2_bank_bus_we);
+	end
+// synthesis translate_off
+	dummy_d_350 = dummy_s;
+// synthesis translate_on
+end
+assign builder_csrbank2_dfii_pi0_baddress0_r = builder_interface2_bank_bus_dat_w[2:0];
+
+// synthesis translate_off
+reg dummy_d_351;
+// synthesis translate_on
+always @(*) begin
+	builder_csrbank2_dfii_pi0_baddress0_re <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd5))) begin
+		builder_csrbank2_dfii_pi0_baddress0_re <= builder_interface2_bank_bus_we;
+	end
+// synthesis translate_off
+	dummy_d_351 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_352;
+// synthesis translate_on
+always @(*) begin
+	builder_csrbank2_dfii_pi0_baddress0_we <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd5))) begin
+		builder_csrbank2_dfii_pi0_baddress0_we <= (~builder_interface2_bank_bus_we);
+	end
+// synthesis translate_off
+	dummy_d_352 = dummy_s;
+// synthesis translate_on
+end
+assign builder_csrbank2_dfii_pi0_wrdata3_r = builder_interface2_bank_bus_dat_w[7:0];
+
+// synthesis translate_off
+reg dummy_d_353;
+// synthesis translate_on
+always @(*) begin
+	builder_csrbank2_dfii_pi0_wrdata3_we <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd6))) begin
+		builder_csrbank2_dfii_pi0_wrdata3_we <= (~builder_interface2_bank_bus_we);
+	end
+// synthesis translate_off
+	dummy_d_353 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_354;
+// synthesis translate_on
+always @(*) begin
+	builder_csrbank2_dfii_pi0_wrdata3_re <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd6))) begin
+		builder_csrbank2_dfii_pi0_wrdata3_re <= builder_interface2_bank_bus_we;
+	end
+// synthesis translate_off
+	dummy_d_354 = dummy_s;
+// synthesis translate_on
+end
+assign builder_csrbank2_dfii_pi0_wrdata2_r = builder_interface2_bank_bus_dat_w[7:0];
+
+// synthesis translate_off
+reg dummy_d_355;
+// synthesis translate_on
+always @(*) begin
+	builder_csrbank2_dfii_pi0_wrdata2_re <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd7))) begin
+		builder_csrbank2_dfii_pi0_wrdata2_re <= builder_interface2_bank_bus_we;
+	end
+// synthesis translate_off
+	dummy_d_355 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_356;
+// synthesis translate_on
+always @(*) begin
+	builder_csrbank2_dfii_pi0_wrdata2_we <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 3'd7))) begin
+		builder_csrbank2_dfii_pi0_wrdata2_we <= (~builder_interface2_bank_bus_we);
+	end
+// synthesis translate_off
+	dummy_d_356 = dummy_s;
+// synthesis translate_on
+end
+assign builder_csrbank2_dfii_pi0_wrdata1_r = builder_interface2_bank_bus_dat_w[7:0];
+
+// synthesis translate_off
+reg dummy_d_357;
+// synthesis translate_on
+always @(*) begin
+	builder_csrbank2_dfii_pi0_wrdata1_we <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd8))) begin
+		builder_csrbank2_dfii_pi0_wrdata1_we <= (~builder_interface2_bank_bus_we);
+	end
+// synthesis translate_off
+	dummy_d_357 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_358;
+// synthesis translate_on
+always @(*) begin
+	builder_csrbank2_dfii_pi0_wrdata1_re <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd8))) begin
+		builder_csrbank2_dfii_pi0_wrdata1_re <= builder_interface2_bank_bus_we;
+	end
+// synthesis translate_off
+	dummy_d_358 = dummy_s;
+// synthesis translate_on
+end
+assign builder_csrbank2_dfii_pi0_wrdata0_r = builder_interface2_bank_bus_dat_w[7:0];
+
+// synthesis translate_off
+reg dummy_d_359;
+// synthesis translate_on
+always @(*) begin
+	builder_csrbank2_dfii_pi0_wrdata0_we <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd9))) begin
+		builder_csrbank2_dfii_pi0_wrdata0_we <= (~builder_interface2_bank_bus_we);
+	end
+// synthesis translate_off
+	dummy_d_359 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_360;
+// synthesis translate_on
+always @(*) begin
+	builder_csrbank2_dfii_pi0_wrdata0_re <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd9))) begin
+		builder_csrbank2_dfii_pi0_wrdata0_re <= builder_interface2_bank_bus_we;
+	end
+// synthesis translate_off
+	dummy_d_360 = dummy_s;
+// synthesis translate_on
+end
+assign builder_csrbank2_dfii_pi0_rddata3_r = builder_interface2_bank_bus_dat_w[7:0];
+
+// synthesis translate_off
+reg dummy_d_361;
+// synthesis translate_on
+always @(*) begin
+	builder_csrbank2_dfii_pi0_rddata3_re <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd10))) begin
+		builder_csrbank2_dfii_pi0_rddata3_re <= builder_interface2_bank_bus_we;
+	end
+// synthesis translate_off
+	dummy_d_361 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_362;
+// synthesis translate_on
+always @(*) begin
+	builder_csrbank2_dfii_pi0_rddata3_we <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd10))) begin
+		builder_csrbank2_dfii_pi0_rddata3_we <= (~builder_interface2_bank_bus_we);
+	end
+// synthesis translate_off
+	dummy_d_362 = dummy_s;
+// synthesis translate_on
+end
+assign builder_csrbank2_dfii_pi0_rddata2_r = builder_interface2_bank_bus_dat_w[7:0];
+
+// synthesis translate_off
+reg dummy_d_363;
+// synthesis translate_on
+always @(*) begin
+	builder_csrbank2_dfii_pi0_rddata2_we <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd11))) begin
+		builder_csrbank2_dfii_pi0_rddata2_we <= (~builder_interface2_bank_bus_we);
+	end
+// synthesis translate_off
+	dummy_d_363 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_364;
+// synthesis translate_on
+always @(*) begin
+	builder_csrbank2_dfii_pi0_rddata2_re <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd11))) begin
+		builder_csrbank2_dfii_pi0_rddata2_re <= builder_interface2_bank_bus_we;
+	end
+// synthesis translate_off
+	dummy_d_364 = dummy_s;
+// synthesis translate_on
+end
+assign builder_csrbank2_dfii_pi0_rddata1_r = builder_interface2_bank_bus_dat_w[7:0];
+
+// synthesis translate_off
+reg dummy_d_365;
+// synthesis translate_on
+always @(*) begin
+	builder_csrbank2_dfii_pi0_rddata1_we <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd12))) begin
+		builder_csrbank2_dfii_pi0_rddata1_we <= (~builder_interface2_bank_bus_we);
+	end
+// synthesis translate_off
+	dummy_d_365 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_366;
+// synthesis translate_on
+always @(*) begin
+	builder_csrbank2_dfii_pi0_rddata1_re <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd12))) begin
+		builder_csrbank2_dfii_pi0_rddata1_re <= builder_interface2_bank_bus_we;
+	end
+// synthesis translate_off
+	dummy_d_366 = dummy_s;
+// synthesis translate_on
+end
+assign builder_csrbank2_dfii_pi0_rddata0_r = builder_interface2_bank_bus_dat_w[7:0];
+
+// synthesis translate_off
+reg dummy_d_367;
+// synthesis translate_on
+always @(*) begin
+	builder_csrbank2_dfii_pi0_rddata0_re <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd13))) begin
+		builder_csrbank2_dfii_pi0_rddata0_re <= builder_interface2_bank_bus_we;
+	end
+// synthesis translate_off
+	dummy_d_367 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_368;
+// synthesis translate_on
+always @(*) begin
+	builder_csrbank2_dfii_pi0_rddata0_we <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd13))) begin
+		builder_csrbank2_dfii_pi0_rddata0_we <= (~builder_interface2_bank_bus_we);
+	end
+// synthesis translate_off
+	dummy_d_368 = dummy_s;
+// synthesis translate_on
+end
+assign builder_csrbank2_dfii_pi1_command0_r = builder_interface2_bank_bus_dat_w[5:0];
+
+// synthesis translate_off
+reg dummy_d_369;
+// synthesis translate_on
+always @(*) begin
+	builder_csrbank2_dfii_pi1_command0_re <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd14))) begin
+		builder_csrbank2_dfii_pi1_command0_re <= builder_interface2_bank_bus_we;
+	end
+// synthesis translate_off
+	dummy_d_369 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_370;
+// synthesis translate_on
+always @(*) begin
+	builder_csrbank2_dfii_pi1_command0_we <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd14))) begin
+		builder_csrbank2_dfii_pi1_command0_we <= (~builder_interface2_bank_bus_we);
+	end
+// synthesis translate_off
+	dummy_d_370 = dummy_s;
+// synthesis translate_on
+end
+assign main_litedramcore_phaseinjector1_command_issue_r = builder_interface2_bank_bus_dat_w[0];
+
+// synthesis translate_off
+reg dummy_d_371;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_phaseinjector1_command_issue_we <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd15))) begin
+		main_litedramcore_phaseinjector1_command_issue_we <= (~builder_interface2_bank_bus_we);
+	end
+// synthesis translate_off
+	dummy_d_371 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_372;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_phaseinjector1_command_issue_re <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 4'd15))) begin
+		main_litedramcore_phaseinjector1_command_issue_re <= builder_interface2_bank_bus_we;
+	end
+// synthesis translate_off
+	dummy_d_372 = dummy_s;
+// synthesis translate_on
+end
+assign builder_csrbank2_dfii_pi1_address1_r = builder_interface2_bank_bus_dat_w[5:0];
+
+// synthesis translate_off
+reg dummy_d_373;
+// synthesis translate_on
+always @(*) begin
+	builder_csrbank2_dfii_pi1_address1_we <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd16))) begin
+		builder_csrbank2_dfii_pi1_address1_we <= (~builder_interface2_bank_bus_we);
+	end
+// synthesis translate_off
+	dummy_d_373 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_374;
+// synthesis translate_on
+always @(*) begin
+	builder_csrbank2_dfii_pi1_address1_re <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd16))) begin
+		builder_csrbank2_dfii_pi1_address1_re <= builder_interface2_bank_bus_we;
+	end
+// synthesis translate_off
+	dummy_d_374 = dummy_s;
+// synthesis translate_on
+end
+assign builder_csrbank2_dfii_pi1_address0_r = builder_interface2_bank_bus_dat_w[7:0];
+
+// synthesis translate_off
+reg dummy_d_375;
+// synthesis translate_on
+always @(*) begin
+	builder_csrbank2_dfii_pi1_address0_re <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd17))) begin
+		builder_csrbank2_dfii_pi1_address0_re <= builder_interface2_bank_bus_we;
+	end
+// synthesis translate_off
+	dummy_d_375 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_376;
+// synthesis translate_on
+always @(*) begin
+	builder_csrbank2_dfii_pi1_address0_we <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd17))) begin
+		builder_csrbank2_dfii_pi1_address0_we <= (~builder_interface2_bank_bus_we);
+	end
+// synthesis translate_off
+	dummy_d_376 = dummy_s;
+// synthesis translate_on
+end
+assign builder_csrbank2_dfii_pi1_baddress0_r = builder_interface2_bank_bus_dat_w[2:0];
+
+// synthesis translate_off
+reg dummy_d_377;
+// synthesis translate_on
+always @(*) begin
+	builder_csrbank2_dfii_pi1_baddress0_re <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd18))) begin
+		builder_csrbank2_dfii_pi1_baddress0_re <= builder_interface2_bank_bus_we;
+	end
+// synthesis translate_off
+	dummy_d_377 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_378;
+// synthesis translate_on
+always @(*) begin
+	builder_csrbank2_dfii_pi1_baddress0_we <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd18))) begin
+		builder_csrbank2_dfii_pi1_baddress0_we <= (~builder_interface2_bank_bus_we);
+	end
+// synthesis translate_off
+	dummy_d_378 = dummy_s;
+// synthesis translate_on
+end
+assign builder_csrbank2_dfii_pi1_wrdata3_r = builder_interface2_bank_bus_dat_w[7:0];
+
+// synthesis translate_off
+reg dummy_d_379;
+// synthesis translate_on
+always @(*) begin
+	builder_csrbank2_dfii_pi1_wrdata3_we <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd19))) begin
+		builder_csrbank2_dfii_pi1_wrdata3_we <= (~builder_interface2_bank_bus_we);
+	end
+// synthesis translate_off
+	dummy_d_379 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_380;
+// synthesis translate_on
+always @(*) begin
+	builder_csrbank2_dfii_pi1_wrdata3_re <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd19))) begin
+		builder_csrbank2_dfii_pi1_wrdata3_re <= builder_interface2_bank_bus_we;
+	end
+// synthesis translate_off
+	dummy_d_380 = dummy_s;
+// synthesis translate_on
+end
+assign builder_csrbank2_dfii_pi1_wrdata2_r = builder_interface2_bank_bus_dat_w[7:0];
+
+// synthesis translate_off
+reg dummy_d_381;
+// synthesis translate_on
+always @(*) begin
+	builder_csrbank2_dfii_pi1_wrdata2_re <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd20))) begin
+		builder_csrbank2_dfii_pi1_wrdata2_re <= builder_interface2_bank_bus_we;
+	end
+// synthesis translate_off
+	dummy_d_381 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_382;
+// synthesis translate_on
+always @(*) begin
+	builder_csrbank2_dfii_pi1_wrdata2_we <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd20))) begin
+		builder_csrbank2_dfii_pi1_wrdata2_we <= (~builder_interface2_bank_bus_we);
+	end
+// synthesis translate_off
+	dummy_d_382 = dummy_s;
+// synthesis translate_on
+end
+assign builder_csrbank2_dfii_pi1_wrdata1_r = builder_interface2_bank_bus_dat_w[7:0];
+
+// synthesis translate_off
+reg dummy_d_383;
+// synthesis translate_on
+always @(*) begin
+	builder_csrbank2_dfii_pi1_wrdata1_we <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd21))) begin
+		builder_csrbank2_dfii_pi1_wrdata1_we <= (~builder_interface2_bank_bus_we);
+	end
+// synthesis translate_off
+	dummy_d_383 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_384;
+// synthesis translate_on
+always @(*) begin
+	builder_csrbank2_dfii_pi1_wrdata1_re <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd21))) begin
+		builder_csrbank2_dfii_pi1_wrdata1_re <= builder_interface2_bank_bus_we;
+	end
+// synthesis translate_off
+	dummy_d_384 = dummy_s;
+// synthesis translate_on
+end
+assign builder_csrbank2_dfii_pi1_wrdata0_r = builder_interface2_bank_bus_dat_w[7:0];
+
+// synthesis translate_off
+reg dummy_d_385;
+// synthesis translate_on
+always @(*) begin
+	builder_csrbank2_dfii_pi1_wrdata0_we <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd22))) begin
+		builder_csrbank2_dfii_pi1_wrdata0_we <= (~builder_interface2_bank_bus_we);
+	end
+// synthesis translate_off
+	dummy_d_385 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_386;
+// synthesis translate_on
+always @(*) begin
+	builder_csrbank2_dfii_pi1_wrdata0_re <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd22))) begin
+		builder_csrbank2_dfii_pi1_wrdata0_re <= builder_interface2_bank_bus_we;
+	end
+// synthesis translate_off
+	dummy_d_386 = dummy_s;
+// synthesis translate_on
+end
+assign builder_csrbank2_dfii_pi1_rddata3_r = builder_interface2_bank_bus_dat_w[7:0];
+
+// synthesis translate_off
+reg dummy_d_387;
+// synthesis translate_on
+always @(*) begin
+	builder_csrbank2_dfii_pi1_rddata3_re <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd23))) begin
+		builder_csrbank2_dfii_pi1_rddata3_re <= builder_interface2_bank_bus_we;
+	end
+// synthesis translate_off
+	dummy_d_387 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_388;
+// synthesis translate_on
+always @(*) begin
+	builder_csrbank2_dfii_pi1_rddata3_we <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd23))) begin
+		builder_csrbank2_dfii_pi1_rddata3_we <= (~builder_interface2_bank_bus_we);
+	end
+// synthesis translate_off
+	dummy_d_388 = dummy_s;
+// synthesis translate_on
+end
+assign builder_csrbank2_dfii_pi1_rddata2_r = builder_interface2_bank_bus_dat_w[7:0];
+
+// synthesis translate_off
+reg dummy_d_389;
+// synthesis translate_on
+always @(*) begin
+	builder_csrbank2_dfii_pi1_rddata2_we <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd24))) begin
+		builder_csrbank2_dfii_pi1_rddata2_we <= (~builder_interface2_bank_bus_we);
+	end
+// synthesis translate_off
+	dummy_d_389 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_390;
+// synthesis translate_on
+always @(*) begin
+	builder_csrbank2_dfii_pi1_rddata2_re <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd24))) begin
+		builder_csrbank2_dfii_pi1_rddata2_re <= builder_interface2_bank_bus_we;
+	end
+// synthesis translate_off
+	dummy_d_390 = dummy_s;
+// synthesis translate_on
+end
+assign builder_csrbank2_dfii_pi1_rddata1_r = builder_interface2_bank_bus_dat_w[7:0];
+
+// synthesis translate_off
+reg dummy_d_391;
+// synthesis translate_on
+always @(*) begin
+	builder_csrbank2_dfii_pi1_rddata1_we <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd25))) begin
+		builder_csrbank2_dfii_pi1_rddata1_we <= (~builder_interface2_bank_bus_we);
+	end
+// synthesis translate_off
+	dummy_d_391 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_392;
+// synthesis translate_on
+always @(*) begin
+	builder_csrbank2_dfii_pi1_rddata1_re <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd25))) begin
+		builder_csrbank2_dfii_pi1_rddata1_re <= builder_interface2_bank_bus_we;
+	end
+// synthesis translate_off
+	dummy_d_392 = dummy_s;
+// synthesis translate_on
+end
+assign builder_csrbank2_dfii_pi1_rddata0_r = builder_interface2_bank_bus_dat_w[7:0];
+
+// synthesis translate_off
+reg dummy_d_393;
+// synthesis translate_on
+always @(*) begin
+	builder_csrbank2_dfii_pi1_rddata0_re <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd26))) begin
+		builder_csrbank2_dfii_pi1_rddata0_re <= builder_interface2_bank_bus_we;
+	end
+// synthesis translate_off
+	dummy_d_393 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_394;
+// synthesis translate_on
+always @(*) begin
+	builder_csrbank2_dfii_pi1_rddata0_we <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd26))) begin
+		builder_csrbank2_dfii_pi1_rddata0_we <= (~builder_interface2_bank_bus_we);
+	end
+// synthesis translate_off
+	dummy_d_394 = dummy_s;
+// synthesis translate_on
+end
+assign builder_csrbank2_dfii_pi2_command0_r = builder_interface2_bank_bus_dat_w[5:0];
+
+// synthesis translate_off
+reg dummy_d_395;
+// synthesis translate_on
+always @(*) begin
+	builder_csrbank2_dfii_pi2_command0_re <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd27))) begin
+		builder_csrbank2_dfii_pi2_command0_re <= builder_interface2_bank_bus_we;
+	end
+// synthesis translate_off
+	dummy_d_395 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_396;
+// synthesis translate_on
+always @(*) begin
+	builder_csrbank2_dfii_pi2_command0_we <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd27))) begin
+		builder_csrbank2_dfii_pi2_command0_we <= (~builder_interface2_bank_bus_we);
+	end
+// synthesis translate_off
+	dummy_d_396 = dummy_s;
+// synthesis translate_on
+end
+assign main_litedramcore_phaseinjector2_command_issue_r = builder_interface2_bank_bus_dat_w[0];
+
+// synthesis translate_off
+reg dummy_d_397;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_phaseinjector2_command_issue_we <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd28))) begin
+		main_litedramcore_phaseinjector2_command_issue_we <= (~builder_interface2_bank_bus_we);
+	end
+// synthesis translate_off
+	dummy_d_397 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_398;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_phaseinjector2_command_issue_re <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd28))) begin
+		main_litedramcore_phaseinjector2_command_issue_re <= builder_interface2_bank_bus_we;
+	end
+// synthesis translate_off
+	dummy_d_398 = dummy_s;
+// synthesis translate_on
+end
+assign builder_csrbank2_dfii_pi2_address1_r = builder_interface2_bank_bus_dat_w[5:0];
+
+// synthesis translate_off
+reg dummy_d_399;
+// synthesis translate_on
+always @(*) begin
+	builder_csrbank2_dfii_pi2_address1_we <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd29))) begin
+		builder_csrbank2_dfii_pi2_address1_we <= (~builder_interface2_bank_bus_we);
+	end
+// synthesis translate_off
+	dummy_d_399 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_400;
+// synthesis translate_on
+always @(*) begin
+	builder_csrbank2_dfii_pi2_address1_re <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd29))) begin
+		builder_csrbank2_dfii_pi2_address1_re <= builder_interface2_bank_bus_we;
+	end
+// synthesis translate_off
+	dummy_d_400 = dummy_s;
+// synthesis translate_on
+end
+assign builder_csrbank2_dfii_pi2_address0_r = builder_interface2_bank_bus_dat_w[7:0];
+
+// synthesis translate_off
+reg dummy_d_401;
+// synthesis translate_on
+always @(*) begin
+	builder_csrbank2_dfii_pi2_address0_re <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd30))) begin
+		builder_csrbank2_dfii_pi2_address0_re <= builder_interface2_bank_bus_we;
+	end
+// synthesis translate_off
+	dummy_d_401 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_402;
+// synthesis translate_on
+always @(*) begin
+	builder_csrbank2_dfii_pi2_address0_we <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd30))) begin
+		builder_csrbank2_dfii_pi2_address0_we <= (~builder_interface2_bank_bus_we);
+	end
+// synthesis translate_off
+	dummy_d_402 = dummy_s;
+// synthesis translate_on
+end
+assign builder_csrbank2_dfii_pi2_baddress0_r = builder_interface2_bank_bus_dat_w[2:0];
+
+// synthesis translate_off
+reg dummy_d_403;
+// synthesis translate_on
+always @(*) begin
+	builder_csrbank2_dfii_pi2_baddress0_re <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd31))) begin
+		builder_csrbank2_dfii_pi2_baddress0_re <= builder_interface2_bank_bus_we;
+	end
+// synthesis translate_off
+	dummy_d_403 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_404;
+// synthesis translate_on
+always @(*) begin
+	builder_csrbank2_dfii_pi2_baddress0_we <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 5'd31))) begin
+		builder_csrbank2_dfii_pi2_baddress0_we <= (~builder_interface2_bank_bus_we);
+	end
+// synthesis translate_off
+	dummy_d_404 = dummy_s;
+// synthesis translate_on
+end
+assign builder_csrbank2_dfii_pi2_wrdata3_r = builder_interface2_bank_bus_dat_w[7:0];
+
+// synthesis translate_off
+reg dummy_d_405;
+// synthesis translate_on
+always @(*) begin
+	builder_csrbank2_dfii_pi2_wrdata3_we <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd32))) begin
+		builder_csrbank2_dfii_pi2_wrdata3_we <= (~builder_interface2_bank_bus_we);
+	end
+// synthesis translate_off
+	dummy_d_405 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_406;
+// synthesis translate_on
+always @(*) begin
+	builder_csrbank2_dfii_pi2_wrdata3_re <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd32))) begin
+		builder_csrbank2_dfii_pi2_wrdata3_re <= builder_interface2_bank_bus_we;
+	end
+// synthesis translate_off
+	dummy_d_406 = dummy_s;
+// synthesis translate_on
+end
+assign builder_csrbank2_dfii_pi2_wrdata2_r = builder_interface2_bank_bus_dat_w[7:0];
+
+// synthesis translate_off
+reg dummy_d_407;
+// synthesis translate_on
+always @(*) begin
+	builder_csrbank2_dfii_pi2_wrdata2_re <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd33))) begin
+		builder_csrbank2_dfii_pi2_wrdata2_re <= builder_interface2_bank_bus_we;
+	end
+// synthesis translate_off
+	dummy_d_407 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_408;
+// synthesis translate_on
+always @(*) begin
+	builder_csrbank2_dfii_pi2_wrdata2_we <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd33))) begin
+		builder_csrbank2_dfii_pi2_wrdata2_we <= (~builder_interface2_bank_bus_we);
+	end
+// synthesis translate_off
+	dummy_d_408 = dummy_s;
+// synthesis translate_on
+end
+assign builder_csrbank2_dfii_pi2_wrdata1_r = builder_interface2_bank_bus_dat_w[7:0];
+
+// synthesis translate_off
+reg dummy_d_409;
+// synthesis translate_on
+always @(*) begin
+	builder_csrbank2_dfii_pi2_wrdata1_we <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd34))) begin
+		builder_csrbank2_dfii_pi2_wrdata1_we <= (~builder_interface2_bank_bus_we);
+	end
+// synthesis translate_off
+	dummy_d_409 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_410;
+// synthesis translate_on
+always @(*) begin
+	builder_csrbank2_dfii_pi2_wrdata1_re <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd34))) begin
+		builder_csrbank2_dfii_pi2_wrdata1_re <= builder_interface2_bank_bus_we;
+	end
+// synthesis translate_off
+	dummy_d_410 = dummy_s;
+// synthesis translate_on
+end
+assign builder_csrbank2_dfii_pi2_wrdata0_r = builder_interface2_bank_bus_dat_w[7:0];
+
+// synthesis translate_off
+reg dummy_d_411;
+// synthesis translate_on
+always @(*) begin
+	builder_csrbank2_dfii_pi2_wrdata0_we <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd35))) begin
+		builder_csrbank2_dfii_pi2_wrdata0_we <= (~builder_interface2_bank_bus_we);
+	end
+// synthesis translate_off
+	dummy_d_411 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_412;
+// synthesis translate_on
+always @(*) begin
+	builder_csrbank2_dfii_pi2_wrdata0_re <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd35))) begin
+		builder_csrbank2_dfii_pi2_wrdata0_re <= builder_interface2_bank_bus_we;
+	end
+// synthesis translate_off
+	dummy_d_412 = dummy_s;
+// synthesis translate_on
+end
+assign builder_csrbank2_dfii_pi2_rddata3_r = builder_interface2_bank_bus_dat_w[7:0];
+
+// synthesis translate_off
+reg dummy_d_413;
+// synthesis translate_on
+always @(*) begin
+	builder_csrbank2_dfii_pi2_rddata3_re <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd36))) begin
+		builder_csrbank2_dfii_pi2_rddata3_re <= builder_interface2_bank_bus_we;
+	end
+// synthesis translate_off
+	dummy_d_413 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_414;
+// synthesis translate_on
+always @(*) begin
+	builder_csrbank2_dfii_pi2_rddata3_we <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd36))) begin
+		builder_csrbank2_dfii_pi2_rddata3_we <= (~builder_interface2_bank_bus_we);
+	end
+// synthesis translate_off
+	dummy_d_414 = dummy_s;
+// synthesis translate_on
+end
+assign builder_csrbank2_dfii_pi2_rddata2_r = builder_interface2_bank_bus_dat_w[7:0];
+
+// synthesis translate_off
+reg dummy_d_415;
+// synthesis translate_on
+always @(*) begin
+	builder_csrbank2_dfii_pi2_rddata2_we <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd37))) begin
+		builder_csrbank2_dfii_pi2_rddata2_we <= (~builder_interface2_bank_bus_we);
+	end
+// synthesis translate_off
+	dummy_d_415 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_416;
+// synthesis translate_on
+always @(*) begin
+	builder_csrbank2_dfii_pi2_rddata2_re <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd37))) begin
+		builder_csrbank2_dfii_pi2_rddata2_re <= builder_interface2_bank_bus_we;
+	end
+// synthesis translate_off
+	dummy_d_416 = dummy_s;
+// synthesis translate_on
+end
+assign builder_csrbank2_dfii_pi2_rddata1_r = builder_interface2_bank_bus_dat_w[7:0];
+
+// synthesis translate_off
+reg dummy_d_417;
+// synthesis translate_on
+always @(*) begin
+	builder_csrbank2_dfii_pi2_rddata1_we <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd38))) begin
+		builder_csrbank2_dfii_pi2_rddata1_we <= (~builder_interface2_bank_bus_we);
+	end
+// synthesis translate_off
+	dummy_d_417 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_418;
+// synthesis translate_on
+always @(*) begin
+	builder_csrbank2_dfii_pi2_rddata1_re <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd38))) begin
+		builder_csrbank2_dfii_pi2_rddata1_re <= builder_interface2_bank_bus_we;
+	end
+// synthesis translate_off
+	dummy_d_418 = dummy_s;
+// synthesis translate_on
+end
+assign builder_csrbank2_dfii_pi2_rddata0_r = builder_interface2_bank_bus_dat_w[7:0];
+
+// synthesis translate_off
+reg dummy_d_419;
+// synthesis translate_on
+always @(*) begin
+	builder_csrbank2_dfii_pi2_rddata0_re <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd39))) begin
+		builder_csrbank2_dfii_pi2_rddata0_re <= builder_interface2_bank_bus_we;
+	end
+// synthesis translate_off
+	dummy_d_419 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_420;
+// synthesis translate_on
+always @(*) begin
+	builder_csrbank2_dfii_pi2_rddata0_we <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd39))) begin
+		builder_csrbank2_dfii_pi2_rddata0_we <= (~builder_interface2_bank_bus_we);
+	end
+// synthesis translate_off
+	dummy_d_420 = dummy_s;
+// synthesis translate_on
+end
+assign builder_csrbank2_dfii_pi3_command0_r = builder_interface2_bank_bus_dat_w[5:0];
+
+// synthesis translate_off
+reg dummy_d_421;
+// synthesis translate_on
+always @(*) begin
+	builder_csrbank2_dfii_pi3_command0_re <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd40))) begin
+		builder_csrbank2_dfii_pi3_command0_re <= builder_interface2_bank_bus_we;
+	end
+// synthesis translate_off
+	dummy_d_421 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_422;
+// synthesis translate_on
+always @(*) begin
+	builder_csrbank2_dfii_pi3_command0_we <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd40))) begin
+		builder_csrbank2_dfii_pi3_command0_we <= (~builder_interface2_bank_bus_we);
+	end
+// synthesis translate_off
+	dummy_d_422 = dummy_s;
+// synthesis translate_on
+end
+assign main_litedramcore_phaseinjector3_command_issue_r = builder_interface2_bank_bus_dat_w[0];
+
+// synthesis translate_off
+reg dummy_d_423;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_phaseinjector3_command_issue_we <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd41))) begin
+		main_litedramcore_phaseinjector3_command_issue_we <= (~builder_interface2_bank_bus_we);
+	end
+// synthesis translate_off
+	dummy_d_423 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_424;
+// synthesis translate_on
+always @(*) begin
+	main_litedramcore_phaseinjector3_command_issue_re <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd41))) begin
+		main_litedramcore_phaseinjector3_command_issue_re <= builder_interface2_bank_bus_we;
+	end
+// synthesis translate_off
+	dummy_d_424 = dummy_s;
+// synthesis translate_on
+end
+assign builder_csrbank2_dfii_pi3_address1_r = builder_interface2_bank_bus_dat_w[5:0];
+
+// synthesis translate_off
+reg dummy_d_425;
+// synthesis translate_on
+always @(*) begin
+	builder_csrbank2_dfii_pi3_address1_we <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd42))) begin
+		builder_csrbank2_dfii_pi3_address1_we <= (~builder_interface2_bank_bus_we);
+	end
+// synthesis translate_off
+	dummy_d_425 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_426;
+// synthesis translate_on
+always @(*) begin
+	builder_csrbank2_dfii_pi3_address1_re <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd42))) begin
+		builder_csrbank2_dfii_pi3_address1_re <= builder_interface2_bank_bus_we;
+	end
+// synthesis translate_off
+	dummy_d_426 = dummy_s;
+// synthesis translate_on
+end
+assign builder_csrbank2_dfii_pi3_address0_r = builder_interface2_bank_bus_dat_w[7:0];
+
+// synthesis translate_off
+reg dummy_d_427;
+// synthesis translate_on
+always @(*) begin
+	builder_csrbank2_dfii_pi3_address0_re <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd43))) begin
+		builder_csrbank2_dfii_pi3_address0_re <= builder_interface2_bank_bus_we;
+	end
+// synthesis translate_off
+	dummy_d_427 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_428;
+// synthesis translate_on
+always @(*) begin
+	builder_csrbank2_dfii_pi3_address0_we <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd43))) begin
+		builder_csrbank2_dfii_pi3_address0_we <= (~builder_interface2_bank_bus_we);
+	end
+// synthesis translate_off
+	dummy_d_428 = dummy_s;
+// synthesis translate_on
+end
+assign builder_csrbank2_dfii_pi3_baddress0_r = builder_interface2_bank_bus_dat_w[2:0];
+
+// synthesis translate_off
+reg dummy_d_429;
+// synthesis translate_on
+always @(*) begin
+	builder_csrbank2_dfii_pi3_baddress0_re <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd44))) begin
+		builder_csrbank2_dfii_pi3_baddress0_re <= builder_interface2_bank_bus_we;
+	end
+// synthesis translate_off
+	dummy_d_429 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_430;
+// synthesis translate_on
+always @(*) begin
+	builder_csrbank2_dfii_pi3_baddress0_we <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd44))) begin
+		builder_csrbank2_dfii_pi3_baddress0_we <= (~builder_interface2_bank_bus_we);
+	end
+// synthesis translate_off
+	dummy_d_430 = dummy_s;
+// synthesis translate_on
+end
+assign builder_csrbank2_dfii_pi3_wrdata3_r = builder_interface2_bank_bus_dat_w[7:0];
+
+// synthesis translate_off
+reg dummy_d_431;
+// synthesis translate_on
+always @(*) begin
+	builder_csrbank2_dfii_pi3_wrdata3_we <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd45))) begin
+		builder_csrbank2_dfii_pi3_wrdata3_we <= (~builder_interface2_bank_bus_we);
+	end
+// synthesis translate_off
+	dummy_d_431 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_432;
+// synthesis translate_on
+always @(*) begin
+	builder_csrbank2_dfii_pi3_wrdata3_re <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd45))) begin
+		builder_csrbank2_dfii_pi3_wrdata3_re <= builder_interface2_bank_bus_we;
+	end
+// synthesis translate_off
+	dummy_d_432 = dummy_s;
+// synthesis translate_on
+end
+assign builder_csrbank2_dfii_pi3_wrdata2_r = builder_interface2_bank_bus_dat_w[7:0];
+
+// synthesis translate_off
+reg dummy_d_433;
+// synthesis translate_on
+always @(*) begin
+	builder_csrbank2_dfii_pi3_wrdata2_re <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd46))) begin
+		builder_csrbank2_dfii_pi3_wrdata2_re <= builder_interface2_bank_bus_we;
+	end
+// synthesis translate_off
+	dummy_d_433 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_434;
+// synthesis translate_on
+always @(*) begin
+	builder_csrbank2_dfii_pi3_wrdata2_we <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd46))) begin
+		builder_csrbank2_dfii_pi3_wrdata2_we <= (~builder_interface2_bank_bus_we);
+	end
+// synthesis translate_off
+	dummy_d_434 = dummy_s;
+// synthesis translate_on
+end
+assign builder_csrbank2_dfii_pi3_wrdata1_r = builder_interface2_bank_bus_dat_w[7:0];
+
+// synthesis translate_off
+reg dummy_d_435;
+// synthesis translate_on
+always @(*) begin
+	builder_csrbank2_dfii_pi3_wrdata1_we <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd47))) begin
+		builder_csrbank2_dfii_pi3_wrdata1_we <= (~builder_interface2_bank_bus_we);
+	end
+// synthesis translate_off
+	dummy_d_435 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_436;
+// synthesis translate_on
+always @(*) begin
+	builder_csrbank2_dfii_pi3_wrdata1_re <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd47))) begin
+		builder_csrbank2_dfii_pi3_wrdata1_re <= builder_interface2_bank_bus_we;
+	end
+// synthesis translate_off
+	dummy_d_436 = dummy_s;
+// synthesis translate_on
+end
+assign builder_csrbank2_dfii_pi3_wrdata0_r = builder_interface2_bank_bus_dat_w[7:0];
+
+// synthesis translate_off
+reg dummy_d_437;
+// synthesis translate_on
+always @(*) begin
+	builder_csrbank2_dfii_pi3_wrdata0_we <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd48))) begin
+		builder_csrbank2_dfii_pi3_wrdata0_we <= (~builder_interface2_bank_bus_we);
+	end
+// synthesis translate_off
+	dummy_d_437 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_438;
+// synthesis translate_on
+always @(*) begin
+	builder_csrbank2_dfii_pi3_wrdata0_re <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd48))) begin
+		builder_csrbank2_dfii_pi3_wrdata0_re <= builder_interface2_bank_bus_we;
+	end
+// synthesis translate_off
+	dummy_d_438 = dummy_s;
+// synthesis translate_on
+end
+assign builder_csrbank2_dfii_pi3_rddata3_r = builder_interface2_bank_bus_dat_w[7:0];
+
+// synthesis translate_off
+reg dummy_d_439;
+// synthesis translate_on
+always @(*) begin
+	builder_csrbank2_dfii_pi3_rddata3_re <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd49))) begin
+		builder_csrbank2_dfii_pi3_rddata3_re <= builder_interface2_bank_bus_we;
+	end
+// synthesis translate_off
+	dummy_d_439 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_440;
+// synthesis translate_on
+always @(*) begin
+	builder_csrbank2_dfii_pi3_rddata3_we <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd49))) begin
+		builder_csrbank2_dfii_pi3_rddata3_we <= (~builder_interface2_bank_bus_we);
+	end
+// synthesis translate_off
+	dummy_d_440 = dummy_s;
+// synthesis translate_on
+end
+assign builder_csrbank2_dfii_pi3_rddata2_r = builder_interface2_bank_bus_dat_w[7:0];
+
+// synthesis translate_off
+reg dummy_d_441;
+// synthesis translate_on
+always @(*) begin
+	builder_csrbank2_dfii_pi3_rddata2_we <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd50))) begin
+		builder_csrbank2_dfii_pi3_rddata2_we <= (~builder_interface2_bank_bus_we);
+	end
+// synthesis translate_off
+	dummy_d_441 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_442;
+// synthesis translate_on
+always @(*) begin
+	builder_csrbank2_dfii_pi3_rddata2_re <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd50))) begin
+		builder_csrbank2_dfii_pi3_rddata2_re <= builder_interface2_bank_bus_we;
+	end
+// synthesis translate_off
+	dummy_d_442 = dummy_s;
+// synthesis translate_on
+end
+assign builder_csrbank2_dfii_pi3_rddata1_r = builder_interface2_bank_bus_dat_w[7:0];
+
+// synthesis translate_off
+reg dummy_d_443;
+// synthesis translate_on
+always @(*) begin
+	builder_csrbank2_dfii_pi3_rddata1_we <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd51))) begin
+		builder_csrbank2_dfii_pi3_rddata1_we <= (~builder_interface2_bank_bus_we);
+	end
+// synthesis translate_off
+	dummy_d_443 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_444;
+// synthesis translate_on
+always @(*) begin
+	builder_csrbank2_dfii_pi3_rddata1_re <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd51))) begin
+		builder_csrbank2_dfii_pi3_rddata1_re <= builder_interface2_bank_bus_we;
+	end
+// synthesis translate_off
+	dummy_d_444 = dummy_s;
+// synthesis translate_on
+end
+assign builder_csrbank2_dfii_pi3_rddata0_r = builder_interface2_bank_bus_dat_w[7:0];
+
+// synthesis translate_off
+reg dummy_d_445;
+// synthesis translate_on
+always @(*) begin
+	builder_csrbank2_dfii_pi3_rddata0_re <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd52))) begin
+		builder_csrbank2_dfii_pi3_rddata0_re <= builder_interface2_bank_bus_we;
+	end
+// synthesis translate_off
+	dummy_d_445 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_446;
+// synthesis translate_on
+always @(*) begin
+	builder_csrbank2_dfii_pi3_rddata0_we <= 1'd0;
+	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 6'd52))) begin
+		builder_csrbank2_dfii_pi3_rddata0_we <= (~builder_interface2_bank_bus_we);
+	end
+// synthesis translate_off
+	dummy_d_446 = dummy_s;
+// synthesis translate_on
+end
+assign main_litedramcore_sel = main_litedramcore_storage[0];
+assign main_litedramcore_cke = main_litedramcore_storage[1];
+assign main_litedramcore_odt = main_litedramcore_storage[2];
+assign main_litedramcore_reset_n = main_litedramcore_storage[3];
+assign builder_csrbank2_dfii_control0_w = main_litedramcore_storage[3:0];
+assign builder_csrbank2_dfii_pi0_command0_w = main_litedramcore_phaseinjector0_command_storage[5:0];
+assign builder_csrbank2_dfii_pi0_address1_w = main_litedramcore_phaseinjector0_address_storage[13:8];
+assign builder_csrbank2_dfii_pi0_address0_w = main_litedramcore_phaseinjector0_address_storage[7:0];
+assign builder_csrbank2_dfii_pi0_baddress0_w = main_litedramcore_phaseinjector0_baddress_storage[2:0];
+assign builder_csrbank2_dfii_pi0_wrdata3_w = main_litedramcore_phaseinjector0_wrdata_storage[31:24];
+assign builder_csrbank2_dfii_pi0_wrdata2_w = main_litedramcore_phaseinjector0_wrdata_storage[23:16];
+assign builder_csrbank2_dfii_pi0_wrdata1_w = main_litedramcore_phaseinjector0_wrdata_storage[15:8];
+assign builder_csrbank2_dfii_pi0_wrdata0_w = main_litedramcore_phaseinjector0_wrdata_storage[7:0];
+assign builder_csrbank2_dfii_pi0_rddata3_w = main_litedramcore_phaseinjector0_rddata_status[31:24];
+assign builder_csrbank2_dfii_pi0_rddata2_w = main_litedramcore_phaseinjector0_rddata_status[23:16];
+assign builder_csrbank2_dfii_pi0_rddata1_w = main_litedramcore_phaseinjector0_rddata_status[15:8];
+assign builder_csrbank2_dfii_pi0_rddata0_w = main_litedramcore_phaseinjector0_rddata_status[7:0];
+assign main_litedramcore_phaseinjector0_rddata_we = builder_csrbank2_dfii_pi0_rddata0_we;
+assign builder_csrbank2_dfii_pi1_command0_w = main_litedramcore_phaseinjector1_command_storage[5:0];
+assign builder_csrbank2_dfii_pi1_address1_w = main_litedramcore_phaseinjector1_address_storage[13:8];
+assign builder_csrbank2_dfii_pi1_address0_w = main_litedramcore_phaseinjector1_address_storage[7:0];
+assign builder_csrbank2_dfii_pi1_baddress0_w = main_litedramcore_phaseinjector1_baddress_storage[2:0];
+assign builder_csrbank2_dfii_pi1_wrdata3_w = main_litedramcore_phaseinjector1_wrdata_storage[31:24];
+assign builder_csrbank2_dfii_pi1_wrdata2_w = main_litedramcore_phaseinjector1_wrdata_storage[23:16];
+assign builder_csrbank2_dfii_pi1_wrdata1_w = main_litedramcore_phaseinjector1_wrdata_storage[15:8];
+assign builder_csrbank2_dfii_pi1_wrdata0_w = main_litedramcore_phaseinjector1_wrdata_storage[7:0];
+assign builder_csrbank2_dfii_pi1_rddata3_w = main_litedramcore_phaseinjector1_rddata_status[31:24];
+assign builder_csrbank2_dfii_pi1_rddata2_w = main_litedramcore_phaseinjector1_rddata_status[23:16];
+assign builder_csrbank2_dfii_pi1_rddata1_w = main_litedramcore_phaseinjector1_rddata_status[15:8];
+assign builder_csrbank2_dfii_pi1_rddata0_w = main_litedramcore_phaseinjector1_rddata_status[7:0];
+assign main_litedramcore_phaseinjector1_rddata_we = builder_csrbank2_dfii_pi1_rddata0_we;
+assign builder_csrbank2_dfii_pi2_command0_w = main_litedramcore_phaseinjector2_command_storage[5:0];
+assign builder_csrbank2_dfii_pi2_address1_w = main_litedramcore_phaseinjector2_address_storage[13:8];
+assign builder_csrbank2_dfii_pi2_address0_w = main_litedramcore_phaseinjector2_address_storage[7:0];
+assign builder_csrbank2_dfii_pi2_baddress0_w = main_litedramcore_phaseinjector2_baddress_storage[2:0];
+assign builder_csrbank2_dfii_pi2_wrdata3_w = main_litedramcore_phaseinjector2_wrdata_storage[31:24];
+assign builder_csrbank2_dfii_pi2_wrdata2_w = main_litedramcore_phaseinjector2_wrdata_storage[23:16];
+assign builder_csrbank2_dfii_pi2_wrdata1_w = main_litedramcore_phaseinjector2_wrdata_storage[15:8];
+assign builder_csrbank2_dfii_pi2_wrdata0_w = main_litedramcore_phaseinjector2_wrdata_storage[7:0];
+assign builder_csrbank2_dfii_pi2_rddata3_w = main_litedramcore_phaseinjector2_rddata_status[31:24];
+assign builder_csrbank2_dfii_pi2_rddata2_w = main_litedramcore_phaseinjector2_rddata_status[23:16];
+assign builder_csrbank2_dfii_pi2_rddata1_w = main_litedramcore_phaseinjector2_rddata_status[15:8];
+assign builder_csrbank2_dfii_pi2_rddata0_w = main_litedramcore_phaseinjector2_rddata_status[7:0];
+assign main_litedramcore_phaseinjector2_rddata_we = builder_csrbank2_dfii_pi2_rddata0_we;
+assign builder_csrbank2_dfii_pi3_command0_w = main_litedramcore_phaseinjector3_command_storage[5:0];
+assign builder_csrbank2_dfii_pi3_address1_w = main_litedramcore_phaseinjector3_address_storage[13:8];
+assign builder_csrbank2_dfii_pi3_address0_w = main_litedramcore_phaseinjector3_address_storage[7:0];
+assign builder_csrbank2_dfii_pi3_baddress0_w = main_litedramcore_phaseinjector3_baddress_storage[2:0];
+assign builder_csrbank2_dfii_pi3_wrdata3_w = main_litedramcore_phaseinjector3_wrdata_storage[31:24];
+assign builder_csrbank2_dfii_pi3_wrdata2_w = main_litedramcore_phaseinjector3_wrdata_storage[23:16];
+assign builder_csrbank2_dfii_pi3_wrdata1_w = main_litedramcore_phaseinjector3_wrdata_storage[15:8];
+assign builder_csrbank2_dfii_pi3_wrdata0_w = main_litedramcore_phaseinjector3_wrdata_storage[7:0];
+assign builder_csrbank2_dfii_pi3_rddata3_w = main_litedramcore_phaseinjector3_rddata_status[31:24];
+assign builder_csrbank2_dfii_pi3_rddata2_w = main_litedramcore_phaseinjector3_rddata_status[23:16];
+assign builder_csrbank2_dfii_pi3_rddata1_w = main_litedramcore_phaseinjector3_rddata_status[15:8];
+assign builder_csrbank2_dfii_pi3_rddata0_w = main_litedramcore_phaseinjector3_rddata_status[7:0];
+assign main_litedramcore_phaseinjector3_rddata_we = builder_csrbank2_dfii_pi3_rddata0_we;
+assign builder_csr_interconnect_adr = builder_litedramcore_adr;
+assign builder_csr_interconnect_we = builder_litedramcore_we;
+assign builder_csr_interconnect_dat_w = builder_litedramcore_dat_w;
+assign builder_litedramcore_dat_r = builder_csr_interconnect_dat_r;
+assign builder_interface0_bank_bus_adr = builder_csr_interconnect_adr;
+assign builder_interface1_bank_bus_adr = builder_csr_interconnect_adr;
+assign builder_interface2_bank_bus_adr = builder_csr_interconnect_adr;
+assign builder_interface0_bank_bus_we = builder_csr_interconnect_we;
+assign builder_interface1_bank_bus_we = builder_csr_interconnect_we;
+assign builder_interface2_bank_bus_we = builder_csr_interconnect_we;
+assign builder_interface0_bank_bus_dat_w = builder_csr_interconnect_dat_w;
+assign builder_interface1_bank_bus_dat_w = builder_csr_interconnect_dat_w;
+assign builder_interface2_bank_bus_dat_w = builder_csr_interconnect_dat_w;
+assign builder_csr_interconnect_dat_r = ((builder_interface0_bank_bus_dat_r | builder_interface1_bank_bus_dat_r) | builder_interface2_bank_bus_dat_r);
+
+// synthesis translate_off
+reg dummy_d_447;
+// synthesis translate_on
+always @(*) begin
+	builder_rhs_array_muxed0 <= 1'd0;
+	case (main_litedramcore_choose_cmd_grant)
+		1'd0: begin
+			builder_rhs_array_muxed0 <= main_litedramcore_choose_cmd_valids[0];
+		end
+		1'd1: begin
+			builder_rhs_array_muxed0 <= main_litedramcore_choose_cmd_valids[1];
+		end
+		2'd2: begin
+			builder_rhs_array_muxed0 <= main_litedramcore_choose_cmd_valids[2];
+		end
+		2'd3: begin
+			builder_rhs_array_muxed0 <= main_litedramcore_choose_cmd_valids[3];
+		end
+		3'd4: begin
+			builder_rhs_array_muxed0 <= main_litedramcore_choose_cmd_valids[4];
+		end
+		3'd5: begin
+			builder_rhs_array_muxed0 <= main_litedramcore_choose_cmd_valids[5];
+		end
+		3'd6: begin
+			builder_rhs_array_muxed0 <= main_litedramcore_choose_cmd_valids[6];
+		end
+		default: begin
+			builder_rhs_array_muxed0 <= main_litedramcore_choose_cmd_valids[7];
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_447 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_448;
+// synthesis translate_on
+always @(*) begin
+	builder_rhs_array_muxed1 <= 14'd0;
+	case (main_litedramcore_choose_cmd_grant)
+		1'd0: begin
+			builder_rhs_array_muxed1 <= main_litedramcore_bankmachine0_cmd_payload_a;
+		end
+		1'd1: begin
+			builder_rhs_array_muxed1 <= main_litedramcore_bankmachine1_cmd_payload_a;
+		end
+		2'd2: begin
+			builder_rhs_array_muxed1 <= main_litedramcore_bankmachine2_cmd_payload_a;
+		end
+		2'd3: begin
+			builder_rhs_array_muxed1 <= main_litedramcore_bankmachine3_cmd_payload_a;
+		end
+		3'd4: begin
+			builder_rhs_array_muxed1 <= main_litedramcore_bankmachine4_cmd_payload_a;
+		end
+		3'd5: begin
+			builder_rhs_array_muxed1 <= main_litedramcore_bankmachine5_cmd_payload_a;
+		end
+		3'd6: begin
+			builder_rhs_array_muxed1 <= main_litedramcore_bankmachine6_cmd_payload_a;
+		end
+		default: begin
+			builder_rhs_array_muxed1 <= main_litedramcore_bankmachine7_cmd_payload_a;
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_448 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_449;
+// synthesis translate_on
+always @(*) begin
+	builder_rhs_array_muxed2 <= 3'd0;
+	case (main_litedramcore_choose_cmd_grant)
+		1'd0: begin
+			builder_rhs_array_muxed2 <= main_litedramcore_bankmachine0_cmd_payload_ba;
+		end
+		1'd1: begin
+			builder_rhs_array_muxed2 <= main_litedramcore_bankmachine1_cmd_payload_ba;
+		end
+		2'd2: begin
+			builder_rhs_array_muxed2 <= main_litedramcore_bankmachine2_cmd_payload_ba;
+		end
+		2'd3: begin
+			builder_rhs_array_muxed2 <= main_litedramcore_bankmachine3_cmd_payload_ba;
+		end
+		3'd4: begin
+			builder_rhs_array_muxed2 <= main_litedramcore_bankmachine4_cmd_payload_ba;
+		end
+		3'd5: begin
+			builder_rhs_array_muxed2 <= main_litedramcore_bankmachine5_cmd_payload_ba;
+		end
+		3'd6: begin
+			builder_rhs_array_muxed2 <= main_litedramcore_bankmachine6_cmd_payload_ba;
+		end
+		default: begin
+			builder_rhs_array_muxed2 <= main_litedramcore_bankmachine7_cmd_payload_ba;
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_449 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_450;
+// synthesis translate_on
+always @(*) begin
+	builder_rhs_array_muxed3 <= 1'd0;
+	case (main_litedramcore_choose_cmd_grant)
+		1'd0: begin
+			builder_rhs_array_muxed3 <= main_litedramcore_bankmachine0_cmd_payload_is_read;
+		end
+		1'd1: begin
+			builder_rhs_array_muxed3 <= main_litedramcore_bankmachine1_cmd_payload_is_read;
+		end
+		2'd2: begin
+			builder_rhs_array_muxed3 <= main_litedramcore_bankmachine2_cmd_payload_is_read;
+		end
+		2'd3: begin
+			builder_rhs_array_muxed3 <= main_litedramcore_bankmachine3_cmd_payload_is_read;
+		end
+		3'd4: begin
+			builder_rhs_array_muxed3 <= main_litedramcore_bankmachine4_cmd_payload_is_read;
+		end
+		3'd5: begin
+			builder_rhs_array_muxed3 <= main_litedramcore_bankmachine5_cmd_payload_is_read;
+		end
+		3'd6: begin
+			builder_rhs_array_muxed3 <= main_litedramcore_bankmachine6_cmd_payload_is_read;
+		end
+		default: begin
+			builder_rhs_array_muxed3 <= main_litedramcore_bankmachine7_cmd_payload_is_read;
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_450 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_451;
+// synthesis translate_on
+always @(*) begin
+	builder_rhs_array_muxed4 <= 1'd0;
+	case (main_litedramcore_choose_cmd_grant)
+		1'd0: begin
+			builder_rhs_array_muxed4 <= main_litedramcore_bankmachine0_cmd_payload_is_write;
+		end
+		1'd1: begin
+			builder_rhs_array_muxed4 <= main_litedramcore_bankmachine1_cmd_payload_is_write;
+		end
+		2'd2: begin
+			builder_rhs_array_muxed4 <= main_litedramcore_bankmachine2_cmd_payload_is_write;
+		end
+		2'd3: begin
+			builder_rhs_array_muxed4 <= main_litedramcore_bankmachine3_cmd_payload_is_write;
+		end
+		3'd4: begin
+			builder_rhs_array_muxed4 <= main_litedramcore_bankmachine4_cmd_payload_is_write;
+		end
+		3'd5: begin
+			builder_rhs_array_muxed4 <= main_litedramcore_bankmachine5_cmd_payload_is_write;
+		end
+		3'd6: begin
+			builder_rhs_array_muxed4 <= main_litedramcore_bankmachine6_cmd_payload_is_write;
+		end
+		default: begin
+			builder_rhs_array_muxed4 <= main_litedramcore_bankmachine7_cmd_payload_is_write;
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_451 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_452;
+// synthesis translate_on
+always @(*) begin
+	builder_rhs_array_muxed5 <= 1'd0;
+	case (main_litedramcore_choose_cmd_grant)
+		1'd0: begin
+			builder_rhs_array_muxed5 <= main_litedramcore_bankmachine0_cmd_payload_is_cmd;
+		end
+		1'd1: begin
+			builder_rhs_array_muxed5 <= main_litedramcore_bankmachine1_cmd_payload_is_cmd;
+		end
+		2'd2: begin
+			builder_rhs_array_muxed5 <= main_litedramcore_bankmachine2_cmd_payload_is_cmd;
+		end
+		2'd3: begin
+			builder_rhs_array_muxed5 <= main_litedramcore_bankmachine3_cmd_payload_is_cmd;
+		end
+		3'd4: begin
+			builder_rhs_array_muxed5 <= main_litedramcore_bankmachine4_cmd_payload_is_cmd;
+		end
+		3'd5: begin
+			builder_rhs_array_muxed5 <= main_litedramcore_bankmachine5_cmd_payload_is_cmd;
+		end
+		3'd6: begin
+			builder_rhs_array_muxed5 <= main_litedramcore_bankmachine6_cmd_payload_is_cmd;
+		end
+		default: begin
+			builder_rhs_array_muxed5 <= main_litedramcore_bankmachine7_cmd_payload_is_cmd;
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_452 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_453;
+// synthesis translate_on
+always @(*) begin
+	builder_t_array_muxed0 <= 1'd0;
+	case (main_litedramcore_choose_cmd_grant)
+		1'd0: begin
+			builder_t_array_muxed0 <= main_litedramcore_bankmachine0_cmd_payload_cas;
+		end
+		1'd1: begin
+			builder_t_array_muxed0 <= main_litedramcore_bankmachine1_cmd_payload_cas;
+		end
+		2'd2: begin
+			builder_t_array_muxed0 <= main_litedramcore_bankmachine2_cmd_payload_cas;
+		end
+		2'd3: begin
+			builder_t_array_muxed0 <= main_litedramcore_bankmachine3_cmd_payload_cas;
+		end
+		3'd4: begin
+			builder_t_array_muxed0 <= main_litedramcore_bankmachine4_cmd_payload_cas;
+		end
+		3'd5: begin
+			builder_t_array_muxed0 <= main_litedramcore_bankmachine5_cmd_payload_cas;
+		end
+		3'd6: begin
+			builder_t_array_muxed0 <= main_litedramcore_bankmachine6_cmd_payload_cas;
+		end
+		default: begin
+			builder_t_array_muxed0 <= main_litedramcore_bankmachine7_cmd_payload_cas;
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_453 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_454;
+// synthesis translate_on
+always @(*) begin
+	builder_t_array_muxed1 <= 1'd0;
+	case (main_litedramcore_choose_cmd_grant)
+		1'd0: begin
+			builder_t_array_muxed1 <= main_litedramcore_bankmachine0_cmd_payload_ras;
+		end
+		1'd1: begin
+			builder_t_array_muxed1 <= main_litedramcore_bankmachine1_cmd_payload_ras;
+		end
+		2'd2: begin
+			builder_t_array_muxed1 <= main_litedramcore_bankmachine2_cmd_payload_ras;
+		end
+		2'd3: begin
+			builder_t_array_muxed1 <= main_litedramcore_bankmachine3_cmd_payload_ras;
+		end
+		3'd4: begin
+			builder_t_array_muxed1 <= main_litedramcore_bankmachine4_cmd_payload_ras;
+		end
+		3'd5: begin
+			builder_t_array_muxed1 <= main_litedramcore_bankmachine5_cmd_payload_ras;
+		end
+		3'd6: begin
+			builder_t_array_muxed1 <= main_litedramcore_bankmachine6_cmd_payload_ras;
+		end
+		default: begin
+			builder_t_array_muxed1 <= main_litedramcore_bankmachine7_cmd_payload_ras;
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_454 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_455;
+// synthesis translate_on
+always @(*) begin
+	builder_t_array_muxed2 <= 1'd0;
+	case (main_litedramcore_choose_cmd_grant)
+		1'd0: begin
+			builder_t_array_muxed2 <= main_litedramcore_bankmachine0_cmd_payload_we;
+		end
+		1'd1: begin
+			builder_t_array_muxed2 <= main_litedramcore_bankmachine1_cmd_payload_we;
+		end
+		2'd2: begin
+			builder_t_array_muxed2 <= main_litedramcore_bankmachine2_cmd_payload_we;
+		end
+		2'd3: begin
+			builder_t_array_muxed2 <= main_litedramcore_bankmachine3_cmd_payload_we;
+		end
+		3'd4: begin
+			builder_t_array_muxed2 <= main_litedramcore_bankmachine4_cmd_payload_we;
+		end
+		3'd5: begin
+			builder_t_array_muxed2 <= main_litedramcore_bankmachine5_cmd_payload_we;
+		end
+		3'd6: begin
+			builder_t_array_muxed2 <= main_litedramcore_bankmachine6_cmd_payload_we;
+		end
+		default: begin
+			builder_t_array_muxed2 <= main_litedramcore_bankmachine7_cmd_payload_we;
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_455 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_456;
+// synthesis translate_on
+always @(*) begin
+	builder_rhs_array_muxed6 <= 1'd0;
+	case (main_litedramcore_choose_req_grant)
+		1'd0: begin
+			builder_rhs_array_muxed6 <= main_litedramcore_choose_req_valids[0];
+		end
+		1'd1: begin
+			builder_rhs_array_muxed6 <= main_litedramcore_choose_req_valids[1];
+		end
+		2'd2: begin
+			builder_rhs_array_muxed6 <= main_litedramcore_choose_req_valids[2];
+		end
+		2'd3: begin
+			builder_rhs_array_muxed6 <= main_litedramcore_choose_req_valids[3];
+		end
+		3'd4: begin
+			builder_rhs_array_muxed6 <= main_litedramcore_choose_req_valids[4];
+		end
+		3'd5: begin
+			builder_rhs_array_muxed6 <= main_litedramcore_choose_req_valids[5];
+		end
+		3'd6: begin
+			builder_rhs_array_muxed6 <= main_litedramcore_choose_req_valids[6];
+		end
+		default: begin
+			builder_rhs_array_muxed6 <= main_litedramcore_choose_req_valids[7];
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_456 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_457;
+// synthesis translate_on
+always @(*) begin
+	builder_rhs_array_muxed7 <= 14'd0;
+	case (main_litedramcore_choose_req_grant)
+		1'd0: begin
+			builder_rhs_array_muxed7 <= main_litedramcore_bankmachine0_cmd_payload_a;
+		end
+		1'd1: begin
+			builder_rhs_array_muxed7 <= main_litedramcore_bankmachine1_cmd_payload_a;
+		end
+		2'd2: begin
+			builder_rhs_array_muxed7 <= main_litedramcore_bankmachine2_cmd_payload_a;
+		end
+		2'd3: begin
+			builder_rhs_array_muxed7 <= main_litedramcore_bankmachine3_cmd_payload_a;
+		end
+		3'd4: begin
+			builder_rhs_array_muxed7 <= main_litedramcore_bankmachine4_cmd_payload_a;
+		end
+		3'd5: begin
+			builder_rhs_array_muxed7 <= main_litedramcore_bankmachine5_cmd_payload_a;
+		end
+		3'd6: begin
+			builder_rhs_array_muxed7 <= main_litedramcore_bankmachine6_cmd_payload_a;
+		end
+		default: begin
+			builder_rhs_array_muxed7 <= main_litedramcore_bankmachine7_cmd_payload_a;
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_457 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_458;
+// synthesis translate_on
+always @(*) begin
+	builder_rhs_array_muxed8 <= 3'd0;
+	case (main_litedramcore_choose_req_grant)
+		1'd0: begin
+			builder_rhs_array_muxed8 <= main_litedramcore_bankmachine0_cmd_payload_ba;
+		end
+		1'd1: begin
+			builder_rhs_array_muxed8 <= main_litedramcore_bankmachine1_cmd_payload_ba;
+		end
+		2'd2: begin
+			builder_rhs_array_muxed8 <= main_litedramcore_bankmachine2_cmd_payload_ba;
+		end
+		2'd3: begin
+			builder_rhs_array_muxed8 <= main_litedramcore_bankmachine3_cmd_payload_ba;
+		end
+		3'd4: begin
+			builder_rhs_array_muxed8 <= main_litedramcore_bankmachine4_cmd_payload_ba;
+		end
+		3'd5: begin
+			builder_rhs_array_muxed8 <= main_litedramcore_bankmachine5_cmd_payload_ba;
+		end
+		3'd6: begin
+			builder_rhs_array_muxed8 <= main_litedramcore_bankmachine6_cmd_payload_ba;
+		end
+		default: begin
+			builder_rhs_array_muxed8 <= main_litedramcore_bankmachine7_cmd_payload_ba;
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_458 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_459;
+// synthesis translate_on
+always @(*) begin
+	builder_rhs_array_muxed9 <= 1'd0;
+	case (main_litedramcore_choose_req_grant)
+		1'd0: begin
+			builder_rhs_array_muxed9 <= main_litedramcore_bankmachine0_cmd_payload_is_read;
+		end
+		1'd1: begin
+			builder_rhs_array_muxed9 <= main_litedramcore_bankmachine1_cmd_payload_is_read;
+		end
+		2'd2: begin
+			builder_rhs_array_muxed9 <= main_litedramcore_bankmachine2_cmd_payload_is_read;
+		end
+		2'd3: begin
+			builder_rhs_array_muxed9 <= main_litedramcore_bankmachine3_cmd_payload_is_read;
+		end
+		3'd4: begin
+			builder_rhs_array_muxed9 <= main_litedramcore_bankmachine4_cmd_payload_is_read;
+		end
+		3'd5: begin
+			builder_rhs_array_muxed9 <= main_litedramcore_bankmachine5_cmd_payload_is_read;
+		end
+		3'd6: begin
+			builder_rhs_array_muxed9 <= main_litedramcore_bankmachine6_cmd_payload_is_read;
+		end
+		default: begin
+			builder_rhs_array_muxed9 <= main_litedramcore_bankmachine7_cmd_payload_is_read;
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_459 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_460;
+// synthesis translate_on
+always @(*) begin
+	builder_rhs_array_muxed10 <= 1'd0;
+	case (main_litedramcore_choose_req_grant)
+		1'd0: begin
+			builder_rhs_array_muxed10 <= main_litedramcore_bankmachine0_cmd_payload_is_write;
+		end
+		1'd1: begin
+			builder_rhs_array_muxed10 <= main_litedramcore_bankmachine1_cmd_payload_is_write;
+		end
+		2'd2: begin
+			builder_rhs_array_muxed10 <= main_litedramcore_bankmachine2_cmd_payload_is_write;
+		end
+		2'd3: begin
+			builder_rhs_array_muxed10 <= main_litedramcore_bankmachine3_cmd_payload_is_write;
+		end
+		3'd4: begin
+			builder_rhs_array_muxed10 <= main_litedramcore_bankmachine4_cmd_payload_is_write;
+		end
+		3'd5: begin
+			builder_rhs_array_muxed10 <= main_litedramcore_bankmachine5_cmd_payload_is_write;
+		end
+		3'd6: begin
+			builder_rhs_array_muxed10 <= main_litedramcore_bankmachine6_cmd_payload_is_write;
+		end
+		default: begin
+			builder_rhs_array_muxed10 <= main_litedramcore_bankmachine7_cmd_payload_is_write;
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_460 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_461;
+// synthesis translate_on
+always @(*) begin
+	builder_rhs_array_muxed11 <= 1'd0;
+	case (main_litedramcore_choose_req_grant)
+		1'd0: begin
+			builder_rhs_array_muxed11 <= main_litedramcore_bankmachine0_cmd_payload_is_cmd;
+		end
+		1'd1: begin
+			builder_rhs_array_muxed11 <= main_litedramcore_bankmachine1_cmd_payload_is_cmd;
+		end
+		2'd2: begin
+			builder_rhs_array_muxed11 <= main_litedramcore_bankmachine2_cmd_payload_is_cmd;
+		end
+		2'd3: begin
+			builder_rhs_array_muxed11 <= main_litedramcore_bankmachine3_cmd_payload_is_cmd;
+		end
+		3'd4: begin
+			builder_rhs_array_muxed11 <= main_litedramcore_bankmachine4_cmd_payload_is_cmd;
+		end
+		3'd5: begin
+			builder_rhs_array_muxed11 <= main_litedramcore_bankmachine5_cmd_payload_is_cmd;
+		end
+		3'd6: begin
+			builder_rhs_array_muxed11 <= main_litedramcore_bankmachine6_cmd_payload_is_cmd;
+		end
+		default: begin
+			builder_rhs_array_muxed11 <= main_litedramcore_bankmachine7_cmd_payload_is_cmd;
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_461 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_462;
+// synthesis translate_on
+always @(*) begin
+	builder_t_array_muxed3 <= 1'd0;
+	case (main_litedramcore_choose_req_grant)
+		1'd0: begin
+			builder_t_array_muxed3 <= main_litedramcore_bankmachine0_cmd_payload_cas;
+		end
+		1'd1: begin
+			builder_t_array_muxed3 <= main_litedramcore_bankmachine1_cmd_payload_cas;
+		end
+		2'd2: begin
+			builder_t_array_muxed3 <= main_litedramcore_bankmachine2_cmd_payload_cas;
+		end
+		2'd3: begin
+			builder_t_array_muxed3 <= main_litedramcore_bankmachine3_cmd_payload_cas;
+		end
+		3'd4: begin
+			builder_t_array_muxed3 <= main_litedramcore_bankmachine4_cmd_payload_cas;
+		end
+		3'd5: begin
+			builder_t_array_muxed3 <= main_litedramcore_bankmachine5_cmd_payload_cas;
+		end
+		3'd6: begin
+			builder_t_array_muxed3 <= main_litedramcore_bankmachine6_cmd_payload_cas;
+		end
+		default: begin
+			builder_t_array_muxed3 <= main_litedramcore_bankmachine7_cmd_payload_cas;
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_462 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_463;
+// synthesis translate_on
+always @(*) begin
+	builder_t_array_muxed4 <= 1'd0;
+	case (main_litedramcore_choose_req_grant)
+		1'd0: begin
+			builder_t_array_muxed4 <= main_litedramcore_bankmachine0_cmd_payload_ras;
+		end
+		1'd1: begin
+			builder_t_array_muxed4 <= main_litedramcore_bankmachine1_cmd_payload_ras;
+		end
+		2'd2: begin
+			builder_t_array_muxed4 <= main_litedramcore_bankmachine2_cmd_payload_ras;
+		end
+		2'd3: begin
+			builder_t_array_muxed4 <= main_litedramcore_bankmachine3_cmd_payload_ras;
+		end
+		3'd4: begin
+			builder_t_array_muxed4 <= main_litedramcore_bankmachine4_cmd_payload_ras;
+		end
+		3'd5: begin
+			builder_t_array_muxed4 <= main_litedramcore_bankmachine5_cmd_payload_ras;
+		end
+		3'd6: begin
+			builder_t_array_muxed4 <= main_litedramcore_bankmachine6_cmd_payload_ras;
+		end
+		default: begin
+			builder_t_array_muxed4 <= main_litedramcore_bankmachine7_cmd_payload_ras;
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_463 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_464;
+// synthesis translate_on
+always @(*) begin
+	builder_t_array_muxed5 <= 1'd0;
+	case (main_litedramcore_choose_req_grant)
+		1'd0: begin
+			builder_t_array_muxed5 <= main_litedramcore_bankmachine0_cmd_payload_we;
+		end
+		1'd1: begin
+			builder_t_array_muxed5 <= main_litedramcore_bankmachine1_cmd_payload_we;
+		end
+		2'd2: begin
+			builder_t_array_muxed5 <= main_litedramcore_bankmachine2_cmd_payload_we;
+		end
+		2'd3: begin
+			builder_t_array_muxed5 <= main_litedramcore_bankmachine3_cmd_payload_we;
+		end
+		3'd4: begin
+			builder_t_array_muxed5 <= main_litedramcore_bankmachine4_cmd_payload_we;
+		end
+		3'd5: begin
+			builder_t_array_muxed5 <= main_litedramcore_bankmachine5_cmd_payload_we;
+		end
+		3'd6: begin
+			builder_t_array_muxed5 <= main_litedramcore_bankmachine6_cmd_payload_we;
+		end
+		default: begin
+			builder_t_array_muxed5 <= main_litedramcore_bankmachine7_cmd_payload_we;
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_464 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_465;
+// synthesis translate_on
+always @(*) begin
+	builder_rhs_array_muxed12 <= 21'd0;
+	case (builder_roundrobin0_grant)
+		default: begin
+			builder_rhs_array_muxed12 <= {main_user_port_cmd_payload_addr[23:10], main_user_port_cmd_payload_addr[6:0]};
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_465 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_466;
+// synthesis translate_on
+always @(*) begin
+	builder_rhs_array_muxed13 <= 1'd0;
+	case (builder_roundrobin0_grant)
+		default: begin
+			builder_rhs_array_muxed13 <= main_user_port_cmd_payload_we;
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_466 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_467;
+// synthesis translate_on
+always @(*) begin
+	builder_rhs_array_muxed14 <= 1'd0;
+	case (builder_roundrobin0_grant)
+		default: begin
+			builder_rhs_array_muxed14 <= (((main_user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((builder_locked0 | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid);
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_467 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_468;
+// synthesis translate_on
+always @(*) begin
+	builder_rhs_array_muxed15 <= 21'd0;
+	case (builder_roundrobin1_grant)
+		default: begin
+			builder_rhs_array_muxed15 <= {main_user_port_cmd_payload_addr[23:10], main_user_port_cmd_payload_addr[6:0]};
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_468 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_469;
+// synthesis translate_on
+always @(*) begin
+	builder_rhs_array_muxed16 <= 1'd0;
+	case (builder_roundrobin1_grant)
+		default: begin
+			builder_rhs_array_muxed16 <= main_user_port_cmd_payload_we;
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_469 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_470;
+// synthesis translate_on
+always @(*) begin
+	builder_rhs_array_muxed17 <= 1'd0;
+	case (builder_roundrobin1_grant)
+		default: begin
+			builder_rhs_array_muxed17 <= (((main_user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((builder_locked1 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid);
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_470 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_471;
+// synthesis translate_on
+always @(*) begin
+	builder_rhs_array_muxed18 <= 21'd0;
+	case (builder_roundrobin2_grant)
+		default: begin
+			builder_rhs_array_muxed18 <= {main_user_port_cmd_payload_addr[23:10], main_user_port_cmd_payload_addr[6:0]};
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_471 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_472;
+// synthesis translate_on
+always @(*) begin
+	builder_rhs_array_muxed19 <= 1'd0;
+	case (builder_roundrobin2_grant)
+		default: begin
+			builder_rhs_array_muxed19 <= main_user_port_cmd_payload_we;
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_472 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_473;
+// synthesis translate_on
+always @(*) begin
+	builder_rhs_array_muxed20 <= 1'd0;
+	case (builder_roundrobin2_grant)
+		default: begin
+			builder_rhs_array_muxed20 <= (((main_user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((builder_locked2 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid);
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_473 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_474;
+// synthesis translate_on
+always @(*) begin
+	builder_rhs_array_muxed21 <= 21'd0;
+	case (builder_roundrobin3_grant)
+		default: begin
+			builder_rhs_array_muxed21 <= {main_user_port_cmd_payload_addr[23:10], main_user_port_cmd_payload_addr[6:0]};
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_474 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_475;
+// synthesis translate_on
+always @(*) begin
+	builder_rhs_array_muxed22 <= 1'd0;
+	case (builder_roundrobin3_grant)
+		default: begin
+			builder_rhs_array_muxed22 <= main_user_port_cmd_payload_we;
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_475 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_476;
+// synthesis translate_on
+always @(*) begin
+	builder_rhs_array_muxed23 <= 1'd0;
+	case (builder_roundrobin3_grant)
+		default: begin
+			builder_rhs_array_muxed23 <= (((main_user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((builder_locked3 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid);
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_476 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_477;
+// synthesis translate_on
+always @(*) begin
+	builder_rhs_array_muxed24 <= 21'd0;
+	case (builder_roundrobin4_grant)
+		default: begin
+			builder_rhs_array_muxed24 <= {main_user_port_cmd_payload_addr[23:10], main_user_port_cmd_payload_addr[6:0]};
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_477 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_478;
+// synthesis translate_on
+always @(*) begin
+	builder_rhs_array_muxed25 <= 1'd0;
+	case (builder_roundrobin4_grant)
+		default: begin
+			builder_rhs_array_muxed25 <= main_user_port_cmd_payload_we;
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_478 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_479;
+// synthesis translate_on
+always @(*) begin
+	builder_rhs_array_muxed26 <= 1'd0;
+	case (builder_roundrobin4_grant)
+		default: begin
+			builder_rhs_array_muxed26 <= (((main_user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((builder_locked4 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid);
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_479 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_480;
+// synthesis translate_on
+always @(*) begin
+	builder_rhs_array_muxed27 <= 21'd0;
+	case (builder_roundrobin5_grant)
+		default: begin
+			builder_rhs_array_muxed27 <= {main_user_port_cmd_payload_addr[23:10], main_user_port_cmd_payload_addr[6:0]};
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_480 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_481;
+// synthesis translate_on
+always @(*) begin
+	builder_rhs_array_muxed28 <= 1'd0;
+	case (builder_roundrobin5_grant)
+		default: begin
+			builder_rhs_array_muxed28 <= main_user_port_cmd_payload_we;
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_481 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_482;
+// synthesis translate_on
+always @(*) begin
+	builder_rhs_array_muxed29 <= 1'd0;
+	case (builder_roundrobin5_grant)
+		default: begin
+			builder_rhs_array_muxed29 <= (((main_user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((builder_locked5 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid);
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_482 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_483;
+// synthesis translate_on
+always @(*) begin
+	builder_rhs_array_muxed30 <= 21'd0;
+	case (builder_roundrobin6_grant)
+		default: begin
+			builder_rhs_array_muxed30 <= {main_user_port_cmd_payload_addr[23:10], main_user_port_cmd_payload_addr[6:0]};
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_483 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_484;
+// synthesis translate_on
+always @(*) begin
+	builder_rhs_array_muxed31 <= 1'd0;
+	case (builder_roundrobin6_grant)
+		default: begin
+			builder_rhs_array_muxed31 <= main_user_port_cmd_payload_we;
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_484 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_485;
+// synthesis translate_on
+always @(*) begin
+	builder_rhs_array_muxed32 <= 1'd0;
+	case (builder_roundrobin6_grant)
+		default: begin
+			builder_rhs_array_muxed32 <= (((main_user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((builder_locked6 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_user_port_cmd_valid);
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_485 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_486;
+// synthesis translate_on
+always @(*) begin
+	builder_rhs_array_muxed33 <= 21'd0;
+	case (builder_roundrobin7_grant)
+		default: begin
+			builder_rhs_array_muxed33 <= {main_user_port_cmd_payload_addr[23:10], main_user_port_cmd_payload_addr[6:0]};
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_486 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_487;
+// synthesis translate_on
+always @(*) begin
+	builder_rhs_array_muxed34 <= 1'd0;
+	case (builder_roundrobin7_grant)
+		default: begin
+			builder_rhs_array_muxed34 <= main_user_port_cmd_payload_we;
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_487 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_488;
+// synthesis translate_on
+always @(*) begin
+	builder_rhs_array_muxed35 <= 1'd0;
+	case (builder_roundrobin7_grant)
+		default: begin
+			builder_rhs_array_muxed35 <= (((main_user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((builder_locked7 | (main_litedramcore_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_litedramcore_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_litedramcore_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_litedramcore_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_litedramcore_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_litedramcore_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_litedramcore_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))))) & main_user_port_cmd_valid);
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_488 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_489;
+// synthesis translate_on
+always @(*) begin
+	builder_array_muxed0 <= 3'd0;
+	case (main_litedramcore_steerer_sel0)
+		1'd0: begin
+			builder_array_muxed0 <= main_litedramcore_nop_ba[2:0];
+		end
+		1'd1: begin
+			builder_array_muxed0 <= main_litedramcore_choose_cmd_cmd_payload_ba[2:0];
+		end
+		2'd2: begin
+			builder_array_muxed0 <= main_litedramcore_choose_req_cmd_payload_ba[2:0];
+		end
+		default: begin
+			builder_array_muxed0 <= main_litedramcore_cmd_payload_ba[2:0];
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_489 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_490;
+// synthesis translate_on
+always @(*) begin
+	builder_array_muxed1 <= 14'd0;
+	case (main_litedramcore_steerer_sel0)
+		1'd0: begin
+			builder_array_muxed1 <= main_litedramcore_nop_a;
+		end
+		1'd1: begin
+			builder_array_muxed1 <= main_litedramcore_choose_cmd_cmd_payload_a;
+		end
+		2'd2: begin
+			builder_array_muxed1 <= main_litedramcore_choose_req_cmd_payload_a;
+		end
+		default: begin
+			builder_array_muxed1 <= main_litedramcore_cmd_payload_a;
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_490 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_491;
+// synthesis translate_on
+always @(*) begin
+	builder_array_muxed2 <= 1'd0;
+	case (main_litedramcore_steerer_sel0)
+		1'd0: begin
+			builder_array_muxed2 <= 1'd0;
+		end
+		1'd1: begin
+			builder_array_muxed2 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_cas);
+		end
+		2'd2: begin
+			builder_array_muxed2 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_cas);
+		end
+		default: begin
+			builder_array_muxed2 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_cas);
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_491 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_492;
+// synthesis translate_on
+always @(*) begin
+	builder_array_muxed3 <= 1'd0;
+	case (main_litedramcore_steerer_sel0)
+		1'd0: begin
+			builder_array_muxed3 <= 1'd0;
+		end
+		1'd1: begin
+			builder_array_muxed3 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_ras);
+		end
+		2'd2: begin
+			builder_array_muxed3 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_ras);
+		end
+		default: begin
+			builder_array_muxed3 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_ras);
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_492 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_493;
+// synthesis translate_on
+always @(*) begin
+	builder_array_muxed4 <= 1'd0;
+	case (main_litedramcore_steerer_sel0)
+		1'd0: begin
+			builder_array_muxed4 <= 1'd0;
+		end
+		1'd1: begin
+			builder_array_muxed4 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_we);
+		end
+		2'd2: begin
+			builder_array_muxed4 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_we);
+		end
+		default: begin
+			builder_array_muxed4 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_we);
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_493 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_494;
+// synthesis translate_on
+always @(*) begin
+	builder_array_muxed5 <= 1'd0;
+	case (main_litedramcore_steerer_sel0)
+		1'd0: begin
+			builder_array_muxed5 <= 1'd0;
+		end
+		1'd1: begin
+			builder_array_muxed5 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_is_read);
+		end
+		2'd2: begin
+			builder_array_muxed5 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_read);
+		end
+		default: begin
+			builder_array_muxed5 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_read);
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_494 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_495;
+// synthesis translate_on
+always @(*) begin
+	builder_array_muxed6 <= 1'd0;
+	case (main_litedramcore_steerer_sel0)
+		1'd0: begin
+			builder_array_muxed6 <= 1'd0;
+		end
+		1'd1: begin
+			builder_array_muxed6 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_is_write);
+		end
+		2'd2: begin
+			builder_array_muxed6 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_write);
+		end
+		default: begin
+			builder_array_muxed6 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_write);
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_495 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_496;
+// synthesis translate_on
+always @(*) begin
+	builder_array_muxed7 <= 3'd0;
+	case (main_litedramcore_steerer_sel1)
+		1'd0: begin
+			builder_array_muxed7 <= main_litedramcore_nop_ba[2:0];
+		end
+		1'd1: begin
+			builder_array_muxed7 <= main_litedramcore_choose_cmd_cmd_payload_ba[2:0];
+		end
+		2'd2: begin
+			builder_array_muxed7 <= main_litedramcore_choose_req_cmd_payload_ba[2:0];
+		end
+		default: begin
+			builder_array_muxed7 <= main_litedramcore_cmd_payload_ba[2:0];
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_496 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_497;
+// synthesis translate_on
+always @(*) begin
+	builder_array_muxed8 <= 14'd0;
+	case (main_litedramcore_steerer_sel1)
+		1'd0: begin
+			builder_array_muxed8 <= main_litedramcore_nop_a;
+		end
+		1'd1: begin
+			builder_array_muxed8 <= main_litedramcore_choose_cmd_cmd_payload_a;
+		end
+		2'd2: begin
+			builder_array_muxed8 <= main_litedramcore_choose_req_cmd_payload_a;
+		end
+		default: begin
+			builder_array_muxed8 <= main_litedramcore_cmd_payload_a;
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_497 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_498;
+// synthesis translate_on
+always @(*) begin
+	builder_array_muxed9 <= 1'd0;
+	case (main_litedramcore_steerer_sel1)
+		1'd0: begin
+			builder_array_muxed9 <= 1'd0;
+		end
+		1'd1: begin
+			builder_array_muxed9 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_cas);
+		end
+		2'd2: begin
+			builder_array_muxed9 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_cas);
+		end
+		default: begin
+			builder_array_muxed9 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_cas);
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_498 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_499;
+// synthesis translate_on
+always @(*) begin
+	builder_array_muxed10 <= 1'd0;
+	case (main_litedramcore_steerer_sel1)
+		1'd0: begin
+			builder_array_muxed10 <= 1'd0;
+		end
+		1'd1: begin
+			builder_array_muxed10 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_ras);
+		end
+		2'd2: begin
+			builder_array_muxed10 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_ras);
+		end
+		default: begin
+			builder_array_muxed10 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_ras);
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_499 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_500;
+// synthesis translate_on
+always @(*) begin
+	builder_array_muxed11 <= 1'd0;
+	case (main_litedramcore_steerer_sel1)
+		1'd0: begin
+			builder_array_muxed11 <= 1'd0;
+		end
+		1'd1: begin
+			builder_array_muxed11 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_we);
+		end
+		2'd2: begin
+			builder_array_muxed11 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_we);
+		end
+		default: begin
+			builder_array_muxed11 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_we);
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_500 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_501;
+// synthesis translate_on
+always @(*) begin
+	builder_array_muxed12 <= 1'd0;
+	case (main_litedramcore_steerer_sel1)
+		1'd0: begin
+			builder_array_muxed12 <= 1'd0;
+		end
+		1'd1: begin
+			builder_array_muxed12 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_is_read);
+		end
+		2'd2: begin
+			builder_array_muxed12 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_read);
+		end
+		default: begin
+			builder_array_muxed12 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_read);
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_501 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_502;
+// synthesis translate_on
+always @(*) begin
+	builder_array_muxed13 <= 1'd0;
+	case (main_litedramcore_steerer_sel1)
+		1'd0: begin
+			builder_array_muxed13 <= 1'd0;
+		end
+		1'd1: begin
+			builder_array_muxed13 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_is_write);
+		end
+		2'd2: begin
+			builder_array_muxed13 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_write);
+		end
+		default: begin
+			builder_array_muxed13 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_write);
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_502 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_503;
+// synthesis translate_on
+always @(*) begin
+	builder_array_muxed14 <= 3'd0;
+	case (main_litedramcore_steerer_sel2)
+		1'd0: begin
+			builder_array_muxed14 <= main_litedramcore_nop_ba[2:0];
+		end
+		1'd1: begin
+			builder_array_muxed14 <= main_litedramcore_choose_cmd_cmd_payload_ba[2:0];
+		end
+		2'd2: begin
+			builder_array_muxed14 <= main_litedramcore_choose_req_cmd_payload_ba[2:0];
+		end
+		default: begin
+			builder_array_muxed14 <= main_litedramcore_cmd_payload_ba[2:0];
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_503 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_504;
+// synthesis translate_on
+always @(*) begin
+	builder_array_muxed15 <= 14'd0;
+	case (main_litedramcore_steerer_sel2)
+		1'd0: begin
+			builder_array_muxed15 <= main_litedramcore_nop_a;
+		end
+		1'd1: begin
+			builder_array_muxed15 <= main_litedramcore_choose_cmd_cmd_payload_a;
+		end
+		2'd2: begin
+			builder_array_muxed15 <= main_litedramcore_choose_req_cmd_payload_a;
+		end
+		default: begin
+			builder_array_muxed15 <= main_litedramcore_cmd_payload_a;
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_504 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_505;
+// synthesis translate_on
+always @(*) begin
+	builder_array_muxed16 <= 1'd0;
+	case (main_litedramcore_steerer_sel2)
+		1'd0: begin
+			builder_array_muxed16 <= 1'd0;
+		end
+		1'd1: begin
+			builder_array_muxed16 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_cas);
+		end
+		2'd2: begin
+			builder_array_muxed16 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_cas);
+		end
+		default: begin
+			builder_array_muxed16 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_cas);
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_505 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_506;
+// synthesis translate_on
+always @(*) begin
+	builder_array_muxed17 <= 1'd0;
+	case (main_litedramcore_steerer_sel2)
+		1'd0: begin
+			builder_array_muxed17 <= 1'd0;
+		end
+		1'd1: begin
+			builder_array_muxed17 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_ras);
+		end
+		2'd2: begin
+			builder_array_muxed17 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_ras);
+		end
+		default: begin
+			builder_array_muxed17 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_ras);
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_506 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_507;
+// synthesis translate_on
+always @(*) begin
+	builder_array_muxed18 <= 1'd0;
+	case (main_litedramcore_steerer_sel2)
+		1'd0: begin
+			builder_array_muxed18 <= 1'd0;
+		end
+		1'd1: begin
+			builder_array_muxed18 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_we);
+		end
+		2'd2: begin
+			builder_array_muxed18 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_we);
+		end
+		default: begin
+			builder_array_muxed18 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_we);
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_507 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_508;
+// synthesis translate_on
+always @(*) begin
+	builder_array_muxed19 <= 1'd0;
+	case (main_litedramcore_steerer_sel2)
+		1'd0: begin
+			builder_array_muxed19 <= 1'd0;
+		end
+		1'd1: begin
+			builder_array_muxed19 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_is_read);
+		end
+		2'd2: begin
+			builder_array_muxed19 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_read);
+		end
+		default: begin
+			builder_array_muxed19 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_read);
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_508 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_509;
+// synthesis translate_on
+always @(*) begin
+	builder_array_muxed20 <= 1'd0;
+	case (main_litedramcore_steerer_sel2)
+		1'd0: begin
+			builder_array_muxed20 <= 1'd0;
+		end
+		1'd1: begin
+			builder_array_muxed20 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_is_write);
+		end
+		2'd2: begin
+			builder_array_muxed20 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_write);
+		end
+		default: begin
+			builder_array_muxed20 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_write);
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_509 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_510;
+// synthesis translate_on
+always @(*) begin
+	builder_array_muxed21 <= 3'd0;
+	case (main_litedramcore_steerer_sel3)
+		1'd0: begin
+			builder_array_muxed21 <= main_litedramcore_nop_ba[2:0];
+		end
+		1'd1: begin
+			builder_array_muxed21 <= main_litedramcore_choose_cmd_cmd_payload_ba[2:0];
+		end
+		2'd2: begin
+			builder_array_muxed21 <= main_litedramcore_choose_req_cmd_payload_ba[2:0];
+		end
+		default: begin
+			builder_array_muxed21 <= main_litedramcore_cmd_payload_ba[2:0];
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_510 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_511;
+// synthesis translate_on
+always @(*) begin
+	builder_array_muxed22 <= 14'd0;
+	case (main_litedramcore_steerer_sel3)
+		1'd0: begin
+			builder_array_muxed22 <= main_litedramcore_nop_a;
+		end
+		1'd1: begin
+			builder_array_muxed22 <= main_litedramcore_choose_cmd_cmd_payload_a;
+		end
+		2'd2: begin
+			builder_array_muxed22 <= main_litedramcore_choose_req_cmd_payload_a;
+		end
+		default: begin
+			builder_array_muxed22 <= main_litedramcore_cmd_payload_a;
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_511 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_512;
+// synthesis translate_on
+always @(*) begin
+	builder_array_muxed23 <= 1'd0;
+	case (main_litedramcore_steerer_sel3)
+		1'd0: begin
+			builder_array_muxed23 <= 1'd0;
+		end
+		1'd1: begin
+			builder_array_muxed23 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_cas);
+		end
+		2'd2: begin
+			builder_array_muxed23 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_cas);
+		end
+		default: begin
+			builder_array_muxed23 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_cas);
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_512 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_513;
+// synthesis translate_on
+always @(*) begin
+	builder_array_muxed24 <= 1'd0;
+	case (main_litedramcore_steerer_sel3)
+		1'd0: begin
+			builder_array_muxed24 <= 1'd0;
+		end
+		1'd1: begin
+			builder_array_muxed24 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_ras);
+		end
+		2'd2: begin
+			builder_array_muxed24 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_ras);
+		end
+		default: begin
+			builder_array_muxed24 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_ras);
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_513 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_514;
+// synthesis translate_on
+always @(*) begin
+	builder_array_muxed25 <= 1'd0;
+	case (main_litedramcore_steerer_sel3)
+		1'd0: begin
+			builder_array_muxed25 <= 1'd0;
+		end
+		1'd1: begin
+			builder_array_muxed25 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_we);
+		end
+		2'd2: begin
+			builder_array_muxed25 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_we);
+		end
+		default: begin
+			builder_array_muxed25 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_we);
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_514 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_515;
+// synthesis translate_on
+always @(*) begin
+	builder_array_muxed26 <= 1'd0;
+	case (main_litedramcore_steerer_sel3)
+		1'd0: begin
+			builder_array_muxed26 <= 1'd0;
+		end
+		1'd1: begin
+			builder_array_muxed26 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_is_read);
+		end
+		2'd2: begin
+			builder_array_muxed26 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_read);
+		end
+		default: begin
+			builder_array_muxed26 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_read);
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_515 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_516;
+// synthesis translate_on
+always @(*) begin
+	builder_array_muxed27 <= 1'd0;
+	case (main_litedramcore_steerer_sel3)
+		1'd0: begin
+			builder_array_muxed27 <= 1'd0;
+		end
+		1'd1: begin
+			builder_array_muxed27 <= ((main_litedramcore_choose_cmd_cmd_valid & main_litedramcore_choose_cmd_cmd_ready) & main_litedramcore_choose_cmd_cmd_payload_is_write);
+		end
+		2'd2: begin
+			builder_array_muxed27 <= ((main_litedramcore_choose_req_cmd_valid & main_litedramcore_choose_req_cmd_ready) & main_litedramcore_choose_req_cmd_payload_is_write);
+		end
+		default: begin
+			builder_array_muxed27 <= ((main_litedramcore_cmd_valid & main_litedramcore_cmd_ready) & main_litedramcore_cmd_payload_is_write);
+		end
+	endcase
+// synthesis translate_off
+	dummy_d_516 = dummy_s;
+// synthesis translate_on
+end
+assign builder_xilinxasyncresetsynchronizerimpl0 = (~main_locked);
+assign builder_xilinxasyncresetsynchronizerimpl1 = (~main_locked);
+assign builder_xilinxasyncresetsynchronizerimpl2 = (~main_locked);
+assign builder_xilinxasyncresetsynchronizerimpl3 = (~main_locked);
+
+always @(posedge iodelay_clk) begin
+	if ((main_reset_counter != 1'd0)) begin
+		main_reset_counter <= (main_reset_counter - 1'd1);
+	end else begin
+		main_ic_reset <= 1'd0;
+	end
+	if (iodelay_rst) begin
+		main_reset_counter <= 4'd15;
+		main_ic_reset <= 1'd1;
+	end
+end
+
+always @(posedge sys_clk) begin
+	main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 <= main_a7ddrphy_dqs_oe_delay_tappeddelayline;
+	main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 <= main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0;
+	main_a7ddrphy_dqspattern_o1 <= main_a7ddrphy_dqspattern_o0;
+	if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
+		main_a7ddrphy_bitslip0_value0 <= (main_a7ddrphy_bitslip0_value0 + 1'd1);
+	end
+	if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+		main_a7ddrphy_bitslip0_value0 <= 3'd7;
+	end
+	main_a7ddrphy_bitslip0_r0 <= {main_a7ddrphy_dqspattern_o1, main_a7ddrphy_bitslip0_r0[15:8]};
+	if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
+		main_a7ddrphy_bitslip1_value0 <= (main_a7ddrphy_bitslip1_value0 + 1'd1);
+	end
+	if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+		main_a7ddrphy_bitslip1_value0 <= 3'd7;
+	end
+	main_a7ddrphy_bitslip1_r0 <= {main_a7ddrphy_dqspattern_o1, main_a7ddrphy_bitslip1_r0[15:8]};
+	if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
+		main_a7ddrphy_bitslip0_value1 <= (main_a7ddrphy_bitslip0_value1 + 1'd1);
+	end
+	if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+		main_a7ddrphy_bitslip0_value1 <= 3'd7;
+	end
+	main_a7ddrphy_bitslip0_r1 <= {{main_a7ddrphy_dfi_p3_wrdata_mask[2], main_a7ddrphy_dfi_p3_wrdata_mask[0], main_a7ddrphy_dfi_p2_wrdata_mask[2], main_a7ddrphy_dfi_p2_wrdata_mask[0], main_a7ddrphy_dfi_p1_wrdata_mask[2], main_a7ddrphy_dfi_p1_wrdata_mask[0], main_a7ddrphy_dfi_p0_wrdata_mask[2], main_a7ddrphy_dfi_p0_wrdata_mask[0]}, main_a7ddrphy_bitslip0_r1[15:8]};
+	if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
+		main_a7ddrphy_bitslip1_value1 <= (main_a7ddrphy_bitslip1_value1 + 1'd1);
+	end
+	if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+		main_a7ddrphy_bitslip1_value1 <= 3'd7;
+	end
+	main_a7ddrphy_bitslip1_r1 <= {{main_a7ddrphy_dfi_p3_wrdata_mask[3], main_a7ddrphy_dfi_p3_wrdata_mask[1], main_a7ddrphy_dfi_p2_wrdata_mask[3], main_a7ddrphy_dfi_p2_wrdata_mask[1], main_a7ddrphy_dfi_p1_wrdata_mask[3], main_a7ddrphy_dfi_p1_wrdata_mask[1], main_a7ddrphy_dfi_p0_wrdata_mask[3], main_a7ddrphy_dfi_p0_wrdata_mask[1]}, main_a7ddrphy_bitslip1_r1[15:8]};
+	main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 <= main_a7ddrphy_dq_oe_delay_tappeddelayline;
+	main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 <= main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0;
+	if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
+		main_a7ddrphy_bitslip0_value2 <= (main_a7ddrphy_bitslip0_value2 + 1'd1);
+	end
+	if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+		main_a7ddrphy_bitslip0_value2 <= 3'd7;
+	end
+	main_a7ddrphy_bitslip0_r2 <= {{main_a7ddrphy_dfi_p3_wrdata[16], main_a7ddrphy_dfi_p3_wrdata[0], main_a7ddrphy_dfi_p2_wrdata[16], main_a7ddrphy_dfi_p2_wrdata[0], main_a7ddrphy_dfi_p1_wrdata[16], main_a7ddrphy_dfi_p1_wrdata[0], main_a7ddrphy_dfi_p0_wrdata[16], main_a7ddrphy_dfi_p0_wrdata[0]}, main_a7ddrphy_bitslip0_r2[15:8]};
+	if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_re)) begin
+		main_a7ddrphy_bitslip0_value3 <= (main_a7ddrphy_bitslip0_value3 + 1'd1);
+	end
+	if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+		main_a7ddrphy_bitslip0_value3 <= 3'd7;
+	end
+	main_a7ddrphy_bitslip0_r3 <= {main_a7ddrphy_bitslip03, main_a7ddrphy_bitslip0_r3[15:8]};
+	if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
+		main_a7ddrphy_bitslip1_value2 <= (main_a7ddrphy_bitslip1_value2 + 1'd1);
+	end
+	if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+		main_a7ddrphy_bitslip1_value2 <= 3'd7;
+	end
+	main_a7ddrphy_bitslip1_r2 <= {{main_a7ddrphy_dfi_p3_wrdata[17], main_a7ddrphy_dfi_p3_wrdata[1], main_a7ddrphy_dfi_p2_wrdata[17], main_a7ddrphy_dfi_p2_wrdata[1], main_a7ddrphy_dfi_p1_wrdata[17], main_a7ddrphy_dfi_p1_wrdata[1], main_a7ddrphy_dfi_p0_wrdata[17], main_a7ddrphy_dfi_p0_wrdata[1]}, main_a7ddrphy_bitslip1_r2[15:8]};
+	if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_re)) begin
+		main_a7ddrphy_bitslip1_value3 <= (main_a7ddrphy_bitslip1_value3 + 1'd1);
+	end
+	if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+		main_a7ddrphy_bitslip1_value3 <= 3'd7;
+	end
+	main_a7ddrphy_bitslip1_r3 <= {main_a7ddrphy_bitslip13, main_a7ddrphy_bitslip1_r3[15:8]};
+	if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
+		main_a7ddrphy_bitslip2_value0 <= (main_a7ddrphy_bitslip2_value0 + 1'd1);
+	end
+	if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+		main_a7ddrphy_bitslip2_value0 <= 3'd7;
+	end
+	main_a7ddrphy_bitslip2_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[18], main_a7ddrphy_dfi_p3_wrdata[2], main_a7ddrphy_dfi_p2_wrdata[18], main_a7ddrphy_dfi_p2_wrdata[2], main_a7ddrphy_dfi_p1_wrdata[18], main_a7ddrphy_dfi_p1_wrdata[2], main_a7ddrphy_dfi_p0_wrdata[18], main_a7ddrphy_dfi_p0_wrdata[2]}, main_a7ddrphy_bitslip2_r0[15:8]};
+	if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_re)) begin
+		main_a7ddrphy_bitslip2_value1 <= (main_a7ddrphy_bitslip2_value1 + 1'd1);
+	end
+	if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+		main_a7ddrphy_bitslip2_value1 <= 3'd7;
+	end
+	main_a7ddrphy_bitslip2_r1 <= {main_a7ddrphy_bitslip21, main_a7ddrphy_bitslip2_r1[15:8]};
+	if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
+		main_a7ddrphy_bitslip3_value0 <= (main_a7ddrphy_bitslip3_value0 + 1'd1);
+	end
+	if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+		main_a7ddrphy_bitslip3_value0 <= 3'd7;
+	end
+	main_a7ddrphy_bitslip3_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[19], main_a7ddrphy_dfi_p3_wrdata[3], main_a7ddrphy_dfi_p2_wrdata[19], main_a7ddrphy_dfi_p2_wrdata[3], main_a7ddrphy_dfi_p1_wrdata[19], main_a7ddrphy_dfi_p1_wrdata[3], main_a7ddrphy_dfi_p0_wrdata[19], main_a7ddrphy_dfi_p0_wrdata[3]}, main_a7ddrphy_bitslip3_r0[15:8]};
+	if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_re)) begin
+		main_a7ddrphy_bitslip3_value1 <= (main_a7ddrphy_bitslip3_value1 + 1'd1);
+	end
+	if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+		main_a7ddrphy_bitslip3_value1 <= 3'd7;
+	end
+	main_a7ddrphy_bitslip3_r1 <= {main_a7ddrphy_bitslip31, main_a7ddrphy_bitslip3_r1[15:8]};
+	if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
+		main_a7ddrphy_bitslip4_value0 <= (main_a7ddrphy_bitslip4_value0 + 1'd1);
+	end
+	if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+		main_a7ddrphy_bitslip4_value0 <= 3'd7;
+	end
+	main_a7ddrphy_bitslip4_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[20], main_a7ddrphy_dfi_p3_wrdata[4], main_a7ddrphy_dfi_p2_wrdata[20], main_a7ddrphy_dfi_p2_wrdata[4], main_a7ddrphy_dfi_p1_wrdata[20], main_a7ddrphy_dfi_p1_wrdata[4], main_a7ddrphy_dfi_p0_wrdata[20], main_a7ddrphy_dfi_p0_wrdata[4]}, main_a7ddrphy_bitslip4_r0[15:8]};
+	if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_re)) begin
+		main_a7ddrphy_bitslip4_value1 <= (main_a7ddrphy_bitslip4_value1 + 1'd1);
+	end
+	if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+		main_a7ddrphy_bitslip4_value1 <= 3'd7;
+	end
+	main_a7ddrphy_bitslip4_r1 <= {main_a7ddrphy_bitslip41, main_a7ddrphy_bitslip4_r1[15:8]};
+	if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
+		main_a7ddrphy_bitslip5_value0 <= (main_a7ddrphy_bitslip5_value0 + 1'd1);
+	end
+	if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+		main_a7ddrphy_bitslip5_value0 <= 3'd7;
+	end
+	main_a7ddrphy_bitslip5_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[21], main_a7ddrphy_dfi_p3_wrdata[5], main_a7ddrphy_dfi_p2_wrdata[21], main_a7ddrphy_dfi_p2_wrdata[5], main_a7ddrphy_dfi_p1_wrdata[21], main_a7ddrphy_dfi_p1_wrdata[5], main_a7ddrphy_dfi_p0_wrdata[21], main_a7ddrphy_dfi_p0_wrdata[5]}, main_a7ddrphy_bitslip5_r0[15:8]};
+	if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_re)) begin
+		main_a7ddrphy_bitslip5_value1 <= (main_a7ddrphy_bitslip5_value1 + 1'd1);
+	end
+	if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+		main_a7ddrphy_bitslip5_value1 <= 3'd7;
+	end
+	main_a7ddrphy_bitslip5_r1 <= {main_a7ddrphy_bitslip51, main_a7ddrphy_bitslip5_r1[15:8]};
+	if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
+		main_a7ddrphy_bitslip6_value0 <= (main_a7ddrphy_bitslip6_value0 + 1'd1);
+	end
+	if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+		main_a7ddrphy_bitslip6_value0 <= 3'd7;
+	end
+	main_a7ddrphy_bitslip6_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[22], main_a7ddrphy_dfi_p3_wrdata[6], main_a7ddrphy_dfi_p2_wrdata[22], main_a7ddrphy_dfi_p2_wrdata[6], main_a7ddrphy_dfi_p1_wrdata[22], main_a7ddrphy_dfi_p1_wrdata[6], main_a7ddrphy_dfi_p0_wrdata[22], main_a7ddrphy_dfi_p0_wrdata[6]}, main_a7ddrphy_bitslip6_r0[15:8]};
+	if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_re)) begin
+		main_a7ddrphy_bitslip6_value1 <= (main_a7ddrphy_bitslip6_value1 + 1'd1);
+	end
+	if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+		main_a7ddrphy_bitslip6_value1 <= 3'd7;
+	end
+	main_a7ddrphy_bitslip6_r1 <= {main_a7ddrphy_bitslip61, main_a7ddrphy_bitslip6_r1[15:8]};
+	if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
+		main_a7ddrphy_bitslip7_value0 <= (main_a7ddrphy_bitslip7_value0 + 1'd1);
+	end
+	if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+		main_a7ddrphy_bitslip7_value0 <= 3'd7;
+	end
+	main_a7ddrphy_bitslip7_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[23], main_a7ddrphy_dfi_p3_wrdata[7], main_a7ddrphy_dfi_p2_wrdata[23], main_a7ddrphy_dfi_p2_wrdata[7], main_a7ddrphy_dfi_p1_wrdata[23], main_a7ddrphy_dfi_p1_wrdata[7], main_a7ddrphy_dfi_p0_wrdata[23], main_a7ddrphy_dfi_p0_wrdata[7]}, main_a7ddrphy_bitslip7_r0[15:8]};
+	if ((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_re)) begin
+		main_a7ddrphy_bitslip7_value1 <= (main_a7ddrphy_bitslip7_value1 + 1'd1);
+	end
+	if (((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+		main_a7ddrphy_bitslip7_value1 <= 3'd7;
+	end
+	main_a7ddrphy_bitslip7_r1 <= {main_a7ddrphy_bitslip71, main_a7ddrphy_bitslip7_r1[15:8]};
+	if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
+		main_a7ddrphy_bitslip8_value0 <= (main_a7ddrphy_bitslip8_value0 + 1'd1);
+	end
+	if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+		main_a7ddrphy_bitslip8_value0 <= 3'd7;
+	end
+	main_a7ddrphy_bitslip8_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[24], main_a7ddrphy_dfi_p3_wrdata[8], main_a7ddrphy_dfi_p2_wrdata[24], main_a7ddrphy_dfi_p2_wrdata[8], main_a7ddrphy_dfi_p1_wrdata[24], main_a7ddrphy_dfi_p1_wrdata[8], main_a7ddrphy_dfi_p0_wrdata[24], main_a7ddrphy_dfi_p0_wrdata[8]}, main_a7ddrphy_bitslip8_r0[15:8]};
+	if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_re)) begin
+		main_a7ddrphy_bitslip8_value1 <= (main_a7ddrphy_bitslip8_value1 + 1'd1);
+	end
+	if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+		main_a7ddrphy_bitslip8_value1 <= 3'd7;
+	end
+	main_a7ddrphy_bitslip8_r1 <= {main_a7ddrphy_bitslip81, main_a7ddrphy_bitslip8_r1[15:8]};
+	if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
+		main_a7ddrphy_bitslip9_value0 <= (main_a7ddrphy_bitslip9_value0 + 1'd1);
+	end
+	if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+		main_a7ddrphy_bitslip9_value0 <= 3'd7;
+	end
+	main_a7ddrphy_bitslip9_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[25], main_a7ddrphy_dfi_p3_wrdata[9], main_a7ddrphy_dfi_p2_wrdata[25], main_a7ddrphy_dfi_p2_wrdata[9], main_a7ddrphy_dfi_p1_wrdata[25], main_a7ddrphy_dfi_p1_wrdata[9], main_a7ddrphy_dfi_p0_wrdata[25], main_a7ddrphy_dfi_p0_wrdata[9]}, main_a7ddrphy_bitslip9_r0[15:8]};
+	if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_re)) begin
+		main_a7ddrphy_bitslip9_value1 <= (main_a7ddrphy_bitslip9_value1 + 1'd1);
+	end
+	if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+		main_a7ddrphy_bitslip9_value1 <= 3'd7;
+	end
+	main_a7ddrphy_bitslip9_r1 <= {main_a7ddrphy_bitslip91, main_a7ddrphy_bitslip9_r1[15:8]};
+	if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
+		main_a7ddrphy_bitslip10_value0 <= (main_a7ddrphy_bitslip10_value0 + 1'd1);
+	end
+	if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+		main_a7ddrphy_bitslip10_value0 <= 3'd7;
+	end
+	main_a7ddrphy_bitslip10_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[26], main_a7ddrphy_dfi_p3_wrdata[10], main_a7ddrphy_dfi_p2_wrdata[26], main_a7ddrphy_dfi_p2_wrdata[10], main_a7ddrphy_dfi_p1_wrdata[26], main_a7ddrphy_dfi_p1_wrdata[10], main_a7ddrphy_dfi_p0_wrdata[26], main_a7ddrphy_dfi_p0_wrdata[10]}, main_a7ddrphy_bitslip10_r0[15:8]};
+	if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_re)) begin
+		main_a7ddrphy_bitslip10_value1 <= (main_a7ddrphy_bitslip10_value1 + 1'd1);
+	end
+	if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+		main_a7ddrphy_bitslip10_value1 <= 3'd7;
+	end
+	main_a7ddrphy_bitslip10_r1 <= {main_a7ddrphy_bitslip101, main_a7ddrphy_bitslip10_r1[15:8]};
+	if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
+		main_a7ddrphy_bitslip11_value0 <= (main_a7ddrphy_bitslip11_value0 + 1'd1);
+	end
+	if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+		main_a7ddrphy_bitslip11_value0 <= 3'd7;
+	end
+	main_a7ddrphy_bitslip11_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[27], main_a7ddrphy_dfi_p3_wrdata[11], main_a7ddrphy_dfi_p2_wrdata[27], main_a7ddrphy_dfi_p2_wrdata[11], main_a7ddrphy_dfi_p1_wrdata[27], main_a7ddrphy_dfi_p1_wrdata[11], main_a7ddrphy_dfi_p0_wrdata[27], main_a7ddrphy_dfi_p0_wrdata[11]}, main_a7ddrphy_bitslip11_r0[15:8]};
+	if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_re)) begin
+		main_a7ddrphy_bitslip11_value1 <= (main_a7ddrphy_bitslip11_value1 + 1'd1);
+	end
+	if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+		main_a7ddrphy_bitslip11_value1 <= 3'd7;
+	end
+	main_a7ddrphy_bitslip11_r1 <= {main_a7ddrphy_bitslip111, main_a7ddrphy_bitslip11_r1[15:8]};
+	if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
+		main_a7ddrphy_bitslip12_value0 <= (main_a7ddrphy_bitslip12_value0 + 1'd1);
+	end
+	if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+		main_a7ddrphy_bitslip12_value0 <= 3'd7;
+	end
+	main_a7ddrphy_bitslip12_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[28], main_a7ddrphy_dfi_p3_wrdata[12], main_a7ddrphy_dfi_p2_wrdata[28], main_a7ddrphy_dfi_p2_wrdata[12], main_a7ddrphy_dfi_p1_wrdata[28], main_a7ddrphy_dfi_p1_wrdata[12], main_a7ddrphy_dfi_p0_wrdata[28], main_a7ddrphy_dfi_p0_wrdata[12]}, main_a7ddrphy_bitslip12_r0[15:8]};
+	if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_re)) begin
+		main_a7ddrphy_bitslip12_value1 <= (main_a7ddrphy_bitslip12_value1 + 1'd1);
+	end
+	if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+		main_a7ddrphy_bitslip12_value1 <= 3'd7;
+	end
+	main_a7ddrphy_bitslip12_r1 <= {main_a7ddrphy_bitslip121, main_a7ddrphy_bitslip12_r1[15:8]};
+	if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
+		main_a7ddrphy_bitslip13_value0 <= (main_a7ddrphy_bitslip13_value0 + 1'd1);
+	end
+	if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+		main_a7ddrphy_bitslip13_value0 <= 3'd7;
+	end
+	main_a7ddrphy_bitslip13_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[29], main_a7ddrphy_dfi_p3_wrdata[13], main_a7ddrphy_dfi_p2_wrdata[29], main_a7ddrphy_dfi_p2_wrdata[13], main_a7ddrphy_dfi_p1_wrdata[29], main_a7ddrphy_dfi_p1_wrdata[13], main_a7ddrphy_dfi_p0_wrdata[29], main_a7ddrphy_dfi_p0_wrdata[13]}, main_a7ddrphy_bitslip13_r0[15:8]};
+	if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_re)) begin
+		main_a7ddrphy_bitslip13_value1 <= (main_a7ddrphy_bitslip13_value1 + 1'd1);
+	end
+	if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+		main_a7ddrphy_bitslip13_value1 <= 3'd7;
+	end
+	main_a7ddrphy_bitslip13_r1 <= {main_a7ddrphy_bitslip131, main_a7ddrphy_bitslip13_r1[15:8]};
+	if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
+		main_a7ddrphy_bitslip14_value0 <= (main_a7ddrphy_bitslip14_value0 + 1'd1);
+	end
+	if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+		main_a7ddrphy_bitslip14_value0 <= 3'd7;
+	end
+	main_a7ddrphy_bitslip14_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[30], main_a7ddrphy_dfi_p3_wrdata[14], main_a7ddrphy_dfi_p2_wrdata[30], main_a7ddrphy_dfi_p2_wrdata[14], main_a7ddrphy_dfi_p1_wrdata[30], main_a7ddrphy_dfi_p1_wrdata[14], main_a7ddrphy_dfi_p0_wrdata[30], main_a7ddrphy_dfi_p0_wrdata[14]}, main_a7ddrphy_bitslip14_r0[15:8]};
+	if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_re)) begin
+		main_a7ddrphy_bitslip14_value1 <= (main_a7ddrphy_bitslip14_value1 + 1'd1);
+	end
+	if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+		main_a7ddrphy_bitslip14_value1 <= 3'd7;
+	end
+	main_a7ddrphy_bitslip14_r1 <= {main_a7ddrphy_bitslip141, main_a7ddrphy_bitslip14_r1[15:8]};
+	if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_re)) begin
+		main_a7ddrphy_bitslip15_value0 <= (main_a7ddrphy_bitslip15_value0 + 1'd1);
+	end
+	if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_wdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+		main_a7ddrphy_bitslip15_value0 <= 3'd7;
+	end
+	main_a7ddrphy_bitslip15_r0 <= {{main_a7ddrphy_dfi_p3_wrdata[31], main_a7ddrphy_dfi_p3_wrdata[15], main_a7ddrphy_dfi_p2_wrdata[31], main_a7ddrphy_dfi_p2_wrdata[15], main_a7ddrphy_dfi_p1_wrdata[31], main_a7ddrphy_dfi_p1_wrdata[15], main_a7ddrphy_dfi_p0_wrdata[31], main_a7ddrphy_dfi_p0_wrdata[15]}, main_a7ddrphy_bitslip15_r0[15:8]};
+	if ((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_re)) begin
+		main_a7ddrphy_bitslip15_value1 <= (main_a7ddrphy_bitslip15_value1 + 1'd1);
+	end
+	if (((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_bitslip_rst_re) | main_a7ddrphy_rst_storage)) begin
+		main_a7ddrphy_bitslip15_value1 <= 3'd7;
+	end
+	main_a7ddrphy_bitslip15_r1 <= {main_a7ddrphy_bitslip151, main_a7ddrphy_bitslip15_r1[15:8]};
+	main_a7ddrphy_rddata_en_tappeddelayline0 <= (((main_a7ddrphy_dfi_p0_rddata_en | main_a7ddrphy_dfi_p1_rddata_en) | main_a7ddrphy_dfi_p2_rddata_en) | main_a7ddrphy_dfi_p3_rddata_en);
+	main_a7ddrphy_rddata_en_tappeddelayline1 <= main_a7ddrphy_rddata_en_tappeddelayline0;
+	main_a7ddrphy_rddata_en_tappeddelayline2 <= main_a7ddrphy_rddata_en_tappeddelayline1;
+	main_a7ddrphy_rddata_en_tappeddelayline3 <= main_a7ddrphy_rddata_en_tappeddelayline2;
+	main_a7ddrphy_rddata_en_tappeddelayline4 <= main_a7ddrphy_rddata_en_tappeddelayline3;
+	main_a7ddrphy_rddata_en_tappeddelayline5 <= main_a7ddrphy_rddata_en_tappeddelayline4;
+	main_a7ddrphy_rddata_en_tappeddelayline6 <= main_a7ddrphy_rddata_en_tappeddelayline5;
+	main_a7ddrphy_rddata_en_tappeddelayline7 <= main_a7ddrphy_rddata_en_tappeddelayline6;
+	main_a7ddrphy_wrdata_en_tappeddelayline0 <= (((main_a7ddrphy_dfi_p0_wrdata_en | main_a7ddrphy_dfi_p1_wrdata_en) | main_a7ddrphy_dfi_p2_wrdata_en) | main_a7ddrphy_dfi_p3_wrdata_en);
+	main_a7ddrphy_wrdata_en_tappeddelayline1 <= main_a7ddrphy_wrdata_en_tappeddelayline0;
+	main_a7ddrphy_wrdata_en_tappeddelayline2 <= main_a7ddrphy_wrdata_en_tappeddelayline1;
+	if (main_litedramcore_inti_p0_rddata_valid) begin
+		main_litedramcore_phaseinjector0_rddata_status <= main_litedramcore_inti_p0_rddata;
+	end
+	if (main_litedramcore_inti_p1_rddata_valid) begin
+		main_litedramcore_phaseinjector1_rddata_status <= main_litedramcore_inti_p1_rddata;
+	end
+	if (main_litedramcore_inti_p2_rddata_valid) begin
+		main_litedramcore_phaseinjector2_rddata_status <= main_litedramcore_inti_p2_rddata;
+	end
+	if (main_litedramcore_inti_p3_rddata_valid) begin
+		main_litedramcore_phaseinjector3_rddata_status <= main_litedramcore_inti_p3_rddata;
+	end
+	if ((main_litedramcore_timer_wait & (~main_litedramcore_timer_done0))) begin
+		main_litedramcore_timer_count1 <= (main_litedramcore_timer_count1 - 1'd1);
+	end else begin
+		main_litedramcore_timer_count1 <= 10'd781;
+	end
+	main_litedramcore_postponer_req_o <= 1'd0;
+	if (main_litedramcore_postponer_req_i) begin
+		main_litedramcore_postponer_count <= (main_litedramcore_postponer_count - 1'd1);
+		if ((main_litedramcore_postponer_count == 1'd0)) begin
+			main_litedramcore_postponer_count <= 1'd0;
+			main_litedramcore_postponer_req_o <= 1'd1;
+		end
+	end
+	if (main_litedramcore_sequencer_start0) begin
+		main_litedramcore_sequencer_count <= 1'd0;
+	end else begin
+		if (main_litedramcore_sequencer_done1) begin
+			if ((main_litedramcore_sequencer_count != 1'd0)) begin
+				main_litedramcore_sequencer_count <= (main_litedramcore_sequencer_count - 1'd1);
+			end
+		end
+	end
+	main_litedramcore_cmd_payload_a <= 1'd0;
+	main_litedramcore_cmd_payload_ba <= 1'd0;
+	main_litedramcore_cmd_payload_cas <= 1'd0;
+	main_litedramcore_cmd_payload_ras <= 1'd0;
+	main_litedramcore_cmd_payload_we <= 1'd0;
+	main_litedramcore_sequencer_done1 <= 1'd0;
+	if ((main_litedramcore_sequencer_start1 & (main_litedramcore_sequencer_counter == 1'd0))) begin
+		main_litedramcore_cmd_payload_a <= 11'd1024;
+		main_litedramcore_cmd_payload_ba <= 1'd0;
+		main_litedramcore_cmd_payload_cas <= 1'd0;
+		main_litedramcore_cmd_payload_ras <= 1'd1;
+		main_litedramcore_cmd_payload_we <= 1'd1;
+	end
+	if ((main_litedramcore_sequencer_counter == 2'd3)) begin
+		main_litedramcore_cmd_payload_a <= 11'd1024;
+		main_litedramcore_cmd_payload_ba <= 1'd0;
+		main_litedramcore_cmd_payload_cas <= 1'd1;
+		main_litedramcore_cmd_payload_ras <= 1'd1;
+		main_litedramcore_cmd_payload_we <= 1'd0;
+	end
+	if ((main_litedramcore_sequencer_counter == 6'd35)) begin
+		main_litedramcore_cmd_payload_a <= 1'd0;
+		main_litedramcore_cmd_payload_ba <= 1'd0;
+		main_litedramcore_cmd_payload_cas <= 1'd0;
+		main_litedramcore_cmd_payload_ras <= 1'd0;
+		main_litedramcore_cmd_payload_we <= 1'd0;
+		main_litedramcore_sequencer_done1 <= 1'd1;
+	end
+	if ((main_litedramcore_sequencer_counter == 6'd35)) begin
+		main_litedramcore_sequencer_counter <= 1'd0;
+	end else begin
+		if ((main_litedramcore_sequencer_counter != 1'd0)) begin
+			main_litedramcore_sequencer_counter <= (main_litedramcore_sequencer_counter + 1'd1);
+		end else begin
+			if (main_litedramcore_sequencer_start1) begin
+				main_litedramcore_sequencer_counter <= 1'd1;
+			end
+		end
+	end
+	if ((main_litedramcore_zqcs_timer_wait & (~main_litedramcore_zqcs_timer_done0))) begin
+		main_litedramcore_zqcs_timer_count1 <= (main_litedramcore_zqcs_timer_count1 - 1'd1);
+	end else begin
+		main_litedramcore_zqcs_timer_count1 <= 27'd99999999;
+	end
+	main_litedramcore_zqcs_executer_done <= 1'd0;
+	if ((main_litedramcore_zqcs_executer_start & (main_litedramcore_zqcs_executer_counter == 1'd0))) begin
+		main_litedramcore_cmd_payload_a <= 11'd1024;
+		main_litedramcore_cmd_payload_ba <= 1'd0;
+		main_litedramcore_cmd_payload_cas <= 1'd0;
+		main_litedramcore_cmd_payload_ras <= 1'd1;
+		main_litedramcore_cmd_payload_we <= 1'd1;
+	end
+	if ((main_litedramcore_zqcs_executer_counter == 2'd3)) begin
+		main_litedramcore_cmd_payload_a <= 1'd0;
+		main_litedramcore_cmd_payload_ba <= 1'd0;
+		main_litedramcore_cmd_payload_cas <= 1'd0;
+		main_litedramcore_cmd_payload_ras <= 1'd0;
+		main_litedramcore_cmd_payload_we <= 1'd1;
+	end
+	if ((main_litedramcore_zqcs_executer_counter == 5'd19)) begin
+		main_litedramcore_cmd_payload_a <= 1'd0;
+		main_litedramcore_cmd_payload_ba <= 1'd0;
+		main_litedramcore_cmd_payload_cas <= 1'd0;
+		main_litedramcore_cmd_payload_ras <= 1'd0;
+		main_litedramcore_cmd_payload_we <= 1'd0;
+		main_litedramcore_zqcs_executer_done <= 1'd1;
+	end
+	if ((main_litedramcore_zqcs_executer_counter == 5'd19)) begin
+		main_litedramcore_zqcs_executer_counter <= 1'd0;
+	end else begin
+		if ((main_litedramcore_zqcs_executer_counter != 1'd0)) begin
+			main_litedramcore_zqcs_executer_counter <= (main_litedramcore_zqcs_executer_counter + 1'd1);
+		end else begin
+			if (main_litedramcore_zqcs_executer_start) begin
+				main_litedramcore_zqcs_executer_counter <= 1'd1;
+			end
+		end
+	end
+	builder_refresher_state <= builder_refresher_next_state;
+	if (main_litedramcore_bankmachine0_row_close) begin
+		main_litedramcore_bankmachine0_row_opened <= 1'd0;
+	end else begin
+		if (main_litedramcore_bankmachine0_row_open) begin
+			main_litedramcore_bankmachine0_row_opened <= 1'd1;
+			main_litedramcore_bankmachine0_row <= main_litedramcore_bankmachine0_cmd_buffer_source_payload_addr[20:7];
+		end
+	end
+	if (((main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable) & (~main_litedramcore_bankmachine0_cmd_buffer_lookahead_replace))) begin
+		main_litedramcore_bankmachine0_cmd_buffer_lookahead_produce <= (main_litedramcore_bankmachine0_cmd_buffer_lookahead_produce + 1'd1);
+	end
+	if (main_litedramcore_bankmachine0_cmd_buffer_lookahead_do_read) begin
+		main_litedramcore_bankmachine0_cmd_buffer_lookahead_consume <= (main_litedramcore_bankmachine0_cmd_buffer_lookahead_consume + 1'd1);
+	end
+	if (((main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & main_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable) & (~main_litedramcore_bankmachine0_cmd_buffer_lookahead_replace))) begin
+		if ((~main_litedramcore_bankmachine0_cmd_buffer_lookahead_do_read)) begin
+			main_litedramcore_bankmachine0_cmd_buffer_lookahead_level <= (main_litedramcore_bankmachine0_cmd_buffer_lookahead_level + 1'd1);
+		end
+	end else begin
+		if (main_litedramcore_bankmachine0_cmd_buffer_lookahead_do_read) begin
+			main_litedramcore_bankmachine0_cmd_buffer_lookahead_level <= (main_litedramcore_bankmachine0_cmd_buffer_lookahead_level - 1'd1);
+		end
+	end
+	if (((~main_litedramcore_bankmachine0_cmd_buffer_source_valid) | main_litedramcore_bankmachine0_cmd_buffer_source_ready)) begin
+		main_litedramcore_bankmachine0_cmd_buffer_source_valid <= main_litedramcore_bankmachine0_cmd_buffer_sink_valid;
+		main_litedramcore_bankmachine0_cmd_buffer_source_first <= main_litedramcore_bankmachine0_cmd_buffer_sink_first;
+		main_litedramcore_bankmachine0_cmd_buffer_source_last <= main_litedramcore_bankmachine0_cmd_buffer_sink_last;
+		main_litedramcore_bankmachine0_cmd_buffer_source_payload_we <= main_litedramcore_bankmachine0_cmd_buffer_sink_payload_we;
+		main_litedramcore_bankmachine0_cmd_buffer_source_payload_addr <= main_litedramcore_bankmachine0_cmd_buffer_sink_payload_addr;
+	end
+	if (main_litedramcore_bankmachine0_twtpcon_valid) begin
+		main_litedramcore_bankmachine0_twtpcon_count <= 3'd5;
+		if (1'd0) begin
+			main_litedramcore_bankmachine0_twtpcon_ready <= 1'd1;
+		end else begin
+			main_litedramcore_bankmachine0_twtpcon_ready <= 1'd0;
+		end
+	end else begin
+		if ((~main_litedramcore_bankmachine0_twtpcon_ready)) begin
+			main_litedramcore_bankmachine0_twtpcon_count <= (main_litedramcore_bankmachine0_twtpcon_count - 1'd1);
+			if ((main_litedramcore_bankmachine0_twtpcon_count == 1'd1)) begin
+				main_litedramcore_bankmachine0_twtpcon_ready <= 1'd1;
+			end
+		end
+	end
+	if (main_litedramcore_bankmachine0_trccon_valid) begin
+		main_litedramcore_bankmachine0_trccon_count <= 3'd5;
+		if (1'd0) begin
+			main_litedramcore_bankmachine0_trccon_ready <= 1'd1;
+		end else begin
+			main_litedramcore_bankmachine0_trccon_ready <= 1'd0;
+		end
+	end else begin
+		if ((~main_litedramcore_bankmachine0_trccon_ready)) begin
+			main_litedramcore_bankmachine0_trccon_count <= (main_litedramcore_bankmachine0_trccon_count - 1'd1);
+			if ((main_litedramcore_bankmachine0_trccon_count == 1'd1)) begin
+				main_litedramcore_bankmachine0_trccon_ready <= 1'd1;
+			end
+		end
+	end
+	if (main_litedramcore_bankmachine0_trascon_valid) begin
+		main_litedramcore_bankmachine0_trascon_count <= 3'd4;
+		if (1'd0) begin
+			main_litedramcore_bankmachine0_trascon_ready <= 1'd1;
+		end else begin
+			main_litedramcore_bankmachine0_trascon_ready <= 1'd0;
+		end
+	end else begin
+		if ((~main_litedramcore_bankmachine0_trascon_ready)) begin
+			main_litedramcore_bankmachine0_trascon_count <= (main_litedramcore_bankmachine0_trascon_count - 1'd1);
+			if ((main_litedramcore_bankmachine0_trascon_count == 1'd1)) begin
+				main_litedramcore_bankmachine0_trascon_ready <= 1'd1;
+			end
+		end
+	end
+	builder_bankmachine0_state <= builder_bankmachine0_next_state;
+	if (main_litedramcore_bankmachine1_row_close) begin
+		main_litedramcore_bankmachine1_row_opened <= 1'd0;
+	end else begin
+		if (main_litedramcore_bankmachine1_row_open) begin
+			main_litedramcore_bankmachine1_row_opened <= 1'd1;
+			main_litedramcore_bankmachine1_row <= main_litedramcore_bankmachine1_cmd_buffer_source_payload_addr[20:7];
+		end
+	end
+	if (((main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable) & (~main_litedramcore_bankmachine1_cmd_buffer_lookahead_replace))) begin
+		main_litedramcore_bankmachine1_cmd_buffer_lookahead_produce <= (main_litedramcore_bankmachine1_cmd_buffer_lookahead_produce + 1'd1);
+	end
+	if (main_litedramcore_bankmachine1_cmd_buffer_lookahead_do_read) begin
+		main_litedramcore_bankmachine1_cmd_buffer_lookahead_consume <= (main_litedramcore_bankmachine1_cmd_buffer_lookahead_consume + 1'd1);
+	end
+	if (((main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & main_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable) & (~main_litedramcore_bankmachine1_cmd_buffer_lookahead_replace))) begin
+		if ((~main_litedramcore_bankmachine1_cmd_buffer_lookahead_do_read)) begin
+			main_litedramcore_bankmachine1_cmd_buffer_lookahead_level <= (main_litedramcore_bankmachine1_cmd_buffer_lookahead_level + 1'd1);
+		end
+	end else begin
+		if (main_litedramcore_bankmachine1_cmd_buffer_lookahead_do_read) begin
+			main_litedramcore_bankmachine1_cmd_buffer_lookahead_level <= (main_litedramcore_bankmachine1_cmd_buffer_lookahead_level - 1'd1);
+		end
+	end
+	if (((~main_litedramcore_bankmachine1_cmd_buffer_source_valid) | main_litedramcore_bankmachine1_cmd_buffer_source_ready)) begin
+		main_litedramcore_bankmachine1_cmd_buffer_source_valid <= main_litedramcore_bankmachine1_cmd_buffer_sink_valid;
+		main_litedramcore_bankmachine1_cmd_buffer_source_first <= main_litedramcore_bankmachine1_cmd_buffer_sink_first;
+		main_litedramcore_bankmachine1_cmd_buffer_source_last <= main_litedramcore_bankmachine1_cmd_buffer_sink_last;
+		main_litedramcore_bankmachine1_cmd_buffer_source_payload_we <= main_litedramcore_bankmachine1_cmd_buffer_sink_payload_we;
+		main_litedramcore_bankmachine1_cmd_buffer_source_payload_addr <= main_litedramcore_bankmachine1_cmd_buffer_sink_payload_addr;
+	end
+	if (main_litedramcore_bankmachine1_twtpcon_valid) begin
+		main_litedramcore_bankmachine1_twtpcon_count <= 3'd5;
+		if (1'd0) begin
+			main_litedramcore_bankmachine1_twtpcon_ready <= 1'd1;
+		end else begin
+			main_litedramcore_bankmachine1_twtpcon_ready <= 1'd0;
+		end
+	end else begin
+		if ((~main_litedramcore_bankmachine1_twtpcon_ready)) begin
+			main_litedramcore_bankmachine1_twtpcon_count <= (main_litedramcore_bankmachine1_twtpcon_count - 1'd1);
+			if ((main_litedramcore_bankmachine1_twtpcon_count == 1'd1)) begin
+				main_litedramcore_bankmachine1_twtpcon_ready <= 1'd1;
+			end
+		end
+	end
+	if (main_litedramcore_bankmachine1_trccon_valid) begin
+		main_litedramcore_bankmachine1_trccon_count <= 3'd5;
+		if (1'd0) begin
+			main_litedramcore_bankmachine1_trccon_ready <= 1'd1;
+		end else begin
+			main_litedramcore_bankmachine1_trccon_ready <= 1'd0;
+		end
+	end else begin
+		if ((~main_litedramcore_bankmachine1_trccon_ready)) begin
+			main_litedramcore_bankmachine1_trccon_count <= (main_litedramcore_bankmachine1_trccon_count - 1'd1);
+			if ((main_litedramcore_bankmachine1_trccon_count == 1'd1)) begin
+				main_litedramcore_bankmachine1_trccon_ready <= 1'd1;
+			end
+		end
+	end
+	if (main_litedramcore_bankmachine1_trascon_valid) begin
+		main_litedramcore_bankmachine1_trascon_count <= 3'd4;
+		if (1'd0) begin
+			main_litedramcore_bankmachine1_trascon_ready <= 1'd1;
+		end else begin
+			main_litedramcore_bankmachine1_trascon_ready <= 1'd0;
+		end
+	end else begin
+		if ((~main_litedramcore_bankmachine1_trascon_ready)) begin
+			main_litedramcore_bankmachine1_trascon_count <= (main_litedramcore_bankmachine1_trascon_count - 1'd1);
+			if ((main_litedramcore_bankmachine1_trascon_count == 1'd1)) begin
+				main_litedramcore_bankmachine1_trascon_ready <= 1'd1;
+			end
+		end
+	end
+	builder_bankmachine1_state <= builder_bankmachine1_next_state;
+	if (main_litedramcore_bankmachine2_row_close) begin
+		main_litedramcore_bankmachine2_row_opened <= 1'd0;
+	end else begin
+		if (main_litedramcore_bankmachine2_row_open) begin
+			main_litedramcore_bankmachine2_row_opened <= 1'd1;
+			main_litedramcore_bankmachine2_row <= main_litedramcore_bankmachine2_cmd_buffer_source_payload_addr[20:7];
+		end
+	end
+	if (((main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable) & (~main_litedramcore_bankmachine2_cmd_buffer_lookahead_replace))) begin
+		main_litedramcore_bankmachine2_cmd_buffer_lookahead_produce <= (main_litedramcore_bankmachine2_cmd_buffer_lookahead_produce + 1'd1);
+	end
+	if (main_litedramcore_bankmachine2_cmd_buffer_lookahead_do_read) begin
+		main_litedramcore_bankmachine2_cmd_buffer_lookahead_consume <= (main_litedramcore_bankmachine2_cmd_buffer_lookahead_consume + 1'd1);
+	end
+	if (((main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & main_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable) & (~main_litedramcore_bankmachine2_cmd_buffer_lookahead_replace))) begin
+		if ((~main_litedramcore_bankmachine2_cmd_buffer_lookahead_do_read)) begin
+			main_litedramcore_bankmachine2_cmd_buffer_lookahead_level <= (main_litedramcore_bankmachine2_cmd_buffer_lookahead_level + 1'd1);
+		end
+	end else begin
+		if (main_litedramcore_bankmachine2_cmd_buffer_lookahead_do_read) begin
+			main_litedramcore_bankmachine2_cmd_buffer_lookahead_level <= (main_litedramcore_bankmachine2_cmd_buffer_lookahead_level - 1'd1);
+		end
+	end
+	if (((~main_litedramcore_bankmachine2_cmd_buffer_source_valid) | main_litedramcore_bankmachine2_cmd_buffer_source_ready)) begin
+		main_litedramcore_bankmachine2_cmd_buffer_source_valid <= main_litedramcore_bankmachine2_cmd_buffer_sink_valid;
+		main_litedramcore_bankmachine2_cmd_buffer_source_first <= main_litedramcore_bankmachine2_cmd_buffer_sink_first;
+		main_litedramcore_bankmachine2_cmd_buffer_source_last <= main_litedramcore_bankmachine2_cmd_buffer_sink_last;
+		main_litedramcore_bankmachine2_cmd_buffer_source_payload_we <= main_litedramcore_bankmachine2_cmd_buffer_sink_payload_we;
+		main_litedramcore_bankmachine2_cmd_buffer_source_payload_addr <= main_litedramcore_bankmachine2_cmd_buffer_sink_payload_addr;
+	end
+	if (main_litedramcore_bankmachine2_twtpcon_valid) begin
+		main_litedramcore_bankmachine2_twtpcon_count <= 3'd5;
+		if (1'd0) begin
+			main_litedramcore_bankmachine2_twtpcon_ready <= 1'd1;
+		end else begin
+			main_litedramcore_bankmachine2_twtpcon_ready <= 1'd0;
+		end
+	end else begin
+		if ((~main_litedramcore_bankmachine2_twtpcon_ready)) begin
+			main_litedramcore_bankmachine2_twtpcon_count <= (main_litedramcore_bankmachine2_twtpcon_count - 1'd1);
+			if ((main_litedramcore_bankmachine2_twtpcon_count == 1'd1)) begin
+				main_litedramcore_bankmachine2_twtpcon_ready <= 1'd1;
+			end
+		end
+	end
+	if (main_litedramcore_bankmachine2_trccon_valid) begin
+		main_litedramcore_bankmachine2_trccon_count <= 3'd5;
+		if (1'd0) begin
+			main_litedramcore_bankmachine2_trccon_ready <= 1'd1;
+		end else begin
+			main_litedramcore_bankmachine2_trccon_ready <= 1'd0;
+		end
+	end else begin
+		if ((~main_litedramcore_bankmachine2_trccon_ready)) begin
+			main_litedramcore_bankmachine2_trccon_count <= (main_litedramcore_bankmachine2_trccon_count - 1'd1);
+			if ((main_litedramcore_bankmachine2_trccon_count == 1'd1)) begin
+				main_litedramcore_bankmachine2_trccon_ready <= 1'd1;
+			end
+		end
+	end
+	if (main_litedramcore_bankmachine2_trascon_valid) begin
+		main_litedramcore_bankmachine2_trascon_count <= 3'd4;
+		if (1'd0) begin
+			main_litedramcore_bankmachine2_trascon_ready <= 1'd1;
+		end else begin
+			main_litedramcore_bankmachine2_trascon_ready <= 1'd0;
+		end
+	end else begin
+		if ((~main_litedramcore_bankmachine2_trascon_ready)) begin
+			main_litedramcore_bankmachine2_trascon_count <= (main_litedramcore_bankmachine2_trascon_count - 1'd1);
+			if ((main_litedramcore_bankmachine2_trascon_count == 1'd1)) begin
+				main_litedramcore_bankmachine2_trascon_ready <= 1'd1;
+			end
+		end
+	end
+	builder_bankmachine2_state <= builder_bankmachine2_next_state;
+	if (main_litedramcore_bankmachine3_row_close) begin
+		main_litedramcore_bankmachine3_row_opened <= 1'd0;
+	end else begin
+		if (main_litedramcore_bankmachine3_row_open) begin
+			main_litedramcore_bankmachine3_row_opened <= 1'd1;
+			main_litedramcore_bankmachine3_row <= main_litedramcore_bankmachine3_cmd_buffer_source_payload_addr[20:7];
+		end
+	end
+	if (((main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable) & (~main_litedramcore_bankmachine3_cmd_buffer_lookahead_replace))) begin
+		main_litedramcore_bankmachine3_cmd_buffer_lookahead_produce <= (main_litedramcore_bankmachine3_cmd_buffer_lookahead_produce + 1'd1);
+	end
+	if (main_litedramcore_bankmachine3_cmd_buffer_lookahead_do_read) begin
+		main_litedramcore_bankmachine3_cmd_buffer_lookahead_consume <= (main_litedramcore_bankmachine3_cmd_buffer_lookahead_consume + 1'd1);
+	end
+	if (((main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & main_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable) & (~main_litedramcore_bankmachine3_cmd_buffer_lookahead_replace))) begin
+		if ((~main_litedramcore_bankmachine3_cmd_buffer_lookahead_do_read)) begin
+			main_litedramcore_bankmachine3_cmd_buffer_lookahead_level <= (main_litedramcore_bankmachine3_cmd_buffer_lookahead_level + 1'd1);
+		end
+	end else begin
+		if (main_litedramcore_bankmachine3_cmd_buffer_lookahead_do_read) begin
+			main_litedramcore_bankmachine3_cmd_buffer_lookahead_level <= (main_litedramcore_bankmachine3_cmd_buffer_lookahead_level - 1'd1);
+		end
+	end
+	if (((~main_litedramcore_bankmachine3_cmd_buffer_source_valid) | main_litedramcore_bankmachine3_cmd_buffer_source_ready)) begin
+		main_litedramcore_bankmachine3_cmd_buffer_source_valid <= main_litedramcore_bankmachine3_cmd_buffer_sink_valid;
+		main_litedramcore_bankmachine3_cmd_buffer_source_first <= main_litedramcore_bankmachine3_cmd_buffer_sink_first;
+		main_litedramcore_bankmachine3_cmd_buffer_source_last <= main_litedramcore_bankmachine3_cmd_buffer_sink_last;
+		main_litedramcore_bankmachine3_cmd_buffer_source_payload_we <= main_litedramcore_bankmachine3_cmd_buffer_sink_payload_we;
+		main_litedramcore_bankmachine3_cmd_buffer_source_payload_addr <= main_litedramcore_bankmachine3_cmd_buffer_sink_payload_addr;
+	end
+	if (main_litedramcore_bankmachine3_twtpcon_valid) begin
+		main_litedramcore_bankmachine3_twtpcon_count <= 3'd5;
+		if (1'd0) begin
+			main_litedramcore_bankmachine3_twtpcon_ready <= 1'd1;
+		end else begin
+			main_litedramcore_bankmachine3_twtpcon_ready <= 1'd0;
+		end
+	end else begin
+		if ((~main_litedramcore_bankmachine3_twtpcon_ready)) begin
+			main_litedramcore_bankmachine3_twtpcon_count <= (main_litedramcore_bankmachine3_twtpcon_count - 1'd1);
+			if ((main_litedramcore_bankmachine3_twtpcon_count == 1'd1)) begin
+				main_litedramcore_bankmachine3_twtpcon_ready <= 1'd1;
+			end
+		end
+	end
+	if (main_litedramcore_bankmachine3_trccon_valid) begin
+		main_litedramcore_bankmachine3_trccon_count <= 3'd5;
+		if (1'd0) begin
+			main_litedramcore_bankmachine3_trccon_ready <= 1'd1;
+		end else begin
+			main_litedramcore_bankmachine3_trccon_ready <= 1'd0;
+		end
+	end else begin
+		if ((~main_litedramcore_bankmachine3_trccon_ready)) begin
+			main_litedramcore_bankmachine3_trccon_count <= (main_litedramcore_bankmachine3_trccon_count - 1'd1);
+			if ((main_litedramcore_bankmachine3_trccon_count == 1'd1)) begin
+				main_litedramcore_bankmachine3_trccon_ready <= 1'd1;
+			end
+		end
+	end
+	if (main_litedramcore_bankmachine3_trascon_valid) begin
+		main_litedramcore_bankmachine3_trascon_count <= 3'd4;
+		if (1'd0) begin
+			main_litedramcore_bankmachine3_trascon_ready <= 1'd1;
+		end else begin
+			main_litedramcore_bankmachine3_trascon_ready <= 1'd0;
+		end
+	end else begin
+		if ((~main_litedramcore_bankmachine3_trascon_ready)) begin
+			main_litedramcore_bankmachine3_trascon_count <= (main_litedramcore_bankmachine3_trascon_count - 1'd1);
+			if ((main_litedramcore_bankmachine3_trascon_count == 1'd1)) begin
+				main_litedramcore_bankmachine3_trascon_ready <= 1'd1;
+			end
+		end
+	end
+	builder_bankmachine3_state <= builder_bankmachine3_next_state;
+	if (main_litedramcore_bankmachine4_row_close) begin
+		main_litedramcore_bankmachine4_row_opened <= 1'd0;
+	end else begin
+		if (main_litedramcore_bankmachine4_row_open) begin
+			main_litedramcore_bankmachine4_row_opened <= 1'd1;
+			main_litedramcore_bankmachine4_row <= main_litedramcore_bankmachine4_cmd_buffer_source_payload_addr[20:7];
+		end
+	end
+	if (((main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable) & (~main_litedramcore_bankmachine4_cmd_buffer_lookahead_replace))) begin
+		main_litedramcore_bankmachine4_cmd_buffer_lookahead_produce <= (main_litedramcore_bankmachine4_cmd_buffer_lookahead_produce + 1'd1);
+	end
+	if (main_litedramcore_bankmachine4_cmd_buffer_lookahead_do_read) begin
+		main_litedramcore_bankmachine4_cmd_buffer_lookahead_consume <= (main_litedramcore_bankmachine4_cmd_buffer_lookahead_consume + 1'd1);
+	end
+	if (((main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & main_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable) & (~main_litedramcore_bankmachine4_cmd_buffer_lookahead_replace))) begin
+		if ((~main_litedramcore_bankmachine4_cmd_buffer_lookahead_do_read)) begin
+			main_litedramcore_bankmachine4_cmd_buffer_lookahead_level <= (main_litedramcore_bankmachine4_cmd_buffer_lookahead_level + 1'd1);
+		end
+	end else begin
+		if (main_litedramcore_bankmachine4_cmd_buffer_lookahead_do_read) begin
+			main_litedramcore_bankmachine4_cmd_buffer_lookahead_level <= (main_litedramcore_bankmachine4_cmd_buffer_lookahead_level - 1'd1);
+		end
+	end
+	if (((~main_litedramcore_bankmachine4_cmd_buffer_source_valid) | main_litedramcore_bankmachine4_cmd_buffer_source_ready)) begin
+		main_litedramcore_bankmachine4_cmd_buffer_source_valid <= main_litedramcore_bankmachine4_cmd_buffer_sink_valid;
+		main_litedramcore_bankmachine4_cmd_buffer_source_first <= main_litedramcore_bankmachine4_cmd_buffer_sink_first;
+		main_litedramcore_bankmachine4_cmd_buffer_source_last <= main_litedramcore_bankmachine4_cmd_buffer_sink_last;
+		main_litedramcore_bankmachine4_cmd_buffer_source_payload_we <= main_litedramcore_bankmachine4_cmd_buffer_sink_payload_we;
+		main_litedramcore_bankmachine4_cmd_buffer_source_payload_addr <= main_litedramcore_bankmachine4_cmd_buffer_sink_payload_addr;
+	end
+	if (main_litedramcore_bankmachine4_twtpcon_valid) begin
+		main_litedramcore_bankmachine4_twtpcon_count <= 3'd5;
+		if (1'd0) begin
+			main_litedramcore_bankmachine4_twtpcon_ready <= 1'd1;
+		end else begin
+			main_litedramcore_bankmachine4_twtpcon_ready <= 1'd0;
+		end
+	end else begin
+		if ((~main_litedramcore_bankmachine4_twtpcon_ready)) begin
+			main_litedramcore_bankmachine4_twtpcon_count <= (main_litedramcore_bankmachine4_twtpcon_count - 1'd1);
+			if ((main_litedramcore_bankmachine4_twtpcon_count == 1'd1)) begin
+				main_litedramcore_bankmachine4_twtpcon_ready <= 1'd1;
+			end
+		end
+	end
+	if (main_litedramcore_bankmachine4_trccon_valid) begin
+		main_litedramcore_bankmachine4_trccon_count <= 3'd5;
+		if (1'd0) begin
+			main_litedramcore_bankmachine4_trccon_ready <= 1'd1;
+		end else begin
+			main_litedramcore_bankmachine4_trccon_ready <= 1'd0;
+		end
+	end else begin
+		if ((~main_litedramcore_bankmachine4_trccon_ready)) begin
+			main_litedramcore_bankmachine4_trccon_count <= (main_litedramcore_bankmachine4_trccon_count - 1'd1);
+			if ((main_litedramcore_bankmachine4_trccon_count == 1'd1)) begin
+				main_litedramcore_bankmachine4_trccon_ready <= 1'd1;
+			end
+		end
+	end
+	if (main_litedramcore_bankmachine4_trascon_valid) begin
+		main_litedramcore_bankmachine4_trascon_count <= 3'd4;
+		if (1'd0) begin
+			main_litedramcore_bankmachine4_trascon_ready <= 1'd1;
+		end else begin
+			main_litedramcore_bankmachine4_trascon_ready <= 1'd0;
+		end
+	end else begin
+		if ((~main_litedramcore_bankmachine4_trascon_ready)) begin
+			main_litedramcore_bankmachine4_trascon_count <= (main_litedramcore_bankmachine4_trascon_count - 1'd1);
+			if ((main_litedramcore_bankmachine4_trascon_count == 1'd1)) begin
+				main_litedramcore_bankmachine4_trascon_ready <= 1'd1;
+			end
+		end
+	end
+	builder_bankmachine4_state <= builder_bankmachine4_next_state;
+	if (main_litedramcore_bankmachine5_row_close) begin
+		main_litedramcore_bankmachine5_row_opened <= 1'd0;
+	end else begin
+		if (main_litedramcore_bankmachine5_row_open) begin
+			main_litedramcore_bankmachine5_row_opened <= 1'd1;
+			main_litedramcore_bankmachine5_row <= main_litedramcore_bankmachine5_cmd_buffer_source_payload_addr[20:7];
+		end
+	end
+	if (((main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable) & (~main_litedramcore_bankmachine5_cmd_buffer_lookahead_replace))) begin
+		main_litedramcore_bankmachine5_cmd_buffer_lookahead_produce <= (main_litedramcore_bankmachine5_cmd_buffer_lookahead_produce + 1'd1);
+	end
+	if (main_litedramcore_bankmachine5_cmd_buffer_lookahead_do_read) begin
+		main_litedramcore_bankmachine5_cmd_buffer_lookahead_consume <= (main_litedramcore_bankmachine5_cmd_buffer_lookahead_consume + 1'd1);
+	end
+	if (((main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & main_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable) & (~main_litedramcore_bankmachine5_cmd_buffer_lookahead_replace))) begin
+		if ((~main_litedramcore_bankmachine5_cmd_buffer_lookahead_do_read)) begin
+			main_litedramcore_bankmachine5_cmd_buffer_lookahead_level <= (main_litedramcore_bankmachine5_cmd_buffer_lookahead_level + 1'd1);
+		end
+	end else begin
+		if (main_litedramcore_bankmachine5_cmd_buffer_lookahead_do_read) begin
+			main_litedramcore_bankmachine5_cmd_buffer_lookahead_level <= (main_litedramcore_bankmachine5_cmd_buffer_lookahead_level - 1'd1);
+		end
+	end
+	if (((~main_litedramcore_bankmachine5_cmd_buffer_source_valid) | main_litedramcore_bankmachine5_cmd_buffer_source_ready)) begin
+		main_litedramcore_bankmachine5_cmd_buffer_source_valid <= main_litedramcore_bankmachine5_cmd_buffer_sink_valid;
+		main_litedramcore_bankmachine5_cmd_buffer_source_first <= main_litedramcore_bankmachine5_cmd_buffer_sink_first;
+		main_litedramcore_bankmachine5_cmd_buffer_source_last <= main_litedramcore_bankmachine5_cmd_buffer_sink_last;
+		main_litedramcore_bankmachine5_cmd_buffer_source_payload_we <= main_litedramcore_bankmachine5_cmd_buffer_sink_payload_we;
+		main_litedramcore_bankmachine5_cmd_buffer_source_payload_addr <= main_litedramcore_bankmachine5_cmd_buffer_sink_payload_addr;
+	end
+	if (main_litedramcore_bankmachine5_twtpcon_valid) begin
+		main_litedramcore_bankmachine5_twtpcon_count <= 3'd5;
+		if (1'd0) begin
+			main_litedramcore_bankmachine5_twtpcon_ready <= 1'd1;
+		end else begin
+			main_litedramcore_bankmachine5_twtpcon_ready <= 1'd0;
+		end
+	end else begin
+		if ((~main_litedramcore_bankmachine5_twtpcon_ready)) begin
+			main_litedramcore_bankmachine5_twtpcon_count <= (main_litedramcore_bankmachine5_twtpcon_count - 1'd1);
+			if ((main_litedramcore_bankmachine5_twtpcon_count == 1'd1)) begin
+				main_litedramcore_bankmachine5_twtpcon_ready <= 1'd1;
+			end
+		end
+	end
+	if (main_litedramcore_bankmachine5_trccon_valid) begin
+		main_litedramcore_bankmachine5_trccon_count <= 3'd5;
+		if (1'd0) begin
+			main_litedramcore_bankmachine5_trccon_ready <= 1'd1;
+		end else begin
+			main_litedramcore_bankmachine5_trccon_ready <= 1'd0;
+		end
+	end else begin
+		if ((~main_litedramcore_bankmachine5_trccon_ready)) begin
+			main_litedramcore_bankmachine5_trccon_count <= (main_litedramcore_bankmachine5_trccon_count - 1'd1);
+			if ((main_litedramcore_bankmachine5_trccon_count == 1'd1)) begin
+				main_litedramcore_bankmachine5_trccon_ready <= 1'd1;
+			end
+		end
+	end
+	if (main_litedramcore_bankmachine5_trascon_valid) begin
+		main_litedramcore_bankmachine5_trascon_count <= 3'd4;
+		if (1'd0) begin
+			main_litedramcore_bankmachine5_trascon_ready <= 1'd1;
+		end else begin
+			main_litedramcore_bankmachine5_trascon_ready <= 1'd0;
+		end
+	end else begin
+		if ((~main_litedramcore_bankmachine5_trascon_ready)) begin
+			main_litedramcore_bankmachine5_trascon_count <= (main_litedramcore_bankmachine5_trascon_count - 1'd1);
+			if ((main_litedramcore_bankmachine5_trascon_count == 1'd1)) begin
+				main_litedramcore_bankmachine5_trascon_ready <= 1'd1;
+			end
+		end
+	end
+	builder_bankmachine5_state <= builder_bankmachine5_next_state;
+	if (main_litedramcore_bankmachine6_row_close) begin
+		main_litedramcore_bankmachine6_row_opened <= 1'd0;
+	end else begin
+		if (main_litedramcore_bankmachine6_row_open) begin
+			main_litedramcore_bankmachine6_row_opened <= 1'd1;
+			main_litedramcore_bankmachine6_row <= main_litedramcore_bankmachine6_cmd_buffer_source_payload_addr[20:7];
+		end
+	end
+	if (((main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable) & (~main_litedramcore_bankmachine6_cmd_buffer_lookahead_replace))) begin
+		main_litedramcore_bankmachine6_cmd_buffer_lookahead_produce <= (main_litedramcore_bankmachine6_cmd_buffer_lookahead_produce + 1'd1);
+	end
+	if (main_litedramcore_bankmachine6_cmd_buffer_lookahead_do_read) begin
+		main_litedramcore_bankmachine6_cmd_buffer_lookahead_consume <= (main_litedramcore_bankmachine6_cmd_buffer_lookahead_consume + 1'd1);
+	end
+	if (((main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & main_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable) & (~main_litedramcore_bankmachine6_cmd_buffer_lookahead_replace))) begin
+		if ((~main_litedramcore_bankmachine6_cmd_buffer_lookahead_do_read)) begin
+			main_litedramcore_bankmachine6_cmd_buffer_lookahead_level <= (main_litedramcore_bankmachine6_cmd_buffer_lookahead_level + 1'd1);
+		end
+	end else begin
+		if (main_litedramcore_bankmachine6_cmd_buffer_lookahead_do_read) begin
+			main_litedramcore_bankmachine6_cmd_buffer_lookahead_level <= (main_litedramcore_bankmachine6_cmd_buffer_lookahead_level - 1'd1);
+		end
+	end
+	if (((~main_litedramcore_bankmachine6_cmd_buffer_source_valid) | main_litedramcore_bankmachine6_cmd_buffer_source_ready)) begin
+		main_litedramcore_bankmachine6_cmd_buffer_source_valid <= main_litedramcore_bankmachine6_cmd_buffer_sink_valid;
+		main_litedramcore_bankmachine6_cmd_buffer_source_first <= main_litedramcore_bankmachine6_cmd_buffer_sink_first;
+		main_litedramcore_bankmachine6_cmd_buffer_source_last <= main_litedramcore_bankmachine6_cmd_buffer_sink_last;
+		main_litedramcore_bankmachine6_cmd_buffer_source_payload_we <= main_litedramcore_bankmachine6_cmd_buffer_sink_payload_we;
+		main_litedramcore_bankmachine6_cmd_buffer_source_payload_addr <= main_litedramcore_bankmachine6_cmd_buffer_sink_payload_addr;
+	end
+	if (main_litedramcore_bankmachine6_twtpcon_valid) begin
+		main_litedramcore_bankmachine6_twtpcon_count <= 3'd5;
+		if (1'd0) begin
+			main_litedramcore_bankmachine6_twtpcon_ready <= 1'd1;
+		end else begin
+			main_litedramcore_bankmachine6_twtpcon_ready <= 1'd0;
+		end
+	end else begin
+		if ((~main_litedramcore_bankmachine6_twtpcon_ready)) begin
+			main_litedramcore_bankmachine6_twtpcon_count <= (main_litedramcore_bankmachine6_twtpcon_count - 1'd1);
+			if ((main_litedramcore_bankmachine6_twtpcon_count == 1'd1)) begin
+				main_litedramcore_bankmachine6_twtpcon_ready <= 1'd1;
+			end
+		end
+	end
+	if (main_litedramcore_bankmachine6_trccon_valid) begin
+		main_litedramcore_bankmachine6_trccon_count <= 3'd5;
+		if (1'd0) begin
+			main_litedramcore_bankmachine6_trccon_ready <= 1'd1;
+		end else begin
+			main_litedramcore_bankmachine6_trccon_ready <= 1'd0;
+		end
+	end else begin
+		if ((~main_litedramcore_bankmachine6_trccon_ready)) begin
+			main_litedramcore_bankmachine6_trccon_count <= (main_litedramcore_bankmachine6_trccon_count - 1'd1);
+			if ((main_litedramcore_bankmachine6_trccon_count == 1'd1)) begin
+				main_litedramcore_bankmachine6_trccon_ready <= 1'd1;
+			end
+		end
+	end
+	if (main_litedramcore_bankmachine6_trascon_valid) begin
+		main_litedramcore_bankmachine6_trascon_count <= 3'd4;
+		if (1'd0) begin
+			main_litedramcore_bankmachine6_trascon_ready <= 1'd1;
+		end else begin
+			main_litedramcore_bankmachine6_trascon_ready <= 1'd0;
+		end
+	end else begin
+		if ((~main_litedramcore_bankmachine6_trascon_ready)) begin
+			main_litedramcore_bankmachine6_trascon_count <= (main_litedramcore_bankmachine6_trascon_count - 1'd1);
+			if ((main_litedramcore_bankmachine6_trascon_count == 1'd1)) begin
+				main_litedramcore_bankmachine6_trascon_ready <= 1'd1;
+			end
+		end
+	end
+	builder_bankmachine6_state <= builder_bankmachine6_next_state;
+	if (main_litedramcore_bankmachine7_row_close) begin
+		main_litedramcore_bankmachine7_row_opened <= 1'd0;
+	end else begin
+		if (main_litedramcore_bankmachine7_row_open) begin
+			main_litedramcore_bankmachine7_row_opened <= 1'd1;
+			main_litedramcore_bankmachine7_row <= main_litedramcore_bankmachine7_cmd_buffer_source_payload_addr[20:7];
+		end
+	end
+	if (((main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable) & (~main_litedramcore_bankmachine7_cmd_buffer_lookahead_replace))) begin
+		main_litedramcore_bankmachine7_cmd_buffer_lookahead_produce <= (main_litedramcore_bankmachine7_cmd_buffer_lookahead_produce + 1'd1);
+	end
+	if (main_litedramcore_bankmachine7_cmd_buffer_lookahead_do_read) begin
+		main_litedramcore_bankmachine7_cmd_buffer_lookahead_consume <= (main_litedramcore_bankmachine7_cmd_buffer_lookahead_consume + 1'd1);
+	end
+	if (((main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & main_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable) & (~main_litedramcore_bankmachine7_cmd_buffer_lookahead_replace))) begin
+		if ((~main_litedramcore_bankmachine7_cmd_buffer_lookahead_do_read)) begin
+			main_litedramcore_bankmachine7_cmd_buffer_lookahead_level <= (main_litedramcore_bankmachine7_cmd_buffer_lookahead_level + 1'd1);
+		end
+	end else begin
+		if (main_litedramcore_bankmachine7_cmd_buffer_lookahead_do_read) begin
+			main_litedramcore_bankmachine7_cmd_buffer_lookahead_level <= (main_litedramcore_bankmachine7_cmd_buffer_lookahead_level - 1'd1);
+		end
+	end
+	if (((~main_litedramcore_bankmachine7_cmd_buffer_source_valid) | main_litedramcore_bankmachine7_cmd_buffer_source_ready)) begin
+		main_litedramcore_bankmachine7_cmd_buffer_source_valid <= main_litedramcore_bankmachine7_cmd_buffer_sink_valid;
+		main_litedramcore_bankmachine7_cmd_buffer_source_first <= main_litedramcore_bankmachine7_cmd_buffer_sink_first;
+		main_litedramcore_bankmachine7_cmd_buffer_source_last <= main_litedramcore_bankmachine7_cmd_buffer_sink_last;
+		main_litedramcore_bankmachine7_cmd_buffer_source_payload_we <= main_litedramcore_bankmachine7_cmd_buffer_sink_payload_we;
+		main_litedramcore_bankmachine7_cmd_buffer_source_payload_addr <= main_litedramcore_bankmachine7_cmd_buffer_sink_payload_addr;
+	end
+	if (main_litedramcore_bankmachine7_twtpcon_valid) begin
+		main_litedramcore_bankmachine7_twtpcon_count <= 3'd5;
+		if (1'd0) begin
+			main_litedramcore_bankmachine7_twtpcon_ready <= 1'd1;
+		end else begin
+			main_litedramcore_bankmachine7_twtpcon_ready <= 1'd0;
+		end
+	end else begin
+		if ((~main_litedramcore_bankmachine7_twtpcon_ready)) begin
+			main_litedramcore_bankmachine7_twtpcon_count <= (main_litedramcore_bankmachine7_twtpcon_count - 1'd1);
+			if ((main_litedramcore_bankmachine7_twtpcon_count == 1'd1)) begin
+				main_litedramcore_bankmachine7_twtpcon_ready <= 1'd1;
+			end
+		end
+	end
+	if (main_litedramcore_bankmachine7_trccon_valid) begin
+		main_litedramcore_bankmachine7_trccon_count <= 3'd5;
+		if (1'd0) begin
+			main_litedramcore_bankmachine7_trccon_ready <= 1'd1;
+		end else begin
+			main_litedramcore_bankmachine7_trccon_ready <= 1'd0;
+		end
+	end else begin
+		if ((~main_litedramcore_bankmachine7_trccon_ready)) begin
+			main_litedramcore_bankmachine7_trccon_count <= (main_litedramcore_bankmachine7_trccon_count - 1'd1);
+			if ((main_litedramcore_bankmachine7_trccon_count == 1'd1)) begin
+				main_litedramcore_bankmachine7_trccon_ready <= 1'd1;
+			end
+		end
+	end
+	if (main_litedramcore_bankmachine7_trascon_valid) begin
+		main_litedramcore_bankmachine7_trascon_count <= 3'd4;
+		if (1'd0) begin
+			main_litedramcore_bankmachine7_trascon_ready <= 1'd1;
+		end else begin
+			main_litedramcore_bankmachine7_trascon_ready <= 1'd0;
+		end
+	end else begin
+		if ((~main_litedramcore_bankmachine7_trascon_ready)) begin
+			main_litedramcore_bankmachine7_trascon_count <= (main_litedramcore_bankmachine7_trascon_count - 1'd1);
+			if ((main_litedramcore_bankmachine7_trascon_count == 1'd1)) begin
+				main_litedramcore_bankmachine7_trascon_ready <= 1'd1;
+			end
+		end
+	end
+	builder_bankmachine7_state <= builder_bankmachine7_next_state;
+	if ((~main_litedramcore_en0)) begin
+		main_litedramcore_time0 <= 5'd31;
+	end else begin
+		if ((~main_litedramcore_max_time0)) begin
+			main_litedramcore_time0 <= (main_litedramcore_time0 - 1'd1);
+		end
+	end
+	if ((~main_litedramcore_en1)) begin
+		main_litedramcore_time1 <= 4'd15;
+	end else begin
+		if ((~main_litedramcore_max_time1)) begin
+			main_litedramcore_time1 <= (main_litedramcore_time1 - 1'd1);
+		end
+	end
+	if (main_litedramcore_choose_cmd_ce) begin
+		case (main_litedramcore_choose_cmd_grant)
+			1'd0: begin
+				if (main_litedramcore_choose_cmd_request[1]) begin
+					main_litedramcore_choose_cmd_grant <= 1'd1;
+				end else begin
+					if (main_litedramcore_choose_cmd_request[2]) begin
+						main_litedramcore_choose_cmd_grant <= 2'd2;
+					end else begin
+						if (main_litedramcore_choose_cmd_request[3]) begin
+							main_litedramcore_choose_cmd_grant <= 2'd3;
+						end else begin
+							if (main_litedramcore_choose_cmd_request[4]) begin
+								main_litedramcore_choose_cmd_grant <= 3'd4;
+							end else begin
+								if (main_litedramcore_choose_cmd_request[5]) begin
+									main_litedramcore_choose_cmd_grant <= 3'd5;
+								end else begin
+									if (main_litedramcore_choose_cmd_request[6]) begin
+										main_litedramcore_choose_cmd_grant <= 3'd6;
+									end else begin
+										if (main_litedramcore_choose_cmd_request[7]) begin
+											main_litedramcore_choose_cmd_grant <= 3'd7;
+										end
+									end
+								end
+							end
+						end
+					end
+				end
+			end
+			1'd1: begin
+				if (main_litedramcore_choose_cmd_request[2]) begin
+					main_litedramcore_choose_cmd_grant <= 2'd2;
+				end else begin
+					if (main_litedramcore_choose_cmd_request[3]) begin
+						main_litedramcore_choose_cmd_grant <= 2'd3;
+					end else begin
+						if (main_litedramcore_choose_cmd_request[4]) begin
+							main_litedramcore_choose_cmd_grant <= 3'd4;
+						end else begin
+							if (main_litedramcore_choose_cmd_request[5]) begin
+								main_litedramcore_choose_cmd_grant <= 3'd5;
+							end else begin
+								if (main_litedramcore_choose_cmd_request[6]) begin
+									main_litedramcore_choose_cmd_grant <= 3'd6;
+								end else begin
+									if (main_litedramcore_choose_cmd_request[7]) begin
+										main_litedramcore_choose_cmd_grant <= 3'd7;
+									end else begin
+										if (main_litedramcore_choose_cmd_request[0]) begin
+											main_litedramcore_choose_cmd_grant <= 1'd0;
+										end
+									end
+								end
+							end
+						end
+					end
+				end
+			end
+			2'd2: begin
+				if (main_litedramcore_choose_cmd_request[3]) begin
+					main_litedramcore_choose_cmd_grant <= 2'd3;
+				end else begin
+					if (main_litedramcore_choose_cmd_request[4]) begin
+						main_litedramcore_choose_cmd_grant <= 3'd4;
+					end else begin
+						if (main_litedramcore_choose_cmd_request[5]) begin
+							main_litedramcore_choose_cmd_grant <= 3'd5;
+						end else begin
+							if (main_litedramcore_choose_cmd_request[6]) begin
+								main_litedramcore_choose_cmd_grant <= 3'd6;
+							end else begin
+								if (main_litedramcore_choose_cmd_request[7]) begin
+									main_litedramcore_choose_cmd_grant <= 3'd7;
+								end else begin
+									if (main_litedramcore_choose_cmd_request[0]) begin
+										main_litedramcore_choose_cmd_grant <= 1'd0;
+									end else begin
+										if (main_litedramcore_choose_cmd_request[1]) begin
+											main_litedramcore_choose_cmd_grant <= 1'd1;
+										end
+									end
+								end
+							end
+						end
+					end
+				end
+			end
+			2'd3: begin
+				if (main_litedramcore_choose_cmd_request[4]) begin
+					main_litedramcore_choose_cmd_grant <= 3'd4;
+				end else begin
+					if (main_litedramcore_choose_cmd_request[5]) begin
+						main_litedramcore_choose_cmd_grant <= 3'd5;
+					end else begin
+						if (main_litedramcore_choose_cmd_request[6]) begin
+							main_litedramcore_choose_cmd_grant <= 3'd6;
+						end else begin
+							if (main_litedramcore_choose_cmd_request[7]) begin
+								main_litedramcore_choose_cmd_grant <= 3'd7;
+							end else begin
+								if (main_litedramcore_choose_cmd_request[0]) begin
+									main_litedramcore_choose_cmd_grant <= 1'd0;
+								end else begin
+									if (main_litedramcore_choose_cmd_request[1]) begin
+										main_litedramcore_choose_cmd_grant <= 1'd1;
+									end else begin
+										if (main_litedramcore_choose_cmd_request[2]) begin
+											main_litedramcore_choose_cmd_grant <= 2'd2;
+										end
+									end
+								end
+							end
+						end
+					end
+				end
+			end
+			3'd4: begin
+				if (main_litedramcore_choose_cmd_request[5]) begin
+					main_litedramcore_choose_cmd_grant <= 3'd5;
+				end else begin
+					if (main_litedramcore_choose_cmd_request[6]) begin
+						main_litedramcore_choose_cmd_grant <= 3'd6;
+					end else begin
+						if (main_litedramcore_choose_cmd_request[7]) begin
+							main_litedramcore_choose_cmd_grant <= 3'd7;
+						end else begin
+							if (main_litedramcore_choose_cmd_request[0]) begin
+								main_litedramcore_choose_cmd_grant <= 1'd0;
+							end else begin
+								if (main_litedramcore_choose_cmd_request[1]) begin
+									main_litedramcore_choose_cmd_grant <= 1'd1;
+								end else begin
+									if (main_litedramcore_choose_cmd_request[2]) begin
+										main_litedramcore_choose_cmd_grant <= 2'd2;
+									end else begin
+										if (main_litedramcore_choose_cmd_request[3]) begin
+											main_litedramcore_choose_cmd_grant <= 2'd3;
+										end
+									end
+								end
+							end
+						end
+					end
+				end
+			end
+			3'd5: begin
+				if (main_litedramcore_choose_cmd_request[6]) begin
+					main_litedramcore_choose_cmd_grant <= 3'd6;
+				end else begin
+					if (main_litedramcore_choose_cmd_request[7]) begin
+						main_litedramcore_choose_cmd_grant <= 3'd7;
+					end else begin
+						if (main_litedramcore_choose_cmd_request[0]) begin
+							main_litedramcore_choose_cmd_grant <= 1'd0;
+						end else begin
+							if (main_litedramcore_choose_cmd_request[1]) begin
+								main_litedramcore_choose_cmd_grant <= 1'd1;
+							end else begin
+								if (main_litedramcore_choose_cmd_request[2]) begin
+									main_litedramcore_choose_cmd_grant <= 2'd2;
+								end else begin
+									if (main_litedramcore_choose_cmd_request[3]) begin
+										main_litedramcore_choose_cmd_grant <= 2'd3;
+									end else begin
+										if (main_litedramcore_choose_cmd_request[4]) begin
+											main_litedramcore_choose_cmd_grant <= 3'd4;
+										end
+									end
+								end
+							end
+						end
+					end
+				end
+			end
+			3'd6: begin
+				if (main_litedramcore_choose_cmd_request[7]) begin
+					main_litedramcore_choose_cmd_grant <= 3'd7;
+				end else begin
+					if (main_litedramcore_choose_cmd_request[0]) begin
+						main_litedramcore_choose_cmd_grant <= 1'd0;
+					end else begin
+						if (main_litedramcore_choose_cmd_request[1]) begin
+							main_litedramcore_choose_cmd_grant <= 1'd1;
+						end else begin
+							if (main_litedramcore_choose_cmd_request[2]) begin
+								main_litedramcore_choose_cmd_grant <= 2'd2;
+							end else begin
+								if (main_litedramcore_choose_cmd_request[3]) begin
+									main_litedramcore_choose_cmd_grant <= 2'd3;
+								end else begin
+									if (main_litedramcore_choose_cmd_request[4]) begin
+										main_litedramcore_choose_cmd_grant <= 3'd4;
+									end else begin
+										if (main_litedramcore_choose_cmd_request[5]) begin
+											main_litedramcore_choose_cmd_grant <= 3'd5;
+										end
+									end
+								end
+							end
+						end
+					end
+				end
+			end
+			3'd7: begin
+				if (main_litedramcore_choose_cmd_request[0]) begin
+					main_litedramcore_choose_cmd_grant <= 1'd0;
+				end else begin
+					if (main_litedramcore_choose_cmd_request[1]) begin
+						main_litedramcore_choose_cmd_grant <= 1'd1;
+					end else begin
+						if (main_litedramcore_choose_cmd_request[2]) begin
+							main_litedramcore_choose_cmd_grant <= 2'd2;
+						end else begin
+							if (main_litedramcore_choose_cmd_request[3]) begin
+								main_litedramcore_choose_cmd_grant <= 2'd3;
+							end else begin
+								if (main_litedramcore_choose_cmd_request[4]) begin
+									main_litedramcore_choose_cmd_grant <= 3'd4;
+								end else begin
+									if (main_litedramcore_choose_cmd_request[5]) begin
+										main_litedramcore_choose_cmd_grant <= 3'd5;
+									end else begin
+										if (main_litedramcore_choose_cmd_request[6]) begin
+											main_litedramcore_choose_cmd_grant <= 3'd6;
+										end
+									end
+								end
+							end
+						end
+					end
+				end
+			end
+		endcase
+	end
+	if (main_litedramcore_choose_req_ce) begin
+		case (main_litedramcore_choose_req_grant)
+			1'd0: begin
+				if (main_litedramcore_choose_req_request[1]) begin
+					main_litedramcore_choose_req_grant <= 1'd1;
+				end else begin
+					if (main_litedramcore_choose_req_request[2]) begin
+						main_litedramcore_choose_req_grant <= 2'd2;
+					end else begin
+						if (main_litedramcore_choose_req_request[3]) begin
+							main_litedramcore_choose_req_grant <= 2'd3;
+						end else begin
+							if (main_litedramcore_choose_req_request[4]) begin
+								main_litedramcore_choose_req_grant <= 3'd4;
+							end else begin
+								if (main_litedramcore_choose_req_request[5]) begin
+									main_litedramcore_choose_req_grant <= 3'd5;
+								end else begin
+									if (main_litedramcore_choose_req_request[6]) begin
+										main_litedramcore_choose_req_grant <= 3'd6;
+									end else begin
+										if (main_litedramcore_choose_req_request[7]) begin
+											main_litedramcore_choose_req_grant <= 3'd7;
+										end
+									end
+								end
+							end
+						end
+					end
+				end
+			end
+			1'd1: begin
+				if (main_litedramcore_choose_req_request[2]) begin
+					main_litedramcore_choose_req_grant <= 2'd2;
+				end else begin
+					if (main_litedramcore_choose_req_request[3]) begin
+						main_litedramcore_choose_req_grant <= 2'd3;
+					end else begin
+						if (main_litedramcore_choose_req_request[4]) begin
+							main_litedramcore_choose_req_grant <= 3'd4;
+						end else begin
+							if (main_litedramcore_choose_req_request[5]) begin
+								main_litedramcore_choose_req_grant <= 3'd5;
+							end else begin
+								if (main_litedramcore_choose_req_request[6]) begin
+									main_litedramcore_choose_req_grant <= 3'd6;
+								end else begin
+									if (main_litedramcore_choose_req_request[7]) begin
+										main_litedramcore_choose_req_grant <= 3'd7;
+									end else begin
+										if (main_litedramcore_choose_req_request[0]) begin
+											main_litedramcore_choose_req_grant <= 1'd0;
+										end
+									end
+								end
+							end
+						end
+					end
+				end
+			end
+			2'd2: begin
+				if (main_litedramcore_choose_req_request[3]) begin
+					main_litedramcore_choose_req_grant <= 2'd3;
+				end else begin
+					if (main_litedramcore_choose_req_request[4]) begin
+						main_litedramcore_choose_req_grant <= 3'd4;
+					end else begin
+						if (main_litedramcore_choose_req_request[5]) begin
+							main_litedramcore_choose_req_grant <= 3'd5;
+						end else begin
+							if (main_litedramcore_choose_req_request[6]) begin
+								main_litedramcore_choose_req_grant <= 3'd6;
+							end else begin
+								if (main_litedramcore_choose_req_request[7]) begin
+									main_litedramcore_choose_req_grant <= 3'd7;
+								end else begin
+									if (main_litedramcore_choose_req_request[0]) begin
+										main_litedramcore_choose_req_grant <= 1'd0;
+									end else begin
+										if (main_litedramcore_choose_req_request[1]) begin
+											main_litedramcore_choose_req_grant <= 1'd1;
+										end
+									end
+								end
+							end
+						end
+					end
+				end
+			end
+			2'd3: begin
+				if (main_litedramcore_choose_req_request[4]) begin
+					main_litedramcore_choose_req_grant <= 3'd4;
+				end else begin
+					if (main_litedramcore_choose_req_request[5]) begin
+						main_litedramcore_choose_req_grant <= 3'd5;
+					end else begin
+						if (main_litedramcore_choose_req_request[6]) begin
+							main_litedramcore_choose_req_grant <= 3'd6;
+						end else begin
+							if (main_litedramcore_choose_req_request[7]) begin
+								main_litedramcore_choose_req_grant <= 3'd7;
+							end else begin
+								if (main_litedramcore_choose_req_request[0]) begin
+									main_litedramcore_choose_req_grant <= 1'd0;
+								end else begin
+									if (main_litedramcore_choose_req_request[1]) begin
+										main_litedramcore_choose_req_grant <= 1'd1;
+									end else begin
+										if (main_litedramcore_choose_req_request[2]) begin
+											main_litedramcore_choose_req_grant <= 2'd2;
+										end
+									end
+								end
+							end
+						end
+					end
+				end
+			end
+			3'd4: begin
+				if (main_litedramcore_choose_req_request[5]) begin
+					main_litedramcore_choose_req_grant <= 3'd5;
+				end else begin
+					if (main_litedramcore_choose_req_request[6]) begin
+						main_litedramcore_choose_req_grant <= 3'd6;
+					end else begin
+						if (main_litedramcore_choose_req_request[7]) begin
+							main_litedramcore_choose_req_grant <= 3'd7;
+						end else begin
+							if (main_litedramcore_choose_req_request[0]) begin
+								main_litedramcore_choose_req_grant <= 1'd0;
+							end else begin
+								if (main_litedramcore_choose_req_request[1]) begin
+									main_litedramcore_choose_req_grant <= 1'd1;
+								end else begin
+									if (main_litedramcore_choose_req_request[2]) begin
+										main_litedramcore_choose_req_grant <= 2'd2;
+									end else begin
+										if (main_litedramcore_choose_req_request[3]) begin
+											main_litedramcore_choose_req_grant <= 2'd3;
+										end
+									end
+								end
+							end
+						end
+					end
+				end
+			end
+			3'd5: begin
+				if (main_litedramcore_choose_req_request[6]) begin
+					main_litedramcore_choose_req_grant <= 3'd6;
+				end else begin
+					if (main_litedramcore_choose_req_request[7]) begin
+						main_litedramcore_choose_req_grant <= 3'd7;
+					end else begin
+						if (main_litedramcore_choose_req_request[0]) begin
+							main_litedramcore_choose_req_grant <= 1'd0;
+						end else begin
+							if (main_litedramcore_choose_req_request[1]) begin
+								main_litedramcore_choose_req_grant <= 1'd1;
+							end else begin
+								if (main_litedramcore_choose_req_request[2]) begin
+									main_litedramcore_choose_req_grant <= 2'd2;
+								end else begin
+									if (main_litedramcore_choose_req_request[3]) begin
+										main_litedramcore_choose_req_grant <= 2'd3;
+									end else begin
+										if (main_litedramcore_choose_req_request[4]) begin
+											main_litedramcore_choose_req_grant <= 3'd4;
+										end
+									end
+								end
+							end
+						end
+					end
+				end
+			end
+			3'd6: begin
+				if (main_litedramcore_choose_req_request[7]) begin
+					main_litedramcore_choose_req_grant <= 3'd7;
+				end else begin
+					if (main_litedramcore_choose_req_request[0]) begin
+						main_litedramcore_choose_req_grant <= 1'd0;
+					end else begin
+						if (main_litedramcore_choose_req_request[1]) begin
+							main_litedramcore_choose_req_grant <= 1'd1;
+						end else begin
+							if (main_litedramcore_choose_req_request[2]) begin
+								main_litedramcore_choose_req_grant <= 2'd2;
+							end else begin
+								if (main_litedramcore_choose_req_request[3]) begin
+									main_litedramcore_choose_req_grant <= 2'd3;
+								end else begin
+									if (main_litedramcore_choose_req_request[4]) begin
+										main_litedramcore_choose_req_grant <= 3'd4;
+									end else begin
+										if (main_litedramcore_choose_req_request[5]) begin
+											main_litedramcore_choose_req_grant <= 3'd5;
+										end
+									end
+								end
+							end
+						end
+					end
+				end
+			end
+			3'd7: begin
+				if (main_litedramcore_choose_req_request[0]) begin
+					main_litedramcore_choose_req_grant <= 1'd0;
+				end else begin
+					if (main_litedramcore_choose_req_request[1]) begin
+						main_litedramcore_choose_req_grant <= 1'd1;
+					end else begin
+						if (main_litedramcore_choose_req_request[2]) begin
+							main_litedramcore_choose_req_grant <= 2'd2;
+						end else begin
+							if (main_litedramcore_choose_req_request[3]) begin
+								main_litedramcore_choose_req_grant <= 2'd3;
+							end else begin
+								if (main_litedramcore_choose_req_request[4]) begin
+									main_litedramcore_choose_req_grant <= 3'd4;
+								end else begin
+									if (main_litedramcore_choose_req_request[5]) begin
+										main_litedramcore_choose_req_grant <= 3'd5;
+									end else begin
+										if (main_litedramcore_choose_req_request[6]) begin
+											main_litedramcore_choose_req_grant <= 3'd6;
+										end
+									end
+								end
+							end
+						end
+					end
+				end
+			end
+		endcase
+	end
+	main_litedramcore_dfi_p0_cs_n <= 1'd0;
+	main_litedramcore_dfi_p0_bank <= builder_array_muxed0;
+	main_litedramcore_dfi_p0_address <= builder_array_muxed1;
+	main_litedramcore_dfi_p0_cas_n <= (~builder_array_muxed2);
+	main_litedramcore_dfi_p0_ras_n <= (~builder_array_muxed3);
+	main_litedramcore_dfi_p0_we_n <= (~builder_array_muxed4);
+	main_litedramcore_dfi_p0_rddata_en <= builder_array_muxed5;
+	main_litedramcore_dfi_p0_wrdata_en <= builder_array_muxed6;
+	main_litedramcore_dfi_p1_cs_n <= 1'd0;
+	main_litedramcore_dfi_p1_bank <= builder_array_muxed7;
+	main_litedramcore_dfi_p1_address <= builder_array_muxed8;
+	main_litedramcore_dfi_p1_cas_n <= (~builder_array_muxed9);
+	main_litedramcore_dfi_p1_ras_n <= (~builder_array_muxed10);
+	main_litedramcore_dfi_p1_we_n <= (~builder_array_muxed11);
+	main_litedramcore_dfi_p1_rddata_en <= builder_array_muxed12;
+	main_litedramcore_dfi_p1_wrdata_en <= builder_array_muxed13;
+	main_litedramcore_dfi_p2_cs_n <= 1'd0;
+	main_litedramcore_dfi_p2_bank <= builder_array_muxed14;
+	main_litedramcore_dfi_p2_address <= builder_array_muxed15;
+	main_litedramcore_dfi_p2_cas_n <= (~builder_array_muxed16);
+	main_litedramcore_dfi_p2_ras_n <= (~builder_array_muxed17);
+	main_litedramcore_dfi_p2_we_n <= (~builder_array_muxed18);
+	main_litedramcore_dfi_p2_rddata_en <= builder_array_muxed19;
+	main_litedramcore_dfi_p2_wrdata_en <= builder_array_muxed20;
+	main_litedramcore_dfi_p3_cs_n <= 1'd0;
+	main_litedramcore_dfi_p3_bank <= builder_array_muxed21;
+	main_litedramcore_dfi_p3_address <= builder_array_muxed22;
+	main_litedramcore_dfi_p3_cas_n <= (~builder_array_muxed23);
+	main_litedramcore_dfi_p3_ras_n <= (~builder_array_muxed24);
+	main_litedramcore_dfi_p3_we_n <= (~builder_array_muxed25);
+	main_litedramcore_dfi_p3_rddata_en <= builder_array_muxed26;
+	main_litedramcore_dfi_p3_wrdata_en <= builder_array_muxed27;
+	if (main_litedramcore_trrdcon_valid) begin
+		main_litedramcore_trrdcon_count <= 1'd1;
+		if (1'd0) begin
+			main_litedramcore_trrdcon_ready <= 1'd1;
+		end else begin
+			main_litedramcore_trrdcon_ready <= 1'd0;
+		end
+	end else begin
+		if ((~main_litedramcore_trrdcon_ready)) begin
+			main_litedramcore_trrdcon_count <= (main_litedramcore_trrdcon_count - 1'd1);
+			if ((main_litedramcore_trrdcon_count == 1'd1)) begin
+				main_litedramcore_trrdcon_ready <= 1'd1;
+			end
+		end
+	end
+	main_litedramcore_tfawcon_window <= {main_litedramcore_tfawcon_window, main_litedramcore_tfawcon_valid};
+	if ((main_litedramcore_tfawcon_count < 3'd4)) begin
+		if ((main_litedramcore_tfawcon_count == 2'd3)) begin
+			main_litedramcore_tfawcon_ready <= (~main_litedramcore_tfawcon_valid);
+		end else begin
+			main_litedramcore_tfawcon_ready <= 1'd1;
+		end
+	end
+	if (main_litedramcore_tccdcon_valid) begin
+		main_litedramcore_tccdcon_count <= 1'd0;
+		if (1'd1) begin
+			main_litedramcore_tccdcon_ready <= 1'd1;
+		end else begin
+			main_litedramcore_tccdcon_ready <= 1'd0;
+		end
+	end else begin
+		if ((~main_litedramcore_tccdcon_ready)) begin
+			main_litedramcore_tccdcon_count <= (main_litedramcore_tccdcon_count - 1'd1);
+			if ((main_litedramcore_tccdcon_count == 1'd1)) begin
+				main_litedramcore_tccdcon_ready <= 1'd1;
+			end
+		end
+	end
+	if (main_litedramcore_twtrcon_valid) begin
+		main_litedramcore_twtrcon_count <= 3'd4;
+		if (1'd0) begin
+			main_litedramcore_twtrcon_ready <= 1'd1;
+		end else begin
+			main_litedramcore_twtrcon_ready <= 1'd0;
+		end
+	end else begin
+		if ((~main_litedramcore_twtrcon_ready)) begin
+			main_litedramcore_twtrcon_count <= (main_litedramcore_twtrcon_count - 1'd1);
+			if ((main_litedramcore_twtrcon_count == 1'd1)) begin
+				main_litedramcore_twtrcon_ready <= 1'd1;
+			end
+		end
+	end
+	builder_multiplexer_state <= builder_multiplexer_next_state;
+	builder_new_master_wdata_ready0 <= ((((((((1'd0 | ((builder_roundrobin0_grant == 1'd0) & main_litedramcore_interface_bank0_wdata_ready)) | ((builder_roundrobin1_grant == 1'd0) & main_litedramcore_interface_bank1_wdata_ready)) | ((builder_roundrobin2_grant == 1'd0) & main_litedramcore_interface_bank2_wdata_ready)) | ((builder_roundrobin3_grant == 1'd0) & main_litedramcore_interface_bank3_wdata_ready)) | ((builder_roundrobin4_grant == 1'd0) & main_litedramcore_interface_bank4_wdata_ready)) | ((builder_roundrobin5_grant == 1'd0) & main_litedramcore_interface_bank5_wdata_ready)) | ((builder_roundrobin6_grant == 1'd0) & main_litedramcore_interface_bank6_wdata_ready)) | ((builder_roundrobin7_grant == 1'd0) & main_litedramcore_interface_bank7_wdata_ready));
+	builder_new_master_wdata_ready1 <= builder_new_master_wdata_ready0;
+	builder_new_master_rdata_valid0 <= ((((((((1'd0 | ((builder_roundrobin0_grant == 1'd0) & main_litedramcore_interface_bank0_rdata_valid)) | ((builder_roundrobin1_grant == 1'd0) & main_litedramcore_interface_bank1_rdata_valid)) | ((builder_roundrobin2_grant == 1'd0) & main_litedramcore_interface_bank2_rdata_valid)) | ((builder_roundrobin3_grant == 1'd0) & main_litedramcore_interface_bank3_rdata_valid)) | ((builder_roundrobin4_grant == 1'd0) & main_litedramcore_interface_bank4_rdata_valid)) | ((builder_roundrobin5_grant == 1'd0) & main_litedramcore_interface_bank5_rdata_valid)) | ((builder_roundrobin6_grant == 1'd0) & main_litedramcore_interface_bank6_rdata_valid)) | ((builder_roundrobin7_grant == 1'd0) & main_litedramcore_interface_bank7_rdata_valid));
+	builder_new_master_rdata_valid1 <= builder_new_master_rdata_valid0;
+	builder_new_master_rdata_valid2 <= builder_new_master_rdata_valid1;
+	builder_new_master_rdata_valid3 <= builder_new_master_rdata_valid2;
+	builder_new_master_rdata_valid4 <= builder_new_master_rdata_valid3;
+	builder_new_master_rdata_valid5 <= builder_new_master_rdata_valid4;
+	builder_new_master_rdata_valid6 <= builder_new_master_rdata_valid5;
+	builder_new_master_rdata_valid7 <= builder_new_master_rdata_valid6;
+	builder_new_master_rdata_valid8 <= builder_new_master_rdata_valid7;
+	builder_state <= builder_next_state;
+	if (builder_litedramcore_dat_w_next_value_ce0) begin
+		builder_litedramcore_dat_w <= builder_litedramcore_dat_w_next_value0;
+	end
+	if (builder_litedramcore_adr_next_value_ce1) begin
+		builder_litedramcore_adr <= builder_litedramcore_adr_next_value1;
+	end
+	if (builder_litedramcore_we_next_value_ce2) begin
+		builder_litedramcore_we <= builder_litedramcore_we_next_value2;
+	end
+	builder_interface0_bank_bus_dat_r <= 1'd0;
+	if (builder_csrbank0_sel) begin
+		case (builder_interface0_bank_bus_adr[8:0])
+			1'd0: begin
+				builder_interface0_bank_bus_dat_r <= builder_csrbank0_init_done0_w;
+			end
+			1'd1: begin
+				builder_interface0_bank_bus_dat_r <= builder_csrbank0_init_error0_w;
+			end
+		endcase
+	end
+	if (builder_csrbank0_init_done0_re) begin
+		main_init_done_storage <= builder_csrbank0_init_done0_r;
+	end
+	main_init_done_re <= builder_csrbank0_init_done0_re;
+	if (builder_csrbank0_init_error0_re) begin
+		main_init_error_storage <= builder_csrbank0_init_error0_r;
+	end
+	main_init_error_re <= builder_csrbank0_init_error0_re;
+	builder_interface1_bank_bus_dat_r <= 1'd0;
+	if (builder_csrbank1_sel) begin
+		case (builder_interface1_bank_bus_adr[8:0])
+			1'd0: begin
+				builder_interface1_bank_bus_dat_r <= builder_csrbank1_rst0_w;
+			end
+			1'd1: begin
+				builder_interface1_bank_bus_dat_r <= builder_csrbank1_half_sys8x_taps0_w;
+			end
+			2'd2: begin
+				builder_interface1_bank_bus_dat_r <= builder_csrbank1_wlevel_en0_w;
+			end
+			2'd3: begin
+				builder_interface1_bank_bus_dat_r <= main_a7ddrphy_wlevel_strobe_w;
+			end
+			3'd4: begin
+				builder_interface1_bank_bus_dat_r <= builder_csrbank1_dly_sel0_w;
+			end
+			3'd5: begin
+				builder_interface1_bank_bus_dat_r <= main_a7ddrphy_rdly_dq_rst_w;
+			end
+			3'd6: begin
+				builder_interface1_bank_bus_dat_r <= main_a7ddrphy_rdly_dq_inc_w;
+			end
+			3'd7: begin
+				builder_interface1_bank_bus_dat_r <= main_a7ddrphy_rdly_dq_bitslip_rst_w;
+			end
+			4'd8: begin
+				builder_interface1_bank_bus_dat_r <= main_a7ddrphy_rdly_dq_bitslip_w;
+			end
+			4'd9: begin
+				builder_interface1_bank_bus_dat_r <= main_a7ddrphy_wdly_dq_bitslip_rst_w;
+			end
+			4'd10: begin
+				builder_interface1_bank_bus_dat_r <= main_a7ddrphy_wdly_dq_bitslip_w;
+			end
+			4'd11: begin
+				builder_interface1_bank_bus_dat_r <= builder_csrbank1_rdphase0_w;
+			end
+			4'd12: begin
+				builder_interface1_bank_bus_dat_r <= builder_csrbank1_wrphase0_w;
+			end
+		endcase
+	end
+	if (builder_csrbank1_rst0_re) begin
+		main_a7ddrphy_rst_storage <= builder_csrbank1_rst0_r;
+	end
+	main_a7ddrphy_rst_re <= builder_csrbank1_rst0_re;
+	if (builder_csrbank1_half_sys8x_taps0_re) begin
+		main_a7ddrphy_half_sys8x_taps_storage[4:0] <= builder_csrbank1_half_sys8x_taps0_r;
+	end
+	main_a7ddrphy_half_sys8x_taps_re <= builder_csrbank1_half_sys8x_taps0_re;
+	if (builder_csrbank1_wlevel_en0_re) begin
+		main_a7ddrphy_wlevel_en_storage <= builder_csrbank1_wlevel_en0_r;
+	end
+	main_a7ddrphy_wlevel_en_re <= builder_csrbank1_wlevel_en0_re;
+	if (builder_csrbank1_dly_sel0_re) begin
+		main_a7ddrphy_dly_sel_storage[1:0] <= builder_csrbank1_dly_sel0_r;
+	end
+	main_a7ddrphy_dly_sel_re <= builder_csrbank1_dly_sel0_re;
+	if (builder_csrbank1_rdphase0_re) begin
+		main_a7ddrphy_rdphase_storage[1:0] <= builder_csrbank1_rdphase0_r;
+	end
+	main_a7ddrphy_rdphase_re <= builder_csrbank1_rdphase0_re;
+	if (builder_csrbank1_wrphase0_re) begin
+		main_a7ddrphy_wrphase_storage[1:0] <= builder_csrbank1_wrphase0_r;
+	end
+	main_a7ddrphy_wrphase_re <= builder_csrbank1_wrphase0_re;
+	builder_interface2_bank_bus_dat_r <= 1'd0;
+	if (builder_csrbank2_sel) begin
+		case (builder_interface2_bank_bus_adr[8:0])
+			1'd0: begin
+				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_control0_w;
+			end
+			1'd1: begin
+				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_command0_w;
+			end
+			2'd2: begin
+				builder_interface2_bank_bus_dat_r <= main_litedramcore_phaseinjector0_command_issue_w;
+			end
+			2'd3: begin
+				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_address1_w;
+			end
+			3'd4: begin
+				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_address0_w;
+			end
+			3'd5: begin
+				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_baddress0_w;
+			end
+			3'd6: begin
+				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_wrdata3_w;
+			end
+			3'd7: begin
+				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_wrdata2_w;
+			end
+			4'd8: begin
+				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_wrdata1_w;
+			end
+			4'd9: begin
+				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_wrdata0_w;
+			end
+			4'd10: begin
+				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_rddata3_w;
+			end
+			4'd11: begin
+				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_rddata2_w;
+			end
+			4'd12: begin
+				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_rddata1_w;
+			end
+			4'd13: begin
+				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi0_rddata0_w;
+			end
+			4'd14: begin
+				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_command0_w;
+			end
+			4'd15: begin
+				builder_interface2_bank_bus_dat_r <= main_litedramcore_phaseinjector1_command_issue_w;
+			end
+			5'd16: begin
+				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_address1_w;
+			end
+			5'd17: begin
+				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_address0_w;
+			end
+			5'd18: begin
+				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_baddress0_w;
+			end
+			5'd19: begin
+				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_wrdata3_w;
+			end
+			5'd20: begin
+				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_wrdata2_w;
+			end
+			5'd21: begin
+				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_wrdata1_w;
+			end
+			5'd22: begin
+				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_wrdata0_w;
+			end
+			5'd23: begin
+				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_rddata3_w;
+			end
+			5'd24: begin
+				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_rddata2_w;
+			end
+			5'd25: begin
+				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_rddata1_w;
+			end
+			5'd26: begin
+				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi1_rddata0_w;
+			end
+			5'd27: begin
+				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_command0_w;
+			end
+			5'd28: begin
+				builder_interface2_bank_bus_dat_r <= main_litedramcore_phaseinjector2_command_issue_w;
+			end
+			5'd29: begin
+				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_address1_w;
+			end
+			5'd30: begin
+				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_address0_w;
+			end
+			5'd31: begin
+				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_baddress0_w;
+			end
+			6'd32: begin
+				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_wrdata3_w;
+			end
+			6'd33: begin
+				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_wrdata2_w;
+			end
+			6'd34: begin
+				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_wrdata1_w;
+			end
+			6'd35: begin
+				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_wrdata0_w;
+			end
+			6'd36: begin
+				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_rddata3_w;
+			end
+			6'd37: begin
+				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_rddata2_w;
+			end
+			6'd38: begin
+				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_rddata1_w;
+			end
+			6'd39: begin
+				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi2_rddata0_w;
+			end
+			6'd40: begin
+				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_command0_w;
+			end
+			6'd41: begin
+				builder_interface2_bank_bus_dat_r <= main_litedramcore_phaseinjector3_command_issue_w;
+			end
+			6'd42: begin
+				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_address1_w;
+			end
+			6'd43: begin
+				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_address0_w;
+			end
+			6'd44: begin
+				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_baddress0_w;
+			end
+			6'd45: begin
+				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_wrdata3_w;
+			end
+			6'd46: begin
+				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_wrdata2_w;
+			end
+			6'd47: begin
+				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_wrdata1_w;
+			end
+			6'd48: begin
+				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_wrdata0_w;
+			end
+			6'd49: begin
+				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_rddata3_w;
+			end
+			6'd50: begin
+				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_rddata2_w;
+			end
+			6'd51: begin
+				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_rddata1_w;
+			end
+			6'd52: begin
+				builder_interface2_bank_bus_dat_r <= builder_csrbank2_dfii_pi3_rddata0_w;
+			end
+		endcase
+	end
+	if (builder_csrbank2_dfii_control0_re) begin
+		main_litedramcore_storage[3:0] <= builder_csrbank2_dfii_control0_r;
+	end
+	main_litedramcore_re <= builder_csrbank2_dfii_control0_re;
+	if (builder_csrbank2_dfii_pi0_command0_re) begin
+		main_litedramcore_phaseinjector0_command_storage[5:0] <= builder_csrbank2_dfii_pi0_command0_r;
+	end
+	main_litedramcore_phaseinjector0_command_re <= builder_csrbank2_dfii_pi0_command0_re;
+	if (builder_csrbank2_dfii_pi0_address1_re) begin
+		main_litedramcore_phaseinjector0_address_storage[13:8] <= builder_csrbank2_dfii_pi0_address1_r;
+	end
+	if (builder_csrbank2_dfii_pi0_address0_re) begin
+		main_litedramcore_phaseinjector0_address_storage[7:0] <= builder_csrbank2_dfii_pi0_address0_r;
+	end
+	main_litedramcore_phaseinjector0_address_re <= builder_csrbank2_dfii_pi0_address0_re;
+	if (builder_csrbank2_dfii_pi0_baddress0_re) begin
+		main_litedramcore_phaseinjector0_baddress_storage[2:0] <= builder_csrbank2_dfii_pi0_baddress0_r;
+	end
+	main_litedramcore_phaseinjector0_baddress_re <= builder_csrbank2_dfii_pi0_baddress0_re;
+	if (builder_csrbank2_dfii_pi0_wrdata3_re) begin
+		main_litedramcore_phaseinjector0_wrdata_storage[31:24] <= builder_csrbank2_dfii_pi0_wrdata3_r;
+	end
+	if (builder_csrbank2_dfii_pi0_wrdata2_re) begin
+		main_litedramcore_phaseinjector0_wrdata_storage[23:16] <= builder_csrbank2_dfii_pi0_wrdata2_r;
+	end
+	if (builder_csrbank2_dfii_pi0_wrdata1_re) begin
+		main_litedramcore_phaseinjector0_wrdata_storage[15:8] <= builder_csrbank2_dfii_pi0_wrdata1_r;
+	end
+	if (builder_csrbank2_dfii_pi0_wrdata0_re) begin
+		main_litedramcore_phaseinjector0_wrdata_storage[7:0] <= builder_csrbank2_dfii_pi0_wrdata0_r;
+	end
+	main_litedramcore_phaseinjector0_wrdata_re <= builder_csrbank2_dfii_pi0_wrdata0_re;
+	main_litedramcore_phaseinjector0_rddata_re <= builder_csrbank2_dfii_pi0_rddata0_re;
+	if (builder_csrbank2_dfii_pi1_command0_re) begin
+		main_litedramcore_phaseinjector1_command_storage[5:0] <= builder_csrbank2_dfii_pi1_command0_r;
+	end
+	main_litedramcore_phaseinjector1_command_re <= builder_csrbank2_dfii_pi1_command0_re;
+	if (builder_csrbank2_dfii_pi1_address1_re) begin
+		main_litedramcore_phaseinjector1_address_storage[13:8] <= builder_csrbank2_dfii_pi1_address1_r;
+	end
+	if (builder_csrbank2_dfii_pi1_address0_re) begin
+		main_litedramcore_phaseinjector1_address_storage[7:0] <= builder_csrbank2_dfii_pi1_address0_r;
+	end
+	main_litedramcore_phaseinjector1_address_re <= builder_csrbank2_dfii_pi1_address0_re;
+	if (builder_csrbank2_dfii_pi1_baddress0_re) begin
+		main_litedramcore_phaseinjector1_baddress_storage[2:0] <= builder_csrbank2_dfii_pi1_baddress0_r;
+	end
+	main_litedramcore_phaseinjector1_baddress_re <= builder_csrbank2_dfii_pi1_baddress0_re;
+	if (builder_csrbank2_dfii_pi1_wrdata3_re) begin
+		main_litedramcore_phaseinjector1_wrdata_storage[31:24] <= builder_csrbank2_dfii_pi1_wrdata3_r;
+	end
+	if (builder_csrbank2_dfii_pi1_wrdata2_re) begin
+		main_litedramcore_phaseinjector1_wrdata_storage[23:16] <= builder_csrbank2_dfii_pi1_wrdata2_r;
+	end
+	if (builder_csrbank2_dfii_pi1_wrdata1_re) begin
+		main_litedramcore_phaseinjector1_wrdata_storage[15:8] <= builder_csrbank2_dfii_pi1_wrdata1_r;
+	end
+	if (builder_csrbank2_dfii_pi1_wrdata0_re) begin
+		main_litedramcore_phaseinjector1_wrdata_storage[7:0] <= builder_csrbank2_dfii_pi1_wrdata0_r;
+	end
+	main_litedramcore_phaseinjector1_wrdata_re <= builder_csrbank2_dfii_pi1_wrdata0_re;
+	main_litedramcore_phaseinjector1_rddata_re <= builder_csrbank2_dfii_pi1_rddata0_re;
+	if (builder_csrbank2_dfii_pi2_command0_re) begin
+		main_litedramcore_phaseinjector2_command_storage[5:0] <= builder_csrbank2_dfii_pi2_command0_r;
+	end
+	main_litedramcore_phaseinjector2_command_re <= builder_csrbank2_dfii_pi2_command0_re;
+	if (builder_csrbank2_dfii_pi2_address1_re) begin
+		main_litedramcore_phaseinjector2_address_storage[13:8] <= builder_csrbank2_dfii_pi2_address1_r;
+	end
+	if (builder_csrbank2_dfii_pi2_address0_re) begin
+		main_litedramcore_phaseinjector2_address_storage[7:0] <= builder_csrbank2_dfii_pi2_address0_r;
+	end
+	main_litedramcore_phaseinjector2_address_re <= builder_csrbank2_dfii_pi2_address0_re;
+	if (builder_csrbank2_dfii_pi2_baddress0_re) begin
+		main_litedramcore_phaseinjector2_baddress_storage[2:0] <= builder_csrbank2_dfii_pi2_baddress0_r;
+	end
+	main_litedramcore_phaseinjector2_baddress_re <= builder_csrbank2_dfii_pi2_baddress0_re;
+	if (builder_csrbank2_dfii_pi2_wrdata3_re) begin
+		main_litedramcore_phaseinjector2_wrdata_storage[31:24] <= builder_csrbank2_dfii_pi2_wrdata3_r;
+	end
+	if (builder_csrbank2_dfii_pi2_wrdata2_re) begin
+		main_litedramcore_phaseinjector2_wrdata_storage[23:16] <= builder_csrbank2_dfii_pi2_wrdata2_r;
+	end
+	if (builder_csrbank2_dfii_pi2_wrdata1_re) begin
+		main_litedramcore_phaseinjector2_wrdata_storage[15:8] <= builder_csrbank2_dfii_pi2_wrdata1_r;
+	end
+	if (builder_csrbank2_dfii_pi2_wrdata0_re) begin
+		main_litedramcore_phaseinjector2_wrdata_storage[7:0] <= builder_csrbank2_dfii_pi2_wrdata0_r;
+	end
+	main_litedramcore_phaseinjector2_wrdata_re <= builder_csrbank2_dfii_pi2_wrdata0_re;
+	main_litedramcore_phaseinjector2_rddata_re <= builder_csrbank2_dfii_pi2_rddata0_re;
+	if (builder_csrbank2_dfii_pi3_command0_re) begin
+		main_litedramcore_phaseinjector3_command_storage[5:0] <= builder_csrbank2_dfii_pi3_command0_r;
+	end
+	main_litedramcore_phaseinjector3_command_re <= builder_csrbank2_dfii_pi3_command0_re;
+	if (builder_csrbank2_dfii_pi3_address1_re) begin
+		main_litedramcore_phaseinjector3_address_storage[13:8] <= builder_csrbank2_dfii_pi3_address1_r;
+	end
+	if (builder_csrbank2_dfii_pi3_address0_re) begin
+		main_litedramcore_phaseinjector3_address_storage[7:0] <= builder_csrbank2_dfii_pi3_address0_r;
+	end
+	main_litedramcore_phaseinjector3_address_re <= builder_csrbank2_dfii_pi3_address0_re;
+	if (builder_csrbank2_dfii_pi3_baddress0_re) begin
+		main_litedramcore_phaseinjector3_baddress_storage[2:0] <= builder_csrbank2_dfii_pi3_baddress0_r;
+	end
+	main_litedramcore_phaseinjector3_baddress_re <= builder_csrbank2_dfii_pi3_baddress0_re;
+	if (builder_csrbank2_dfii_pi3_wrdata3_re) begin
+		main_litedramcore_phaseinjector3_wrdata_storage[31:24] <= builder_csrbank2_dfii_pi3_wrdata3_r;
+	end
+	if (builder_csrbank2_dfii_pi3_wrdata2_re) begin
+		main_litedramcore_phaseinjector3_wrdata_storage[23:16] <= builder_csrbank2_dfii_pi3_wrdata2_r;
+	end
+	if (builder_csrbank2_dfii_pi3_wrdata1_re) begin
+		main_litedramcore_phaseinjector3_wrdata_storage[15:8] <= builder_csrbank2_dfii_pi3_wrdata1_r;
+	end
+	if (builder_csrbank2_dfii_pi3_wrdata0_re) begin
+		main_litedramcore_phaseinjector3_wrdata_storage[7:0] <= builder_csrbank2_dfii_pi3_wrdata0_r;
+	end
+	main_litedramcore_phaseinjector3_wrdata_re <= builder_csrbank2_dfii_pi3_wrdata0_re;
+	main_litedramcore_phaseinjector3_rddata_re <= builder_csrbank2_dfii_pi3_rddata0_re;
+	if (sys_rst) begin
+		main_a7ddrphy_rst_storage <= 1'd0;
+		main_a7ddrphy_rst_re <= 1'd0;
+		main_a7ddrphy_half_sys8x_taps_storage <= 5'd8;
+		main_a7ddrphy_half_sys8x_taps_re <= 1'd0;
+		main_a7ddrphy_wlevel_en_storage <= 1'd0;
+		main_a7ddrphy_wlevel_en_re <= 1'd0;
+		main_a7ddrphy_dly_sel_storage <= 2'd0;
+		main_a7ddrphy_dly_sel_re <= 1'd0;
+		main_a7ddrphy_rdphase_storage <= 2'd2;
+		main_a7ddrphy_rdphase_re <= 1'd0;
+		main_a7ddrphy_wrphase_storage <= 2'd3;
+		main_a7ddrphy_wrphase_re <= 1'd0;
+		main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 <= 1'd0;
+		main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 <= 1'd0;
+		main_a7ddrphy_dqspattern_o1 <= 8'd0;
+		main_a7ddrphy_bitslip0_value0 <= 3'd7;
+		main_a7ddrphy_bitslip1_value0 <= 3'd7;
+		main_a7ddrphy_bitslip0_value1 <= 3'd7;
+		main_a7ddrphy_bitslip1_value1 <= 3'd7;
+		main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 <= 1'd0;
+		main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 <= 1'd0;
+		main_a7ddrphy_bitslip0_value2 <= 3'd7;
+		main_a7ddrphy_bitslip0_value3 <= 3'd7;
+		main_a7ddrphy_bitslip1_value2 <= 3'd7;
+		main_a7ddrphy_bitslip1_value3 <= 3'd7;
+		main_a7ddrphy_bitslip2_value0 <= 3'd7;
+		main_a7ddrphy_bitslip2_value1 <= 3'd7;
+		main_a7ddrphy_bitslip3_value0 <= 3'd7;
+		main_a7ddrphy_bitslip3_value1 <= 3'd7;
+		main_a7ddrphy_bitslip4_value0 <= 3'd7;
+		main_a7ddrphy_bitslip4_value1 <= 3'd7;
+		main_a7ddrphy_bitslip5_value0 <= 3'd7;
+		main_a7ddrphy_bitslip5_value1 <= 3'd7;
+		main_a7ddrphy_bitslip6_value0 <= 3'd7;
+		main_a7ddrphy_bitslip6_value1 <= 3'd7;
+		main_a7ddrphy_bitslip7_value0 <= 3'd7;
+		main_a7ddrphy_bitslip7_value1 <= 3'd7;
+		main_a7ddrphy_bitslip8_value0 <= 3'd7;
+		main_a7ddrphy_bitslip8_value1 <= 3'd7;
+		main_a7ddrphy_bitslip9_value0 <= 3'd7;
+		main_a7ddrphy_bitslip9_value1 <= 3'd7;
+		main_a7ddrphy_bitslip10_value0 <= 3'd7;
+		main_a7ddrphy_bitslip10_value1 <= 3'd7;
+		main_a7ddrphy_bitslip11_value0 <= 3'd7;
+		main_a7ddrphy_bitslip11_value1 <= 3'd7;
+		main_a7ddrphy_bitslip12_value0 <= 3'd7;
+		main_a7ddrphy_bitslip12_value1 <= 3'd7;
+		main_a7ddrphy_bitslip13_value0 <= 3'd7;
+		main_a7ddrphy_bitslip13_value1 <= 3'd7;
+		main_a7ddrphy_bitslip14_value0 <= 3'd7;
+		main_a7ddrphy_bitslip14_value1 <= 3'd7;
+		main_a7ddrphy_bitslip15_value0 <= 3'd7;
+		main_a7ddrphy_bitslip15_value1 <= 3'd7;
+		main_a7ddrphy_rddata_en_tappeddelayline0 <= 1'd0;
+		main_a7ddrphy_rddata_en_tappeddelayline1 <= 1'd0;
+		main_a7ddrphy_rddata_en_tappeddelayline2 <= 1'd0;
+		main_a7ddrphy_rddata_en_tappeddelayline3 <= 1'd0;
+		main_a7ddrphy_rddata_en_tappeddelayline4 <= 1'd0;
+		main_a7ddrphy_rddata_en_tappeddelayline5 <= 1'd0;
+		main_a7ddrphy_rddata_en_tappeddelayline6 <= 1'd0;
+		main_a7ddrphy_rddata_en_tappeddelayline7 <= 1'd0;
+		main_a7ddrphy_wrdata_en_tappeddelayline0 <= 1'd0;
+		main_a7ddrphy_wrdata_en_tappeddelayline1 <= 1'd0;
+		main_a7ddrphy_wrdata_en_tappeddelayline2 <= 1'd0;
+		main_litedramcore_storage <= 4'd1;
+		main_litedramcore_re <= 1'd0;
+		main_litedramcore_phaseinjector0_command_storage <= 6'd0;
+		main_litedramcore_phaseinjector0_command_re <= 1'd0;
+		main_litedramcore_phaseinjector0_address_re <= 1'd0;
+		main_litedramcore_phaseinjector0_baddress_re <= 1'd0;
+		main_litedramcore_phaseinjector0_wrdata_re <= 1'd0;
+		main_litedramcore_phaseinjector0_rddata_status <= 32'd0;
+		main_litedramcore_phaseinjector0_rddata_re <= 1'd0;
+		main_litedramcore_phaseinjector1_command_storage <= 6'd0;
+		main_litedramcore_phaseinjector1_command_re <= 1'd0;
+		main_litedramcore_phaseinjector1_address_re <= 1'd0;
+		main_litedramcore_phaseinjector1_baddress_re <= 1'd0;
+		main_litedramcore_phaseinjector1_wrdata_re <= 1'd0;
+		main_litedramcore_phaseinjector1_rddata_status <= 32'd0;
+		main_litedramcore_phaseinjector1_rddata_re <= 1'd0;
+		main_litedramcore_phaseinjector2_command_storage <= 6'd0;
+		main_litedramcore_phaseinjector2_command_re <= 1'd0;
+		main_litedramcore_phaseinjector2_address_re <= 1'd0;
+		main_litedramcore_phaseinjector2_baddress_re <= 1'd0;
+		main_litedramcore_phaseinjector2_wrdata_re <= 1'd0;
+		main_litedramcore_phaseinjector2_rddata_status <= 32'd0;
+		main_litedramcore_phaseinjector2_rddata_re <= 1'd0;
+		main_litedramcore_phaseinjector3_command_storage <= 6'd0;
+		main_litedramcore_phaseinjector3_command_re <= 1'd0;
+		main_litedramcore_phaseinjector3_address_re <= 1'd0;
+		main_litedramcore_phaseinjector3_baddress_re <= 1'd0;
+		main_litedramcore_phaseinjector3_wrdata_re <= 1'd0;
+		main_litedramcore_phaseinjector3_rddata_status <= 32'd0;
+		main_litedramcore_phaseinjector3_rddata_re <= 1'd0;
+		main_litedramcore_dfi_p0_address <= 14'd0;
+		main_litedramcore_dfi_p0_bank <= 3'd0;
+		main_litedramcore_dfi_p0_cas_n <= 1'd1;
+		main_litedramcore_dfi_p0_cs_n <= 1'd1;
+		main_litedramcore_dfi_p0_ras_n <= 1'd1;
+		main_litedramcore_dfi_p0_we_n <= 1'd1;
+		main_litedramcore_dfi_p0_wrdata_en <= 1'd0;
+		main_litedramcore_dfi_p0_rddata_en <= 1'd0;
+		main_litedramcore_dfi_p1_address <= 14'd0;
+		main_litedramcore_dfi_p1_bank <= 3'd0;
+		main_litedramcore_dfi_p1_cas_n <= 1'd1;
+		main_litedramcore_dfi_p1_cs_n <= 1'd1;
+		main_litedramcore_dfi_p1_ras_n <= 1'd1;
+		main_litedramcore_dfi_p1_we_n <= 1'd1;
+		main_litedramcore_dfi_p1_wrdata_en <= 1'd0;
+		main_litedramcore_dfi_p1_rddata_en <= 1'd0;
+		main_litedramcore_dfi_p2_address <= 14'd0;
+		main_litedramcore_dfi_p2_bank <= 3'd0;
+		main_litedramcore_dfi_p2_cas_n <= 1'd1;
+		main_litedramcore_dfi_p2_cs_n <= 1'd1;
+		main_litedramcore_dfi_p2_ras_n <= 1'd1;
+		main_litedramcore_dfi_p2_we_n <= 1'd1;
+		main_litedramcore_dfi_p2_wrdata_en <= 1'd0;
+		main_litedramcore_dfi_p2_rddata_en <= 1'd0;
+		main_litedramcore_dfi_p3_address <= 14'd0;
+		main_litedramcore_dfi_p3_bank <= 3'd0;
+		main_litedramcore_dfi_p3_cas_n <= 1'd1;
+		main_litedramcore_dfi_p3_cs_n <= 1'd1;
+		main_litedramcore_dfi_p3_ras_n <= 1'd1;
+		main_litedramcore_dfi_p3_we_n <= 1'd1;
+		main_litedramcore_dfi_p3_wrdata_en <= 1'd0;
+		main_litedramcore_dfi_p3_rddata_en <= 1'd0;
+		main_litedramcore_cmd_payload_a <= 14'd0;
+		main_litedramcore_cmd_payload_ba <= 3'd0;
+		main_litedramcore_cmd_payload_cas <= 1'd0;
+		main_litedramcore_cmd_payload_ras <= 1'd0;
+		main_litedramcore_cmd_payload_we <= 1'd0;
+		main_litedramcore_timer_count1 <= 10'd781;
+		main_litedramcore_postponer_req_o <= 1'd0;
+		main_litedramcore_postponer_count <= 1'd0;
+		main_litedramcore_sequencer_done1 <= 1'd0;
+		main_litedramcore_sequencer_counter <= 6'd0;
+		main_litedramcore_sequencer_count <= 1'd0;
+		main_litedramcore_zqcs_timer_count1 <= 27'd99999999;
+		main_litedramcore_zqcs_executer_done <= 1'd0;
+		main_litedramcore_zqcs_executer_counter <= 5'd0;
+		main_litedramcore_bankmachine0_cmd_buffer_lookahead_level <= 5'd0;
+		main_litedramcore_bankmachine0_cmd_buffer_lookahead_produce <= 4'd0;
+		main_litedramcore_bankmachine0_cmd_buffer_lookahead_consume <= 4'd0;
+		main_litedramcore_bankmachine0_cmd_buffer_source_valid <= 1'd0;
+		main_litedramcore_bankmachine0_cmd_buffer_source_payload_we <= 1'd0;
+		main_litedramcore_bankmachine0_cmd_buffer_source_payload_addr <= 21'd0;
+		main_litedramcore_bankmachine0_row <= 14'd0;
+		main_litedramcore_bankmachine0_row_opened <= 1'd0;
+		main_litedramcore_bankmachine0_twtpcon_ready <= 1'd0;
+		main_litedramcore_bankmachine0_twtpcon_count <= 3'd0;
+		main_litedramcore_bankmachine0_trccon_ready <= 1'd0;
+		main_litedramcore_bankmachine0_trccon_count <= 3'd0;
+		main_litedramcore_bankmachine0_trascon_ready <= 1'd0;
+		main_litedramcore_bankmachine0_trascon_count <= 3'd0;
+		main_litedramcore_bankmachine1_cmd_buffer_lookahead_level <= 5'd0;
+		main_litedramcore_bankmachine1_cmd_buffer_lookahead_produce <= 4'd0;
+		main_litedramcore_bankmachine1_cmd_buffer_lookahead_consume <= 4'd0;
+		main_litedramcore_bankmachine1_cmd_buffer_source_valid <= 1'd0;
+		main_litedramcore_bankmachine1_cmd_buffer_source_payload_we <= 1'd0;
+		main_litedramcore_bankmachine1_cmd_buffer_source_payload_addr <= 21'd0;
+		main_litedramcore_bankmachine1_row <= 14'd0;
+		main_litedramcore_bankmachine1_row_opened <= 1'd0;
+		main_litedramcore_bankmachine1_twtpcon_ready <= 1'd0;
+		main_litedramcore_bankmachine1_twtpcon_count <= 3'd0;
+		main_litedramcore_bankmachine1_trccon_ready <= 1'd0;
+		main_litedramcore_bankmachine1_trccon_count <= 3'd0;
+		main_litedramcore_bankmachine1_trascon_ready <= 1'd0;
+		main_litedramcore_bankmachine1_trascon_count <= 3'd0;
+		main_litedramcore_bankmachine2_cmd_buffer_lookahead_level <= 5'd0;
+		main_litedramcore_bankmachine2_cmd_buffer_lookahead_produce <= 4'd0;
+		main_litedramcore_bankmachine2_cmd_buffer_lookahead_consume <= 4'd0;
+		main_litedramcore_bankmachine2_cmd_buffer_source_valid <= 1'd0;
+		main_litedramcore_bankmachine2_cmd_buffer_source_payload_we <= 1'd0;
+		main_litedramcore_bankmachine2_cmd_buffer_source_payload_addr <= 21'd0;
+		main_litedramcore_bankmachine2_row <= 14'd0;
+		main_litedramcore_bankmachine2_row_opened <= 1'd0;
+		main_litedramcore_bankmachine2_twtpcon_ready <= 1'd0;
+		main_litedramcore_bankmachine2_twtpcon_count <= 3'd0;
+		main_litedramcore_bankmachine2_trccon_ready <= 1'd0;
+		main_litedramcore_bankmachine2_trccon_count <= 3'd0;
+		main_litedramcore_bankmachine2_trascon_ready <= 1'd0;
+		main_litedramcore_bankmachine2_trascon_count <= 3'd0;
+		main_litedramcore_bankmachine3_cmd_buffer_lookahead_level <= 5'd0;
+		main_litedramcore_bankmachine3_cmd_buffer_lookahead_produce <= 4'd0;
+		main_litedramcore_bankmachine3_cmd_buffer_lookahead_consume <= 4'd0;
+		main_litedramcore_bankmachine3_cmd_buffer_source_valid <= 1'd0;
+		main_litedramcore_bankmachine3_cmd_buffer_source_payload_we <= 1'd0;
+		main_litedramcore_bankmachine3_cmd_buffer_source_payload_addr <= 21'd0;
+		main_litedramcore_bankmachine3_row <= 14'd0;
+		main_litedramcore_bankmachine3_row_opened <= 1'd0;
+		main_litedramcore_bankmachine3_twtpcon_ready <= 1'd0;
+		main_litedramcore_bankmachine3_twtpcon_count <= 3'd0;
+		main_litedramcore_bankmachine3_trccon_ready <= 1'd0;
+		main_litedramcore_bankmachine3_trccon_count <= 3'd0;
+		main_litedramcore_bankmachine3_trascon_ready <= 1'd0;
+		main_litedramcore_bankmachine3_trascon_count <= 3'd0;
+		main_litedramcore_bankmachine4_cmd_buffer_lookahead_level <= 5'd0;
+		main_litedramcore_bankmachine4_cmd_buffer_lookahead_produce <= 4'd0;
+		main_litedramcore_bankmachine4_cmd_buffer_lookahead_consume <= 4'd0;
+		main_litedramcore_bankmachine4_cmd_buffer_source_valid <= 1'd0;
+		main_litedramcore_bankmachine4_cmd_buffer_source_payload_we <= 1'd0;
+		main_litedramcore_bankmachine4_cmd_buffer_source_payload_addr <= 21'd0;
+		main_litedramcore_bankmachine4_row <= 14'd0;
+		main_litedramcore_bankmachine4_row_opened <= 1'd0;
+		main_litedramcore_bankmachine4_twtpcon_ready <= 1'd0;
+		main_litedramcore_bankmachine4_twtpcon_count <= 3'd0;
+		main_litedramcore_bankmachine4_trccon_ready <= 1'd0;
+		main_litedramcore_bankmachine4_trccon_count <= 3'd0;
+		main_litedramcore_bankmachine4_trascon_ready <= 1'd0;
+		main_litedramcore_bankmachine4_trascon_count <= 3'd0;
+		main_litedramcore_bankmachine5_cmd_buffer_lookahead_level <= 5'd0;
+		main_litedramcore_bankmachine5_cmd_buffer_lookahead_produce <= 4'd0;
+		main_litedramcore_bankmachine5_cmd_buffer_lookahead_consume <= 4'd0;
+		main_litedramcore_bankmachine5_cmd_buffer_source_valid <= 1'd0;
+		main_litedramcore_bankmachine5_cmd_buffer_source_payload_we <= 1'd0;
+		main_litedramcore_bankmachine5_cmd_buffer_source_payload_addr <= 21'd0;
+		main_litedramcore_bankmachine5_row <= 14'd0;
+		main_litedramcore_bankmachine5_row_opened <= 1'd0;
+		main_litedramcore_bankmachine5_twtpcon_ready <= 1'd0;
+		main_litedramcore_bankmachine5_twtpcon_count <= 3'd0;
+		main_litedramcore_bankmachine5_trccon_ready <= 1'd0;
+		main_litedramcore_bankmachine5_trccon_count <= 3'd0;
+		main_litedramcore_bankmachine5_trascon_ready <= 1'd0;
+		main_litedramcore_bankmachine5_trascon_count <= 3'd0;
+		main_litedramcore_bankmachine6_cmd_buffer_lookahead_level <= 5'd0;
+		main_litedramcore_bankmachine6_cmd_buffer_lookahead_produce <= 4'd0;
+		main_litedramcore_bankmachine6_cmd_buffer_lookahead_consume <= 4'd0;
+		main_litedramcore_bankmachine6_cmd_buffer_source_valid <= 1'd0;
+		main_litedramcore_bankmachine6_cmd_buffer_source_payload_we <= 1'd0;
+		main_litedramcore_bankmachine6_cmd_buffer_source_payload_addr <= 21'd0;
+		main_litedramcore_bankmachine6_row <= 14'd0;
+		main_litedramcore_bankmachine6_row_opened <= 1'd0;
+		main_litedramcore_bankmachine6_twtpcon_ready <= 1'd0;
+		main_litedramcore_bankmachine6_twtpcon_count <= 3'd0;
+		main_litedramcore_bankmachine6_trccon_ready <= 1'd0;
+		main_litedramcore_bankmachine6_trccon_count <= 3'd0;
+		main_litedramcore_bankmachine6_trascon_ready <= 1'd0;
+		main_litedramcore_bankmachine6_trascon_count <= 3'd0;
+		main_litedramcore_bankmachine7_cmd_buffer_lookahead_level <= 5'd0;
+		main_litedramcore_bankmachine7_cmd_buffer_lookahead_produce <= 4'd0;
+		main_litedramcore_bankmachine7_cmd_buffer_lookahead_consume <= 4'd0;
+		main_litedramcore_bankmachine7_cmd_buffer_source_valid <= 1'd0;
+		main_litedramcore_bankmachine7_cmd_buffer_source_payload_we <= 1'd0;
+		main_litedramcore_bankmachine7_cmd_buffer_source_payload_addr <= 21'd0;
+		main_litedramcore_bankmachine7_row <= 14'd0;
+		main_litedramcore_bankmachine7_row_opened <= 1'd0;
+		main_litedramcore_bankmachine7_twtpcon_ready <= 1'd0;
+		main_litedramcore_bankmachine7_twtpcon_count <= 3'd0;
+		main_litedramcore_bankmachine7_trccon_ready <= 1'd0;
+		main_litedramcore_bankmachine7_trccon_count <= 3'd0;
+		main_litedramcore_bankmachine7_trascon_ready <= 1'd0;
+		main_litedramcore_bankmachine7_trascon_count <= 3'd0;
+		main_litedramcore_choose_cmd_grant <= 3'd0;
+		main_litedramcore_choose_req_grant <= 3'd0;
+		main_litedramcore_trrdcon_ready <= 1'd0;
+		main_litedramcore_trrdcon_count <= 1'd0;
+		main_litedramcore_tfawcon_ready <= 1'd1;
+		main_litedramcore_tfawcon_window <= 5'd0;
+		main_litedramcore_tccdcon_ready <= 1'd0;
+		main_litedramcore_tccdcon_count <= 1'd0;
+		main_litedramcore_twtrcon_ready <= 1'd0;
+		main_litedramcore_twtrcon_count <= 3'd0;
+		main_litedramcore_time0 <= 5'd0;
+		main_litedramcore_time1 <= 4'd0;
+		main_init_done_storage <= 1'd0;
+		main_init_done_re <= 1'd0;
+		main_init_error_storage <= 1'd0;
+		main_init_error_re <= 1'd0;
+		builder_refresher_state <= 2'd0;
+		builder_bankmachine0_state <= 4'd0;
+		builder_bankmachine1_state <= 4'd0;
+		builder_bankmachine2_state <= 4'd0;
+		builder_bankmachine3_state <= 4'd0;
+		builder_bankmachine4_state <= 4'd0;
+		builder_bankmachine5_state <= 4'd0;
+		builder_bankmachine6_state <= 4'd0;
+		builder_bankmachine7_state <= 4'd0;
+		builder_multiplexer_state <= 4'd0;
+		builder_new_master_wdata_ready0 <= 1'd0;
+		builder_new_master_wdata_ready1 <= 1'd0;
+		builder_new_master_rdata_valid0 <= 1'd0;
+		builder_new_master_rdata_valid1 <= 1'd0;
+		builder_new_master_rdata_valid2 <= 1'd0;
+		builder_new_master_rdata_valid3 <= 1'd0;
+		builder_new_master_rdata_valid4 <= 1'd0;
+		builder_new_master_rdata_valid5 <= 1'd0;
+		builder_new_master_rdata_valid6 <= 1'd0;
+		builder_new_master_rdata_valid7 <= 1'd0;
+		builder_new_master_rdata_valid8 <= 1'd0;
+		builder_litedramcore_we <= 1'd0;
+		builder_state <= 2'd0;
+	end
+end
+
+BUFG BUFG(
+	.I(main_clkout0),
+	.O(main_clkout_buf0)
+);
+
+BUFG BUFG_1(
+	.I(main_clkout1),
+	.O(main_clkout_buf1)
+);
+
+BUFG BUFG_2(
+	.I(main_clkout2),
+	.O(main_clkout_buf2)
+);
+
+BUFG BUFG_3(
+	.I(main_clkout3),
+	.O(main_clkout_buf3)
+);
+
+IDELAYCTRL IDELAYCTRL(
+	.REFCLK(iodelay_clk),
+	.RST(main_ic_reset)
+);
+
+OSERDESE2 #(
+	.DATA_RATE_OQ("DDR"),
+	.DATA_RATE_TQ("BUF"),
+	.DATA_WIDTH(4'd8),
+	.SERDES_MODE("MASTER"),
+	.TRISTATE_WIDTH(1'd1)
+) OSERDESE2 (
+	.CLK(sys4x_clk),
+	.CLKDIV(sys_clk),
+	.D1(1'd0),
+	.D2(1'd1),
+	.D3(1'd0),
+	.D4(1'd1),
+	.D5(1'd0),
+	.D6(1'd1),
+	.D7(1'd0),
+	.D8(1'd1),
+	.OCE(1'd1),
+	.RST((sys_rst | main_a7ddrphy_rst_storage)),
+	.OQ(main_a7ddrphy_sd_clk_se_nodelay)
+);
+
+OBUFDS OBUFDS(
+	.I(main_a7ddrphy_sd_clk_se_nodelay),
+	.O(ddram_clk_p),
+	.OB(ddram_clk_n)
+);
+
+OSERDESE2 #(
+	.DATA_RATE_OQ("DDR"),
+	.DATA_RATE_TQ("BUF"),
+	.DATA_WIDTH(4'd8),
+	.SERDES_MODE("MASTER"),
+	.TRISTATE_WIDTH(1'd1)
+) OSERDESE2_1 (
+	.CLK(sys4x_clk),
+	.CLKDIV(sys_clk),
+	.D1(main_a7ddrphy_dfi_p0_reset_n),
+	.D2(main_a7ddrphy_dfi_p0_reset_n),
+	.D3(main_a7ddrphy_dfi_p1_reset_n),
+	.D4(main_a7ddrphy_dfi_p1_reset_n),
+	.D5(main_a7ddrphy_dfi_p2_reset_n),
+	.D6(main_a7ddrphy_dfi_p2_reset_n),
+	.D7(main_a7ddrphy_dfi_p3_reset_n),
+	.D8(main_a7ddrphy_dfi_p3_reset_n),
+	.OCE(1'd1),
+	.RST((sys_rst | main_a7ddrphy_rst_storage)),
+	.OQ(ddram_reset_n)
+);
+
+OSERDESE2 #(
+	.DATA_RATE_OQ("DDR"),
+	.DATA_RATE_TQ("BUF"),
+	.DATA_WIDTH(4'd8),
+	.SERDES_MODE("MASTER"),
+	.TRISTATE_WIDTH(1'd1)
+) OSERDESE2_2 (
+	.CLK(sys4x_clk),
+	.CLKDIV(sys_clk),
+	.D1(main_a7ddrphy_dfi_p0_cs_n),
+	.D2(main_a7ddrphy_dfi_p0_cs_n),
+	.D3(main_a7ddrphy_dfi_p1_cs_n),
+	.D4(main_a7ddrphy_dfi_p1_cs_n),
+	.D5(main_a7ddrphy_dfi_p2_cs_n),
+	.D6(main_a7ddrphy_dfi_p2_cs_n),
+	.D7(main_a7ddrphy_dfi_p3_cs_n),
+	.D8(main_a7ddrphy_dfi_p3_cs_n),
+	.OCE(1'd1),
+	.RST((sys_rst | main_a7ddrphy_rst_storage)),
+	.OQ(ddram_cs_n)
+);
+
+OSERDESE2 #(
+	.DATA_RATE_OQ("DDR"),
+	.DATA_RATE_TQ("BUF"),
+	.DATA_WIDTH(4'd8),
+	.SERDES_MODE("MASTER"),
+	.TRISTATE_WIDTH(1'd1)
+) OSERDESE2_3 (
+	.CLK(sys4x_clk),
+	.CLKDIV(sys_clk),
+	.D1(main_a7ddrphy_dfi_p0_address[0]),
+	.D2(main_a7ddrphy_dfi_p0_address[0]),
+	.D3(main_a7ddrphy_dfi_p1_address[0]),
+	.D4(main_a7ddrphy_dfi_p1_address[0]),
+	.D5(main_a7ddrphy_dfi_p2_address[0]),
+	.D6(main_a7ddrphy_dfi_p2_address[0]),
+	.D7(main_a7ddrphy_dfi_p3_address[0]),
+	.D8(main_a7ddrphy_dfi_p3_address[0]),
+	.OCE(1'd1),
+	.RST((sys_rst | main_a7ddrphy_rst_storage)),
+	.OQ(ddram_a[0])
+);
+
+OSERDESE2 #(
+	.DATA_RATE_OQ("DDR"),
+	.DATA_RATE_TQ("BUF"),
+	.DATA_WIDTH(4'd8),
+	.SERDES_MODE("MASTER"),
+	.TRISTATE_WIDTH(1'd1)
+) OSERDESE2_4 (
+	.CLK(sys4x_clk),
+	.CLKDIV(sys_clk),
+	.D1(main_a7ddrphy_dfi_p0_address[1]),
+	.D2(main_a7ddrphy_dfi_p0_address[1]),
+	.D3(main_a7ddrphy_dfi_p1_address[1]),
+	.D4(main_a7ddrphy_dfi_p1_address[1]),
+	.D5(main_a7ddrphy_dfi_p2_address[1]),
+	.D6(main_a7ddrphy_dfi_p2_address[1]),
+	.D7(main_a7ddrphy_dfi_p3_address[1]),
+	.D8(main_a7ddrphy_dfi_p3_address[1]),
+	.OCE(1'd1),
+	.RST((sys_rst | main_a7ddrphy_rst_storage)),
+	.OQ(ddram_a[1])
+);
+
+OSERDESE2 #(
+	.DATA_RATE_OQ("DDR"),
+	.DATA_RATE_TQ("BUF"),
+	.DATA_WIDTH(4'd8),
+	.SERDES_MODE("MASTER"),
+	.TRISTATE_WIDTH(1'd1)
+) OSERDESE2_5 (
+	.CLK(sys4x_clk),
+	.CLKDIV(sys_clk),
+	.D1(main_a7ddrphy_dfi_p0_address[2]),
+	.D2(main_a7ddrphy_dfi_p0_address[2]),
+	.D3(main_a7ddrphy_dfi_p1_address[2]),
+	.D4(main_a7ddrphy_dfi_p1_address[2]),
+	.D5(main_a7ddrphy_dfi_p2_address[2]),
+	.D6(main_a7ddrphy_dfi_p2_address[2]),
+	.D7(main_a7ddrphy_dfi_p3_address[2]),
+	.D8(main_a7ddrphy_dfi_p3_address[2]),
+	.OCE(1'd1),
+	.RST((sys_rst | main_a7ddrphy_rst_storage)),
+	.OQ(ddram_a[2])
+);
+
+OSERDESE2 #(
+	.DATA_RATE_OQ("DDR"),
+	.DATA_RATE_TQ("BUF"),
+	.DATA_WIDTH(4'd8),
+	.SERDES_MODE("MASTER"),
+	.TRISTATE_WIDTH(1'd1)
+) OSERDESE2_6 (
+	.CLK(sys4x_clk),
+	.CLKDIV(sys_clk),
+	.D1(main_a7ddrphy_dfi_p0_address[3]),
+	.D2(main_a7ddrphy_dfi_p0_address[3]),
+	.D3(main_a7ddrphy_dfi_p1_address[3]),
+	.D4(main_a7ddrphy_dfi_p1_address[3]),
+	.D5(main_a7ddrphy_dfi_p2_address[3]),
+	.D6(main_a7ddrphy_dfi_p2_address[3]),
+	.D7(main_a7ddrphy_dfi_p3_address[3]),
+	.D8(main_a7ddrphy_dfi_p3_address[3]),
+	.OCE(1'd1),
+	.RST((sys_rst | main_a7ddrphy_rst_storage)),
+	.OQ(ddram_a[3])
+);
+
+OSERDESE2 #(
+	.DATA_RATE_OQ("DDR"),
+	.DATA_RATE_TQ("BUF"),
+	.DATA_WIDTH(4'd8),
+	.SERDES_MODE("MASTER"),
+	.TRISTATE_WIDTH(1'd1)
+) OSERDESE2_7 (
+	.CLK(sys4x_clk),
+	.CLKDIV(sys_clk),
+	.D1(main_a7ddrphy_dfi_p0_address[4]),
+	.D2(main_a7ddrphy_dfi_p0_address[4]),
+	.D3(main_a7ddrphy_dfi_p1_address[4]),
+	.D4(main_a7ddrphy_dfi_p1_address[4]),
+	.D5(main_a7ddrphy_dfi_p2_address[4]),
+	.D6(main_a7ddrphy_dfi_p2_address[4]),
+	.D7(main_a7ddrphy_dfi_p3_address[4]),
+	.D8(main_a7ddrphy_dfi_p3_address[4]),
+	.OCE(1'd1),
+	.RST((sys_rst | main_a7ddrphy_rst_storage)),
+	.OQ(ddram_a[4])
+);
+
+OSERDESE2 #(
+	.DATA_RATE_OQ("DDR"),
+	.DATA_RATE_TQ("BUF"),
+	.DATA_WIDTH(4'd8),
+	.SERDES_MODE("MASTER"),
+	.TRISTATE_WIDTH(1'd1)
+) OSERDESE2_8 (
+	.CLK(sys4x_clk),
+	.CLKDIV(sys_clk),
+	.D1(main_a7ddrphy_dfi_p0_address[5]),
+	.D2(main_a7ddrphy_dfi_p0_address[5]),
+	.D3(main_a7ddrphy_dfi_p1_address[5]),
+	.D4(main_a7ddrphy_dfi_p1_address[5]),
+	.D5(main_a7ddrphy_dfi_p2_address[5]),
+	.D6(main_a7ddrphy_dfi_p2_address[5]),
+	.D7(main_a7ddrphy_dfi_p3_address[5]),
+	.D8(main_a7ddrphy_dfi_p3_address[5]),
+	.OCE(1'd1),
+	.RST((sys_rst | main_a7ddrphy_rst_storage)),
+	.OQ(ddram_a[5])
+);
+
+OSERDESE2 #(
+	.DATA_RATE_OQ("DDR"),
+	.DATA_RATE_TQ("BUF"),
+	.DATA_WIDTH(4'd8),
+	.SERDES_MODE("MASTER"),
+	.TRISTATE_WIDTH(1'd1)
+) OSERDESE2_9 (
+	.CLK(sys4x_clk),
+	.CLKDIV(sys_clk),
+	.D1(main_a7ddrphy_dfi_p0_address[6]),
+	.D2(main_a7ddrphy_dfi_p0_address[6]),
+	.D3(main_a7ddrphy_dfi_p1_address[6]),
+	.D4(main_a7ddrphy_dfi_p1_address[6]),
+	.D5(main_a7ddrphy_dfi_p2_address[6]),
+	.D6(main_a7ddrphy_dfi_p2_address[6]),
+	.D7(main_a7ddrphy_dfi_p3_address[6]),
+	.D8(main_a7ddrphy_dfi_p3_address[6]),
+	.OCE(1'd1),
+	.RST((sys_rst | main_a7ddrphy_rst_storage)),
+	.OQ(ddram_a[6])
+);
+
+OSERDESE2 #(
+	.DATA_RATE_OQ("DDR"),
+	.DATA_RATE_TQ("BUF"),
+	.DATA_WIDTH(4'd8),
+	.SERDES_MODE("MASTER"),
+	.TRISTATE_WIDTH(1'd1)
+) OSERDESE2_10 (
+	.CLK(sys4x_clk),
+	.CLKDIV(sys_clk),
+	.D1(main_a7ddrphy_dfi_p0_address[7]),
+	.D2(main_a7ddrphy_dfi_p0_address[7]),
+	.D3(main_a7ddrphy_dfi_p1_address[7]),
+	.D4(main_a7ddrphy_dfi_p1_address[7]),
+	.D5(main_a7ddrphy_dfi_p2_address[7]),
+	.D6(main_a7ddrphy_dfi_p2_address[7]),
+	.D7(main_a7ddrphy_dfi_p3_address[7]),
+	.D8(main_a7ddrphy_dfi_p3_address[7]),
+	.OCE(1'd1),
+	.RST((sys_rst | main_a7ddrphy_rst_storage)),
+	.OQ(ddram_a[7])
+);
+
+OSERDESE2 #(
+	.DATA_RATE_OQ("DDR"),
+	.DATA_RATE_TQ("BUF"),
+	.DATA_WIDTH(4'd8),
+	.SERDES_MODE("MASTER"),
+	.TRISTATE_WIDTH(1'd1)
+) OSERDESE2_11 (
+	.CLK(sys4x_clk),
+	.CLKDIV(sys_clk),
+	.D1(main_a7ddrphy_dfi_p0_address[8]),
+	.D2(main_a7ddrphy_dfi_p0_address[8]),
+	.D3(main_a7ddrphy_dfi_p1_address[8]),
+	.D4(main_a7ddrphy_dfi_p1_address[8]),
+	.D5(main_a7ddrphy_dfi_p2_address[8]),
+	.D6(main_a7ddrphy_dfi_p2_address[8]),
+	.D7(main_a7ddrphy_dfi_p3_address[8]),
+	.D8(main_a7ddrphy_dfi_p3_address[8]),
+	.OCE(1'd1),
+	.RST((sys_rst | main_a7ddrphy_rst_storage)),
+	.OQ(ddram_a[8])
+);
+
+OSERDESE2 #(
+	.DATA_RATE_OQ("DDR"),
+	.DATA_RATE_TQ("BUF"),
+	.DATA_WIDTH(4'd8),
+	.SERDES_MODE("MASTER"),
+	.TRISTATE_WIDTH(1'd1)
+) OSERDESE2_12 (
+	.CLK(sys4x_clk),
+	.CLKDIV(sys_clk),
+	.D1(main_a7ddrphy_dfi_p0_address[9]),
+	.D2(main_a7ddrphy_dfi_p0_address[9]),
+	.D3(main_a7ddrphy_dfi_p1_address[9]),
+	.D4(main_a7ddrphy_dfi_p1_address[9]),
+	.D5(main_a7ddrphy_dfi_p2_address[9]),
+	.D6(main_a7ddrphy_dfi_p2_address[9]),
+	.D7(main_a7ddrphy_dfi_p3_address[9]),
+	.D8(main_a7ddrphy_dfi_p3_address[9]),
+	.OCE(1'd1),
+	.RST((sys_rst | main_a7ddrphy_rst_storage)),
+	.OQ(ddram_a[9])
+);
+
+OSERDESE2 #(
+	.DATA_RATE_OQ("DDR"),
+	.DATA_RATE_TQ("BUF"),
+	.DATA_WIDTH(4'd8),
+	.SERDES_MODE("MASTER"),
+	.TRISTATE_WIDTH(1'd1)
+) OSERDESE2_13 (
+	.CLK(sys4x_clk),
+	.CLKDIV(sys_clk),
+	.D1(main_a7ddrphy_dfi_p0_address[10]),
+	.D2(main_a7ddrphy_dfi_p0_address[10]),
+	.D3(main_a7ddrphy_dfi_p1_address[10]),
+	.D4(main_a7ddrphy_dfi_p1_address[10]),
+	.D5(main_a7ddrphy_dfi_p2_address[10]),
+	.D6(main_a7ddrphy_dfi_p2_address[10]),
+	.D7(main_a7ddrphy_dfi_p3_address[10]),
+	.D8(main_a7ddrphy_dfi_p3_address[10]),
+	.OCE(1'd1),
+	.RST((sys_rst | main_a7ddrphy_rst_storage)),
+	.OQ(ddram_a[10])
+);
+
+OSERDESE2 #(
+	.DATA_RATE_OQ("DDR"),
+	.DATA_RATE_TQ("BUF"),
+	.DATA_WIDTH(4'd8),
+	.SERDES_MODE("MASTER"),
+	.TRISTATE_WIDTH(1'd1)
+) OSERDESE2_14 (
+	.CLK(sys4x_clk),
+	.CLKDIV(sys_clk),
+	.D1(main_a7ddrphy_dfi_p0_address[11]),
+	.D2(main_a7ddrphy_dfi_p0_address[11]),
+	.D3(main_a7ddrphy_dfi_p1_address[11]),
+	.D4(main_a7ddrphy_dfi_p1_address[11]),
+	.D5(main_a7ddrphy_dfi_p2_address[11]),
+	.D6(main_a7ddrphy_dfi_p2_address[11]),
+	.D7(main_a7ddrphy_dfi_p3_address[11]),
+	.D8(main_a7ddrphy_dfi_p3_address[11]),
+	.OCE(1'd1),
+	.RST((sys_rst | main_a7ddrphy_rst_storage)),
+	.OQ(ddram_a[11])
+);
+
+OSERDESE2 #(
+	.DATA_RATE_OQ("DDR"),
+	.DATA_RATE_TQ("BUF"),
+	.DATA_WIDTH(4'd8),
+	.SERDES_MODE("MASTER"),
+	.TRISTATE_WIDTH(1'd1)
+) OSERDESE2_15 (
+	.CLK(sys4x_clk),
+	.CLKDIV(sys_clk),
+	.D1(main_a7ddrphy_dfi_p0_address[12]),
+	.D2(main_a7ddrphy_dfi_p0_address[12]),
+	.D3(main_a7ddrphy_dfi_p1_address[12]),
+	.D4(main_a7ddrphy_dfi_p1_address[12]),
+	.D5(main_a7ddrphy_dfi_p2_address[12]),
+	.D6(main_a7ddrphy_dfi_p2_address[12]),
+	.D7(main_a7ddrphy_dfi_p3_address[12]),
+	.D8(main_a7ddrphy_dfi_p3_address[12]),
+	.OCE(1'd1),
+	.RST((sys_rst | main_a7ddrphy_rst_storage)),
+	.OQ(ddram_a[12])
+);
+
+OSERDESE2 #(
+	.DATA_RATE_OQ("DDR"),
+	.DATA_RATE_TQ("BUF"),
+	.DATA_WIDTH(4'd8),
+	.SERDES_MODE("MASTER"),
+	.TRISTATE_WIDTH(1'd1)
+) OSERDESE2_16 (
+	.CLK(sys4x_clk),
+	.CLKDIV(sys_clk),
+	.D1(main_a7ddrphy_dfi_p0_address[13]),
+	.D2(main_a7ddrphy_dfi_p0_address[13]),
+	.D3(main_a7ddrphy_dfi_p1_address[13]),
+	.D4(main_a7ddrphy_dfi_p1_address[13]),
+	.D5(main_a7ddrphy_dfi_p2_address[13]),
+	.D6(main_a7ddrphy_dfi_p2_address[13]),
+	.D7(main_a7ddrphy_dfi_p3_address[13]),
+	.D8(main_a7ddrphy_dfi_p3_address[13]),
+	.OCE(1'd1),
+	.RST((sys_rst | main_a7ddrphy_rst_storage)),
+	.OQ(ddram_a[13])
+);
+
+OSERDESE2 #(
+	.DATA_RATE_OQ("DDR"),
+	.DATA_RATE_TQ("BUF"),
+	.DATA_WIDTH(4'd8),
+	.SERDES_MODE("MASTER"),
+	.TRISTATE_WIDTH(1'd1)
+) OSERDESE2_17 (
+	.CLK(sys4x_clk),
+	.CLKDIV(sys_clk),
+	.D1(main_a7ddrphy_dfi_p0_bank[0]),
+	.D2(main_a7ddrphy_dfi_p0_bank[0]),
+	.D3(main_a7ddrphy_dfi_p1_bank[0]),
+	.D4(main_a7ddrphy_dfi_p1_bank[0]),
+	.D5(main_a7ddrphy_dfi_p2_bank[0]),
+	.D6(main_a7ddrphy_dfi_p2_bank[0]),
+	.D7(main_a7ddrphy_dfi_p3_bank[0]),
+	.D8(main_a7ddrphy_dfi_p3_bank[0]),
+	.OCE(1'd1),
+	.RST((sys_rst | main_a7ddrphy_rst_storage)),
+	.OQ(ddram_ba[0])
+);
+
+OSERDESE2 #(
+	.DATA_RATE_OQ("DDR"),
+	.DATA_RATE_TQ("BUF"),
+	.DATA_WIDTH(4'd8),
+	.SERDES_MODE("MASTER"),
+	.TRISTATE_WIDTH(1'd1)
+) OSERDESE2_18 (
+	.CLK(sys4x_clk),
+	.CLKDIV(sys_clk),
+	.D1(main_a7ddrphy_dfi_p0_bank[1]),
+	.D2(main_a7ddrphy_dfi_p0_bank[1]),
+	.D3(main_a7ddrphy_dfi_p1_bank[1]),
+	.D4(main_a7ddrphy_dfi_p1_bank[1]),
+	.D5(main_a7ddrphy_dfi_p2_bank[1]),
+	.D6(main_a7ddrphy_dfi_p2_bank[1]),
+	.D7(main_a7ddrphy_dfi_p3_bank[1]),
+	.D8(main_a7ddrphy_dfi_p3_bank[1]),
+	.OCE(1'd1),
+	.RST((sys_rst | main_a7ddrphy_rst_storage)),
+	.OQ(ddram_ba[1])
+);
+
+OSERDESE2 #(
+	.DATA_RATE_OQ("DDR"),
+	.DATA_RATE_TQ("BUF"),
+	.DATA_WIDTH(4'd8),
+	.SERDES_MODE("MASTER"),
+	.TRISTATE_WIDTH(1'd1)
+) OSERDESE2_19 (
+	.CLK(sys4x_clk),
+	.CLKDIV(sys_clk),
+	.D1(main_a7ddrphy_dfi_p0_bank[2]),
+	.D2(main_a7ddrphy_dfi_p0_bank[2]),
+	.D3(main_a7ddrphy_dfi_p1_bank[2]),
+	.D4(main_a7ddrphy_dfi_p1_bank[2]),
+	.D5(main_a7ddrphy_dfi_p2_bank[2]),
+	.D6(main_a7ddrphy_dfi_p2_bank[2]),
+	.D7(main_a7ddrphy_dfi_p3_bank[2]),
+	.D8(main_a7ddrphy_dfi_p3_bank[2]),
+	.OCE(1'd1),
+	.RST((sys_rst | main_a7ddrphy_rst_storage)),
+	.OQ(ddram_ba[2])
+);
+
+OSERDESE2 #(
+	.DATA_RATE_OQ("DDR"),
+	.DATA_RATE_TQ("BUF"),
+	.DATA_WIDTH(4'd8),
+	.SERDES_MODE("MASTER"),
+	.TRISTATE_WIDTH(1'd1)
+) OSERDESE2_20 (
+	.CLK(sys4x_clk),
+	.CLKDIV(sys_clk),
+	.D1(main_a7ddrphy_dfi_p0_ras_n),
+	.D2(main_a7ddrphy_dfi_p0_ras_n),
+	.D3(main_a7ddrphy_dfi_p1_ras_n),
+	.D4(main_a7ddrphy_dfi_p1_ras_n),
+	.D5(main_a7ddrphy_dfi_p2_ras_n),
+	.D6(main_a7ddrphy_dfi_p2_ras_n),
+	.D7(main_a7ddrphy_dfi_p3_ras_n),
+	.D8(main_a7ddrphy_dfi_p3_ras_n),
+	.OCE(1'd1),
+	.RST((sys_rst | main_a7ddrphy_rst_storage)),
+	.OQ(ddram_ras_n)
+);
+
+OSERDESE2 #(
+	.DATA_RATE_OQ("DDR"),
+	.DATA_RATE_TQ("BUF"),
+	.DATA_WIDTH(4'd8),
+	.SERDES_MODE("MASTER"),
+	.TRISTATE_WIDTH(1'd1)
+) OSERDESE2_21 (
+	.CLK(sys4x_clk),
+	.CLKDIV(sys_clk),
+	.D1(main_a7ddrphy_dfi_p0_cas_n),
+	.D2(main_a7ddrphy_dfi_p0_cas_n),
+	.D3(main_a7ddrphy_dfi_p1_cas_n),
+	.D4(main_a7ddrphy_dfi_p1_cas_n),
+	.D5(main_a7ddrphy_dfi_p2_cas_n),
+	.D6(main_a7ddrphy_dfi_p2_cas_n),
+	.D7(main_a7ddrphy_dfi_p3_cas_n),
+	.D8(main_a7ddrphy_dfi_p3_cas_n),
+	.OCE(1'd1),
+	.RST((sys_rst | main_a7ddrphy_rst_storage)),
+	.OQ(ddram_cas_n)
+);
+
+OSERDESE2 #(
+	.DATA_RATE_OQ("DDR"),
+	.DATA_RATE_TQ("BUF"),
+	.DATA_WIDTH(4'd8),
+	.SERDES_MODE("MASTER"),
+	.TRISTATE_WIDTH(1'd1)
+) OSERDESE2_22 (
+	.CLK(sys4x_clk),
+	.CLKDIV(sys_clk),
+	.D1(main_a7ddrphy_dfi_p0_we_n),
+	.D2(main_a7ddrphy_dfi_p0_we_n),
+	.D3(main_a7ddrphy_dfi_p1_we_n),
+	.D4(main_a7ddrphy_dfi_p1_we_n),
+	.D5(main_a7ddrphy_dfi_p2_we_n),
+	.D6(main_a7ddrphy_dfi_p2_we_n),
+	.D7(main_a7ddrphy_dfi_p3_we_n),
+	.D8(main_a7ddrphy_dfi_p3_we_n),
+	.OCE(1'd1),
+	.RST((sys_rst | main_a7ddrphy_rst_storage)),
+	.OQ(ddram_we_n)
+);
+
+OSERDESE2 #(
+	.DATA_RATE_OQ("DDR"),
+	.DATA_RATE_TQ("BUF"),
+	.DATA_WIDTH(4'd8),
+	.SERDES_MODE("MASTER"),
+	.TRISTATE_WIDTH(1'd1)
+) OSERDESE2_23 (
+	.CLK(sys4x_clk),
+	.CLKDIV(sys_clk),
+	.D1(main_a7ddrphy_dfi_p0_cke),
+	.D2(main_a7ddrphy_dfi_p0_cke),
+	.D3(main_a7ddrphy_dfi_p1_cke),
+	.D4(main_a7ddrphy_dfi_p1_cke),
+	.D5(main_a7ddrphy_dfi_p2_cke),
+	.D6(main_a7ddrphy_dfi_p2_cke),
+	.D7(main_a7ddrphy_dfi_p3_cke),
+	.D8(main_a7ddrphy_dfi_p3_cke),
+	.OCE(1'd1),
+	.RST((sys_rst | main_a7ddrphy_rst_storage)),
+	.OQ(ddram_cke)
+);
+
+OSERDESE2 #(
+	.DATA_RATE_OQ("DDR"),
+	.DATA_RATE_TQ("BUF"),
+	.DATA_WIDTH(4'd8),
+	.SERDES_MODE("MASTER"),
+	.TRISTATE_WIDTH(1'd1)
+) OSERDESE2_24 (
+	.CLK(sys4x_clk),
+	.CLKDIV(sys_clk),
+	.D1(main_a7ddrphy_dfi_p0_odt),
+	.D2(main_a7ddrphy_dfi_p0_odt),
+	.D3(main_a7ddrphy_dfi_p1_odt),
+	.D4(main_a7ddrphy_dfi_p1_odt),
+	.D5(main_a7ddrphy_dfi_p2_odt),
+	.D6(main_a7ddrphy_dfi_p2_odt),
+	.D7(main_a7ddrphy_dfi_p3_odt),
+	.D8(main_a7ddrphy_dfi_p3_odt),
+	.OCE(1'd1),
+	.RST((sys_rst | main_a7ddrphy_rst_storage)),
+	.OQ(ddram_odt)
+);
+
+OSERDESE2 #(
+	.DATA_RATE_OQ("DDR"),
+	.DATA_RATE_TQ("BUF"),
+	.DATA_WIDTH(4'd8),
+	.SERDES_MODE("MASTER"),
+	.TRISTATE_WIDTH(1'd1)
+) OSERDESE2_25 (
+	.CLK(sys4x_dqs_clk),
+	.CLKDIV(sys_clk),
+	.D1(main_a7ddrphy_bitslip00[0]),
+	.D2(main_a7ddrphy_bitslip00[1]),
+	.D3(main_a7ddrphy_bitslip00[2]),
+	.D4(main_a7ddrphy_bitslip00[3]),
+	.D5(main_a7ddrphy_bitslip00[4]),
+	.D6(main_a7ddrphy_bitslip00[5]),
+	.D7(main_a7ddrphy_bitslip00[6]),
+	.D8(main_a7ddrphy_bitslip00[7]),
+	.OCE(1'd1),
+	.RST((sys_rst | main_a7ddrphy_rst_storage)),
+	.T1((~main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1)),
+	.TCE(1'd1),
+	.OFB(main_a7ddrphy0),
+	.OQ(main_a7ddrphy_dqs_o_no_delay0),
+	.TQ(main_a7ddrphy_dqs_t0)
+);
+
+IOBUFDS IOBUFDS(
+	.I(main_a7ddrphy_dqs_o_no_delay0),
+	.T(main_a7ddrphy_dqs_t0),
+	.IO(ddram_dqs_p[0]),
+	.IOB(ddram_dqs_n[0])
+);
+
+OSERDESE2 #(
+	.DATA_RATE_OQ("DDR"),
+	.DATA_RATE_TQ("BUF"),
+	.DATA_WIDTH(4'd8),
+	.SERDES_MODE("MASTER"),
+	.TRISTATE_WIDTH(1'd1)
+) OSERDESE2_26 (
+	.CLK(sys4x_dqs_clk),
+	.CLKDIV(sys_clk),
+	.D1(main_a7ddrphy_bitslip10[0]),
+	.D2(main_a7ddrphy_bitslip10[1]),
+	.D3(main_a7ddrphy_bitslip10[2]),
+	.D4(main_a7ddrphy_bitslip10[3]),
+	.D5(main_a7ddrphy_bitslip10[4]),
+	.D6(main_a7ddrphy_bitslip10[5]),
+	.D7(main_a7ddrphy_bitslip10[6]),
+	.D8(main_a7ddrphy_bitslip10[7]),
+	.OCE(1'd1),
+	.RST((sys_rst | main_a7ddrphy_rst_storage)),
+	.T1((~main_a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1)),
+	.TCE(1'd1),
+	.OFB(main_a7ddrphy1),
+	.OQ(main_a7ddrphy_dqs_o_no_delay1),
+	.TQ(main_a7ddrphy_dqs_t1)
+);
+
+IOBUFDS IOBUFDS_1(
+	.I(main_a7ddrphy_dqs_o_no_delay1),
+	.T(main_a7ddrphy_dqs_t1),
+	.IO(ddram_dqs_p[1]),
+	.IOB(ddram_dqs_n[1])
+);
+
+OSERDESE2 #(
+	.DATA_RATE_OQ("DDR"),
+	.DATA_RATE_TQ("BUF"),
+	.DATA_WIDTH(4'd8),
+	.SERDES_MODE("MASTER"),
+	.TRISTATE_WIDTH(1'd1)
+) OSERDESE2_27 (
+	.CLK(sys4x_clk),
+	.CLKDIV(sys_clk),
+	.D1(main_a7ddrphy_bitslip01[0]),
+	.D2(main_a7ddrphy_bitslip01[1]),
+	.D3(main_a7ddrphy_bitslip01[2]),
+	.D4(main_a7ddrphy_bitslip01[3]),
+	.D5(main_a7ddrphy_bitslip01[4]),
+	.D6(main_a7ddrphy_bitslip01[5]),
+	.D7(main_a7ddrphy_bitslip01[6]),
+	.D8(main_a7ddrphy_bitslip01[7]),
+	.OCE(1'd1),
+	.RST((sys_rst | main_a7ddrphy_rst_storage)),
+	.OQ(ddram_dm[0])
+);
+
+OSERDESE2 #(
+	.DATA_RATE_OQ("DDR"),
+	.DATA_RATE_TQ("BUF"),
+	.DATA_WIDTH(4'd8),
+	.SERDES_MODE("MASTER"),
+	.TRISTATE_WIDTH(1'd1)
+) OSERDESE2_28 (
+	.CLK(sys4x_clk),
+	.CLKDIV(sys_clk),
+	.D1(main_a7ddrphy_bitslip11[0]),
+	.D2(main_a7ddrphy_bitslip11[1]),
+	.D3(main_a7ddrphy_bitslip11[2]),
+	.D4(main_a7ddrphy_bitslip11[3]),
+	.D5(main_a7ddrphy_bitslip11[4]),
+	.D6(main_a7ddrphy_bitslip11[5]),
+	.D7(main_a7ddrphy_bitslip11[6]),
+	.D8(main_a7ddrphy_bitslip11[7]),
+	.OCE(1'd1),
+	.RST((sys_rst | main_a7ddrphy_rst_storage)),
+	.OQ(ddram_dm[1])
+);
+
+OSERDESE2 #(
+	.DATA_RATE_OQ("DDR"),
+	.DATA_RATE_TQ("BUF"),
+	.DATA_WIDTH(4'd8),
+	.SERDES_MODE("MASTER"),
+	.TRISTATE_WIDTH(1'd1)
+) OSERDESE2_29 (
+	.CLK(sys4x_clk),
+	.CLKDIV(sys_clk),
+	.D1(main_a7ddrphy_bitslip02[0]),
+	.D2(main_a7ddrphy_bitslip02[1]),
+	.D3(main_a7ddrphy_bitslip02[2]),
+	.D4(main_a7ddrphy_bitslip02[3]),
+	.D5(main_a7ddrphy_bitslip02[4]),
+	.D6(main_a7ddrphy_bitslip02[5]),
+	.D7(main_a7ddrphy_bitslip02[6]),
+	.D8(main_a7ddrphy_bitslip02[7]),
+	.OCE(1'd1),
+	.RST((sys_rst | main_a7ddrphy_rst_storage)),
+	.T1((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.TCE(1'd1),
+	.OQ(main_a7ddrphy_dq_o_nodelay0),
+	.TQ(main_a7ddrphy_dq_t0)
+);
+
+ISERDESE2 #(
+	.DATA_RATE("DDR"),
+	.DATA_WIDTH(4'd8),
+	.INTERFACE_TYPE("NETWORKING"),
+	.IOBDELAY("IFD"),
+	.NUM_CE(1'd1),
+	.SERDES_MODE("MASTER")
+) ISERDESE2 (
+	.BITSLIP(1'd0),
+	.CE1(1'd1),
+	.CLK(sys4x_clk),
+	.CLKB((~sys4x_clk)),
+	.CLKDIV(sys_clk),
+	.DDLY(main_a7ddrphy_dq_i_delayed0),
+	.RST((sys_rst | main_a7ddrphy_rst_storage)),
+	.Q1(main_a7ddrphy_bitslip03[7]),
+	.Q2(main_a7ddrphy_bitslip03[6]),
+	.Q3(main_a7ddrphy_bitslip03[5]),
+	.Q4(main_a7ddrphy_bitslip03[4]),
+	.Q5(main_a7ddrphy_bitslip03[3]),
+	.Q6(main_a7ddrphy_bitslip03[2]),
+	.Q7(main_a7ddrphy_bitslip03[1]),
+	.Q8(main_a7ddrphy_bitslip03[0])
+);
+
+IDELAYE2 #(
+	.CINVCTRL_SEL("FALSE"),
+	.DELAY_SRC("IDATAIN"),
+	.HIGH_PERFORMANCE_MODE("TRUE"),
+	.IDELAY_TYPE("VARIABLE"),
+	.IDELAY_VALUE(1'd0),
+	.PIPE_SEL("FALSE"),
+	.REFCLK_FREQUENCY(200.0),
+	.SIGNAL_PATTERN("DATA")
+) IDELAYE2 (
+	.C(sys_clk),
+	.CE((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN(main_a7ddrphy_dq_i_nodelay0),
+	.INC(1'd1),
+	.LD(((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)),
+	.LDPIPEEN(1'd0),
+	.DATAOUT(main_a7ddrphy_dq_i_delayed0)
+);
+
+IOBUF IOBUF(
+	.I(main_a7ddrphy_dq_o_nodelay0),
+	.T(main_a7ddrphy_dq_t0),
+	.IO(ddram_dq[0]),
+	.O(main_a7ddrphy_dq_i_nodelay0)
+);
+
+OSERDESE2 #(
+	.DATA_RATE_OQ("DDR"),
+	.DATA_RATE_TQ("BUF"),
+	.DATA_WIDTH(4'd8),
+	.SERDES_MODE("MASTER"),
+	.TRISTATE_WIDTH(1'd1)
+) OSERDESE2_30 (
+	.CLK(sys4x_clk),
+	.CLKDIV(sys_clk),
+	.D1(main_a7ddrphy_bitslip12[0]),
+	.D2(main_a7ddrphy_bitslip12[1]),
+	.D3(main_a7ddrphy_bitslip12[2]),
+	.D4(main_a7ddrphy_bitslip12[3]),
+	.D5(main_a7ddrphy_bitslip12[4]),
+	.D6(main_a7ddrphy_bitslip12[5]),
+	.D7(main_a7ddrphy_bitslip12[6]),
+	.D8(main_a7ddrphy_bitslip12[7]),
+	.OCE(1'd1),
+	.RST((sys_rst | main_a7ddrphy_rst_storage)),
+	.T1((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.TCE(1'd1),
+	.OQ(main_a7ddrphy_dq_o_nodelay1),
+	.TQ(main_a7ddrphy_dq_t1)
+);
+
+ISERDESE2 #(
+	.DATA_RATE("DDR"),
+	.DATA_WIDTH(4'd8),
+	.INTERFACE_TYPE("NETWORKING"),
+	.IOBDELAY("IFD"),
+	.NUM_CE(1'd1),
+	.SERDES_MODE("MASTER")
+) ISERDESE2_1 (
+	.BITSLIP(1'd0),
+	.CE1(1'd1),
+	.CLK(sys4x_clk),
+	.CLKB((~sys4x_clk)),
+	.CLKDIV(sys_clk),
+	.DDLY(main_a7ddrphy_dq_i_delayed1),
+	.RST((sys_rst | main_a7ddrphy_rst_storage)),
+	.Q1(main_a7ddrphy_bitslip13[7]),
+	.Q2(main_a7ddrphy_bitslip13[6]),
+	.Q3(main_a7ddrphy_bitslip13[5]),
+	.Q4(main_a7ddrphy_bitslip13[4]),
+	.Q5(main_a7ddrphy_bitslip13[3]),
+	.Q6(main_a7ddrphy_bitslip13[2]),
+	.Q7(main_a7ddrphy_bitslip13[1]),
+	.Q8(main_a7ddrphy_bitslip13[0])
+);
+
+IDELAYE2 #(
+	.CINVCTRL_SEL("FALSE"),
+	.DELAY_SRC("IDATAIN"),
+	.HIGH_PERFORMANCE_MODE("TRUE"),
+	.IDELAY_TYPE("VARIABLE"),
+	.IDELAY_VALUE(1'd0),
+	.PIPE_SEL("FALSE"),
+	.REFCLK_FREQUENCY(200.0),
+	.SIGNAL_PATTERN("DATA")
+) IDELAYE2_1 (
+	.C(sys_clk),
+	.CE((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN(main_a7ddrphy_dq_i_nodelay1),
+	.INC(1'd1),
+	.LD(((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)),
+	.LDPIPEEN(1'd0),
+	.DATAOUT(main_a7ddrphy_dq_i_delayed1)
+);
+
+IOBUF IOBUF_1(
+	.I(main_a7ddrphy_dq_o_nodelay1),
+	.T(main_a7ddrphy_dq_t1),
+	.IO(ddram_dq[1]),
+	.O(main_a7ddrphy_dq_i_nodelay1)
+);
+
+OSERDESE2 #(
+	.DATA_RATE_OQ("DDR"),
+	.DATA_RATE_TQ("BUF"),
+	.DATA_WIDTH(4'd8),
+	.SERDES_MODE("MASTER"),
+	.TRISTATE_WIDTH(1'd1)
+) OSERDESE2_31 (
+	.CLK(sys4x_clk),
+	.CLKDIV(sys_clk),
+	.D1(main_a7ddrphy_bitslip20[0]),
+	.D2(main_a7ddrphy_bitslip20[1]),
+	.D3(main_a7ddrphy_bitslip20[2]),
+	.D4(main_a7ddrphy_bitslip20[3]),
+	.D5(main_a7ddrphy_bitslip20[4]),
+	.D6(main_a7ddrphy_bitslip20[5]),
+	.D7(main_a7ddrphy_bitslip20[6]),
+	.D8(main_a7ddrphy_bitslip20[7]),
+	.OCE(1'd1),
+	.RST((sys_rst | main_a7ddrphy_rst_storage)),
+	.T1((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.TCE(1'd1),
+	.OQ(main_a7ddrphy_dq_o_nodelay2),
+	.TQ(main_a7ddrphy_dq_t2)
+);
+
+ISERDESE2 #(
+	.DATA_RATE("DDR"),
+	.DATA_WIDTH(4'd8),
+	.INTERFACE_TYPE("NETWORKING"),
+	.IOBDELAY("IFD"),
+	.NUM_CE(1'd1),
+	.SERDES_MODE("MASTER")
+) ISERDESE2_2 (
+	.BITSLIP(1'd0),
+	.CE1(1'd1),
+	.CLK(sys4x_clk),
+	.CLKB((~sys4x_clk)),
+	.CLKDIV(sys_clk),
+	.DDLY(main_a7ddrphy_dq_i_delayed2),
+	.RST((sys_rst | main_a7ddrphy_rst_storage)),
+	.Q1(main_a7ddrphy_bitslip21[7]),
+	.Q2(main_a7ddrphy_bitslip21[6]),
+	.Q3(main_a7ddrphy_bitslip21[5]),
+	.Q4(main_a7ddrphy_bitslip21[4]),
+	.Q5(main_a7ddrphy_bitslip21[3]),
+	.Q6(main_a7ddrphy_bitslip21[2]),
+	.Q7(main_a7ddrphy_bitslip21[1]),
+	.Q8(main_a7ddrphy_bitslip21[0])
+);
+
+IDELAYE2 #(
+	.CINVCTRL_SEL("FALSE"),
+	.DELAY_SRC("IDATAIN"),
+	.HIGH_PERFORMANCE_MODE("TRUE"),
+	.IDELAY_TYPE("VARIABLE"),
+	.IDELAY_VALUE(1'd0),
+	.PIPE_SEL("FALSE"),
+	.REFCLK_FREQUENCY(200.0),
+	.SIGNAL_PATTERN("DATA")
+) IDELAYE2_2 (
+	.C(sys_clk),
+	.CE((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN(main_a7ddrphy_dq_i_nodelay2),
+	.INC(1'd1),
+	.LD(((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)),
+	.LDPIPEEN(1'd0),
+	.DATAOUT(main_a7ddrphy_dq_i_delayed2)
+);
+
+IOBUF IOBUF_2(
+	.I(main_a7ddrphy_dq_o_nodelay2),
+	.T(main_a7ddrphy_dq_t2),
+	.IO(ddram_dq[2]),
+	.O(main_a7ddrphy_dq_i_nodelay2)
+);
+
+OSERDESE2 #(
+	.DATA_RATE_OQ("DDR"),
+	.DATA_RATE_TQ("BUF"),
+	.DATA_WIDTH(4'd8),
+	.SERDES_MODE("MASTER"),
+	.TRISTATE_WIDTH(1'd1)
+) OSERDESE2_32 (
+	.CLK(sys4x_clk),
+	.CLKDIV(sys_clk),
+	.D1(main_a7ddrphy_bitslip30[0]),
+	.D2(main_a7ddrphy_bitslip30[1]),
+	.D3(main_a7ddrphy_bitslip30[2]),
+	.D4(main_a7ddrphy_bitslip30[3]),
+	.D5(main_a7ddrphy_bitslip30[4]),
+	.D6(main_a7ddrphy_bitslip30[5]),
+	.D7(main_a7ddrphy_bitslip30[6]),
+	.D8(main_a7ddrphy_bitslip30[7]),
+	.OCE(1'd1),
+	.RST((sys_rst | main_a7ddrphy_rst_storage)),
+	.T1((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.TCE(1'd1),
+	.OQ(main_a7ddrphy_dq_o_nodelay3),
+	.TQ(main_a7ddrphy_dq_t3)
+);
+
+ISERDESE2 #(
+	.DATA_RATE("DDR"),
+	.DATA_WIDTH(4'd8),
+	.INTERFACE_TYPE("NETWORKING"),
+	.IOBDELAY("IFD"),
+	.NUM_CE(1'd1),
+	.SERDES_MODE("MASTER")
+) ISERDESE2_3 (
+	.BITSLIP(1'd0),
+	.CE1(1'd1),
+	.CLK(sys4x_clk),
+	.CLKB((~sys4x_clk)),
+	.CLKDIV(sys_clk),
+	.DDLY(main_a7ddrphy_dq_i_delayed3),
+	.RST((sys_rst | main_a7ddrphy_rst_storage)),
+	.Q1(main_a7ddrphy_bitslip31[7]),
+	.Q2(main_a7ddrphy_bitslip31[6]),
+	.Q3(main_a7ddrphy_bitslip31[5]),
+	.Q4(main_a7ddrphy_bitslip31[4]),
+	.Q5(main_a7ddrphy_bitslip31[3]),
+	.Q6(main_a7ddrphy_bitslip31[2]),
+	.Q7(main_a7ddrphy_bitslip31[1]),
+	.Q8(main_a7ddrphy_bitslip31[0])
+);
+
+IDELAYE2 #(
+	.CINVCTRL_SEL("FALSE"),
+	.DELAY_SRC("IDATAIN"),
+	.HIGH_PERFORMANCE_MODE("TRUE"),
+	.IDELAY_TYPE("VARIABLE"),
+	.IDELAY_VALUE(1'd0),
+	.PIPE_SEL("FALSE"),
+	.REFCLK_FREQUENCY(200.0),
+	.SIGNAL_PATTERN("DATA")
+) IDELAYE2_3 (
+	.C(sys_clk),
+	.CE((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN(main_a7ddrphy_dq_i_nodelay3),
+	.INC(1'd1),
+	.LD(((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)),
+	.LDPIPEEN(1'd0),
+	.DATAOUT(main_a7ddrphy_dq_i_delayed3)
+);
+
+IOBUF IOBUF_3(
+	.I(main_a7ddrphy_dq_o_nodelay3),
+	.T(main_a7ddrphy_dq_t3),
+	.IO(ddram_dq[3]),
+	.O(main_a7ddrphy_dq_i_nodelay3)
+);
+
+OSERDESE2 #(
+	.DATA_RATE_OQ("DDR"),
+	.DATA_RATE_TQ("BUF"),
+	.DATA_WIDTH(4'd8),
+	.SERDES_MODE("MASTER"),
+	.TRISTATE_WIDTH(1'd1)
+) OSERDESE2_33 (
+	.CLK(sys4x_clk),
+	.CLKDIV(sys_clk),
+	.D1(main_a7ddrphy_bitslip40[0]),
+	.D2(main_a7ddrphy_bitslip40[1]),
+	.D3(main_a7ddrphy_bitslip40[2]),
+	.D4(main_a7ddrphy_bitslip40[3]),
+	.D5(main_a7ddrphy_bitslip40[4]),
+	.D6(main_a7ddrphy_bitslip40[5]),
+	.D7(main_a7ddrphy_bitslip40[6]),
+	.D8(main_a7ddrphy_bitslip40[7]),
+	.OCE(1'd1),
+	.RST((sys_rst | main_a7ddrphy_rst_storage)),
+	.T1((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.TCE(1'd1),
+	.OQ(main_a7ddrphy_dq_o_nodelay4),
+	.TQ(main_a7ddrphy_dq_t4)
+);
+
+ISERDESE2 #(
+	.DATA_RATE("DDR"),
+	.DATA_WIDTH(4'd8),
+	.INTERFACE_TYPE("NETWORKING"),
+	.IOBDELAY("IFD"),
+	.NUM_CE(1'd1),
+	.SERDES_MODE("MASTER")
+) ISERDESE2_4 (
+	.BITSLIP(1'd0),
+	.CE1(1'd1),
+	.CLK(sys4x_clk),
+	.CLKB((~sys4x_clk)),
+	.CLKDIV(sys_clk),
+	.DDLY(main_a7ddrphy_dq_i_delayed4),
+	.RST((sys_rst | main_a7ddrphy_rst_storage)),
+	.Q1(main_a7ddrphy_bitslip41[7]),
+	.Q2(main_a7ddrphy_bitslip41[6]),
+	.Q3(main_a7ddrphy_bitslip41[5]),
+	.Q4(main_a7ddrphy_bitslip41[4]),
+	.Q5(main_a7ddrphy_bitslip41[3]),
+	.Q6(main_a7ddrphy_bitslip41[2]),
+	.Q7(main_a7ddrphy_bitslip41[1]),
+	.Q8(main_a7ddrphy_bitslip41[0])
+);
+
+IDELAYE2 #(
+	.CINVCTRL_SEL("FALSE"),
+	.DELAY_SRC("IDATAIN"),
+	.HIGH_PERFORMANCE_MODE("TRUE"),
+	.IDELAY_TYPE("VARIABLE"),
+	.IDELAY_VALUE(1'd0),
+	.PIPE_SEL("FALSE"),
+	.REFCLK_FREQUENCY(200.0),
+	.SIGNAL_PATTERN("DATA")
+) IDELAYE2_4 (
+	.C(sys_clk),
+	.CE((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN(main_a7ddrphy_dq_i_nodelay4),
+	.INC(1'd1),
+	.LD(((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)),
+	.LDPIPEEN(1'd0),
+	.DATAOUT(main_a7ddrphy_dq_i_delayed4)
+);
+
+IOBUF IOBUF_4(
+	.I(main_a7ddrphy_dq_o_nodelay4),
+	.T(main_a7ddrphy_dq_t4),
+	.IO(ddram_dq[4]),
+	.O(main_a7ddrphy_dq_i_nodelay4)
+);
+
+OSERDESE2 #(
+	.DATA_RATE_OQ("DDR"),
+	.DATA_RATE_TQ("BUF"),
+	.DATA_WIDTH(4'd8),
+	.SERDES_MODE("MASTER"),
+	.TRISTATE_WIDTH(1'd1)
+) OSERDESE2_34 (
+	.CLK(sys4x_clk),
+	.CLKDIV(sys_clk),
+	.D1(main_a7ddrphy_bitslip50[0]),
+	.D2(main_a7ddrphy_bitslip50[1]),
+	.D3(main_a7ddrphy_bitslip50[2]),
+	.D4(main_a7ddrphy_bitslip50[3]),
+	.D5(main_a7ddrphy_bitslip50[4]),
+	.D6(main_a7ddrphy_bitslip50[5]),
+	.D7(main_a7ddrphy_bitslip50[6]),
+	.D8(main_a7ddrphy_bitslip50[7]),
+	.OCE(1'd1),
+	.RST((sys_rst | main_a7ddrphy_rst_storage)),
+	.T1((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.TCE(1'd1),
+	.OQ(main_a7ddrphy_dq_o_nodelay5),
+	.TQ(main_a7ddrphy_dq_t5)
+);
+
+ISERDESE2 #(
+	.DATA_RATE("DDR"),
+	.DATA_WIDTH(4'd8),
+	.INTERFACE_TYPE("NETWORKING"),
+	.IOBDELAY("IFD"),
+	.NUM_CE(1'd1),
+	.SERDES_MODE("MASTER")
+) ISERDESE2_5 (
+	.BITSLIP(1'd0),
+	.CE1(1'd1),
+	.CLK(sys4x_clk),
+	.CLKB((~sys4x_clk)),
+	.CLKDIV(sys_clk),
+	.DDLY(main_a7ddrphy_dq_i_delayed5),
+	.RST((sys_rst | main_a7ddrphy_rst_storage)),
+	.Q1(main_a7ddrphy_bitslip51[7]),
+	.Q2(main_a7ddrphy_bitslip51[6]),
+	.Q3(main_a7ddrphy_bitslip51[5]),
+	.Q4(main_a7ddrphy_bitslip51[4]),
+	.Q5(main_a7ddrphy_bitslip51[3]),
+	.Q6(main_a7ddrphy_bitslip51[2]),
+	.Q7(main_a7ddrphy_bitslip51[1]),
+	.Q8(main_a7ddrphy_bitslip51[0])
+);
+
+IDELAYE2 #(
+	.CINVCTRL_SEL("FALSE"),
+	.DELAY_SRC("IDATAIN"),
+	.HIGH_PERFORMANCE_MODE("TRUE"),
+	.IDELAY_TYPE("VARIABLE"),
+	.IDELAY_VALUE(1'd0),
+	.PIPE_SEL("FALSE"),
+	.REFCLK_FREQUENCY(200.0),
+	.SIGNAL_PATTERN("DATA")
+) IDELAYE2_5 (
+	.C(sys_clk),
+	.CE((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN(main_a7ddrphy_dq_i_nodelay5),
+	.INC(1'd1),
+	.LD(((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)),
+	.LDPIPEEN(1'd0),
+	.DATAOUT(main_a7ddrphy_dq_i_delayed5)
+);
+
+IOBUF IOBUF_5(
+	.I(main_a7ddrphy_dq_o_nodelay5),
+	.T(main_a7ddrphy_dq_t5),
+	.IO(ddram_dq[5]),
+	.O(main_a7ddrphy_dq_i_nodelay5)
+);
+
+OSERDESE2 #(
+	.DATA_RATE_OQ("DDR"),
+	.DATA_RATE_TQ("BUF"),
+	.DATA_WIDTH(4'd8),
+	.SERDES_MODE("MASTER"),
+	.TRISTATE_WIDTH(1'd1)
+) OSERDESE2_35 (
+	.CLK(sys4x_clk),
+	.CLKDIV(sys_clk),
+	.D1(main_a7ddrphy_bitslip60[0]),
+	.D2(main_a7ddrphy_bitslip60[1]),
+	.D3(main_a7ddrphy_bitslip60[2]),
+	.D4(main_a7ddrphy_bitslip60[3]),
+	.D5(main_a7ddrphy_bitslip60[4]),
+	.D6(main_a7ddrphy_bitslip60[5]),
+	.D7(main_a7ddrphy_bitslip60[6]),
+	.D8(main_a7ddrphy_bitslip60[7]),
+	.OCE(1'd1),
+	.RST((sys_rst | main_a7ddrphy_rst_storage)),
+	.T1((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.TCE(1'd1),
+	.OQ(main_a7ddrphy_dq_o_nodelay6),
+	.TQ(main_a7ddrphy_dq_t6)
+);
+
+ISERDESE2 #(
+	.DATA_RATE("DDR"),
+	.DATA_WIDTH(4'd8),
+	.INTERFACE_TYPE("NETWORKING"),
+	.IOBDELAY("IFD"),
+	.NUM_CE(1'd1),
+	.SERDES_MODE("MASTER")
+) ISERDESE2_6 (
+	.BITSLIP(1'd0),
+	.CE1(1'd1),
+	.CLK(sys4x_clk),
+	.CLKB((~sys4x_clk)),
+	.CLKDIV(sys_clk),
+	.DDLY(main_a7ddrphy_dq_i_delayed6),
+	.RST((sys_rst | main_a7ddrphy_rst_storage)),
+	.Q1(main_a7ddrphy_bitslip61[7]),
+	.Q2(main_a7ddrphy_bitslip61[6]),
+	.Q3(main_a7ddrphy_bitslip61[5]),
+	.Q4(main_a7ddrphy_bitslip61[4]),
+	.Q5(main_a7ddrphy_bitslip61[3]),
+	.Q6(main_a7ddrphy_bitslip61[2]),
+	.Q7(main_a7ddrphy_bitslip61[1]),
+	.Q8(main_a7ddrphy_bitslip61[0])
+);
+
+IDELAYE2 #(
+	.CINVCTRL_SEL("FALSE"),
+	.DELAY_SRC("IDATAIN"),
+	.HIGH_PERFORMANCE_MODE("TRUE"),
+	.IDELAY_TYPE("VARIABLE"),
+	.IDELAY_VALUE(1'd0),
+	.PIPE_SEL("FALSE"),
+	.REFCLK_FREQUENCY(200.0),
+	.SIGNAL_PATTERN("DATA")
+) IDELAYE2_6 (
+	.C(sys_clk),
+	.CE((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN(main_a7ddrphy_dq_i_nodelay6),
+	.INC(1'd1),
+	.LD(((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)),
+	.LDPIPEEN(1'd0),
+	.DATAOUT(main_a7ddrphy_dq_i_delayed6)
+);
+
+IOBUF IOBUF_6(
+	.I(main_a7ddrphy_dq_o_nodelay6),
+	.T(main_a7ddrphy_dq_t6),
+	.IO(ddram_dq[6]),
+	.O(main_a7ddrphy_dq_i_nodelay6)
+);
+
+OSERDESE2 #(
+	.DATA_RATE_OQ("DDR"),
+	.DATA_RATE_TQ("BUF"),
+	.DATA_WIDTH(4'd8),
+	.SERDES_MODE("MASTER"),
+	.TRISTATE_WIDTH(1'd1)
+) OSERDESE2_36 (
+	.CLK(sys4x_clk),
+	.CLKDIV(sys_clk),
+	.D1(main_a7ddrphy_bitslip70[0]),
+	.D2(main_a7ddrphy_bitslip70[1]),
+	.D3(main_a7ddrphy_bitslip70[2]),
+	.D4(main_a7ddrphy_bitslip70[3]),
+	.D5(main_a7ddrphy_bitslip70[4]),
+	.D6(main_a7ddrphy_bitslip70[5]),
+	.D7(main_a7ddrphy_bitslip70[6]),
+	.D8(main_a7ddrphy_bitslip70[7]),
+	.OCE(1'd1),
+	.RST((sys_rst | main_a7ddrphy_rst_storage)),
+	.T1((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.TCE(1'd1),
+	.OQ(main_a7ddrphy_dq_o_nodelay7),
+	.TQ(main_a7ddrphy_dq_t7)
+);
+
+ISERDESE2 #(
+	.DATA_RATE("DDR"),
+	.DATA_WIDTH(4'd8),
+	.INTERFACE_TYPE("NETWORKING"),
+	.IOBDELAY("IFD"),
+	.NUM_CE(1'd1),
+	.SERDES_MODE("MASTER")
+) ISERDESE2_7 (
+	.BITSLIP(1'd0),
+	.CE1(1'd1),
+	.CLK(sys4x_clk),
+	.CLKB((~sys4x_clk)),
+	.CLKDIV(sys_clk),
+	.DDLY(main_a7ddrphy_dq_i_delayed7),
+	.RST((sys_rst | main_a7ddrphy_rst_storage)),
+	.Q1(main_a7ddrphy_bitslip71[7]),
+	.Q2(main_a7ddrphy_bitslip71[6]),
+	.Q3(main_a7ddrphy_bitslip71[5]),
+	.Q4(main_a7ddrphy_bitslip71[4]),
+	.Q5(main_a7ddrphy_bitslip71[3]),
+	.Q6(main_a7ddrphy_bitslip71[2]),
+	.Q7(main_a7ddrphy_bitslip71[1]),
+	.Q8(main_a7ddrphy_bitslip71[0])
+);
+
+IDELAYE2 #(
+	.CINVCTRL_SEL("FALSE"),
+	.DELAY_SRC("IDATAIN"),
+	.HIGH_PERFORMANCE_MODE("TRUE"),
+	.IDELAY_TYPE("VARIABLE"),
+	.IDELAY_VALUE(1'd0),
+	.PIPE_SEL("FALSE"),
+	.REFCLK_FREQUENCY(200.0),
+	.SIGNAL_PATTERN("DATA")
+) IDELAYE2_7 (
+	.C(sys_clk),
+	.CE((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN(main_a7ddrphy_dq_i_nodelay7),
+	.INC(1'd1),
+	.LD(((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)),
+	.LDPIPEEN(1'd0),
+	.DATAOUT(main_a7ddrphy_dq_i_delayed7)
+);
+
+IOBUF IOBUF_7(
+	.I(main_a7ddrphy_dq_o_nodelay7),
+	.T(main_a7ddrphy_dq_t7),
+	.IO(ddram_dq[7]),
+	.O(main_a7ddrphy_dq_i_nodelay7)
+);
+
+OSERDESE2 #(
+	.DATA_RATE_OQ("DDR"),
+	.DATA_RATE_TQ("BUF"),
+	.DATA_WIDTH(4'd8),
+	.SERDES_MODE("MASTER"),
+	.TRISTATE_WIDTH(1'd1)
+) OSERDESE2_37 (
+	.CLK(sys4x_clk),
+	.CLKDIV(sys_clk),
+	.D1(main_a7ddrphy_bitslip80[0]),
+	.D2(main_a7ddrphy_bitslip80[1]),
+	.D3(main_a7ddrphy_bitslip80[2]),
+	.D4(main_a7ddrphy_bitslip80[3]),
+	.D5(main_a7ddrphy_bitslip80[4]),
+	.D6(main_a7ddrphy_bitslip80[5]),
+	.D7(main_a7ddrphy_bitslip80[6]),
+	.D8(main_a7ddrphy_bitslip80[7]),
+	.OCE(1'd1),
+	.RST((sys_rst | main_a7ddrphy_rst_storage)),
+	.T1((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.TCE(1'd1),
+	.OQ(main_a7ddrphy_dq_o_nodelay8),
+	.TQ(main_a7ddrphy_dq_t8)
+);
+
+ISERDESE2 #(
+	.DATA_RATE("DDR"),
+	.DATA_WIDTH(4'd8),
+	.INTERFACE_TYPE("NETWORKING"),
+	.IOBDELAY("IFD"),
+	.NUM_CE(1'd1),
+	.SERDES_MODE("MASTER")
+) ISERDESE2_8 (
+	.BITSLIP(1'd0),
+	.CE1(1'd1),
+	.CLK(sys4x_clk),
+	.CLKB((~sys4x_clk)),
+	.CLKDIV(sys_clk),
+	.DDLY(main_a7ddrphy_dq_i_delayed8),
+	.RST((sys_rst | main_a7ddrphy_rst_storage)),
+	.Q1(main_a7ddrphy_bitslip81[7]),
+	.Q2(main_a7ddrphy_bitslip81[6]),
+	.Q3(main_a7ddrphy_bitslip81[5]),
+	.Q4(main_a7ddrphy_bitslip81[4]),
+	.Q5(main_a7ddrphy_bitslip81[3]),
+	.Q6(main_a7ddrphy_bitslip81[2]),
+	.Q7(main_a7ddrphy_bitslip81[1]),
+	.Q8(main_a7ddrphy_bitslip81[0])
+);
+
+IDELAYE2 #(
+	.CINVCTRL_SEL("FALSE"),
+	.DELAY_SRC("IDATAIN"),
+	.HIGH_PERFORMANCE_MODE("TRUE"),
+	.IDELAY_TYPE("VARIABLE"),
+	.IDELAY_VALUE(1'd0),
+	.PIPE_SEL("FALSE"),
+	.REFCLK_FREQUENCY(200.0),
+	.SIGNAL_PATTERN("DATA")
+) IDELAYE2_8 (
+	.C(sys_clk),
+	.CE((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN(main_a7ddrphy_dq_i_nodelay8),
+	.INC(1'd1),
+	.LD(((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)),
+	.LDPIPEEN(1'd0),
+	.DATAOUT(main_a7ddrphy_dq_i_delayed8)
+);
+
+IOBUF IOBUF_8(
+	.I(main_a7ddrphy_dq_o_nodelay8),
+	.T(main_a7ddrphy_dq_t8),
+	.IO(ddram_dq[8]),
+	.O(main_a7ddrphy_dq_i_nodelay8)
+);
+
+OSERDESE2 #(
+	.DATA_RATE_OQ("DDR"),
+	.DATA_RATE_TQ("BUF"),
+	.DATA_WIDTH(4'd8),
+	.SERDES_MODE("MASTER"),
+	.TRISTATE_WIDTH(1'd1)
+) OSERDESE2_38 (
+	.CLK(sys4x_clk),
+	.CLKDIV(sys_clk),
+	.D1(main_a7ddrphy_bitslip90[0]),
+	.D2(main_a7ddrphy_bitslip90[1]),
+	.D3(main_a7ddrphy_bitslip90[2]),
+	.D4(main_a7ddrphy_bitslip90[3]),
+	.D5(main_a7ddrphy_bitslip90[4]),
+	.D6(main_a7ddrphy_bitslip90[5]),
+	.D7(main_a7ddrphy_bitslip90[6]),
+	.D8(main_a7ddrphy_bitslip90[7]),
+	.OCE(1'd1),
+	.RST((sys_rst | main_a7ddrphy_rst_storage)),
+	.T1((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.TCE(1'd1),
+	.OQ(main_a7ddrphy_dq_o_nodelay9),
+	.TQ(main_a7ddrphy_dq_t9)
+);
+
+ISERDESE2 #(
+	.DATA_RATE("DDR"),
+	.DATA_WIDTH(4'd8),
+	.INTERFACE_TYPE("NETWORKING"),
+	.IOBDELAY("IFD"),
+	.NUM_CE(1'd1),
+	.SERDES_MODE("MASTER")
+) ISERDESE2_9 (
+	.BITSLIP(1'd0),
+	.CE1(1'd1),
+	.CLK(sys4x_clk),
+	.CLKB((~sys4x_clk)),
+	.CLKDIV(sys_clk),
+	.DDLY(main_a7ddrphy_dq_i_delayed9),
+	.RST((sys_rst | main_a7ddrphy_rst_storage)),
+	.Q1(main_a7ddrphy_bitslip91[7]),
+	.Q2(main_a7ddrphy_bitslip91[6]),
+	.Q3(main_a7ddrphy_bitslip91[5]),
+	.Q4(main_a7ddrphy_bitslip91[4]),
+	.Q5(main_a7ddrphy_bitslip91[3]),
+	.Q6(main_a7ddrphy_bitslip91[2]),
+	.Q7(main_a7ddrphy_bitslip91[1]),
+	.Q8(main_a7ddrphy_bitslip91[0])
+);
+
+IDELAYE2 #(
+	.CINVCTRL_SEL("FALSE"),
+	.DELAY_SRC("IDATAIN"),
+	.HIGH_PERFORMANCE_MODE("TRUE"),
+	.IDELAY_TYPE("VARIABLE"),
+	.IDELAY_VALUE(1'd0),
+	.PIPE_SEL("FALSE"),
+	.REFCLK_FREQUENCY(200.0),
+	.SIGNAL_PATTERN("DATA")
+) IDELAYE2_9 (
+	.C(sys_clk),
+	.CE((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN(main_a7ddrphy_dq_i_nodelay9),
+	.INC(1'd1),
+	.LD(((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)),
+	.LDPIPEEN(1'd0),
+	.DATAOUT(main_a7ddrphy_dq_i_delayed9)
+);
+
+IOBUF IOBUF_9(
+	.I(main_a7ddrphy_dq_o_nodelay9),
+	.T(main_a7ddrphy_dq_t9),
+	.IO(ddram_dq[9]),
+	.O(main_a7ddrphy_dq_i_nodelay9)
+);
+
+OSERDESE2 #(
+	.DATA_RATE_OQ("DDR"),
+	.DATA_RATE_TQ("BUF"),
+	.DATA_WIDTH(4'd8),
+	.SERDES_MODE("MASTER"),
+	.TRISTATE_WIDTH(1'd1)
+) OSERDESE2_39 (
+	.CLK(sys4x_clk),
+	.CLKDIV(sys_clk),
+	.D1(main_a7ddrphy_bitslip100[0]),
+	.D2(main_a7ddrphy_bitslip100[1]),
+	.D3(main_a7ddrphy_bitslip100[2]),
+	.D4(main_a7ddrphy_bitslip100[3]),
+	.D5(main_a7ddrphy_bitslip100[4]),
+	.D6(main_a7ddrphy_bitslip100[5]),
+	.D7(main_a7ddrphy_bitslip100[6]),
+	.D8(main_a7ddrphy_bitslip100[7]),
+	.OCE(1'd1),
+	.RST((sys_rst | main_a7ddrphy_rst_storage)),
+	.T1((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.TCE(1'd1),
+	.OQ(main_a7ddrphy_dq_o_nodelay10),
+	.TQ(main_a7ddrphy_dq_t10)
+);
+
+ISERDESE2 #(
+	.DATA_RATE("DDR"),
+	.DATA_WIDTH(4'd8),
+	.INTERFACE_TYPE("NETWORKING"),
+	.IOBDELAY("IFD"),
+	.NUM_CE(1'd1),
+	.SERDES_MODE("MASTER")
+) ISERDESE2_10 (
+	.BITSLIP(1'd0),
+	.CE1(1'd1),
+	.CLK(sys4x_clk),
+	.CLKB((~sys4x_clk)),
+	.CLKDIV(sys_clk),
+	.DDLY(main_a7ddrphy_dq_i_delayed10),
+	.RST((sys_rst | main_a7ddrphy_rst_storage)),
+	.Q1(main_a7ddrphy_bitslip101[7]),
+	.Q2(main_a7ddrphy_bitslip101[6]),
+	.Q3(main_a7ddrphy_bitslip101[5]),
+	.Q4(main_a7ddrphy_bitslip101[4]),
+	.Q5(main_a7ddrphy_bitslip101[3]),
+	.Q6(main_a7ddrphy_bitslip101[2]),
+	.Q7(main_a7ddrphy_bitslip101[1]),
+	.Q8(main_a7ddrphy_bitslip101[0])
+);
+
+IDELAYE2 #(
+	.CINVCTRL_SEL("FALSE"),
+	.DELAY_SRC("IDATAIN"),
+	.HIGH_PERFORMANCE_MODE("TRUE"),
+	.IDELAY_TYPE("VARIABLE"),
+	.IDELAY_VALUE(1'd0),
+	.PIPE_SEL("FALSE"),
+	.REFCLK_FREQUENCY(200.0),
+	.SIGNAL_PATTERN("DATA")
+) IDELAYE2_10 (
+	.C(sys_clk),
+	.CE((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN(main_a7ddrphy_dq_i_nodelay10),
+	.INC(1'd1),
+	.LD(((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)),
+	.LDPIPEEN(1'd0),
+	.DATAOUT(main_a7ddrphy_dq_i_delayed10)
+);
+
+IOBUF IOBUF_10(
+	.I(main_a7ddrphy_dq_o_nodelay10),
+	.T(main_a7ddrphy_dq_t10),
+	.IO(ddram_dq[10]),
+	.O(main_a7ddrphy_dq_i_nodelay10)
+);
+
+OSERDESE2 #(
+	.DATA_RATE_OQ("DDR"),
+	.DATA_RATE_TQ("BUF"),
+	.DATA_WIDTH(4'd8),
+	.SERDES_MODE("MASTER"),
+	.TRISTATE_WIDTH(1'd1)
+) OSERDESE2_40 (
+	.CLK(sys4x_clk),
+	.CLKDIV(sys_clk),
+	.D1(main_a7ddrphy_bitslip110[0]),
+	.D2(main_a7ddrphy_bitslip110[1]),
+	.D3(main_a7ddrphy_bitslip110[2]),
+	.D4(main_a7ddrphy_bitslip110[3]),
+	.D5(main_a7ddrphy_bitslip110[4]),
+	.D6(main_a7ddrphy_bitslip110[5]),
+	.D7(main_a7ddrphy_bitslip110[6]),
+	.D8(main_a7ddrphy_bitslip110[7]),
+	.OCE(1'd1),
+	.RST((sys_rst | main_a7ddrphy_rst_storage)),
+	.T1((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.TCE(1'd1),
+	.OQ(main_a7ddrphy_dq_o_nodelay11),
+	.TQ(main_a7ddrphy_dq_t11)
+);
+
+ISERDESE2 #(
+	.DATA_RATE("DDR"),
+	.DATA_WIDTH(4'd8),
+	.INTERFACE_TYPE("NETWORKING"),
+	.IOBDELAY("IFD"),
+	.NUM_CE(1'd1),
+	.SERDES_MODE("MASTER")
+) ISERDESE2_11 (
+	.BITSLIP(1'd0),
+	.CE1(1'd1),
+	.CLK(sys4x_clk),
+	.CLKB((~sys4x_clk)),
+	.CLKDIV(sys_clk),
+	.DDLY(main_a7ddrphy_dq_i_delayed11),
+	.RST((sys_rst | main_a7ddrphy_rst_storage)),
+	.Q1(main_a7ddrphy_bitslip111[7]),
+	.Q2(main_a7ddrphy_bitslip111[6]),
+	.Q3(main_a7ddrphy_bitslip111[5]),
+	.Q4(main_a7ddrphy_bitslip111[4]),
+	.Q5(main_a7ddrphy_bitslip111[3]),
+	.Q6(main_a7ddrphy_bitslip111[2]),
+	.Q7(main_a7ddrphy_bitslip111[1]),
+	.Q8(main_a7ddrphy_bitslip111[0])
+);
+
+IDELAYE2 #(
+	.CINVCTRL_SEL("FALSE"),
+	.DELAY_SRC("IDATAIN"),
+	.HIGH_PERFORMANCE_MODE("TRUE"),
+	.IDELAY_TYPE("VARIABLE"),
+	.IDELAY_VALUE(1'd0),
+	.PIPE_SEL("FALSE"),
+	.REFCLK_FREQUENCY(200.0),
+	.SIGNAL_PATTERN("DATA")
+) IDELAYE2_11 (
+	.C(sys_clk),
+	.CE((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN(main_a7ddrphy_dq_i_nodelay11),
+	.INC(1'd1),
+	.LD(((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)),
+	.LDPIPEEN(1'd0),
+	.DATAOUT(main_a7ddrphy_dq_i_delayed11)
+);
+
+IOBUF IOBUF_11(
+	.I(main_a7ddrphy_dq_o_nodelay11),
+	.T(main_a7ddrphy_dq_t11),
+	.IO(ddram_dq[11]),
+	.O(main_a7ddrphy_dq_i_nodelay11)
+);
+
+OSERDESE2 #(
+	.DATA_RATE_OQ("DDR"),
+	.DATA_RATE_TQ("BUF"),
+	.DATA_WIDTH(4'd8),
+	.SERDES_MODE("MASTER"),
+	.TRISTATE_WIDTH(1'd1)
+) OSERDESE2_41 (
+	.CLK(sys4x_clk),
+	.CLKDIV(sys_clk),
+	.D1(main_a7ddrphy_bitslip120[0]),
+	.D2(main_a7ddrphy_bitslip120[1]),
+	.D3(main_a7ddrphy_bitslip120[2]),
+	.D4(main_a7ddrphy_bitslip120[3]),
+	.D5(main_a7ddrphy_bitslip120[4]),
+	.D6(main_a7ddrphy_bitslip120[5]),
+	.D7(main_a7ddrphy_bitslip120[6]),
+	.D8(main_a7ddrphy_bitslip120[7]),
+	.OCE(1'd1),
+	.RST((sys_rst | main_a7ddrphy_rst_storage)),
+	.T1((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.TCE(1'd1),
+	.OQ(main_a7ddrphy_dq_o_nodelay12),
+	.TQ(main_a7ddrphy_dq_t12)
+);
+
+ISERDESE2 #(
+	.DATA_RATE("DDR"),
+	.DATA_WIDTH(4'd8),
+	.INTERFACE_TYPE("NETWORKING"),
+	.IOBDELAY("IFD"),
+	.NUM_CE(1'd1),
+	.SERDES_MODE("MASTER")
+) ISERDESE2_12 (
+	.BITSLIP(1'd0),
+	.CE1(1'd1),
+	.CLK(sys4x_clk),
+	.CLKB((~sys4x_clk)),
+	.CLKDIV(sys_clk),
+	.DDLY(main_a7ddrphy_dq_i_delayed12),
+	.RST((sys_rst | main_a7ddrphy_rst_storage)),
+	.Q1(main_a7ddrphy_bitslip121[7]),
+	.Q2(main_a7ddrphy_bitslip121[6]),
+	.Q3(main_a7ddrphy_bitslip121[5]),
+	.Q4(main_a7ddrphy_bitslip121[4]),
+	.Q5(main_a7ddrphy_bitslip121[3]),
+	.Q6(main_a7ddrphy_bitslip121[2]),
+	.Q7(main_a7ddrphy_bitslip121[1]),
+	.Q8(main_a7ddrphy_bitslip121[0])
+);
+
+IDELAYE2 #(
+	.CINVCTRL_SEL("FALSE"),
+	.DELAY_SRC("IDATAIN"),
+	.HIGH_PERFORMANCE_MODE("TRUE"),
+	.IDELAY_TYPE("VARIABLE"),
+	.IDELAY_VALUE(1'd0),
+	.PIPE_SEL("FALSE"),
+	.REFCLK_FREQUENCY(200.0),
+	.SIGNAL_PATTERN("DATA")
+) IDELAYE2_12 (
+	.C(sys_clk),
+	.CE((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN(main_a7ddrphy_dq_i_nodelay12),
+	.INC(1'd1),
+	.LD(((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)),
+	.LDPIPEEN(1'd0),
+	.DATAOUT(main_a7ddrphy_dq_i_delayed12)
+);
+
+IOBUF IOBUF_12(
+	.I(main_a7ddrphy_dq_o_nodelay12),
+	.T(main_a7ddrphy_dq_t12),
+	.IO(ddram_dq[12]),
+	.O(main_a7ddrphy_dq_i_nodelay12)
+);
+
+OSERDESE2 #(
+	.DATA_RATE_OQ("DDR"),
+	.DATA_RATE_TQ("BUF"),
+	.DATA_WIDTH(4'd8),
+	.SERDES_MODE("MASTER"),
+	.TRISTATE_WIDTH(1'd1)
+) OSERDESE2_42 (
+	.CLK(sys4x_clk),
+	.CLKDIV(sys_clk),
+	.D1(main_a7ddrphy_bitslip130[0]),
+	.D2(main_a7ddrphy_bitslip130[1]),
+	.D3(main_a7ddrphy_bitslip130[2]),
+	.D4(main_a7ddrphy_bitslip130[3]),
+	.D5(main_a7ddrphy_bitslip130[4]),
+	.D6(main_a7ddrphy_bitslip130[5]),
+	.D7(main_a7ddrphy_bitslip130[6]),
+	.D8(main_a7ddrphy_bitslip130[7]),
+	.OCE(1'd1),
+	.RST((sys_rst | main_a7ddrphy_rst_storage)),
+	.T1((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.TCE(1'd1),
+	.OQ(main_a7ddrphy_dq_o_nodelay13),
+	.TQ(main_a7ddrphy_dq_t13)
+);
+
+ISERDESE2 #(
+	.DATA_RATE("DDR"),
+	.DATA_WIDTH(4'd8),
+	.INTERFACE_TYPE("NETWORKING"),
+	.IOBDELAY("IFD"),
+	.NUM_CE(1'd1),
+	.SERDES_MODE("MASTER")
+) ISERDESE2_13 (
+	.BITSLIP(1'd0),
+	.CE1(1'd1),
+	.CLK(sys4x_clk),
+	.CLKB((~sys4x_clk)),
+	.CLKDIV(sys_clk),
+	.DDLY(main_a7ddrphy_dq_i_delayed13),
+	.RST((sys_rst | main_a7ddrphy_rst_storage)),
+	.Q1(main_a7ddrphy_bitslip131[7]),
+	.Q2(main_a7ddrphy_bitslip131[6]),
+	.Q3(main_a7ddrphy_bitslip131[5]),
+	.Q4(main_a7ddrphy_bitslip131[4]),
+	.Q5(main_a7ddrphy_bitslip131[3]),
+	.Q6(main_a7ddrphy_bitslip131[2]),
+	.Q7(main_a7ddrphy_bitslip131[1]),
+	.Q8(main_a7ddrphy_bitslip131[0])
+);
+
+IDELAYE2 #(
+	.CINVCTRL_SEL("FALSE"),
+	.DELAY_SRC("IDATAIN"),
+	.HIGH_PERFORMANCE_MODE("TRUE"),
+	.IDELAY_TYPE("VARIABLE"),
+	.IDELAY_VALUE(1'd0),
+	.PIPE_SEL("FALSE"),
+	.REFCLK_FREQUENCY(200.0),
+	.SIGNAL_PATTERN("DATA")
+) IDELAYE2_13 (
+	.C(sys_clk),
+	.CE((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN(main_a7ddrphy_dq_i_nodelay13),
+	.INC(1'd1),
+	.LD(((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)),
+	.LDPIPEEN(1'd0),
+	.DATAOUT(main_a7ddrphy_dq_i_delayed13)
+);
+
+IOBUF IOBUF_13(
+	.I(main_a7ddrphy_dq_o_nodelay13),
+	.T(main_a7ddrphy_dq_t13),
+	.IO(ddram_dq[13]),
+	.O(main_a7ddrphy_dq_i_nodelay13)
+);
+
+OSERDESE2 #(
+	.DATA_RATE_OQ("DDR"),
+	.DATA_RATE_TQ("BUF"),
+	.DATA_WIDTH(4'd8),
+	.SERDES_MODE("MASTER"),
+	.TRISTATE_WIDTH(1'd1)
+) OSERDESE2_43 (
+	.CLK(sys4x_clk),
+	.CLKDIV(sys_clk),
+	.D1(main_a7ddrphy_bitslip140[0]),
+	.D2(main_a7ddrphy_bitslip140[1]),
+	.D3(main_a7ddrphy_bitslip140[2]),
+	.D4(main_a7ddrphy_bitslip140[3]),
+	.D5(main_a7ddrphy_bitslip140[4]),
+	.D6(main_a7ddrphy_bitslip140[5]),
+	.D7(main_a7ddrphy_bitslip140[6]),
+	.D8(main_a7ddrphy_bitslip140[7]),
+	.OCE(1'd1),
+	.RST((sys_rst | main_a7ddrphy_rst_storage)),
+	.T1((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.TCE(1'd1),
+	.OQ(main_a7ddrphy_dq_o_nodelay14),
+	.TQ(main_a7ddrphy_dq_t14)
+);
+
+ISERDESE2 #(
+	.DATA_RATE("DDR"),
+	.DATA_WIDTH(4'd8),
+	.INTERFACE_TYPE("NETWORKING"),
+	.IOBDELAY("IFD"),
+	.NUM_CE(1'd1),
+	.SERDES_MODE("MASTER")
+) ISERDESE2_14 (
+	.BITSLIP(1'd0),
+	.CE1(1'd1),
+	.CLK(sys4x_clk),
+	.CLKB((~sys4x_clk)),
+	.CLKDIV(sys_clk),
+	.DDLY(main_a7ddrphy_dq_i_delayed14),
+	.RST((sys_rst | main_a7ddrphy_rst_storage)),
+	.Q1(main_a7ddrphy_bitslip141[7]),
+	.Q2(main_a7ddrphy_bitslip141[6]),
+	.Q3(main_a7ddrphy_bitslip141[5]),
+	.Q4(main_a7ddrphy_bitslip141[4]),
+	.Q5(main_a7ddrphy_bitslip141[3]),
+	.Q6(main_a7ddrphy_bitslip141[2]),
+	.Q7(main_a7ddrphy_bitslip141[1]),
+	.Q8(main_a7ddrphy_bitslip141[0])
+);
+
+IDELAYE2 #(
+	.CINVCTRL_SEL("FALSE"),
+	.DELAY_SRC("IDATAIN"),
+	.HIGH_PERFORMANCE_MODE("TRUE"),
+	.IDELAY_TYPE("VARIABLE"),
+	.IDELAY_VALUE(1'd0),
+	.PIPE_SEL("FALSE"),
+	.REFCLK_FREQUENCY(200.0),
+	.SIGNAL_PATTERN("DATA")
+) IDELAYE2_14 (
+	.C(sys_clk),
+	.CE((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN(main_a7ddrphy_dq_i_nodelay14),
+	.INC(1'd1),
+	.LD(((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)),
+	.LDPIPEEN(1'd0),
+	.DATAOUT(main_a7ddrphy_dq_i_delayed14)
+);
+
+IOBUF IOBUF_14(
+	.I(main_a7ddrphy_dq_o_nodelay14),
+	.T(main_a7ddrphy_dq_t14),
+	.IO(ddram_dq[14]),
+	.O(main_a7ddrphy_dq_i_nodelay14)
+);
+
+OSERDESE2 #(
+	.DATA_RATE_OQ("DDR"),
+	.DATA_RATE_TQ("BUF"),
+	.DATA_WIDTH(4'd8),
+	.SERDES_MODE("MASTER"),
+	.TRISTATE_WIDTH(1'd1)
+) OSERDESE2_44 (
+	.CLK(sys4x_clk),
+	.CLKDIV(sys_clk),
+	.D1(main_a7ddrphy_bitslip150[0]),
+	.D2(main_a7ddrphy_bitslip150[1]),
+	.D3(main_a7ddrphy_bitslip150[2]),
+	.D4(main_a7ddrphy_bitslip150[3]),
+	.D5(main_a7ddrphy_bitslip150[4]),
+	.D6(main_a7ddrphy_bitslip150[5]),
+	.D7(main_a7ddrphy_bitslip150[6]),
+	.D8(main_a7ddrphy_bitslip150[7]),
+	.OCE(1'd1),
+	.RST((sys_rst | main_a7ddrphy_rst_storage)),
+	.T1((~main_a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1)),
+	.TCE(1'd1),
+	.OQ(main_a7ddrphy_dq_o_nodelay15),
+	.TQ(main_a7ddrphy_dq_t15)
+);
+
+ISERDESE2 #(
+	.DATA_RATE("DDR"),
+	.DATA_WIDTH(4'd8),
+	.INTERFACE_TYPE("NETWORKING"),
+	.IOBDELAY("IFD"),
+	.NUM_CE(1'd1),
+	.SERDES_MODE("MASTER")
+) ISERDESE2_15 (
+	.BITSLIP(1'd0),
+	.CE1(1'd1),
+	.CLK(sys4x_clk),
+	.CLKB((~sys4x_clk)),
+	.CLKDIV(sys_clk),
+	.DDLY(main_a7ddrphy_dq_i_delayed15),
+	.RST((sys_rst | main_a7ddrphy_rst_storage)),
+	.Q1(main_a7ddrphy_bitslip151[7]),
+	.Q2(main_a7ddrphy_bitslip151[6]),
+	.Q3(main_a7ddrphy_bitslip151[5]),
+	.Q4(main_a7ddrphy_bitslip151[4]),
+	.Q5(main_a7ddrphy_bitslip151[3]),
+	.Q6(main_a7ddrphy_bitslip151[2]),
+	.Q7(main_a7ddrphy_bitslip151[1]),
+	.Q8(main_a7ddrphy_bitslip151[0])
+);
+
+IDELAYE2 #(
+	.CINVCTRL_SEL("FALSE"),
+	.DELAY_SRC("IDATAIN"),
+	.HIGH_PERFORMANCE_MODE("TRUE"),
+	.IDELAY_TYPE("VARIABLE"),
+	.IDELAY_VALUE(1'd0),
+	.PIPE_SEL("FALSE"),
+	.REFCLK_FREQUENCY(200.0),
+	.SIGNAL_PATTERN("DATA")
+) IDELAYE2_15 (
+	.C(sys_clk),
+	.CE((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_inc_re)),
+	.IDATAIN(main_a7ddrphy_dq_i_nodelay15),
+	.INC(1'd1),
+	.LD(((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_rst_re) | main_a7ddrphy_rst_storage)),
+	.LDPIPEEN(1'd0),
+	.DATAOUT(main_a7ddrphy_dq_i_delayed15)
+);
+
+IOBUF IOBUF_15(
+	.I(main_a7ddrphy_dq_o_nodelay15),
+	.T(main_a7ddrphy_dq_t15),
+	.IO(ddram_dq[15]),
+	.O(main_a7ddrphy_dq_i_nodelay15)
+);
+
+reg [23:0] storage[0:15];
+reg [23:0] memdat;
+always @(posedge sys_clk) begin
+	if (main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we)
+		storage[main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr] <= main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w;
+	memdat <= storage[main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr];
+end
+
+always @(posedge sys_clk) begin
+end
+
+assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_r = memdat;
+assign main_litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r = storage[main_litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr];
+
+reg [23:0] storage_1[0:15];
+reg [23:0] memdat_1;
+always @(posedge sys_clk) begin
+	if (main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we)
+		storage_1[main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr] <= main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w;
+	memdat_1 <= storage_1[main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr];
+end
+
+always @(posedge sys_clk) begin
+end
+
+assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_r = memdat_1;
+assign main_litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r = storage_1[main_litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr];
+
+reg [23:0] storage_2[0:15];
+reg [23:0] memdat_2;
+always @(posedge sys_clk) begin
+	if (main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we)
+		storage_2[main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr] <= main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w;
+	memdat_2 <= storage_2[main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr];
+end
+
+always @(posedge sys_clk) begin
+end
+
+assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_r = memdat_2;
+assign main_litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r = storage_2[main_litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr];
+
+reg [23:0] storage_3[0:15];
+reg [23:0] memdat_3;
+always @(posedge sys_clk) begin
+	if (main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we)
+		storage_3[main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr] <= main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w;
+	memdat_3 <= storage_3[main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr];
+end
+
+always @(posedge sys_clk) begin
+end
+
+assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_r = memdat_3;
+assign main_litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r = storage_3[main_litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr];
+
+reg [23:0] storage_4[0:15];
+reg [23:0] memdat_4;
+always @(posedge sys_clk) begin
+	if (main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we)
+		storage_4[main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr] <= main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w;
+	memdat_4 <= storage_4[main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr];
+end
+
+always @(posedge sys_clk) begin
+end
+
+assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_r = memdat_4;
+assign main_litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r = storage_4[main_litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr];
+
+reg [23:0] storage_5[0:15];
+reg [23:0] memdat_5;
+always @(posedge sys_clk) begin
+	if (main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we)
+		storage_5[main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr] <= main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w;
+	memdat_5 <= storage_5[main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr];
+end
+
+always @(posedge sys_clk) begin
+end
+
+assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_r = memdat_5;
+assign main_litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r = storage_5[main_litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr];
+
+reg [23:0] storage_6[0:15];
+reg [23:0] memdat_6;
+always @(posedge sys_clk) begin
+	if (main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we)
+		storage_6[main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr] <= main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w;
+	memdat_6 <= storage_6[main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr];
+end
+
+always @(posedge sys_clk) begin
+end
+
+assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_r = memdat_6;
+assign main_litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r = storage_6[main_litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr];
+
+reg [23:0] storage_7[0:15];
+reg [23:0] memdat_7;
+always @(posedge sys_clk) begin
+	if (main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we)
+		storage_7[main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr] <= main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w;
+	memdat_7 <= storage_7[main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr];
+end
+
+always @(posedge sys_clk) begin
+end
+
+assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_r = memdat_7;
+assign main_litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r = storage_7[main_litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr];
+
+FD FD(
+	.C(main_clkin),
+	.D(main_reset),
+	.Q(builder_reset0)
+);
+
+FD FD_1(
+	.C(main_clkin),
+	.D(builder_reset0),
+	.Q(builder_reset1)
+);
+
+FD FD_2(
+	.C(main_clkin),
+	.D(builder_reset1),
+	.Q(builder_reset2)
+);
+
+FD FD_3(
+	.C(main_clkin),
+	.D(builder_reset2),
+	.Q(builder_reset3)
+);
+
+FD FD_4(
+	.C(main_clkin),
+	.D(builder_reset3),
+	.Q(builder_reset4)
+);
+
+FD FD_5(
+	.C(main_clkin),
+	.D(builder_reset4),
+	.Q(builder_reset5)
+);
+
+FD FD_6(
+	.C(main_clkin),
+	.D(builder_reset5),
+	.Q(builder_reset6)
+);
+
+FD FD_7(
+	.C(main_clkin),
+	.D(builder_reset6),
+	.Q(builder_reset7)
+);
+
+PLLE2_ADV #(
+	.CLKFBOUT_MULT(6'd32),
+	.CLKIN1_PERIOD(20.0),
+	.CLKOUT0_DIVIDE(4'd8),
+	.CLKOUT0_PHASE(1'd0),
+	.CLKOUT1_DIVIDE(5'd16),
+	.CLKOUT1_PHASE(1'd0),
+	.CLKOUT2_DIVIDE(3'd4),
+	.CLKOUT2_PHASE(1'd0),
+	.CLKOUT3_DIVIDE(3'd4),
+	.CLKOUT3_PHASE(7'd90),
+	.DIVCLK_DIVIDE(1'd1),
+	.REF_JITTER1(0.01),
+	.STARTUP_WAIT("FALSE")
+) PLLE2_ADV (
+	.CLKFBIN(builder_pll_fb),
+	.CLKIN1(main_clkin),
+	.PWRDWN(main_power_down),
+	.RST(builder_reset7),
+	.CLKFBOUT(builder_pll_fb),
+	.CLKOUT0(main_clkout0),
+	.CLKOUT1(main_clkout1),
+	.CLKOUT2(main_clkout2),
+	.CLKOUT3(main_clkout3),
+	.LOCKED(main_locked)
+);
+
+(* ars_ff1 = "true", async_reg = "true" *) FDPE #(
+	.INIT(1'd1)
+) FDPE (
+	.C(iodelay_clk),
+	.CE(1'd1),
+	.D(1'd0),
+	.PRE(builder_xilinxasyncresetsynchronizerimpl0),
+	.Q(builder_xilinxasyncresetsynchronizerimpl0_rst_meta)
+);
+
+(* ars_ff2 = "true", async_reg = "true" *) FDPE #(
+	.INIT(1'd1)
+) FDPE_1 (
+	.C(iodelay_clk),
+	.CE(1'd1),
+	.D(builder_xilinxasyncresetsynchronizerimpl0_rst_meta),
+	.PRE(builder_xilinxasyncresetsynchronizerimpl0),
+	.Q(iodelay_rst)
+);
+
+(* ars_ff1 = "true", async_reg = "true" *) FDPE #(
+	.INIT(1'd1)
+) FDPE_2 (
+	.C(sys_clk),
+	.CE(1'd1),
+	.D(1'd0),
+	.PRE(builder_xilinxasyncresetsynchronizerimpl1),
+	.Q(builder_xilinxasyncresetsynchronizerimpl1_rst_meta)
+);
+
+(* ars_ff2 = "true", async_reg = "true" *) FDPE #(
+	.INIT(1'd1)
+) FDPE_3 (
+	.C(sys_clk),
+	.CE(1'd1),
+	.D(builder_xilinxasyncresetsynchronizerimpl1_rst_meta),
+	.PRE(builder_xilinxasyncresetsynchronizerimpl1),
+	.Q(sys_rst)
+);
+
+(* ars_ff1 = "true", async_reg = "true" *) FDPE #(
+	.INIT(1'd1)
+) FDPE_4 (
+	.C(sys4x_clk),
+	.CE(1'd1),
+	.D(1'd0),
+	.PRE(builder_xilinxasyncresetsynchronizerimpl2),
+	.Q(builder_xilinxasyncresetsynchronizerimpl2_rst_meta)
+);
+
+(* ars_ff2 = "true", async_reg = "true" *) FDPE #(
+	.INIT(1'd1)
+) FDPE_5 (
+	.C(sys4x_clk),
+	.CE(1'd1),
+	.D(builder_xilinxasyncresetsynchronizerimpl2_rst_meta),
+	.PRE(builder_xilinxasyncresetsynchronizerimpl2),
+	.Q(builder_xilinxasyncresetsynchronizerimpl2_expr)
+);
+
+(* ars_ff1 = "true", async_reg = "true" *) FDPE #(
+	.INIT(1'd1)
+) FDPE_6 (
+	.C(sys4x_dqs_clk),
+	.CE(1'd1),
+	.D(1'd0),
+	.PRE(builder_xilinxasyncresetsynchronizerimpl3),
+	.Q(builder_xilinxasyncresetsynchronizerimpl3_rst_meta)
+);
+
+(* ars_ff2 = "true", async_reg = "true" *) FDPE #(
+	.INIT(1'd1)
+) FDPE_7 (
+	.C(sys4x_dqs_clk),
+	.CE(1'd1),
+	.D(builder_xilinxasyncresetsynchronizerimpl3_rst_meta),
+	.PRE(builder_xilinxasyncresetsynchronizerimpl3),
+	.Q(builder_xilinxasyncresetsynchronizerimpl3_expr)
+);
+
+endmodule
diff --git a/liteeth/generated/arty/liteeth_core.v b/liteeth/generated/arty/liteeth_core.v
index 9546971..3f5ac6c 100644
--- a/liteeth/generated/arty/liteeth_core.v
+++ b/liteeth/generated/arty/liteeth_core.v
@@ -1,5 +1,5 @@
 //--------------------------------------------------------------------------------
-// Auto-generated by Migen (35203d6) & LiteX (--------) on 2021-08-09 13:54:48
+// Auto-generated by Migen (a5bc262) & LiteX (de028765) on 2021-09-24 12:37:00
 //--------------------------------------------------------------------------------
 module liteeth_core(
 	input wire sys_clock,
@@ -41,15 +41,15 @@ wire main_maccore_maccore_bus_errors_we;
 reg main_maccore_maccore_bus_errors_re = 1'd0;
 wire main_maccore_maccore_bus_error;
 reg [31:0] main_maccore_maccore_bus_errors = 32'd0;
-wire sys_clk;
+(* dont_touch = "true" *) wire sys_clk;
 wire sys_rst;
 wire por_clk;
 reg main_maccore_int_rst = 1'd1;
 reg main_maccore_ethphy_reset_storage = 1'd0;
 reg main_maccore_ethphy_reset_re = 1'd0;
-wire eth_rx_clk;
+(* dont_touch = "true" *) wire eth_rx_clk;
 wire eth_rx_rst;
-wire eth_tx_clk;
+(* dont_touch = "true" *) wire eth_tx_clk;
 wire eth_tx_rst;
 wire main_maccore_ethphy_reset0;
 wire main_maccore_ethphy_reset1;
@@ -1260,13 +1260,13 @@ end
 assign main_preamble_checker_source_payload_data = main_preamble_checker_sink_payload_data;
 assign main_preamble_checker_source_payload_last_be = main_preamble_checker_sink_payload_last_be;
 always @(*) begin
+	builder_liteethmacpreamblechecker_next_state <= 1'd0;
 	main_preamble_checker_source_first <= 1'd0;
 	main_preamble_checker_sink_ready <= 1'd0;
 	main_preamble_checker_source_last <= 1'd0;
 	main_preamble_checker_source_payload_error <= 1'd0;
 	main_preamble_checker_error <= 1'd0;
 	main_preamble_checker_source_valid <= 1'd0;
-	builder_liteethmacpreamblechecker_next_state <= 1'd0;
 	builder_liteethmacpreamblechecker_next_state <= builder_liteethmacpreamblechecker_state;
 	case (builder_liteethmacpreamblechecker_state)
 		1'd1: begin
@@ -1602,13 +1602,13 @@ assign main_padding_checker_source_payload_data = main_padding_checker_sink_payl
 assign main_padding_checker_source_payload_last_be = main_padding_checker_sink_payload_last_be;
 assign main_padding_checker_source_payload_error = main_padding_checker_sink_payload_error;
 always @(*) begin
+	main_tx_last_be_source_valid <= 1'd0;
 	main_tx_last_be_sink_ready <= 1'd0;
 	main_tx_last_be_source_first <= 1'd0;
 	main_tx_last_be_source_last <= 1'd0;
 	main_tx_last_be_source_payload_data <= 8'd0;
 	main_tx_last_be_source_payload_error <= 1'd0;
 	builder_liteethmactxlastbe_next_state <= 1'd0;
-	main_tx_last_be_source_valid <= 1'd0;
 	builder_liteethmactxlastbe_next_state <= builder_liteethmactxlastbe_state;
 	case (builder_liteethmactxlastbe_state)
 		1'd1: begin
@@ -2041,15 +2041,15 @@ assign main_writer_stat_fifo_syncfifo_dout = main_writer_stat_fifo_rdport_dat_r;
 assign main_writer_stat_fifo_syncfifo_writable = (main_writer_stat_fifo_level != 2'd2);
 assign main_writer_stat_fifo_syncfifo_readable = (main_writer_stat_fifo_level != 1'd0);
 always @(*) begin
+	main_writer_start <= 1'd0;
+	main_writer_counter_t_next_value_ce <= 1'd0;
 	main_writer_ongoing <= 1'd0;
+	main_writer_slot_ce <= 1'd0;
 	main_writer_errors_status_f_next_value <= 32'd0;
 	main_writer_stat_fifo_sink_valid <= 1'd0;
 	main_writer_errors_status_f_next_value_ce <= 1'd0;
-	main_writer_start <= 1'd0;
 	builder_liteethmacsramwriter_next_state <= 3'd0;
 	main_writer_counter_t_next_value <= 32'd0;
-	main_writer_slot_ce <= 1'd0;
-	main_writer_counter_t_next_value_ce <= 1'd0;
 	builder_liteethmacsramwriter_next_state <= builder_liteethmacsramwriter_state;
 	case (builder_liteethmacsramwriter_state)
 		1'd1: begin
@@ -2181,6 +2181,7 @@ assign main_reader_cmd_fifo_syncfifo_dout = main_reader_cmd_fifo_rdport_dat_r;
 assign main_reader_cmd_fifo_syncfifo_writable = (main_reader_cmd_fifo_level != 2'd2);
 assign main_reader_cmd_fifo_syncfifo_readable = (main_reader_cmd_fifo_level != 1'd0);
 always @(*) begin
+	main_reader_source_source_last <= 1'd0;
 	builder_liteethmacsramreader_next_state <= 2'd0;
 	main_reader_counter_next_value <= 11'd0;
 	main_reader_read_address <= 11'd0;
@@ -2189,7 +2190,6 @@ always @(*) begin
 	main_reader_eventsourcepulse_trigger <= 1'd0;
 	main_reader_source_source_valid <= 1'd0;
 	main_reader_start <= 1'd0;
-	main_reader_source_source_last <= 1'd0;
 	builder_liteethmacsramreader_next_state <= builder_liteethmacsramreader_state;
 	case (builder_liteethmacsramreader_state)
 		1'd1: begin
@@ -2292,8 +2292,8 @@ always @(*) begin
 	builder_maccore_wishbone_dat_r <= 32'd0;
 	builder_maccore_adr <= 14'd0;
 	builder_maccore_we <= 1'd0;
-	builder_maccore_dat_w <= 32'd0;
 	builder_maccore_wishbone_ack <= 1'd0;
+	builder_maccore_dat_w <= 32'd0;
 	builder_next_state <= builder_state;
 	case (builder_state)
 		1'd1: begin
@@ -2348,9 +2348,9 @@ assign builder_maccore_wishbone_cyc = (builder_shared_cyc & builder_slave_sel[1]
 assign builder_shared_err = (main_bus_err | builder_maccore_wishbone_err);
 assign builder_wait = ((builder_shared_stb & builder_shared_cyc) & (~builder_shared_ack));
 always @(*) begin
+	builder_shared_ack <= 1'd0;
 	builder_error <= 1'd0;
 	builder_shared_dat_r <= 32'd0;
-	builder_shared_ack <= 1'd0;
 	builder_shared_ack <= (main_bus_ack | builder_maccore_wishbone_ack);
 	builder_shared_dat_r <= (({32{builder_slave_sel_r[0]}} & main_bus_dat_r) | ({32{builder_slave_sel_r[1]}} & builder_maccore_wishbone_dat_r));
 	if (builder_done) begin
@@ -2381,8 +2381,8 @@ always @(*) begin
 end
 assign builder_csrbank0_bus_errors_r = builder_interface0_bank_bus_dat_w[31:0];
 always @(*) begin
-	builder_csrbank0_bus_errors_we <= 1'd0;
 	builder_csrbank0_bus_errors_re <= 1'd0;
+	builder_csrbank0_bus_errors_we <= 1'd0;
 	if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 2'd2))) begin
 		builder_csrbank0_bus_errors_re <= builder_interface0_bank_bus_we;
 		builder_csrbank0_bus_errors_we <= (~builder_interface0_bank_bus_we);
@@ -2411,8 +2411,8 @@ always @(*) begin
 end
 assign builder_csrbank1_sram_writer_length_r = builder_interface1_bank_bus_dat_w[31:0];
 always @(*) begin
-	builder_csrbank1_sram_writer_length_we <= 1'd0;
 	builder_csrbank1_sram_writer_length_re <= 1'd0;
+	builder_csrbank1_sram_writer_length_we <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 1'd1))) begin
 		builder_csrbank1_sram_writer_length_re <= builder_interface1_bank_bus_we;
 		builder_csrbank1_sram_writer_length_we <= (~builder_interface1_bank_bus_we);
@@ -2429,8 +2429,8 @@ always @(*) begin
 end
 assign builder_csrbank1_sram_writer_ev_status_r = builder_interface1_bank_bus_dat_w[0];
 always @(*) begin
-	builder_csrbank1_sram_writer_ev_status_re <= 1'd0;
 	builder_csrbank1_sram_writer_ev_status_we <= 1'd0;
+	builder_csrbank1_sram_writer_ev_status_re <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 2'd3))) begin
 		builder_csrbank1_sram_writer_ev_status_re <= builder_interface1_bank_bus_we;
 		builder_csrbank1_sram_writer_ev_status_we <= (~builder_interface1_bank_bus_we);
@@ -2465,8 +2465,8 @@ always @(*) begin
 end
 assign builder_csrbank1_sram_reader_ready_r = builder_interface1_bank_bus_dat_w[0];
 always @(*) begin
-	builder_csrbank1_sram_reader_ready_re <= 1'd0;
 	builder_csrbank1_sram_reader_ready_we <= 1'd0;
+	builder_csrbank1_sram_reader_ready_re <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd7))) begin
 		builder_csrbank1_sram_reader_ready_re <= builder_interface1_bank_bus_we;
 		builder_csrbank1_sram_reader_ready_we <= (~builder_interface1_bank_bus_we);
@@ -2483,8 +2483,8 @@ always @(*) begin
 end
 assign builder_csrbank1_sram_reader_slot0_r = builder_interface1_bank_bus_dat_w[0];
 always @(*) begin
-	builder_csrbank1_sram_reader_slot0_we <= 1'd0;
 	builder_csrbank1_sram_reader_slot0_re <= 1'd0;
+	builder_csrbank1_sram_reader_slot0_we <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd9))) begin
 		builder_csrbank1_sram_reader_slot0_re <= builder_interface1_bank_bus_we;
 		builder_csrbank1_sram_reader_slot0_we <= (~builder_interface1_bank_bus_we);
@@ -2510,8 +2510,8 @@ always @(*) begin
 end
 assign builder_csrbank1_sram_reader_ev_pending_r = builder_interface1_bank_bus_dat_w[0];
 always @(*) begin
-	builder_csrbank1_sram_reader_ev_pending_we <= 1'd0;
 	builder_csrbank1_sram_reader_ev_pending_re <= 1'd0;
+	builder_csrbank1_sram_reader_ev_pending_we <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd12))) begin
 		builder_csrbank1_sram_reader_ev_pending_re <= builder_interface1_bank_bus_we;
 		builder_csrbank1_sram_reader_ev_pending_we <= (~builder_interface1_bank_bus_we);
@@ -2537,8 +2537,8 @@ always @(*) begin
 end
 assign builder_csrbank1_preamble_errors_r = builder_interface1_bank_bus_dat_w[31:0];
 always @(*) begin
-	builder_csrbank1_preamble_errors_we <= 1'd0;
 	builder_csrbank1_preamble_errors_re <= 1'd0;
+	builder_csrbank1_preamble_errors_we <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 4'd15))) begin
 		builder_csrbank1_preamble_errors_re <= builder_interface1_bank_bus_we;
 		builder_csrbank1_preamble_errors_we <= (~builder_interface1_bank_bus_we);
@@ -2608,8 +2608,8 @@ always @(*) begin
 end
 assign builder_csrbank2_mdio_r_r = builder_interface2_bank_bus_dat_w[0];
 always @(*) begin
-	builder_csrbank2_mdio_r_we <= 1'd0;
 	builder_csrbank2_mdio_r_re <= 1'd0;
+	builder_csrbank2_mdio_r_we <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 2'd2))) begin
 		builder_csrbank2_mdio_r_re <= builder_interface2_bank_bus_we;
 		builder_csrbank2_mdio_r_we <= (~builder_interface2_bank_bus_we);
@@ -3334,275 +3334,95 @@ end
 assign main_writer_stat_fifo_wrport_dat_r = memdat_1;
 assign main_writer_stat_fifo_rdport_dat_r = storage_3[main_writer_stat_fifo_rdport_adr];
 
-reg [13:0] storage_4[0:1];
-reg [13:0] memdat_2;
-always @(posedge sys_clk) begin
-	if (main_reader_cmd_fifo_wrport_we)
-		storage_4[main_reader_cmd_fifo_wrport_adr] <= main_reader_cmd_fifo_wrport_dat_w;
-	memdat_2 <= storage_4[main_reader_cmd_fifo_wrport_adr];
-end
-
-always @(posedge sys_clk) begin
-end
-
-assign main_reader_cmd_fifo_wrport_dat_r = memdat_2;
-assign main_reader_cmd_fifo_rdport_dat_r = storage_4[main_reader_cmd_fifo_rdport_adr];
-
-reg [7:0] mem_grain0[0:381];
+reg [31:0] mem[0:381];
 reg [8:0] memadr_4;
-reg [7:0] memdat_3;
+reg [31:0] memdat_2;
 always @(posedge sys_clk) begin
 	if (main_writer_memory0_we)
-		mem_grain0[main_writer_memory0_adr] <= main_writer_memory0_dat_w[7:0];
+		mem[main_writer_memory0_adr] <= main_writer_memory0_dat_w;
 	memadr_4 <= main_writer_memory0_adr;
 end
 
 always @(posedge sys_clk) begin
-	memdat_3 <= mem_grain0[main_sram0_adr0];
+	memdat_2 <= mem[main_sram0_adr0];
 end
 
-assign main_writer_memory0_dat_r[7:0] = mem_grain0[memadr_4];
-assign main_sram0_dat_r0[7:0] = memdat_3;
+assign main_writer_memory0_dat_r = mem[memadr_4];
+assign main_sram0_dat_r0 = memdat_2;
 
-reg [7:0] mem_grain1[0:381];
+reg [31:0] mem_1[0:381];
 reg [8:0] memadr_5;
-reg [7:0] memdat_4;
-always @(posedge sys_clk) begin
-	if (main_writer_memory0_we)
-		mem_grain1[main_writer_memory0_adr] <= main_writer_memory0_dat_w[15:8];
-	memadr_5 <= main_writer_memory0_adr;
-end
-
-always @(posedge sys_clk) begin
-	memdat_4 <= mem_grain1[main_sram0_adr0];
-end
-
-assign main_writer_memory0_dat_r[15:8] = mem_grain1[memadr_5];
-assign main_sram0_dat_r0[15:8] = memdat_4;
-
-reg [7:0] mem_grain2[0:381];
-reg [8:0] memadr_6;
-reg [7:0] memdat_5;
-always @(posedge sys_clk) begin
-	if (main_writer_memory0_we)
-		mem_grain2[main_writer_memory0_adr] <= main_writer_memory0_dat_w[23:16];
-	memadr_6 <= main_writer_memory0_adr;
-end
-
-always @(posedge sys_clk) begin
-	memdat_5 <= mem_grain2[main_sram0_adr0];
-end
-
-assign main_writer_memory0_dat_r[23:16] = mem_grain2[memadr_6];
-assign main_sram0_dat_r0[23:16] = memdat_5;
-
-reg [7:0] mem_grain3[0:381];
-reg [8:0] memadr_7;
-reg [7:0] memdat_6;
-always @(posedge sys_clk) begin
-	if (main_writer_memory0_we)
-		mem_grain3[main_writer_memory0_adr] <= main_writer_memory0_dat_w[31:24];
-	memadr_7 <= main_writer_memory0_adr;
-end
-
-always @(posedge sys_clk) begin
-	memdat_6 <= mem_grain3[main_sram0_adr0];
-end
-
-assign main_writer_memory0_dat_r[31:24] = mem_grain3[memadr_7];
-assign main_sram0_dat_r0[31:24] = memdat_6;
-
-reg [7:0] mem_grain0_1[0:381];
-reg [8:0] memadr_8;
-reg [7:0] memdat_7;
-always @(posedge sys_clk) begin
-	if (main_writer_memory1_we)
-		mem_grain0_1[main_writer_memory1_adr] <= main_writer_memory1_dat_w[7:0];
-	memadr_8 <= main_writer_memory1_adr;
-end
-
-always @(posedge sys_clk) begin
-	memdat_7 <= mem_grain0_1[main_sram1_adr0];
-end
-
-assign main_writer_memory1_dat_r[7:0] = mem_grain0_1[memadr_8];
-assign main_sram1_dat_r0[7:0] = memdat_7;
-
-reg [7:0] mem_grain1_1[0:381];
-reg [8:0] memadr_9;
-reg [7:0] memdat_8;
-always @(posedge sys_clk) begin
-	if (main_writer_memory1_we)
-		mem_grain1_1[main_writer_memory1_adr] <= main_writer_memory1_dat_w[15:8];
-	memadr_9 <= main_writer_memory1_adr;
-end
-
-always @(posedge sys_clk) begin
-	memdat_8 <= mem_grain1_1[main_sram1_adr0];
-end
-
-assign main_writer_memory1_dat_r[15:8] = mem_grain1_1[memadr_9];
-assign main_sram1_dat_r0[15:8] = memdat_8;
-
-reg [7:0] mem_grain2_1[0:381];
-reg [8:0] memadr_10;
-reg [7:0] memdat_9;
+reg [31:0] memdat_3;
 always @(posedge sys_clk) begin
 	if (main_writer_memory1_we)
-		mem_grain2_1[main_writer_memory1_adr] <= main_writer_memory1_dat_w[23:16];
-	memadr_10 <= main_writer_memory1_adr;
+		mem_1[main_writer_memory1_adr] <= main_writer_memory1_dat_w;
+	memadr_5 <= main_writer_memory1_adr;
 end
 
 always @(posedge sys_clk) begin
-	memdat_9 <= mem_grain2_1[main_sram1_adr0];
+	memdat_3 <= mem_1[main_sram1_adr0];
 end
 
-assign main_writer_memory1_dat_r[23:16] = mem_grain2_1[memadr_10];
-assign main_sram1_dat_r0[23:16] = memdat_9;
+assign main_writer_memory1_dat_r = mem_1[memadr_5];
+assign main_sram1_dat_r0 = memdat_3;
 
-reg [7:0] mem_grain3_1[0:381];
-reg [8:0] memadr_11;
-reg [7:0] memdat_10;
+reg [13:0] storage_4[0:1];
+reg [13:0] memdat_4;
 always @(posedge sys_clk) begin
-	if (main_writer_memory1_we)
-		mem_grain3_1[main_writer_memory1_adr] <= main_writer_memory1_dat_w[31:24];
-	memadr_11 <= main_writer_memory1_adr;
+	if (main_reader_cmd_fifo_wrport_we)
+		storage_4[main_reader_cmd_fifo_wrport_adr] <= main_reader_cmd_fifo_wrport_dat_w;
+	memdat_4 <= storage_4[main_reader_cmd_fifo_wrport_adr];
 end
 
 always @(posedge sys_clk) begin
-	memdat_10 <= mem_grain3_1[main_sram1_adr0];
 end
 
-assign main_writer_memory1_dat_r[31:24] = mem_grain3_1[memadr_11];
-assign main_sram1_dat_r0[31:24] = memdat_10;
+assign main_reader_cmd_fifo_wrport_dat_r = memdat_4;
+assign main_reader_cmd_fifo_rdport_dat_r = storage_4[main_reader_cmd_fifo_rdport_adr];
 
-reg [7:0] mem_grain0_2[0:381];
-reg [8:0] memadr_12;
-reg [8:0] memadr_13;
+reg [31:0] mem_2[0:381];
+reg [8:0] memadr_6;
+reg [8:0] memadr_7;
 always @(posedge sys_clk) begin
-	memadr_12 <= main_reader_memory0_adr;
+	memadr_6 <= main_reader_memory0_adr;
 end
 
 always @(posedge sys_clk) begin
 	if (main_sram0_we[0])
-		mem_grain0_2[main_sram0_adr1] <= main_sram0_dat_w[7:0];
-	memadr_13 <= main_sram0_adr1;
-end
-
-assign main_reader_memory0_dat_r[7:0] = mem_grain0_2[memadr_12];
-assign main_sram0_dat_r1[7:0] = mem_grain0_2[memadr_13];
-
-reg [7:0] mem_grain1_2[0:381];
-reg [8:0] memadr_14;
-reg [8:0] memadr_15;
-always @(posedge sys_clk) begin
-	memadr_14 <= main_reader_memory0_adr;
-end
-
-always @(posedge sys_clk) begin
+		mem_2[main_sram0_adr1][7:0] <= main_sram0_dat_w[7:0];
 	if (main_sram0_we[1])
-		mem_grain1_2[main_sram0_adr1] <= main_sram0_dat_w[15:8];
-	memadr_15 <= main_sram0_adr1;
-end
-
-assign main_reader_memory0_dat_r[15:8] = mem_grain1_2[memadr_14];
-assign main_sram0_dat_r1[15:8] = mem_grain1_2[memadr_15];
-
-reg [7:0] mem_grain2_2[0:381];
-reg [8:0] memadr_16;
-reg [8:0] memadr_17;
-always @(posedge sys_clk) begin
-	memadr_16 <= main_reader_memory0_adr;
-end
-
-always @(posedge sys_clk) begin
+		mem_2[main_sram0_adr1][15:8] <= main_sram0_dat_w[15:8];
 	if (main_sram0_we[2])
-		mem_grain2_2[main_sram0_adr1] <= main_sram0_dat_w[23:16];
-	memadr_17 <= main_sram0_adr1;
-end
-
-assign main_reader_memory0_dat_r[23:16] = mem_grain2_2[memadr_16];
-assign main_sram0_dat_r1[23:16] = mem_grain2_2[memadr_17];
-
-reg [7:0] mem_grain3_2[0:381];
-reg [8:0] memadr_18;
-reg [8:0] memadr_19;
-always @(posedge sys_clk) begin
-	memadr_18 <= main_reader_memory0_adr;
-end
-
-always @(posedge sys_clk) begin
+		mem_2[main_sram0_adr1][23:16] <= main_sram0_dat_w[23:16];
 	if (main_sram0_we[3])
-		mem_grain3_2[main_sram0_adr1] <= main_sram0_dat_w[31:24];
-	memadr_19 <= main_sram0_adr1;
+		mem_2[main_sram0_adr1][31:24] <= main_sram0_dat_w[31:24];
+	memadr_7 <= main_sram0_adr1;
 end
 
-assign main_reader_memory0_dat_r[31:24] = mem_grain3_2[memadr_18];
-assign main_sram0_dat_r1[31:24] = mem_grain3_2[memadr_19];
+assign main_reader_memory0_dat_r = mem_2[memadr_6];
+assign main_sram0_dat_r1 = mem_2[memadr_7];
 
-reg [7:0] mem_grain0_3[0:381];
-reg [8:0] memadr_20;
-reg [8:0] memadr_21;
+reg [31:0] mem_3[0:381];
+reg [8:0] memadr_8;
+reg [8:0] memadr_9;
 always @(posedge sys_clk) begin
-	memadr_20 <= main_reader_memory1_adr;
+	memadr_8 <= main_reader_memory1_adr;
 end
 
 always @(posedge sys_clk) begin
 	if (main_sram1_we[0])
-		mem_grain0_3[main_sram1_adr1] <= main_sram1_dat_w[7:0];
-	memadr_21 <= main_sram1_adr1;
-end
-
-assign main_reader_memory1_dat_r[7:0] = mem_grain0_3[memadr_20];
-assign main_sram1_dat_r1[7:0] = mem_grain0_3[memadr_21];
-
-reg [7:0] mem_grain1_3[0:381];
-reg [8:0] memadr_22;
-reg [8:0] memadr_23;
-always @(posedge sys_clk) begin
-	memadr_22 <= main_reader_memory1_adr;
-end
-
-always @(posedge sys_clk) begin
+		mem_3[main_sram1_adr1][7:0] <= main_sram1_dat_w[7:0];
 	if (main_sram1_we[1])
-		mem_grain1_3[main_sram1_adr1] <= main_sram1_dat_w[15:8];
-	memadr_23 <= main_sram1_adr1;
-end
-
-assign main_reader_memory1_dat_r[15:8] = mem_grain1_3[memadr_22];
-assign main_sram1_dat_r1[15:8] = mem_grain1_3[memadr_23];
-
-reg [7:0] mem_grain2_3[0:381];
-reg [8:0] memadr_24;
-reg [8:0] memadr_25;
-always @(posedge sys_clk) begin
-	memadr_24 <= main_reader_memory1_adr;
-end
-
-always @(posedge sys_clk) begin
+		mem_3[main_sram1_adr1][15:8] <= main_sram1_dat_w[15:8];
 	if (main_sram1_we[2])
-		mem_grain2_3[main_sram1_adr1] <= main_sram1_dat_w[23:16];
-	memadr_25 <= main_sram1_adr1;
-end
-
-assign main_reader_memory1_dat_r[23:16] = mem_grain2_3[memadr_24];
-assign main_sram1_dat_r1[23:16] = mem_grain2_3[memadr_25];
-
-reg [7:0] mem_grain3_3[0:381];
-reg [8:0] memadr_26;
-reg [8:0] memadr_27;
-always @(posedge sys_clk) begin
-	memadr_26 <= main_reader_memory1_adr;
-end
-
-always @(posedge sys_clk) begin
+		mem_3[main_sram1_adr1][23:16] <= main_sram1_dat_w[23:16];
 	if (main_sram1_we[3])
-		mem_grain3_3[main_sram1_adr1] <= main_sram1_dat_w[31:24];
-	memadr_27 <= main_sram1_adr1;
+		mem_3[main_sram1_adr1][31:24] <= main_sram1_dat_w[31:24];
+	memadr_9 <= main_sram1_adr1;
 end
 
-assign main_reader_memory1_dat_r[31:24] = mem_grain3_3[memadr_26];
-assign main_sram1_dat_r1[31:24] = mem_grain3_3[memadr_27];
+assign main_reader_memory1_dat_r = mem_3[memadr_8];
+assign main_sram1_dat_r1 = mem_3[memadr_9];
 
 (* ars_ff1 = "true", async_reg = "true" *) FDPE #(
 	.INIT(1'd1)
diff --git a/liteeth/generated/nexys-video/liteeth_core.v b/liteeth/generated/nexys-video/liteeth_core.v
index 925d3e7..6fd6fb3 100644
--- a/liteeth/generated/nexys-video/liteeth_core.v
+++ b/liteeth/generated/nexys-video/liteeth_core.v
@@ -1,5 +1,5 @@
 //--------------------------------------------------------------------------------
-// Auto-generated by Migen (35203d6) & LiteX (--------) on 2021-08-09 13:54:49
+// Auto-generated by Migen (a5bc262) & LiteX (de028765) on 2021-09-24 12:37:01
 //--------------------------------------------------------------------------------
 module liteeth_core(
 	input wire sys_clock,
@@ -39,16 +39,16 @@ wire main_maccore_maccore_bus_errors_we;
 reg main_maccore_maccore_bus_errors_re = 1'd0;
 wire main_maccore_maccore_bus_error;
 reg [31:0] main_maccore_maccore_bus_errors = 32'd0;
-wire sys_clk;
+(* dont_touch = "true" *) wire sys_clk;
 wire sys_rst;
 wire por_clk;
 reg main_maccore_int_rst = 1'd1;
 reg main_maccore_ethphy_reset_storage = 1'd0;
 reg main_maccore_ethphy_reset_re = 1'd0;
-wire eth_rx_clk;
+(* dont_touch = "true" *) wire eth_rx_clk;
 wire eth_rx_rst;
 wire main_maccore_ethphy_eth_rx_clk_ibuf;
-wire eth_tx_clk;
+(* dont_touch = "true" *) wire eth_tx_clk;
 wire eth_tx_rst;
 wire eth_tx_delayed_clk;
 reg main_maccore_ethphy_reset0 = 1'd0;
@@ -1051,6 +1051,7 @@ assign main_sink_payload_error = main_rx_cdc_source_source_payload_error;
 assign main_ps_preamble_error_i = main_preamble_checker_error;
 assign main_ps_crc_error_i = main_liteethmaccrc32checker_error;
 always @(*) begin
+	main_tx_gap_inserter_source_payload_last_be <= 1'd0;
 	main_tx_gap_inserter_source_payload_error <= 1'd0;
 	main_tx_gap_inserter_sink_ready <= 1'd0;
 	main_tx_gap_inserter_source_valid <= 1'd0;
@@ -1060,7 +1061,6 @@ always @(*) begin
 	main_tx_gap_inserter_counter_liteethmacgap_next_value_ce <= 1'd0;
 	main_tx_gap_inserter_source_last <= 1'd0;
 	main_tx_gap_inserter_source_payload_data <= 8'd0;
-	main_tx_gap_inserter_source_payload_last_be <= 1'd0;
 	builder_liteethmacgap_next_state <= builder_liteethmacgap_state;
 	case (builder_liteethmacgap_state)
 		1'd1: begin
@@ -1163,8 +1163,8 @@ assign main_preamble_checker_source_payload_last_be = main_preamble_checker_sink
 always @(*) begin
 	main_preamble_checker_source_payload_error <= 1'd0;
 	main_preamble_checker_error <= 1'd0;
-	main_preamble_checker_sink_ready <= 1'd0;
 	main_preamble_checker_source_valid <= 1'd0;
+	main_preamble_checker_sink_ready <= 1'd0;
 	builder_liteethmacpreamblechecker_next_state <= 1'd0;
 	main_preamble_checker_source_first <= 1'd0;
 	main_preamble_checker_source_last <= 1'd0;
@@ -1445,6 +1445,7 @@ assign main_ps_preamble_error_o = (main_ps_preamble_error_toggle_o ^ main_ps_pre
 assign main_ps_crc_error_o = (main_ps_crc_error_toggle_o ^ main_ps_crc_error_toggle_o_r);
 assign main_padding_inserter_counter_done = (main_padding_inserter_counter >= 6'd59);
 always @(*) begin
+	builder_liteethmacpaddinginserter_next_state <= 1'd0;
 	main_padding_inserter_counter_liteethmacpaddinginserter_next_value <= 16'd0;
 	main_padding_inserter_counter_liteethmacpaddinginserter_next_value_ce <= 1'd0;
 	main_padding_inserter_sink_ready <= 1'd0;
@@ -1454,7 +1455,6 @@ always @(*) begin
 	main_padding_inserter_source_payload_data <= 8'd0;
 	main_padding_inserter_source_payload_last_be <= 1'd0;
 	main_padding_inserter_source_payload_error <= 1'd0;
-	builder_liteethmacpaddinginserter_next_state <= 1'd0;
 	builder_liteethmacpaddinginserter_next_state <= builder_liteethmacpaddinginserter_state;
 	case (builder_liteethmacpaddinginserter_state)
 		1'd1: begin
@@ -1945,8 +1945,8 @@ always @(*) begin
 	builder_liteethmacsramwriter_next_state <= 3'd0;
 	main_writer_slot_ce <= 1'd0;
 	main_writer_counter_t_next_value <= 32'd0;
-	main_writer_start <= 1'd0;
 	main_writer_counter_t_next_value_ce <= 1'd0;
+	main_writer_start <= 1'd0;
 	main_writer_ongoing <= 1'd0;
 	main_writer_errors_status_f_next_value <= 32'd0;
 	main_writer_stat_fifo_sink_valid <= 1'd0;
@@ -2191,8 +2191,8 @@ assign main_bus_dat_r = (((({32{main_slave_sel_r[0]}} & main_sram0_bus_dat_r0) |
 always @(*) begin
 	builder_maccore_adr <= 14'd0;
 	builder_maccore_we <= 1'd0;
-	builder_maccore_wishbone_ack <= 1'd0;
 	builder_maccore_dat_w <= 32'd0;
+	builder_maccore_wishbone_ack <= 1'd0;
 	builder_next_state <= 1'd0;
 	builder_maccore_wishbone_dat_r <= 32'd0;
 	builder_next_state <= builder_state;
@@ -2250,8 +2250,8 @@ assign builder_shared_err = (main_bus_err | builder_maccore_wishbone_err);
 assign builder_wait = ((builder_shared_stb & builder_shared_cyc) & (~builder_shared_ack));
 always @(*) begin
 	builder_shared_ack <= 1'd0;
-	builder_shared_dat_r <= 32'd0;
 	builder_error <= 1'd0;
+	builder_shared_dat_r <= 32'd0;
 	builder_shared_ack <= (main_bus_ack | builder_maccore_wishbone_ack);
 	builder_shared_dat_r <= (({32{builder_slave_sel_r[0]}} & main_bus_dat_r) | ({32{builder_slave_sel_r[1]}} & builder_maccore_wishbone_dat_r));
 	if (builder_done) begin
@@ -2273,8 +2273,8 @@ always @(*) begin
 end
 assign builder_csrbank0_scratch0_r = builder_interface0_bank_bus_dat_w[31:0];
 always @(*) begin
-	builder_csrbank0_scratch0_we <= 1'd0;
 	builder_csrbank0_scratch0_re <= 1'd0;
+	builder_csrbank0_scratch0_we <= 1'd0;
 	if ((builder_csrbank0_sel & (builder_interface0_bank_bus_adr[8:0] == 1'd1))) begin
 		builder_csrbank0_scratch0_re <= builder_interface0_bank_bus_we;
 		builder_csrbank0_scratch0_we <= (~builder_interface0_bank_bus_we);
@@ -2348,8 +2348,8 @@ always @(*) begin
 end
 assign builder_csrbank1_sram_writer_ev_enable0_r = builder_interface1_bank_bus_dat_w[0];
 always @(*) begin
-	builder_csrbank1_sram_writer_ev_enable0_re <= 1'd0;
 	builder_csrbank1_sram_writer_ev_enable0_we <= 1'd0;
+	builder_csrbank1_sram_writer_ev_enable0_re <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd5))) begin
 		builder_csrbank1_sram_writer_ev_enable0_re <= builder_interface1_bank_bus_we;
 		builder_csrbank1_sram_writer_ev_enable0_we <= (~builder_interface1_bank_bus_we);
@@ -2357,8 +2357,8 @@ always @(*) begin
 end
 assign main_reader_start_start_r = builder_interface1_bank_bus_dat_w[0];
 always @(*) begin
-	main_reader_start_start_re <= 1'd0;
 	main_reader_start_start_we <= 1'd0;
+	main_reader_start_start_re <= 1'd0;
 	if ((builder_csrbank1_sel & (builder_interface1_bank_bus_adr[8:0] == 3'd6))) begin
 		main_reader_start_start_re <= builder_interface1_bank_bus_we;
 		main_reader_start_start_we <= (~builder_interface1_bank_bus_we);
@@ -2500,8 +2500,8 @@ always @(*) begin
 end
 assign builder_csrbank2_mdio_w0_r = builder_interface2_bank_bus_dat_w[2:0];
 always @(*) begin
-	builder_csrbank2_mdio_w0_we <= 1'd0;
 	builder_csrbank2_mdio_w0_re <= 1'd0;
+	builder_csrbank2_mdio_w0_we <= 1'd0;
 	if ((builder_csrbank2_sel & (builder_interface2_bank_bus_adr[8:0] == 1'd1))) begin
 		builder_csrbank2_mdio_w0_re <= builder_interface2_bank_bus_we;
 		builder_csrbank2_mdio_w0_we <= (~builder_interface2_bank_bus_we);
@@ -3451,20 +3451,96 @@ end
 assign main_writer_stat_fifo_wrport_dat_r = memdat_1;
 assign main_writer_stat_fifo_rdport_dat_r = storage_3[main_writer_stat_fifo_rdport_adr];
 
+reg [31:0] mem[0:381];
+reg [8:0] memadr_4;
+reg [31:0] memdat_2;
+always @(posedge sys_clk) begin
+	if (main_writer_memory0_we)
+		mem[main_writer_memory0_adr] <= main_writer_memory0_dat_w;
+	memadr_4 <= main_writer_memory0_adr;
+end
+
+always @(posedge sys_clk) begin
+	memdat_2 <= mem[main_sram0_adr0];
+end
+
+assign main_writer_memory0_dat_r = mem[memadr_4];
+assign main_sram0_dat_r0 = memdat_2;
+
+reg [31:0] mem_1[0:381];
+reg [8:0] memadr_5;
+reg [31:0] memdat_3;
+always @(posedge sys_clk) begin
+	if (main_writer_memory1_we)
+		mem_1[main_writer_memory1_adr] <= main_writer_memory1_dat_w;
+	memadr_5 <= main_writer_memory1_adr;
+end
+
+always @(posedge sys_clk) begin
+	memdat_3 <= mem_1[main_sram1_adr0];
+end
+
+assign main_writer_memory1_dat_r = mem_1[memadr_5];
+assign main_sram1_dat_r0 = memdat_3;
+
 reg [13:0] storage_4[0:1];
-reg [13:0] memdat_2;
+reg [13:0] memdat_4;
 always @(posedge sys_clk) begin
 	if (main_reader_cmd_fifo_wrport_we)
 		storage_4[main_reader_cmd_fifo_wrport_adr] <= main_reader_cmd_fifo_wrport_dat_w;
-	memdat_2 <= storage_4[main_reader_cmd_fifo_wrport_adr];
+	memdat_4 <= storage_4[main_reader_cmd_fifo_wrport_adr];
 end
 
 always @(posedge sys_clk) begin
 end
 
-assign main_reader_cmd_fifo_wrport_dat_r = memdat_2;
+assign main_reader_cmd_fifo_wrport_dat_r = memdat_4;
 assign main_reader_cmd_fifo_rdport_dat_r = storage_4[main_reader_cmd_fifo_rdport_adr];
 
+reg [31:0] mem_2[0:381];
+reg [8:0] memadr_6;
+reg [8:0] memadr_7;
+always @(posedge sys_clk) begin
+	memadr_6 <= main_reader_memory0_adr;
+end
+
+always @(posedge sys_clk) begin
+	if (main_sram0_we[0])
+		mem_2[main_sram0_adr1][7:0] <= main_sram0_dat_w[7:0];
+	if (main_sram0_we[1])
+		mem_2[main_sram0_adr1][15:8] <= main_sram0_dat_w[15:8];
+	if (main_sram0_we[2])
+		mem_2[main_sram0_adr1][23:16] <= main_sram0_dat_w[23:16];
+	if (main_sram0_we[3])
+		mem_2[main_sram0_adr1][31:24] <= main_sram0_dat_w[31:24];
+	memadr_7 <= main_sram0_adr1;
+end
+
+assign main_reader_memory0_dat_r = mem_2[memadr_6];
+assign main_sram0_dat_r1 = mem_2[memadr_7];
+
+reg [31:0] mem_3[0:381];
+reg [8:0] memadr_8;
+reg [8:0] memadr_9;
+always @(posedge sys_clk) begin
+	memadr_8 <= main_reader_memory1_adr;
+end
+
+always @(posedge sys_clk) begin
+	if (main_sram1_we[0])
+		mem_3[main_sram1_adr1][7:0] <= main_sram1_dat_w[7:0];
+	if (main_sram1_we[1])
+		mem_3[main_sram1_adr1][15:8] <= main_sram1_dat_w[15:8];
+	if (main_sram1_we[2])
+		mem_3[main_sram1_adr1][23:16] <= main_sram1_dat_w[23:16];
+	if (main_sram1_we[3])
+		mem_3[main_sram1_adr1][31:24] <= main_sram1_dat_w[31:24];
+	memadr_9 <= main_sram1_adr1;
+end
+
+assign main_reader_memory1_dat_r = mem_3[memadr_8];
+assign main_sram1_dat_r1 = mem_3[memadr_9];
+
 FD FD(
 	.C(main_maccore_ethphy_clkin),
 	.D(main_maccore_ethphy_reset0),
@@ -3534,262 +3610,6 @@ PLLE2_ADV #(
 	.LOCKED(main_maccore_ethphy_locked)
 );
 
-reg [7:0] mem_grain0[0:381];
-reg [8:0] memadr_4;
-reg [7:0] memdat_3;
-always @(posedge sys_clk) begin
-	if (main_writer_memory0_we)
-		mem_grain0[main_writer_memory0_adr] <= main_writer_memory0_dat_w[7:0];
-	memadr_4 <= main_writer_memory0_adr;
-end
-
-always @(posedge sys_clk) begin
-	memdat_3 <= mem_grain0[main_sram0_adr0];
-end
-
-assign main_writer_memory0_dat_r[7:0] = mem_grain0[memadr_4];
-assign main_sram0_dat_r0[7:0] = memdat_3;
-
-reg [7:0] mem_grain1[0:381];
-reg [8:0] memadr_5;
-reg [7:0] memdat_4;
-always @(posedge sys_clk) begin
-	if (main_writer_memory0_we)
-		mem_grain1[main_writer_memory0_adr] <= main_writer_memory0_dat_w[15:8];
-	memadr_5 <= main_writer_memory0_adr;
-end
-
-always @(posedge sys_clk) begin
-	memdat_4 <= mem_grain1[main_sram0_adr0];
-end
-
-assign main_writer_memory0_dat_r[15:8] = mem_grain1[memadr_5];
-assign main_sram0_dat_r0[15:8] = memdat_4;
-
-reg [7:0] mem_grain2[0:381];
-reg [8:0] memadr_6;
-reg [7:0] memdat_5;
-always @(posedge sys_clk) begin
-	if (main_writer_memory0_we)
-		mem_grain2[main_writer_memory0_adr] <= main_writer_memory0_dat_w[23:16];
-	memadr_6 <= main_writer_memory0_adr;
-end
-
-always @(posedge sys_clk) begin
-	memdat_5 <= mem_grain2[main_sram0_adr0];
-end
-
-assign main_writer_memory0_dat_r[23:16] = mem_grain2[memadr_6];
-assign main_sram0_dat_r0[23:16] = memdat_5;
-
-reg [7:0] mem_grain3[0:381];
-reg [8:0] memadr_7;
-reg [7:0] memdat_6;
-always @(posedge sys_clk) begin
-	if (main_writer_memory0_we)
-		mem_grain3[main_writer_memory0_adr] <= main_writer_memory0_dat_w[31:24];
-	memadr_7 <= main_writer_memory0_adr;
-end
-
-always @(posedge sys_clk) begin
-	memdat_6 <= mem_grain3[main_sram0_adr0];
-end
-
-assign main_writer_memory0_dat_r[31:24] = mem_grain3[memadr_7];
-assign main_sram0_dat_r0[31:24] = memdat_6;
-
-reg [7:0] mem_grain0_1[0:381];
-reg [8:0] memadr_8;
-reg [7:0] memdat_7;
-always @(posedge sys_clk) begin
-	if (main_writer_memory1_we)
-		mem_grain0_1[main_writer_memory1_adr] <= main_writer_memory1_dat_w[7:0];
-	memadr_8 <= main_writer_memory1_adr;
-end
-
-always @(posedge sys_clk) begin
-	memdat_7 <= mem_grain0_1[main_sram1_adr0];
-end
-
-assign main_writer_memory1_dat_r[7:0] = mem_grain0_1[memadr_8];
-assign main_sram1_dat_r0[7:0] = memdat_7;
-
-reg [7:0] mem_grain1_1[0:381];
-reg [8:0] memadr_9;
-reg [7:0] memdat_8;
-always @(posedge sys_clk) begin
-	if (main_writer_memory1_we)
-		mem_grain1_1[main_writer_memory1_adr] <= main_writer_memory1_dat_w[15:8];
-	memadr_9 <= main_writer_memory1_adr;
-end
-
-always @(posedge sys_clk) begin
-	memdat_8 <= mem_grain1_1[main_sram1_adr0];
-end
-
-assign main_writer_memory1_dat_r[15:8] = mem_grain1_1[memadr_9];
-assign main_sram1_dat_r0[15:8] = memdat_8;
-
-reg [7:0] mem_grain2_1[0:381];
-reg [8:0] memadr_10;
-reg [7:0] memdat_9;
-always @(posedge sys_clk) begin
-	if (main_writer_memory1_we)
-		mem_grain2_1[main_writer_memory1_adr] <= main_writer_memory1_dat_w[23:16];
-	memadr_10 <= main_writer_memory1_adr;
-end
-
-always @(posedge sys_clk) begin
-	memdat_9 <= mem_grain2_1[main_sram1_adr0];
-end
-
-assign main_writer_memory1_dat_r[23:16] = mem_grain2_1[memadr_10];
-assign main_sram1_dat_r0[23:16] = memdat_9;
-
-reg [7:0] mem_grain3_1[0:381];
-reg [8:0] memadr_11;
-reg [7:0] memdat_10;
-always @(posedge sys_clk) begin
-	if (main_writer_memory1_we)
-		mem_grain3_1[main_writer_memory1_adr] <= main_writer_memory1_dat_w[31:24];
-	memadr_11 <= main_writer_memory1_adr;
-end
-
-always @(posedge sys_clk) begin
-	memdat_10 <= mem_grain3_1[main_sram1_adr0];
-end
-
-assign main_writer_memory1_dat_r[31:24] = mem_grain3_1[memadr_11];
-assign main_sram1_dat_r0[31:24] = memdat_10;
-
-reg [7:0] mem_grain0_2[0:381];
-reg [8:0] memadr_12;
-reg [8:0] memadr_13;
-always @(posedge sys_clk) begin
-	memadr_12 <= main_reader_memory0_adr;
-end
-
-always @(posedge sys_clk) begin
-	if (main_sram0_we[0])
-		mem_grain0_2[main_sram0_adr1] <= main_sram0_dat_w[7:0];
-	memadr_13 <= main_sram0_adr1;
-end
-
-assign main_reader_memory0_dat_r[7:0] = mem_grain0_2[memadr_12];
-assign main_sram0_dat_r1[7:0] = mem_grain0_2[memadr_13];
-
-reg [7:0] mem_grain1_2[0:381];
-reg [8:0] memadr_14;
-reg [8:0] memadr_15;
-always @(posedge sys_clk) begin
-	memadr_14 <= main_reader_memory0_adr;
-end
-
-always @(posedge sys_clk) begin
-	if (main_sram0_we[1])
-		mem_grain1_2[main_sram0_adr1] <= main_sram0_dat_w[15:8];
-	memadr_15 <= main_sram0_adr1;
-end
-
-assign main_reader_memory0_dat_r[15:8] = mem_grain1_2[memadr_14];
-assign main_sram0_dat_r1[15:8] = mem_grain1_2[memadr_15];
-
-reg [7:0] mem_grain2_2[0:381];
-reg [8:0] memadr_16;
-reg [8:0] memadr_17;
-always @(posedge sys_clk) begin
-	memadr_16 <= main_reader_memory0_adr;
-end
-
-always @(posedge sys_clk) begin
-	if (main_sram0_we[2])
-		mem_grain2_2[main_sram0_adr1] <= main_sram0_dat_w[23:16];
-	memadr_17 <= main_sram0_adr1;
-end
-
-assign main_reader_memory0_dat_r[23:16] = mem_grain2_2[memadr_16];
-assign main_sram0_dat_r1[23:16] = mem_grain2_2[memadr_17];
-
-reg [7:0] mem_grain3_2[0:381];
-reg [8:0] memadr_18;
-reg [8:0] memadr_19;
-always @(posedge sys_clk) begin
-	memadr_18 <= main_reader_memory0_adr;
-end
-
-always @(posedge sys_clk) begin
-	if (main_sram0_we[3])
-		mem_grain3_2[main_sram0_adr1] <= main_sram0_dat_w[31:24];
-	memadr_19 <= main_sram0_adr1;
-end
-
-assign main_reader_memory0_dat_r[31:24] = mem_grain3_2[memadr_18];
-assign main_sram0_dat_r1[31:24] = mem_grain3_2[memadr_19];
-
-reg [7:0] mem_grain0_3[0:381];
-reg [8:0] memadr_20;
-reg [8:0] memadr_21;
-always @(posedge sys_clk) begin
-	memadr_20 <= main_reader_memory1_adr;
-end
-
-always @(posedge sys_clk) begin
-	if (main_sram1_we[0])
-		mem_grain0_3[main_sram1_adr1] <= main_sram1_dat_w[7:0];
-	memadr_21 <= main_sram1_adr1;
-end
-
-assign main_reader_memory1_dat_r[7:0] = mem_grain0_3[memadr_20];
-assign main_sram1_dat_r1[7:0] = mem_grain0_3[memadr_21];
-
-reg [7:0] mem_grain1_3[0:381];
-reg [8:0] memadr_22;
-reg [8:0] memadr_23;
-always @(posedge sys_clk) begin
-	memadr_22 <= main_reader_memory1_adr;
-end
-
-always @(posedge sys_clk) begin
-	if (main_sram1_we[1])
-		mem_grain1_3[main_sram1_adr1] <= main_sram1_dat_w[15:8];
-	memadr_23 <= main_sram1_adr1;
-end
-
-assign main_reader_memory1_dat_r[15:8] = mem_grain1_3[memadr_22];
-assign main_sram1_dat_r1[15:8] = mem_grain1_3[memadr_23];
-
-reg [7:0] mem_grain2_3[0:381];
-reg [8:0] memadr_24;
-reg [8:0] memadr_25;
-always @(posedge sys_clk) begin
-	memadr_24 <= main_reader_memory1_adr;
-end
-
-always @(posedge sys_clk) begin
-	if (main_sram1_we[2])
-		mem_grain2_3[main_sram1_adr1] <= main_sram1_dat_w[23:16];
-	memadr_25 <= main_sram1_adr1;
-end
-
-assign main_reader_memory1_dat_r[23:16] = mem_grain2_3[memadr_24];
-assign main_sram1_dat_r1[23:16] = mem_grain2_3[memadr_25];
-
-reg [7:0] mem_grain3_3[0:381];
-reg [8:0] memadr_26;
-reg [8:0] memadr_27;
-always @(posedge sys_clk) begin
-	memadr_26 <= main_reader_memory1_adr;
-end
-
-always @(posedge sys_clk) begin
-	if (main_sram1_we[3])
-		mem_grain3_3[main_sram1_adr1] <= main_sram1_dat_w[31:24];
-	memadr_27 <= main_sram1_adr1;
-end
-
-assign main_reader_memory1_dat_r[31:24] = mem_grain3_3[memadr_26];
-assign main_sram1_dat_r1[31:24] = mem_grain3_3[memadr_27];
-
 (* ars_ff1 = "true", async_reg = "true" *) FDPE #(
 	.INIT(1'd1)
 ) FDPE (
diff --git a/liteeth/generated/wukong-v2/liteeth_core.v b/liteeth/generated/wukong-v2/liteeth_core.v
new file mode 100644
index 0000000..ba65299
--- /dev/null
+++ b/liteeth/generated/wukong-v2/liteeth_core.v
@@ -0,0 +1,3810 @@
+//--------------------------------------------------------------------------------
+// Auto-generated by Migen (a5bc262) & LiteX (de028765) on 2021-09-24 12:37:01
+//--------------------------------------------------------------------------------
+module liteeth_core(
+	input wire sys_clock,
+	input wire sys_reset,
+	input wire gmii_eth_clocks_tx,
+	output wire gmii_eth_clocks_gtx,
+	input wire gmii_eth_clocks_rx,
+	output wire gmii_eth_rst_n,
+	input wire gmii_eth_int_n,
+	inout wire gmii_eth_mdio,
+	output wire gmii_eth_mdc,
+	input wire gmii_eth_rx_dv,
+	input wire gmii_eth_rx_er,
+	input wire [7:0] gmii_eth_rx_data,
+	output reg gmii_eth_tx_en,
+	output wire gmii_eth_tx_er,
+	output reg [7:0] gmii_eth_tx_data,
+	input wire gmii_eth_col,
+	input wire gmii_eth_crs,
+	input wire [29:0] wishbone_adr,
+	input wire [31:0] wishbone_dat_w,
+	output wire [31:0] wishbone_dat_r,
+	input wire [3:0] wishbone_sel,
+	input wire wishbone_cyc,
+	input wire wishbone_stb,
+	output wire wishbone_ack,
+	input wire wishbone_we,
+	input wire [2:0] wishbone_cti,
+	input wire [1:0] wishbone_bte,
+	output wire wishbone_err,
+	output wire interrupt
+);
+
+reg maccore_maccore_soc_rst = 1'd0;
+wire maccore_maccore_cpu_rst;
+reg [1:0] maccore_maccore_reset_storage = 2'd0;
+reg maccore_maccore_reset_re = 1'd0;
+reg [31:0] maccore_maccore_scratch_storage = 32'd305419896;
+reg maccore_maccore_scratch_re = 1'd0;
+wire [31:0] maccore_maccore_bus_errors_status;
+wire maccore_maccore_bus_errors_we;
+reg maccore_maccore_bus_errors_re = 1'd0;
+wire maccore_maccore_bus_error;
+reg [31:0] maccore_maccore_bus_errors = 32'd0;
+(* dont_touch = "true" *) wire sys_clk;
+wire sys_rst;
+wire por_clk;
+reg maccore_int_rst = 1'd1;
+reg maccore_ethphy_mode0 = 1'd0;
+wire maccore_ethphy_mode_status;
+wire maccore_ethphy_mode_we;
+reg maccore_ethphy_mode_re = 1'd0;
+reg maccore_ethphy_mode1 = 1'd0;
+reg maccore_ethphy_update_mode = 1'd0;
+wire maccore_ethphy_eth_tick;
+reg [9:0] maccore_ethphy_eth_counter = 10'd0;
+wire maccore_ethphy_sys_tick;
+wire maccore_ethphy_i;
+wire maccore_ethphy_o;
+reg maccore_ethphy_toggle_i = 1'd0;
+wire maccore_ethphy_toggle_o;
+reg maccore_ethphy_toggle_o_r = 1'd0;
+reg [23:0] maccore_ethphy_sys_counter = 24'd0;
+reg maccore_ethphy_sys_counter_reset = 1'd0;
+reg maccore_ethphy_sys_counter_ce = 1'd0;
+reg maccore_ethphy_reset_storage = 1'd0;
+reg maccore_ethphy_reset_re = 1'd0;
+(* dont_touch = "true" *) wire eth_rx_clk;
+wire eth_rx_rst;
+(* dont_touch = "true" *) wire eth_tx_clk;
+wire eth_tx_rst;
+reg maccore_ethphy_eth_tx_clk = 1'd0;
+wire maccore_ethphy_reset0;
+wire maccore_ethphy_reset1;
+reg [8:0] maccore_ethphy_counter = 9'd0;
+wire maccore_ethphy_counter_done;
+wire maccore_ethphy_counter_ce;
+wire maccore_ethphy_liteethphygmiimiitx_sink_sink_valid0;
+wire maccore_ethphy_liteethphygmiimiitx_sink_sink_ready0;
+wire maccore_ethphy_liteethphygmiimiitx_sink_sink_first0;
+wire maccore_ethphy_liteethphygmiimiitx_sink_sink_last0;
+wire [7:0] maccore_ethphy_liteethphygmiimiitx_sink_sink_payload_data0;
+wire maccore_ethphy_liteethphygmiimiitx_sink_sink_payload_last_be0;
+wire maccore_ethphy_liteethphygmiimiitx_sink_sink_payload_error0;
+reg maccore_ethphy_liteethphygmiimiitx_gmii_tx_pads_tx_er = 1'd0;
+reg maccore_ethphy_liteethphygmiimiitx_gmii_tx_pads_tx_en = 1'd0;
+reg [7:0] maccore_ethphy_liteethphygmiimiitx_gmii_tx_pads_tx_data = 8'd0;
+wire maccore_ethphy_liteethphygmiimiitx_gmii_tx_sink_valid;
+reg maccore_ethphy_liteethphygmiimiitx_gmii_tx_sink_ready = 1'd0;
+wire maccore_ethphy_liteethphygmiimiitx_gmii_tx_sink_first;
+wire maccore_ethphy_liteethphygmiimiitx_gmii_tx_sink_last;
+wire [7:0] maccore_ethphy_liteethphygmiimiitx_gmii_tx_sink_payload_data;
+wire maccore_ethphy_liteethphygmiimiitx_gmii_tx_sink_payload_last_be;
+wire maccore_ethphy_liteethphygmiimiitx_gmii_tx_sink_payload_error;
+reg maccore_ethphy_liteethphygmiimiitx_mii_tx_pads_tx_er = 1'd0;
+reg maccore_ethphy_liteethphygmiimiitx_mii_tx_pads_tx_en = 1'd0;
+reg [7:0] maccore_ethphy_liteethphygmiimiitx_mii_tx_pads_tx_data = 8'd0;
+wire maccore_ethphy_liteethphygmiimiitx_sink_sink_valid1;
+wire maccore_ethphy_liteethphygmiimiitx_sink_sink_ready1;
+wire maccore_ethphy_liteethphygmiimiitx_sink_sink_first1;
+wire maccore_ethphy_liteethphygmiimiitx_sink_sink_last1;
+wire [7:0] maccore_ethphy_liteethphygmiimiitx_sink_sink_payload_data1;
+wire maccore_ethphy_liteethphygmiimiitx_sink_sink_payload_last_be1;
+wire maccore_ethphy_liteethphygmiimiitx_sink_sink_payload_error1;
+wire maccore_ethphy_liteethphygmiimiitx_converter_sink_valid;
+wire maccore_ethphy_liteethphygmiimiitx_converter_sink_ready;
+reg maccore_ethphy_liteethphygmiimiitx_converter_sink_first = 1'd0;
+reg maccore_ethphy_liteethphygmiimiitx_converter_sink_last = 1'd0;
+wire [7:0] maccore_ethphy_liteethphygmiimiitx_converter_sink_payload_data;
+wire maccore_ethphy_liteethphygmiimiitx_converter_source_valid;
+wire maccore_ethphy_liteethphygmiimiitx_converter_source_ready;
+wire maccore_ethphy_liteethphygmiimiitx_converter_source_first;
+wire maccore_ethphy_liteethphygmiimiitx_converter_source_last;
+wire [3:0] maccore_ethphy_liteethphygmiimiitx_converter_source_payload_data;
+wire maccore_ethphy_liteethphygmiimiitx_converter_converter_sink_valid;
+wire maccore_ethphy_liteethphygmiimiitx_converter_converter_sink_ready;
+wire maccore_ethphy_liteethphygmiimiitx_converter_converter_sink_first;
+wire maccore_ethphy_liteethphygmiimiitx_converter_converter_sink_last;
+reg [7:0] maccore_ethphy_liteethphygmiimiitx_converter_converter_sink_payload_data = 8'd0;
+wire maccore_ethphy_liteethphygmiimiitx_converter_converter_source_valid;
+wire maccore_ethphy_liteethphygmiimiitx_converter_converter_source_ready;
+wire maccore_ethphy_liteethphygmiimiitx_converter_converter_source_first;
+wire maccore_ethphy_liteethphygmiimiitx_converter_converter_source_last;
+reg [3:0] maccore_ethphy_liteethphygmiimiitx_converter_converter_source_payload_data = 4'd0;
+wire maccore_ethphy_liteethphygmiimiitx_converter_converter_source_payload_valid_token_count;
+reg maccore_ethphy_liteethphygmiimiitx_converter_converter_mux = 1'd0;
+wire maccore_ethphy_liteethphygmiimiitx_converter_converter_first;
+wire maccore_ethphy_liteethphygmiimiitx_converter_converter_last;
+wire maccore_ethphy_liteethphygmiimiitx_converter_source_source_valid;
+wire maccore_ethphy_liteethphygmiimiitx_converter_source_source_ready;
+wire maccore_ethphy_liteethphygmiimiitx_converter_source_source_first;
+wire maccore_ethphy_liteethphygmiimiitx_converter_source_source_last;
+wire [3:0] maccore_ethphy_liteethphygmiimiitx_converter_source_source_payload_data;
+wire maccore_ethphy_liteethphygmiimiitx_demux_sink_valid;
+reg maccore_ethphy_liteethphygmiimiitx_demux_sink_ready = 1'd0;
+wire maccore_ethphy_liteethphygmiimiitx_demux_sink_first;
+wire maccore_ethphy_liteethphygmiimiitx_demux_sink_last;
+wire [7:0] maccore_ethphy_liteethphygmiimiitx_demux_sink_payload_data;
+wire maccore_ethphy_liteethphygmiimiitx_demux_sink_payload_last_be;
+wire maccore_ethphy_liteethphygmiimiitx_demux_sink_payload_error;
+reg maccore_ethphy_liteethphygmiimiitx_demux_endpoint0_source_valid = 1'd0;
+wire maccore_ethphy_liteethphygmiimiitx_demux_endpoint0_source_ready;
+reg maccore_ethphy_liteethphygmiimiitx_demux_endpoint0_source_first = 1'd0;
+reg maccore_ethphy_liteethphygmiimiitx_demux_endpoint0_source_last = 1'd0;
+reg [7:0] maccore_ethphy_liteethphygmiimiitx_demux_endpoint0_source_payload_data = 8'd0;
+reg maccore_ethphy_liteethphygmiimiitx_demux_endpoint0_source_payload_last_be = 1'd0;
+reg maccore_ethphy_liteethphygmiimiitx_demux_endpoint0_source_payload_error = 1'd0;
+reg maccore_ethphy_liteethphygmiimiitx_demux_endpoint1_source_valid = 1'd0;
+wire maccore_ethphy_liteethphygmiimiitx_demux_endpoint1_source_ready;
+reg maccore_ethphy_liteethphygmiimiitx_demux_endpoint1_source_first = 1'd0;
+reg maccore_ethphy_liteethphygmiimiitx_demux_endpoint1_source_last = 1'd0;
+reg [7:0] maccore_ethphy_liteethphygmiimiitx_demux_endpoint1_source_payload_data = 8'd0;
+reg maccore_ethphy_liteethphygmiimiitx_demux_endpoint1_source_payload_last_be = 1'd0;
+reg maccore_ethphy_liteethphygmiimiitx_demux_endpoint1_source_payload_error = 1'd0;
+wire maccore_ethphy_liteethphygmiimiitx_demux_sel;
+wire maccore_ethphy_liteethphygmiimiirx_source_source_valid0;
+wire maccore_ethphy_liteethphygmiimiirx_source_source_ready0;
+wire maccore_ethphy_liteethphygmiimiirx_source_source_first0;
+wire maccore_ethphy_liteethphygmiimiirx_source_source_last0;
+wire [7:0] maccore_ethphy_liteethphygmiimiirx_source_source_payload_data0;
+wire maccore_ethphy_liteethphygmiimiirx_source_source_payload_last_be0;
+wire maccore_ethphy_liteethphygmiimiirx_source_source_payload_error0;
+reg maccore_ethphy_liteethphygmiimiirx_pads_d_rx_dv = 1'd0;
+reg [7:0] maccore_ethphy_liteethphygmiimiirx_pads_d_rx_data = 8'd0;
+reg maccore_ethphy_liteethphygmiimiirx_gmii_rx_source_valid = 1'd0;
+wire maccore_ethphy_liteethphygmiimiirx_gmii_rx_source_ready;
+reg maccore_ethphy_liteethphygmiimiirx_gmii_rx_source_first = 1'd0;
+wire maccore_ethphy_liteethphygmiimiirx_gmii_rx_source_last;
+reg [7:0] maccore_ethphy_liteethphygmiimiirx_gmii_rx_source_payload_data = 8'd0;
+reg maccore_ethphy_liteethphygmiimiirx_gmii_rx_source_payload_last_be = 1'd0;
+reg maccore_ethphy_liteethphygmiimiirx_gmii_rx_source_payload_error = 1'd0;
+reg maccore_ethphy_liteethphygmiimiirx_gmii_rx_dv_d = 1'd0;
+wire maccore_ethphy_liteethphygmiimiirx_source_source_valid1;
+wire maccore_ethphy_liteethphygmiimiirx_source_source_ready1;
+wire maccore_ethphy_liteethphygmiimiirx_source_source_first1;
+wire maccore_ethphy_liteethphygmiimiirx_source_source_last1;
+wire [7:0] maccore_ethphy_liteethphygmiimiirx_source_source_payload_data1;
+reg maccore_ethphy_liteethphygmiimiirx_source_source_payload_last_be1 = 1'd0;
+reg maccore_ethphy_liteethphygmiimiirx_source_source_payload_error1 = 1'd0;
+reg maccore_ethphy_liteethphygmiimiirx_converter_sink_valid = 1'd0;
+wire maccore_ethphy_liteethphygmiimiirx_converter_sink_ready;
+reg maccore_ethphy_liteethphygmiimiirx_converter_sink_first = 1'd0;
+wire maccore_ethphy_liteethphygmiimiirx_converter_sink_last;
+reg [3:0] maccore_ethphy_liteethphygmiimiirx_converter_sink_payload_data = 4'd0;
+wire maccore_ethphy_liteethphygmiimiirx_converter_source_valid;
+wire maccore_ethphy_liteethphygmiimiirx_converter_source_ready;
+wire maccore_ethphy_liteethphygmiimiirx_converter_source_first;
+wire maccore_ethphy_liteethphygmiimiirx_converter_source_last;
+reg [7:0] maccore_ethphy_liteethphygmiimiirx_converter_source_payload_data = 8'd0;
+wire maccore_ethphy_liteethphygmiimiirx_converter_converter_sink_valid;
+wire maccore_ethphy_liteethphygmiimiirx_converter_converter_sink_ready;
+wire maccore_ethphy_liteethphygmiimiirx_converter_converter_sink_first;
+wire maccore_ethphy_liteethphygmiimiirx_converter_converter_sink_last;
+wire [3:0] maccore_ethphy_liteethphygmiimiirx_converter_converter_sink_payload_data;
+wire maccore_ethphy_liteethphygmiimiirx_converter_converter_source_valid;
+wire maccore_ethphy_liteethphygmiimiirx_converter_converter_source_ready;
+reg maccore_ethphy_liteethphygmiimiirx_converter_converter_source_first = 1'd0;
+reg maccore_ethphy_liteethphygmiimiirx_converter_converter_source_last = 1'd0;
+reg [7:0] maccore_ethphy_liteethphygmiimiirx_converter_converter_source_payload_data = 8'd0;
+reg [1:0] maccore_ethphy_liteethphygmiimiirx_converter_converter_source_payload_valid_token_count = 2'd0;
+reg maccore_ethphy_liteethphygmiimiirx_converter_converter_demux = 1'd0;
+wire maccore_ethphy_liteethphygmiimiirx_converter_converter_load_part;
+reg maccore_ethphy_liteethphygmiimiirx_converter_converter_strobe_all = 1'd0;
+wire maccore_ethphy_liteethphygmiimiirx_converter_source_source_valid;
+wire maccore_ethphy_liteethphygmiimiirx_converter_source_source_ready;
+wire maccore_ethphy_liteethphygmiimiirx_converter_source_source_first;
+wire maccore_ethphy_liteethphygmiimiirx_converter_source_source_last;
+wire [7:0] maccore_ethphy_liteethphygmiimiirx_converter_source_source_payload_data;
+reg maccore_ethphy_liteethphygmiimiirx_converter_reset = 1'd0;
+reg maccore_ethphy_liteethphygmiimiirx_mux_source_valid = 1'd0;
+wire maccore_ethphy_liteethphygmiimiirx_mux_source_ready;
+reg maccore_ethphy_liteethphygmiimiirx_mux_source_first = 1'd0;
+reg maccore_ethphy_liteethphygmiimiirx_mux_source_last = 1'd0;
+reg [7:0] maccore_ethphy_liteethphygmiimiirx_mux_source_payload_data = 8'd0;
+reg maccore_ethphy_liteethphygmiimiirx_mux_source_payload_last_be = 1'd0;
+reg maccore_ethphy_liteethphygmiimiirx_mux_source_payload_error = 1'd0;
+wire maccore_ethphy_liteethphygmiimiirx_mux_endpoint0_sink_valid;
+reg maccore_ethphy_liteethphygmiimiirx_mux_endpoint0_sink_ready = 1'd0;
+wire maccore_ethphy_liteethphygmiimiirx_mux_endpoint0_sink_first;
+wire maccore_ethphy_liteethphygmiimiirx_mux_endpoint0_sink_last;
+wire [7:0] maccore_ethphy_liteethphygmiimiirx_mux_endpoint0_sink_payload_data;
+wire maccore_ethphy_liteethphygmiimiirx_mux_endpoint0_sink_payload_last_be;
+wire maccore_ethphy_liteethphygmiimiirx_mux_endpoint0_sink_payload_error;
+wire maccore_ethphy_liteethphygmiimiirx_mux_endpoint1_sink_valid;
+reg maccore_ethphy_liteethphygmiimiirx_mux_endpoint1_sink_ready = 1'd0;
+wire maccore_ethphy_liteethphygmiimiirx_mux_endpoint1_sink_first;
+wire maccore_ethphy_liteethphygmiimiirx_mux_endpoint1_sink_last;
+wire [7:0] maccore_ethphy_liteethphygmiimiirx_mux_endpoint1_sink_payload_data;
+wire maccore_ethphy_liteethphygmiimiirx_mux_endpoint1_sink_payload_last_be;
+wire maccore_ethphy_liteethphygmiimiirx_mux_endpoint1_sink_payload_error;
+wire maccore_ethphy_liteethphygmiimiirx_mux_sel;
+wire maccore_ethphy_mdc;
+wire maccore_ethphy_oe;
+wire maccore_ethphy_w;
+reg [2:0] maccore_ethphy__w_storage = 3'd0;
+reg maccore_ethphy__w_re = 1'd0;
+reg maccore_ethphy_r = 1'd0;
+reg maccore_ethphy__r_status = 1'd0;
+wire maccore_ethphy__r_we;
+reg maccore_ethphy__r_re = 1'd0;
+wire maccore_ethphy_data_w;
+wire maccore_ethphy_data_oe;
+wire maccore_ethphy_data_r;
+wire tx_gap_inserter_sink_valid;
+reg tx_gap_inserter_sink_ready = 1'd0;
+wire tx_gap_inserter_sink_first;
+wire tx_gap_inserter_sink_last;
+wire [7:0] tx_gap_inserter_sink_payload_data;
+wire tx_gap_inserter_sink_payload_last_be;
+wire tx_gap_inserter_sink_payload_error;
+reg tx_gap_inserter_source_valid = 1'd0;
+wire tx_gap_inserter_source_ready;
+reg tx_gap_inserter_source_first = 1'd0;
+reg tx_gap_inserter_source_last = 1'd0;
+reg [7:0] tx_gap_inserter_source_payload_data = 8'd0;
+reg tx_gap_inserter_source_payload_last_be = 1'd0;
+reg tx_gap_inserter_source_payload_error = 1'd0;
+reg [3:0] tx_gap_inserter_counter = 4'd0;
+reg preamble_crc_status = 1'd1;
+wire preamble_crc_we;
+reg preamble_crc_re = 1'd0;
+reg [31:0] preamble_errors_status = 32'd0;
+wire preamble_errors_we;
+reg preamble_errors_re = 1'd0;
+reg [31:0] crc_errors_status = 32'd0;
+wire crc_errors_we;
+reg crc_errors_re = 1'd0;
+wire preamble_inserter_sink_valid;
+reg preamble_inserter_sink_ready = 1'd0;
+wire preamble_inserter_sink_first;
+wire preamble_inserter_sink_last;
+wire [7:0] preamble_inserter_sink_payload_data;
+wire preamble_inserter_sink_payload_last_be;
+wire preamble_inserter_sink_payload_error;
+reg preamble_inserter_source_valid = 1'd0;
+wire preamble_inserter_source_ready;
+reg preamble_inserter_source_first = 1'd0;
+reg preamble_inserter_source_last = 1'd0;
+reg [7:0] preamble_inserter_source_payload_data = 8'd0;
+wire preamble_inserter_source_payload_last_be;
+reg preamble_inserter_source_payload_error = 1'd0;
+reg [63:0] preamble_inserter_preamble = 64'd15372286728091293013;
+reg [2:0] preamble_inserter_count = 3'd0;
+wire preamble_checker_sink_valid;
+reg preamble_checker_sink_ready = 1'd0;
+wire preamble_checker_sink_first;
+wire preamble_checker_sink_last;
+wire [7:0] preamble_checker_sink_payload_data;
+wire preamble_checker_sink_payload_last_be;
+wire preamble_checker_sink_payload_error;
+reg preamble_checker_source_valid = 1'd0;
+wire preamble_checker_source_ready;
+reg preamble_checker_source_first = 1'd0;
+reg preamble_checker_source_last = 1'd0;
+wire [7:0] preamble_checker_source_payload_data;
+wire preamble_checker_source_payload_last_be;
+reg preamble_checker_source_payload_error = 1'd0;
+reg preamble_checker_error = 1'd0;
+wire liteethmaccrc32inserter_sink_valid;
+reg liteethmaccrc32inserter_sink_ready = 1'd0;
+wire liteethmaccrc32inserter_sink_first;
+wire liteethmaccrc32inserter_sink_last;
+wire [7:0] liteethmaccrc32inserter_sink_payload_data;
+wire liteethmaccrc32inserter_sink_payload_last_be;
+wire liteethmaccrc32inserter_sink_payload_error;
+reg liteethmaccrc32inserter_source_valid = 1'd0;
+wire liteethmaccrc32inserter_source_ready;
+reg liteethmaccrc32inserter_source_first = 1'd0;
+reg liteethmaccrc32inserter_source_last = 1'd0;
+reg [7:0] liteethmaccrc32inserter_source_payload_data = 8'd0;
+reg liteethmaccrc32inserter_source_payload_last_be = 1'd0;
+reg liteethmaccrc32inserter_source_payload_error = 1'd0;
+reg [7:0] liteethmaccrc32inserter_data0 = 8'd0;
+wire [31:0] liteethmaccrc32inserter_value;
+wire liteethmaccrc32inserter_error;
+wire [7:0] liteethmaccrc32inserter_data1;
+wire [31:0] liteethmaccrc32inserter_last;
+reg [31:0] liteethmaccrc32inserter_next = 32'd0;
+reg [31:0] liteethmaccrc32inserter_reg = 32'd4294967295;
+reg liteethmaccrc32inserter_ce = 1'd0;
+reg liteethmaccrc32inserter_reset = 1'd0;
+reg [1:0] liteethmaccrc32inserter_cnt = 2'd3;
+wire liteethmaccrc32inserter_cnt_done;
+reg liteethmaccrc32inserter_is_ongoing0 = 1'd0;
+reg liteethmaccrc32inserter_is_ongoing1 = 1'd0;
+wire crc32_inserter_sink_valid;
+wire crc32_inserter_sink_ready;
+wire crc32_inserter_sink_first;
+wire crc32_inserter_sink_last;
+wire [7:0] crc32_inserter_sink_payload_data;
+wire crc32_inserter_sink_payload_last_be;
+wire crc32_inserter_sink_payload_error;
+reg crc32_inserter_source_valid = 1'd0;
+wire crc32_inserter_source_ready;
+reg crc32_inserter_source_first = 1'd0;
+reg crc32_inserter_source_last = 1'd0;
+reg [7:0] crc32_inserter_source_payload_data = 8'd0;
+reg crc32_inserter_source_payload_last_be = 1'd0;
+reg crc32_inserter_source_payload_error = 1'd0;
+wire liteethmaccrc32checker_sink_sink_valid;
+reg liteethmaccrc32checker_sink_sink_ready = 1'd0;
+wire liteethmaccrc32checker_sink_sink_first;
+wire liteethmaccrc32checker_sink_sink_last;
+wire [7:0] liteethmaccrc32checker_sink_sink_payload_data;
+wire liteethmaccrc32checker_sink_sink_payload_last_be;
+wire liteethmaccrc32checker_sink_sink_payload_error;
+wire liteethmaccrc32checker_source_source_valid;
+wire liteethmaccrc32checker_source_source_ready;
+reg liteethmaccrc32checker_source_source_first = 1'd0;
+wire liteethmaccrc32checker_source_source_last;
+wire [7:0] liteethmaccrc32checker_source_source_payload_data;
+wire liteethmaccrc32checker_source_source_payload_last_be;
+reg liteethmaccrc32checker_source_source_payload_error = 1'd0;
+wire liteethmaccrc32checker_error;
+wire [7:0] liteethmaccrc32checker_crc_data0;
+wire [31:0] liteethmaccrc32checker_crc_value;
+wire liteethmaccrc32checker_crc_error;
+wire [7:0] liteethmaccrc32checker_crc_data1;
+wire [31:0] liteethmaccrc32checker_crc_last;
+reg [31:0] liteethmaccrc32checker_crc_next = 32'd0;
+reg [31:0] liteethmaccrc32checker_crc_reg = 32'd4294967295;
+reg liteethmaccrc32checker_crc_ce = 1'd0;
+reg liteethmaccrc32checker_crc_reset = 1'd0;
+reg liteethmaccrc32checker_syncfifo_sink_valid = 1'd0;
+wire liteethmaccrc32checker_syncfifo_sink_ready;
+wire liteethmaccrc32checker_syncfifo_sink_first;
+wire liteethmaccrc32checker_syncfifo_sink_last;
+wire [7:0] liteethmaccrc32checker_syncfifo_sink_payload_data;
+wire liteethmaccrc32checker_syncfifo_sink_payload_last_be;
+wire liteethmaccrc32checker_syncfifo_sink_payload_error;
+wire liteethmaccrc32checker_syncfifo_source_valid;
+wire liteethmaccrc32checker_syncfifo_source_ready;
+wire liteethmaccrc32checker_syncfifo_source_first;
+wire liteethmaccrc32checker_syncfifo_source_last;
+wire [7:0] liteethmaccrc32checker_syncfifo_source_payload_data;
+wire liteethmaccrc32checker_syncfifo_source_payload_last_be;
+wire liteethmaccrc32checker_syncfifo_source_payload_error;
+wire liteethmaccrc32checker_syncfifo_syncfifo_we;
+wire liteethmaccrc32checker_syncfifo_syncfifo_writable;
+wire liteethmaccrc32checker_syncfifo_syncfifo_re;
+wire liteethmaccrc32checker_syncfifo_syncfifo_readable;
+wire [11:0] liteethmaccrc32checker_syncfifo_syncfifo_din;
+wire [11:0] liteethmaccrc32checker_syncfifo_syncfifo_dout;
+reg [2:0] liteethmaccrc32checker_syncfifo_level = 3'd0;
+reg liteethmaccrc32checker_syncfifo_replace = 1'd0;
+reg [2:0] liteethmaccrc32checker_syncfifo_produce = 3'd0;
+reg [2:0] liteethmaccrc32checker_syncfifo_consume = 3'd0;
+reg [2:0] liteethmaccrc32checker_syncfifo_wrport_adr = 3'd0;
+wire [11:0] liteethmaccrc32checker_syncfifo_wrport_dat_r;
+wire liteethmaccrc32checker_syncfifo_wrport_we;
+wire [11:0] liteethmaccrc32checker_syncfifo_wrport_dat_w;
+wire liteethmaccrc32checker_syncfifo_do_read;
+wire [2:0] liteethmaccrc32checker_syncfifo_rdport_adr;
+wire [11:0] liteethmaccrc32checker_syncfifo_rdport_dat_r;
+wire [7:0] liteethmaccrc32checker_syncfifo_fifo_in_payload_data;
+wire liteethmaccrc32checker_syncfifo_fifo_in_payload_last_be;
+wire liteethmaccrc32checker_syncfifo_fifo_in_payload_error;
+wire liteethmaccrc32checker_syncfifo_fifo_in_first;
+wire liteethmaccrc32checker_syncfifo_fifo_in_last;
+wire [7:0] liteethmaccrc32checker_syncfifo_fifo_out_payload_data;
+wire liteethmaccrc32checker_syncfifo_fifo_out_payload_last_be;
+wire liteethmaccrc32checker_syncfifo_fifo_out_payload_error;
+wire liteethmaccrc32checker_syncfifo_fifo_out_first;
+wire liteethmaccrc32checker_syncfifo_fifo_out_last;
+reg liteethmaccrc32checker_fifo_reset = 1'd0;
+wire liteethmaccrc32checker_fifo_in;
+wire liteethmaccrc32checker_fifo_out;
+wire liteethmaccrc32checker_fifo_full;
+wire crc32_checker_sink_valid;
+wire crc32_checker_sink_ready;
+wire crc32_checker_sink_first;
+wire crc32_checker_sink_last;
+wire [7:0] crc32_checker_sink_payload_data;
+wire crc32_checker_sink_payload_last_be;
+wire crc32_checker_sink_payload_error;
+reg crc32_checker_source_valid = 1'd0;
+wire crc32_checker_source_ready;
+reg crc32_checker_source_first = 1'd0;
+reg crc32_checker_source_last = 1'd0;
+reg [7:0] crc32_checker_source_payload_data = 8'd0;
+reg crc32_checker_source_payload_last_be = 1'd0;
+reg crc32_checker_source_payload_error = 1'd0;
+wire ps_preamble_error_i;
+wire ps_preamble_error_o;
+reg ps_preamble_error_toggle_i = 1'd0;
+wire ps_preamble_error_toggle_o;
+reg ps_preamble_error_toggle_o_r = 1'd0;
+wire ps_crc_error_i;
+wire ps_crc_error_o;
+reg ps_crc_error_toggle_i = 1'd0;
+wire ps_crc_error_toggle_o;
+reg ps_crc_error_toggle_o_r = 1'd0;
+wire padding_inserter_sink_valid;
+reg padding_inserter_sink_ready = 1'd0;
+wire padding_inserter_sink_first;
+wire padding_inserter_sink_last;
+wire [7:0] padding_inserter_sink_payload_data;
+wire padding_inserter_sink_payload_last_be;
+wire padding_inserter_sink_payload_error;
+reg padding_inserter_source_valid = 1'd0;
+wire padding_inserter_source_ready;
+reg padding_inserter_source_first = 1'd0;
+reg padding_inserter_source_last = 1'd0;
+reg [7:0] padding_inserter_source_payload_data = 8'd0;
+reg padding_inserter_source_payload_last_be = 1'd0;
+reg padding_inserter_source_payload_error = 1'd0;
+reg [15:0] padding_inserter_counter = 16'd0;
+wire padding_inserter_counter_done;
+wire padding_checker_sink_valid;
+wire padding_checker_sink_ready;
+wire padding_checker_sink_first;
+wire padding_checker_sink_last;
+wire [7:0] padding_checker_sink_payload_data;
+wire padding_checker_sink_payload_last_be;
+wire padding_checker_sink_payload_error;
+wire padding_checker_source_valid;
+wire padding_checker_source_ready;
+wire padding_checker_source_first;
+wire padding_checker_source_last;
+wire [7:0] padding_checker_source_payload_data;
+wire padding_checker_source_payload_last_be;
+wire padding_checker_source_payload_error;
+wire tx_last_be_sink_valid;
+reg tx_last_be_sink_ready = 1'd0;
+wire tx_last_be_sink_first;
+wire tx_last_be_sink_last;
+wire [7:0] tx_last_be_sink_payload_data;
+wire tx_last_be_sink_payload_last_be;
+wire tx_last_be_sink_payload_error;
+reg tx_last_be_source_valid = 1'd0;
+wire tx_last_be_source_ready;
+reg tx_last_be_source_first = 1'd0;
+reg tx_last_be_source_last = 1'd0;
+reg [7:0] tx_last_be_source_payload_data = 8'd0;
+reg tx_last_be_source_payload_last_be = 1'd0;
+reg tx_last_be_source_payload_error = 1'd0;
+wire rx_last_be_sink_valid;
+wire rx_last_be_sink_ready;
+wire rx_last_be_sink_first;
+wire rx_last_be_sink_last;
+wire [7:0] rx_last_be_sink_payload_data;
+wire rx_last_be_sink_payload_last_be;
+wire rx_last_be_sink_payload_error;
+wire rx_last_be_source_valid;
+wire rx_last_be_source_ready;
+wire rx_last_be_source_first;
+wire rx_last_be_source_last;
+wire [7:0] rx_last_be_source_payload_data;
+reg rx_last_be_source_payload_last_be = 1'd0;
+wire rx_last_be_source_payload_error;
+wire tx_converter_sink_valid;
+wire tx_converter_sink_ready;
+wire tx_converter_sink_first;
+wire tx_converter_sink_last;
+wire [31:0] tx_converter_sink_payload_data;
+wire [3:0] tx_converter_sink_payload_last_be;
+wire [3:0] tx_converter_sink_payload_error;
+wire tx_converter_source_valid;
+wire tx_converter_source_ready;
+wire tx_converter_source_first;
+wire tx_converter_source_last;
+wire [7:0] tx_converter_source_payload_data;
+wire tx_converter_source_payload_last_be;
+wire tx_converter_source_payload_error;
+wire tx_converter_converter_sink_valid;
+wire tx_converter_converter_sink_ready;
+wire tx_converter_converter_sink_first;
+wire tx_converter_converter_sink_last;
+reg [39:0] tx_converter_converter_sink_payload_data = 40'd0;
+wire tx_converter_converter_source_valid;
+wire tx_converter_converter_source_ready;
+wire tx_converter_converter_source_first;
+wire tx_converter_converter_source_last;
+reg [9:0] tx_converter_converter_source_payload_data = 10'd0;
+wire tx_converter_converter_source_payload_valid_token_count;
+reg [1:0] tx_converter_converter_mux = 2'd0;
+wire tx_converter_converter_first;
+wire tx_converter_converter_last;
+wire tx_converter_source_source_valid;
+wire tx_converter_source_source_ready;
+wire tx_converter_source_source_first;
+wire tx_converter_source_source_last;
+wire [9:0] tx_converter_source_source_payload_data;
+wire rx_converter_sink_valid;
+wire rx_converter_sink_ready;
+wire rx_converter_sink_first;
+wire rx_converter_sink_last;
+wire [7:0] rx_converter_sink_payload_data;
+wire rx_converter_sink_payload_last_be;
+wire rx_converter_sink_payload_error;
+wire rx_converter_source_valid;
+wire rx_converter_source_ready;
+wire rx_converter_source_first;
+wire rx_converter_source_last;
+reg [31:0] rx_converter_source_payload_data = 32'd0;
+reg [3:0] rx_converter_source_payload_last_be = 4'd0;
+reg [3:0] rx_converter_source_payload_error = 4'd0;
+wire rx_converter_converter_sink_valid;
+wire rx_converter_converter_sink_ready;
+wire rx_converter_converter_sink_first;
+wire rx_converter_converter_sink_last;
+wire [9:0] rx_converter_converter_sink_payload_data;
+wire rx_converter_converter_source_valid;
+wire rx_converter_converter_source_ready;
+reg rx_converter_converter_source_first = 1'd0;
+reg rx_converter_converter_source_last = 1'd0;
+reg [39:0] rx_converter_converter_source_payload_data = 40'd0;
+reg [2:0] rx_converter_converter_source_payload_valid_token_count = 3'd0;
+reg [1:0] rx_converter_converter_demux = 2'd0;
+wire rx_converter_converter_load_part;
+reg rx_converter_converter_strobe_all = 1'd0;
+wire rx_converter_source_source_valid;
+wire rx_converter_source_source_ready;
+wire rx_converter_source_source_first;
+wire rx_converter_source_source_last;
+wire [39:0] rx_converter_source_source_payload_data;
+wire tx_cdc_sink_sink_valid;
+wire tx_cdc_sink_sink_ready;
+wire tx_cdc_sink_sink_first;
+wire tx_cdc_sink_sink_last;
+wire [31:0] tx_cdc_sink_sink_payload_data;
+wire [3:0] tx_cdc_sink_sink_payload_last_be;
+wire [3:0] tx_cdc_sink_sink_payload_error;
+wire tx_cdc_source_source_valid;
+wire tx_cdc_source_source_ready;
+wire tx_cdc_source_source_first;
+wire tx_cdc_source_source_last;
+wire [31:0] tx_cdc_source_source_payload_data;
+wire [3:0] tx_cdc_source_source_payload_last_be;
+wire [3:0] tx_cdc_source_source_payload_error;
+wire tx_cdc_cdc_sink_valid;
+wire tx_cdc_cdc_sink_ready;
+wire tx_cdc_cdc_sink_first;
+wire tx_cdc_cdc_sink_last;
+wire [31:0] tx_cdc_cdc_sink_payload_data;
+wire [3:0] tx_cdc_cdc_sink_payload_last_be;
+wire [3:0] tx_cdc_cdc_sink_payload_error;
+wire tx_cdc_cdc_source_valid;
+wire tx_cdc_cdc_source_ready;
+wire tx_cdc_cdc_source_first;
+wire tx_cdc_cdc_source_last;
+wire [31:0] tx_cdc_cdc_source_payload_data;
+wire [3:0] tx_cdc_cdc_source_payload_last_be;
+wire [3:0] tx_cdc_cdc_source_payload_error;
+wire tx_cdc_cdc_asyncfifo_we;
+wire tx_cdc_cdc_asyncfifo_writable;
+wire tx_cdc_cdc_asyncfifo_re;
+wire tx_cdc_cdc_asyncfifo_readable;
+wire [41:0] tx_cdc_cdc_asyncfifo_din;
+wire [41:0] tx_cdc_cdc_asyncfifo_dout;
+wire tx_cdc_cdc_graycounter0_ce;
+(* dont_touch = "true" *) reg [5:0] tx_cdc_cdc_graycounter0_q = 6'd0;
+wire [5:0] tx_cdc_cdc_graycounter0_q_next;
+reg [5:0] tx_cdc_cdc_graycounter0_q_binary = 6'd0;
+reg [5:0] tx_cdc_cdc_graycounter0_q_next_binary = 6'd0;
+wire tx_cdc_cdc_graycounter1_ce;
+(* dont_touch = "true" *) reg [5:0] tx_cdc_cdc_graycounter1_q = 6'd0;
+wire [5:0] tx_cdc_cdc_graycounter1_q_next;
+reg [5:0] tx_cdc_cdc_graycounter1_q_binary = 6'd0;
+reg [5:0] tx_cdc_cdc_graycounter1_q_next_binary = 6'd0;
+wire [5:0] tx_cdc_cdc_produce_rdomain;
+wire [5:0] tx_cdc_cdc_consume_wdomain;
+wire [4:0] tx_cdc_cdc_wrport_adr;
+wire [41:0] tx_cdc_cdc_wrport_dat_r;
+wire tx_cdc_cdc_wrport_we;
+wire [41:0] tx_cdc_cdc_wrport_dat_w;
+wire [4:0] tx_cdc_cdc_rdport_adr;
+wire [41:0] tx_cdc_cdc_rdport_dat_r;
+wire [31:0] tx_cdc_cdc_fifo_in_payload_data;
+wire [3:0] tx_cdc_cdc_fifo_in_payload_last_be;
+wire [3:0] tx_cdc_cdc_fifo_in_payload_error;
+wire tx_cdc_cdc_fifo_in_first;
+wire tx_cdc_cdc_fifo_in_last;
+wire [31:0] tx_cdc_cdc_fifo_out_payload_data;
+wire [3:0] tx_cdc_cdc_fifo_out_payload_last_be;
+wire [3:0] tx_cdc_cdc_fifo_out_payload_error;
+wire tx_cdc_cdc_fifo_out_first;
+wire tx_cdc_cdc_fifo_out_last;
+wire rx_cdc_sink_sink_valid;
+wire rx_cdc_sink_sink_ready;
+wire rx_cdc_sink_sink_first;
+wire rx_cdc_sink_sink_last;
+wire [31:0] rx_cdc_sink_sink_payload_data;
+wire [3:0] rx_cdc_sink_sink_payload_last_be;
+wire [3:0] rx_cdc_sink_sink_payload_error;
+wire rx_cdc_source_source_valid;
+wire rx_cdc_source_source_ready;
+wire rx_cdc_source_source_first;
+wire rx_cdc_source_source_last;
+wire [31:0] rx_cdc_source_source_payload_data;
+wire [3:0] rx_cdc_source_source_payload_last_be;
+wire [3:0] rx_cdc_source_source_payload_error;
+wire rx_cdc_cdc_sink_valid;
+wire rx_cdc_cdc_sink_ready;
+wire rx_cdc_cdc_sink_first;
+wire rx_cdc_cdc_sink_last;
+wire [31:0] rx_cdc_cdc_sink_payload_data;
+wire [3:0] rx_cdc_cdc_sink_payload_last_be;
+wire [3:0] rx_cdc_cdc_sink_payload_error;
+wire rx_cdc_cdc_source_valid;
+wire rx_cdc_cdc_source_ready;
+wire rx_cdc_cdc_source_first;
+wire rx_cdc_cdc_source_last;
+wire [31:0] rx_cdc_cdc_source_payload_data;
+wire [3:0] rx_cdc_cdc_source_payload_last_be;
+wire [3:0] rx_cdc_cdc_source_payload_error;
+wire rx_cdc_cdc_asyncfifo_we;
+wire rx_cdc_cdc_asyncfifo_writable;
+wire rx_cdc_cdc_asyncfifo_re;
+wire rx_cdc_cdc_asyncfifo_readable;
+wire [41:0] rx_cdc_cdc_asyncfifo_din;
+wire [41:0] rx_cdc_cdc_asyncfifo_dout;
+wire rx_cdc_cdc_graycounter0_ce;
+(* dont_touch = "true" *) reg [5:0] rx_cdc_cdc_graycounter0_q = 6'd0;
+wire [5:0] rx_cdc_cdc_graycounter0_q_next;
+reg [5:0] rx_cdc_cdc_graycounter0_q_binary = 6'd0;
+reg [5:0] rx_cdc_cdc_graycounter0_q_next_binary = 6'd0;
+wire rx_cdc_cdc_graycounter1_ce;
+(* dont_touch = "true" *) reg [5:0] rx_cdc_cdc_graycounter1_q = 6'd0;
+wire [5:0] rx_cdc_cdc_graycounter1_q_next;
+reg [5:0] rx_cdc_cdc_graycounter1_q_binary = 6'd0;
+reg [5:0] rx_cdc_cdc_graycounter1_q_next_binary = 6'd0;
+wire [5:0] rx_cdc_cdc_produce_rdomain;
+wire [5:0] rx_cdc_cdc_consume_wdomain;
+wire [4:0] rx_cdc_cdc_wrport_adr;
+wire [41:0] rx_cdc_cdc_wrport_dat_r;
+wire rx_cdc_cdc_wrport_we;
+wire [41:0] rx_cdc_cdc_wrport_dat_w;
+wire [4:0] rx_cdc_cdc_rdport_adr;
+wire [41:0] rx_cdc_cdc_rdport_dat_r;
+wire [31:0] rx_cdc_cdc_fifo_in_payload_data;
+wire [3:0] rx_cdc_cdc_fifo_in_payload_last_be;
+wire [3:0] rx_cdc_cdc_fifo_in_payload_error;
+wire rx_cdc_cdc_fifo_in_first;
+wire rx_cdc_cdc_fifo_in_last;
+wire [31:0] rx_cdc_cdc_fifo_out_payload_data;
+wire [3:0] rx_cdc_cdc_fifo_out_payload_last_be;
+wire [3:0] rx_cdc_cdc_fifo_out_payload_error;
+wire rx_cdc_cdc_fifo_out_first;
+wire rx_cdc_cdc_fifo_out_last;
+wire sink_valid;
+wire sink_ready;
+wire sink_first;
+wire sink_last;
+wire [31:0] sink_payload_data;
+wire [3:0] sink_payload_last_be;
+wire [3:0] sink_payload_error;
+wire source_valid;
+wire source_ready;
+wire source_first;
+wire source_last;
+wire [31:0] source_payload_data;
+wire [3:0] source_payload_last_be;
+wire [3:0] source_payload_error;
+wire [29:0] bus_adr;
+wire [31:0] bus_dat_w;
+wire [31:0] bus_dat_r;
+wire [3:0] bus_sel;
+wire bus_cyc;
+wire bus_stb;
+wire bus_ack;
+wire bus_we;
+wire [2:0] bus_cti;
+wire [1:0] bus_bte;
+wire bus_err;
+wire writer_sink_sink_valid;
+reg writer_sink_sink_ready = 1'd1;
+wire writer_sink_sink_first;
+wire writer_sink_sink_last;
+wire [31:0] writer_sink_sink_payload_data;
+wire [3:0] writer_sink_sink_payload_last_be;
+wire [3:0] writer_sink_sink_payload_error;
+wire writer_slot_status;
+wire writer_slot_we;
+reg writer_slot_re = 1'd0;
+wire [31:0] writer_length_status;
+wire writer_length_we;
+reg writer_length_re = 1'd0;
+reg [31:0] writer_errors_status = 32'd0;
+wire writer_errors_we;
+reg writer_errors_re = 1'd0;
+wire writer_irq;
+wire writer_available_status;
+wire writer_available_pending;
+wire writer_available_trigger;
+reg writer_available_clear = 1'd0;
+wire writer_available0;
+wire writer_status_status;
+wire writer_status_we;
+reg writer_status_re = 1'd0;
+wire writer_available1;
+wire writer_pending_status;
+wire writer_pending_we;
+reg writer_pending_re = 1'd0;
+reg writer_pending_r = 1'd0;
+wire writer_available2;
+reg writer_enable_storage = 1'd0;
+reg writer_enable_re = 1'd0;
+reg [2:0] writer_inc = 3'd0;
+reg [31:0] writer_counter = 32'd0;
+reg writer_slot = 1'd0;
+reg writer_slot_ce = 1'd0;
+reg writer_start = 1'd0;
+reg writer_ongoing = 1'd0;
+reg writer_stat_fifo_sink_valid = 1'd0;
+wire writer_stat_fifo_sink_ready;
+reg writer_stat_fifo_sink_first = 1'd0;
+reg writer_stat_fifo_sink_last = 1'd0;
+wire writer_stat_fifo_sink_payload_slot;
+wire [31:0] writer_stat_fifo_sink_payload_length;
+wire writer_stat_fifo_source_valid;
+wire writer_stat_fifo_source_ready;
+wire writer_stat_fifo_source_first;
+wire writer_stat_fifo_source_last;
+wire writer_stat_fifo_source_payload_slot;
+wire [31:0] writer_stat_fifo_source_payload_length;
+wire writer_stat_fifo_syncfifo_we;
+wire writer_stat_fifo_syncfifo_writable;
+wire writer_stat_fifo_syncfifo_re;
+wire writer_stat_fifo_syncfifo_readable;
+wire [34:0] writer_stat_fifo_syncfifo_din;
+wire [34:0] writer_stat_fifo_syncfifo_dout;
+reg [1:0] writer_stat_fifo_level = 2'd0;
+reg writer_stat_fifo_replace = 1'd0;
+reg writer_stat_fifo_produce = 1'd0;
+reg writer_stat_fifo_consume = 1'd0;
+reg writer_stat_fifo_wrport_adr = 1'd0;
+wire [34:0] writer_stat_fifo_wrport_dat_r;
+wire writer_stat_fifo_wrport_we;
+wire [34:0] writer_stat_fifo_wrport_dat_w;
+wire writer_stat_fifo_do_read;
+wire writer_stat_fifo_rdport_adr;
+wire [34:0] writer_stat_fifo_rdport_dat_r;
+wire writer_stat_fifo_fifo_in_payload_slot;
+wire [31:0] writer_stat_fifo_fifo_in_payload_length;
+wire writer_stat_fifo_fifo_in_first;
+wire writer_stat_fifo_fifo_in_last;
+wire writer_stat_fifo_fifo_out_payload_slot;
+wire [31:0] writer_stat_fifo_fifo_out_payload_length;
+wire writer_stat_fifo_fifo_out_first;
+wire writer_stat_fifo_fifo_out_last;
+reg [8:0] writer_memory0_adr = 9'd0;
+wire [31:0] writer_memory0_dat_r;
+reg writer_memory0_we = 1'd0;
+reg [31:0] writer_memory0_dat_w = 32'd0;
+reg [8:0] writer_memory1_adr = 9'd0;
+wire [31:0] writer_memory1_dat_r;
+reg writer_memory1_we = 1'd0;
+reg [31:0] writer_memory1_dat_w = 32'd0;
+reg reader_source_source_valid = 1'd0;
+wire reader_source_source_ready;
+reg reader_source_source_first = 1'd0;
+reg reader_source_source_last = 1'd0;
+reg [31:0] reader_source_source_payload_data = 32'd0;
+reg [3:0] reader_source_source_payload_last_be = 4'd0;
+reg [3:0] reader_source_source_payload_error = 4'd0;
+reg reader_start_start_re = 1'd0;
+wire reader_start_start_r;
+reg reader_start_start_we = 1'd0;
+reg reader_start_start_w = 1'd0;
+wire reader_ready_status;
+wire reader_ready_we;
+reg reader_ready_re = 1'd0;
+wire [1:0] reader_level_status;
+wire reader_level_we;
+reg reader_level_re = 1'd0;
+reg reader_slot_storage = 1'd0;
+reg reader_slot_re = 1'd0;
+reg [10:0] reader_length_storage = 11'd0;
+reg reader_length_re = 1'd0;
+wire reader_irq;
+wire reader_eventsourcepulse_status;
+reg reader_eventsourcepulse_pending = 1'd0;
+reg reader_eventsourcepulse_trigger = 1'd0;
+reg reader_eventsourcepulse_clear = 1'd0;
+wire reader_event00;
+wire reader_status_status;
+wire reader_status_we;
+reg reader_status_re = 1'd0;
+wire reader_event01;
+wire reader_pending_status;
+wire reader_pending_we;
+reg reader_pending_re = 1'd0;
+reg reader_pending_r = 1'd0;
+wire reader_event02;
+reg reader_enable_storage = 1'd0;
+reg reader_enable_re = 1'd0;
+reg reader_start = 1'd0;
+wire reader_cmd_fifo_sink_valid;
+wire reader_cmd_fifo_sink_ready;
+reg reader_cmd_fifo_sink_first = 1'd0;
+reg reader_cmd_fifo_sink_last = 1'd0;
+wire reader_cmd_fifo_sink_payload_slot;
+wire [10:0] reader_cmd_fifo_sink_payload_length;
+wire reader_cmd_fifo_source_valid;
+reg reader_cmd_fifo_source_ready = 1'd0;
+wire reader_cmd_fifo_source_first;
+wire reader_cmd_fifo_source_last;
+wire reader_cmd_fifo_source_payload_slot;
+wire [10:0] reader_cmd_fifo_source_payload_length;
+wire reader_cmd_fifo_syncfifo_we;
+wire reader_cmd_fifo_syncfifo_writable;
+wire reader_cmd_fifo_syncfifo_re;
+wire reader_cmd_fifo_syncfifo_readable;
+wire [13:0] reader_cmd_fifo_syncfifo_din;
+wire [13:0] reader_cmd_fifo_syncfifo_dout;
+reg [1:0] reader_cmd_fifo_level = 2'd0;
+reg reader_cmd_fifo_replace = 1'd0;
+reg reader_cmd_fifo_produce = 1'd0;
+reg reader_cmd_fifo_consume = 1'd0;
+reg reader_cmd_fifo_wrport_adr = 1'd0;
+wire [13:0] reader_cmd_fifo_wrport_dat_r;
+wire reader_cmd_fifo_wrport_we;
+wire [13:0] reader_cmd_fifo_wrport_dat_w;
+wire reader_cmd_fifo_do_read;
+wire reader_cmd_fifo_rdport_adr;
+wire [13:0] reader_cmd_fifo_rdport_dat_r;
+wire reader_cmd_fifo_fifo_in_payload_slot;
+wire [10:0] reader_cmd_fifo_fifo_in_payload_length;
+wire reader_cmd_fifo_fifo_in_first;
+wire reader_cmd_fifo_fifo_in_last;
+wire reader_cmd_fifo_fifo_out_payload_slot;
+wire [10:0] reader_cmd_fifo_fifo_out_payload_length;
+wire reader_cmd_fifo_fifo_out_first;
+wire reader_cmd_fifo_fifo_out_last;
+reg [10:0] reader_read_address = 11'd0;
+reg [10:0] reader_counter = 11'd0;
+wire [8:0] reader_memory0_adr;
+wire [31:0] reader_memory0_dat_r;
+wire [8:0] reader_memory1_adr;
+wire [31:0] reader_memory1_dat_r;
+wire ev_irq;
+wire [29:0] sram0_bus_adr0;
+wire [31:0] sram0_bus_dat_w0;
+wire [31:0] sram0_bus_dat_r0;
+wire [3:0] sram0_bus_sel0;
+wire sram0_bus_cyc0;
+wire sram0_bus_stb0;
+reg sram0_bus_ack0 = 1'd0;
+wire sram0_bus_we0;
+wire [2:0] sram0_bus_cti0;
+wire [1:0] sram0_bus_bte0;
+reg sram0_bus_err0 = 1'd0;
+wire [8:0] sram0_adr0;
+wire [31:0] sram0_dat_r0;
+wire [29:0] sram1_bus_adr0;
+wire [31:0] sram1_bus_dat_w0;
+wire [31:0] sram1_bus_dat_r0;
+wire [3:0] sram1_bus_sel0;
+wire sram1_bus_cyc0;
+wire sram1_bus_stb0;
+reg sram1_bus_ack0 = 1'd0;
+wire sram1_bus_we0;
+wire [2:0] sram1_bus_cti0;
+wire [1:0] sram1_bus_bte0;
+reg sram1_bus_err0 = 1'd0;
+wire [8:0] sram1_adr0;
+wire [31:0] sram1_dat_r0;
+wire [29:0] sram0_bus_adr1;
+wire [31:0] sram0_bus_dat_w1;
+wire [31:0] sram0_bus_dat_r1;
+wire [3:0] sram0_bus_sel1;
+wire sram0_bus_cyc1;
+wire sram0_bus_stb1;
+reg sram0_bus_ack1 = 1'd0;
+wire sram0_bus_we1;
+wire [2:0] sram0_bus_cti1;
+wire [1:0] sram0_bus_bte1;
+reg sram0_bus_err1 = 1'd0;
+wire [8:0] sram0_adr1;
+wire [31:0] sram0_dat_r1;
+reg [3:0] sram0_we = 4'd0;
+wire [31:0] sram0_dat_w;
+wire [29:0] sram1_bus_adr1;
+wire [31:0] sram1_bus_dat_w1;
+wire [31:0] sram1_bus_dat_r1;
+wire [3:0] sram1_bus_sel1;
+wire sram1_bus_cyc1;
+wire sram1_bus_stb1;
+reg sram1_bus_ack1 = 1'd0;
+wire sram1_bus_we1;
+wire [2:0] sram1_bus_cti1;
+wire [1:0] sram1_bus_bte1;
+reg sram1_bus_err1 = 1'd0;
+wire [8:0] sram1_adr1;
+wire [31:0] sram1_dat_r1;
+reg [3:0] sram1_we = 4'd0;
+wire [31:0] sram1_dat_w;
+reg [3:0] slave_sel = 4'd0;
+reg [3:0] slave_sel_r = 4'd0;
+wire [29:0] wb_bus_adr;
+wire [31:0] wb_bus_dat_w;
+wire [31:0] wb_bus_dat_r;
+wire [3:0] wb_bus_sel;
+wire wb_bus_cyc;
+wire wb_bus_stb;
+wire wb_bus_ack;
+wire wb_bus_we;
+wire [2:0] wb_bus_cti;
+wire [1:0] wb_bus_bte;
+wire wb_bus_err;
+reg [1:0] subfragments_state = 2'd0;
+reg [1:0] subfragments_next_state = 2'd0;
+reg subfragments_liteethmacgap_state = 1'd0;
+reg subfragments_liteethmacgap_next_state = 1'd0;
+reg [3:0] tx_gap_inserter_counter_liteethmacgap_next_value = 4'd0;
+reg tx_gap_inserter_counter_liteethmacgap_next_value_ce = 1'd0;
+reg [1:0] subfragments_liteethmacpreambleinserter_state = 2'd0;
+reg [1:0] subfragments_liteethmacpreambleinserter_next_state = 2'd0;
+reg [2:0] preamble_inserter_count_liteethmacpreambleinserter_next_value = 3'd0;
+reg preamble_inserter_count_liteethmacpreambleinserter_next_value_ce = 1'd0;
+reg subfragments_liteethmacpreamblechecker_state = 1'd0;
+reg subfragments_liteethmacpreamblechecker_next_state = 1'd0;
+reg [1:0] subfragments_liteethmaccrc32inserter_state = 2'd0;
+reg [1:0] subfragments_liteethmaccrc32inserter_next_state = 2'd0;
+reg [1:0] subfragments_liteethmaccrc32checker_state = 2'd0;
+reg [1:0] subfragments_liteethmaccrc32checker_next_state = 2'd0;
+reg subfragments_liteethmacpaddinginserter_state = 1'd0;
+reg subfragments_liteethmacpaddinginserter_next_state = 1'd0;
+reg [15:0] padding_inserter_counter_liteethmacpaddinginserter_next_value = 16'd0;
+reg padding_inserter_counter_liteethmacpaddinginserter_next_value_ce = 1'd0;
+reg subfragments_liteethmactxlastbe_state = 1'd0;
+reg subfragments_liteethmactxlastbe_next_state = 1'd0;
+reg [2:0] subfragments_liteethmacsramwriter_state = 3'd0;
+reg [2:0] subfragments_liteethmacsramwriter_next_state = 3'd0;
+reg [31:0] writer_counter_t_next_value = 32'd0;
+reg writer_counter_t_next_value_ce = 1'd0;
+reg [31:0] writer_errors_status_f_next_value = 32'd0;
+reg writer_errors_status_f_next_value_ce = 1'd0;
+reg [1:0] subfragments_liteethmacsramreader_state = 2'd0;
+reg [1:0] subfragments_liteethmacsramreader_next_state = 2'd0;
+reg [10:0] reader_counter_next_value = 11'd0;
+reg reader_counter_next_value_ce = 1'd0;
+reg [13:0] maccore_maccore_adr = 14'd0;
+reg maccore_maccore_we = 1'd0;
+reg [31:0] maccore_maccore_dat_w = 32'd0;
+wire [31:0] maccore_maccore_dat_r;
+wire [29:0] maccore_maccore_wishbone_adr;
+wire [31:0] maccore_maccore_wishbone_dat_w;
+reg [31:0] maccore_maccore_wishbone_dat_r = 32'd0;
+wire [3:0] maccore_maccore_wishbone_sel;
+wire maccore_maccore_wishbone_cyc;
+wire maccore_maccore_wishbone_stb;
+reg maccore_maccore_wishbone_ack = 1'd0;
+wire maccore_maccore_wishbone_we;
+wire [2:0] maccore_maccore_wishbone_cti;
+wire [1:0] maccore_maccore_wishbone_bte;
+reg maccore_maccore_wishbone_err = 1'd0;
+wire [29:0] maccore_shared_adr;
+wire [31:0] maccore_shared_dat_w;
+reg [31:0] maccore_shared_dat_r = 32'd0;
+wire [3:0] maccore_shared_sel;
+wire maccore_shared_cyc;
+wire maccore_shared_stb;
+reg maccore_shared_ack = 1'd0;
+wire maccore_shared_we;
+wire [2:0] maccore_shared_cti;
+wire [1:0] maccore_shared_bte;
+wire maccore_shared_err;
+wire maccore_request;
+wire maccore_grant;
+reg [1:0] maccore_slave_sel = 2'd0;
+reg [1:0] maccore_slave_sel_r = 2'd0;
+reg maccore_error = 1'd0;
+wire maccore_wait;
+wire maccore_done;
+reg [19:0] maccore_count = 20'd1000000;
+wire [13:0] maccore_interface0_bank_bus_adr;
+wire maccore_interface0_bank_bus_we;
+wire [31:0] maccore_interface0_bank_bus_dat_w;
+reg [31:0] maccore_interface0_bank_bus_dat_r = 32'd0;
+reg maccore_csrbank0_reset0_re = 1'd0;
+wire [1:0] maccore_csrbank0_reset0_r;
+reg maccore_csrbank0_reset0_we = 1'd0;
+wire [1:0] maccore_csrbank0_reset0_w;
+reg maccore_csrbank0_scratch0_re = 1'd0;
+wire [31:0] maccore_csrbank0_scratch0_r;
+reg maccore_csrbank0_scratch0_we = 1'd0;
+wire [31:0] maccore_csrbank0_scratch0_w;
+reg maccore_csrbank0_bus_errors_re = 1'd0;
+wire [31:0] maccore_csrbank0_bus_errors_r;
+reg maccore_csrbank0_bus_errors_we = 1'd0;
+wire [31:0] maccore_csrbank0_bus_errors_w;
+wire maccore_csrbank0_sel;
+wire [13:0] maccore_interface1_bank_bus_adr;
+wire maccore_interface1_bank_bus_we;
+wire [31:0] maccore_interface1_bank_bus_dat_w;
+reg [31:0] maccore_interface1_bank_bus_dat_r = 32'd0;
+reg maccore_csrbank1_sram_writer_slot_re = 1'd0;
+wire maccore_csrbank1_sram_writer_slot_r;
+reg maccore_csrbank1_sram_writer_slot_we = 1'd0;
+wire maccore_csrbank1_sram_writer_slot_w;
+reg maccore_csrbank1_sram_writer_length_re = 1'd0;
+wire [31:0] maccore_csrbank1_sram_writer_length_r;
+reg maccore_csrbank1_sram_writer_length_we = 1'd0;
+wire [31:0] maccore_csrbank1_sram_writer_length_w;
+reg maccore_csrbank1_sram_writer_errors_re = 1'd0;
+wire [31:0] maccore_csrbank1_sram_writer_errors_r;
+reg maccore_csrbank1_sram_writer_errors_we = 1'd0;
+wire [31:0] maccore_csrbank1_sram_writer_errors_w;
+reg maccore_csrbank1_sram_writer_ev_status_re = 1'd0;
+wire maccore_csrbank1_sram_writer_ev_status_r;
+reg maccore_csrbank1_sram_writer_ev_status_we = 1'd0;
+wire maccore_csrbank1_sram_writer_ev_status_w;
+reg maccore_csrbank1_sram_writer_ev_pending_re = 1'd0;
+wire maccore_csrbank1_sram_writer_ev_pending_r;
+reg maccore_csrbank1_sram_writer_ev_pending_we = 1'd0;
+wire maccore_csrbank1_sram_writer_ev_pending_w;
+reg maccore_csrbank1_sram_writer_ev_enable0_re = 1'd0;
+wire maccore_csrbank1_sram_writer_ev_enable0_r;
+reg maccore_csrbank1_sram_writer_ev_enable0_we = 1'd0;
+wire maccore_csrbank1_sram_writer_ev_enable0_w;
+reg maccore_csrbank1_sram_reader_ready_re = 1'd0;
+wire maccore_csrbank1_sram_reader_ready_r;
+reg maccore_csrbank1_sram_reader_ready_we = 1'd0;
+wire maccore_csrbank1_sram_reader_ready_w;
+reg maccore_csrbank1_sram_reader_level_re = 1'd0;
+wire [1:0] maccore_csrbank1_sram_reader_level_r;
+reg maccore_csrbank1_sram_reader_level_we = 1'd0;
+wire [1:0] maccore_csrbank1_sram_reader_level_w;
+reg maccore_csrbank1_sram_reader_slot0_re = 1'd0;
+wire maccore_csrbank1_sram_reader_slot0_r;
+reg maccore_csrbank1_sram_reader_slot0_we = 1'd0;
+wire maccore_csrbank1_sram_reader_slot0_w;
+reg maccore_csrbank1_sram_reader_length0_re = 1'd0;
+wire [10:0] maccore_csrbank1_sram_reader_length0_r;
+reg maccore_csrbank1_sram_reader_length0_we = 1'd0;
+wire [10:0] maccore_csrbank1_sram_reader_length0_w;
+reg maccore_csrbank1_sram_reader_ev_status_re = 1'd0;
+wire maccore_csrbank1_sram_reader_ev_status_r;
+reg maccore_csrbank1_sram_reader_ev_status_we = 1'd0;
+wire maccore_csrbank1_sram_reader_ev_status_w;
+reg maccore_csrbank1_sram_reader_ev_pending_re = 1'd0;
+wire maccore_csrbank1_sram_reader_ev_pending_r;
+reg maccore_csrbank1_sram_reader_ev_pending_we = 1'd0;
+wire maccore_csrbank1_sram_reader_ev_pending_w;
+reg maccore_csrbank1_sram_reader_ev_enable0_re = 1'd0;
+wire maccore_csrbank1_sram_reader_ev_enable0_r;
+reg maccore_csrbank1_sram_reader_ev_enable0_we = 1'd0;
+wire maccore_csrbank1_sram_reader_ev_enable0_w;
+reg maccore_csrbank1_preamble_crc_re = 1'd0;
+wire maccore_csrbank1_preamble_crc_r;
+reg maccore_csrbank1_preamble_crc_we = 1'd0;
+wire maccore_csrbank1_preamble_crc_w;
+reg maccore_csrbank1_preamble_errors_re = 1'd0;
+wire [31:0] maccore_csrbank1_preamble_errors_r;
+reg maccore_csrbank1_preamble_errors_we = 1'd0;
+wire [31:0] maccore_csrbank1_preamble_errors_w;
+reg maccore_csrbank1_crc_errors_re = 1'd0;
+wire [31:0] maccore_csrbank1_crc_errors_r;
+reg maccore_csrbank1_crc_errors_we = 1'd0;
+wire [31:0] maccore_csrbank1_crc_errors_w;
+wire maccore_csrbank1_sel;
+wire [13:0] maccore_interface2_bank_bus_adr;
+wire maccore_interface2_bank_bus_we;
+wire [31:0] maccore_interface2_bank_bus_dat_w;
+reg [31:0] maccore_interface2_bank_bus_dat_r = 32'd0;
+reg maccore_csrbank2_mode_detection_mode_re = 1'd0;
+wire maccore_csrbank2_mode_detection_mode_r;
+reg maccore_csrbank2_mode_detection_mode_we = 1'd0;
+wire maccore_csrbank2_mode_detection_mode_w;
+reg maccore_csrbank2_crg_reset0_re = 1'd0;
+wire maccore_csrbank2_crg_reset0_r;
+reg maccore_csrbank2_crg_reset0_we = 1'd0;
+wire maccore_csrbank2_crg_reset0_w;
+reg maccore_csrbank2_mdio_w0_re = 1'd0;
+wire [2:0] maccore_csrbank2_mdio_w0_r;
+reg maccore_csrbank2_mdio_w0_we = 1'd0;
+wire [2:0] maccore_csrbank2_mdio_w0_w;
+reg maccore_csrbank2_mdio_r_re = 1'd0;
+wire maccore_csrbank2_mdio_r_r;
+reg maccore_csrbank2_mdio_r_we = 1'd0;
+wire maccore_csrbank2_mdio_r_w;
+wire maccore_csrbank2_sel;
+wire [13:0] maccore_csr_interconnect_adr;
+wire maccore_csr_interconnect_we;
+wire [31:0] maccore_csr_interconnect_dat_w;
+wire [31:0] maccore_csr_interconnect_dat_r;
+reg maccore_state = 1'd0;
+reg maccore_next_state = 1'd0;
+reg [29:0] array_muxed0 = 30'd0;
+reg [31:0] array_muxed1 = 32'd0;
+reg [3:0] array_muxed2 = 4'd0;
+reg array_muxed3 = 1'd0;
+reg array_muxed4 = 1'd0;
+reg array_muxed5 = 1'd0;
+reg [2:0] array_muxed6 = 3'd0;
+reg [1:0] array_muxed7 = 2'd0;
+(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg xilinxmultiregimpl0_regs0 = 1'd0;
+(* async_reg = "true", dont_touch = "true" *) reg xilinxmultiregimpl0_regs1 = 1'd0;
+wire rst_meta0;
+wire rst_meta1;
+(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg xilinxmultiregimpl1_regs0 = 1'd0;
+(* async_reg = "true", dont_touch = "true" *) reg xilinxmultiregimpl1_regs1 = 1'd0;
+(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg xilinxmultiregimpl2_regs0 = 1'd0;
+(* async_reg = "true", dont_touch = "true" *) reg xilinxmultiregimpl2_regs1 = 1'd0;
+(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg xilinxmultiregimpl3_regs0 = 1'd0;
+(* async_reg = "true", dont_touch = "true" *) reg xilinxmultiregimpl3_regs1 = 1'd0;
+(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg [5:0] xilinxmultiregimpl4_regs0 = 6'd0;
+(* async_reg = "true", dont_touch = "true" *) reg [5:0] xilinxmultiregimpl4_regs1 = 6'd0;
+(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg [5:0] xilinxmultiregimpl5_regs0 = 6'd0;
+(* async_reg = "true", dont_touch = "true" *) reg [5:0] xilinxmultiregimpl5_regs1 = 6'd0;
+(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg [5:0] xilinxmultiregimpl6_regs0 = 6'd0;
+(* async_reg = "true", dont_touch = "true" *) reg [5:0] xilinxmultiregimpl6_regs1 = 6'd0;
+(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg [5:0] xilinxmultiregimpl7_regs0 = 6'd0;
+(* async_reg = "true", dont_touch = "true" *) reg [5:0] xilinxmultiregimpl7_regs1 = 6'd0;
+
+assign wb_bus_adr = wishbone_adr;
+assign wb_bus_dat_w = wishbone_dat_w;
+assign wishbone_dat_r = wb_bus_dat_r;
+assign wb_bus_sel = wishbone_sel;
+assign wb_bus_cyc = wishbone_cyc;
+assign wb_bus_stb = wishbone_stb;
+assign wishbone_ack = wb_bus_ack;
+assign wb_bus_we = wishbone_we;
+assign wb_bus_cti = wishbone_cti;
+assign wb_bus_bte = wishbone_bte;
+assign wishbone_err = wb_bus_err;
+assign interrupt = ev_irq;
+assign maccore_maccore_bus_error = maccore_error;
+assign maccore_maccore_bus_errors_status = maccore_maccore_bus_errors;
+assign sys_clk = sys_clock;
+assign por_clk = sys_clock;
+assign sys_rst = maccore_int_rst;
+assign maccore_ethphy_mode_status = maccore_ethphy_mode0;
+assign maccore_ethphy_eth_tick = (maccore_ethphy_eth_counter == 1'd0);
+assign maccore_ethphy_i = maccore_ethphy_eth_tick;
+assign maccore_ethphy_sys_tick = maccore_ethphy_o;
+assign maccore_ethphy_o = (maccore_ethphy_toggle_o ^ maccore_ethphy_toggle_o_r);
+always @(*) begin
+	subfragments_next_state <= 2'd0;
+	maccore_ethphy_sys_counter_reset <= 1'd0;
+	maccore_ethphy_sys_counter_ce <= 1'd0;
+	maccore_ethphy_mode1 <= 1'd0;
+	maccore_ethphy_update_mode <= 1'd0;
+	subfragments_next_state <= subfragments_state;
+	case (subfragments_state)
+		1'd1: begin
+			maccore_ethphy_sys_counter_ce <= 1'd1;
+			if (maccore_ethphy_sys_tick) begin
+				subfragments_next_state <= 2'd2;
+			end
+		end
+		2'd2: begin
+			maccore_ethphy_update_mode <= 1'd1;
+			if ((maccore_ethphy_sys_counter > 10'd860)) begin
+				maccore_ethphy_mode1 <= 1'd1;
+			end else begin
+				maccore_ethphy_mode1 <= 1'd0;
+			end
+			subfragments_next_state <= 1'd0;
+		end
+		default: begin
+			maccore_ethphy_sys_counter_reset <= 1'd1;
+			if (maccore_ethphy_sys_tick) begin
+				subfragments_next_state <= 1'd1;
+			end
+		end
+	endcase
+end
+always @(*) begin
+	maccore_ethphy_eth_tx_clk <= 1'd0;
+	if ((maccore_ethphy_mode0 == 1'd1)) begin
+		maccore_ethphy_eth_tx_clk <= gmii_eth_clocks_tx;
+	end else begin
+		maccore_ethphy_eth_tx_clk <= gmii_eth_clocks_rx;
+	end
+end
+assign maccore_ethphy_reset0 = (maccore_ethphy_reset_storage | maccore_ethphy_reset1);
+assign gmii_eth_rst_n = (~maccore_ethphy_reset0);
+assign maccore_ethphy_counter_done = (maccore_ethphy_counter == 9'd256);
+assign maccore_ethphy_counter_ce = (~maccore_ethphy_counter_done);
+assign maccore_ethphy_reset1 = (~maccore_ethphy_counter_done);
+assign maccore_ethphy_liteethphygmiimiitx_demux_sel = (maccore_ethphy_mode0 == 1'd1);
+assign maccore_ethphy_liteethphygmiimiitx_demux_sink_valid = maccore_ethphy_liteethphygmiimiitx_sink_sink_valid0;
+assign maccore_ethphy_liteethphygmiimiitx_sink_sink_ready0 = maccore_ethphy_liteethphygmiimiitx_demux_sink_ready;
+assign maccore_ethphy_liteethphygmiimiitx_demux_sink_first = maccore_ethphy_liteethphygmiimiitx_sink_sink_first0;
+assign maccore_ethphy_liteethphygmiimiitx_demux_sink_last = maccore_ethphy_liteethphygmiimiitx_sink_sink_last0;
+assign maccore_ethphy_liteethphygmiimiitx_demux_sink_payload_data = maccore_ethphy_liteethphygmiimiitx_sink_sink_payload_data0;
+assign maccore_ethphy_liteethphygmiimiitx_demux_sink_payload_last_be = maccore_ethphy_liteethphygmiimiitx_sink_sink_payload_last_be0;
+assign maccore_ethphy_liteethphygmiimiitx_demux_sink_payload_error = maccore_ethphy_liteethphygmiimiitx_sink_sink_payload_error0;
+assign maccore_ethphy_liteethphygmiimiitx_gmii_tx_sink_valid = maccore_ethphy_liteethphygmiimiitx_demux_endpoint0_source_valid;
+assign maccore_ethphy_liteethphygmiimiitx_demux_endpoint0_source_ready = maccore_ethphy_liteethphygmiimiitx_gmii_tx_sink_ready;
+assign maccore_ethphy_liteethphygmiimiitx_gmii_tx_sink_first = maccore_ethphy_liteethphygmiimiitx_demux_endpoint0_source_first;
+assign maccore_ethphy_liteethphygmiimiitx_gmii_tx_sink_last = maccore_ethphy_liteethphygmiimiitx_demux_endpoint0_source_last;
+assign maccore_ethphy_liteethphygmiimiitx_gmii_tx_sink_payload_data = maccore_ethphy_liteethphygmiimiitx_demux_endpoint0_source_payload_data;
+assign maccore_ethphy_liteethphygmiimiitx_gmii_tx_sink_payload_last_be = maccore_ethphy_liteethphygmiimiitx_demux_endpoint0_source_payload_last_be;
+assign maccore_ethphy_liteethphygmiimiitx_gmii_tx_sink_payload_error = maccore_ethphy_liteethphygmiimiitx_demux_endpoint0_source_payload_error;
+assign maccore_ethphy_liteethphygmiimiitx_sink_sink_valid1 = maccore_ethphy_liteethphygmiimiitx_demux_endpoint1_source_valid;
+assign maccore_ethphy_liteethphygmiimiitx_demux_endpoint1_source_ready = maccore_ethphy_liteethphygmiimiitx_sink_sink_ready1;
+assign maccore_ethphy_liteethphygmiimiitx_sink_sink_first1 = maccore_ethphy_liteethphygmiimiitx_demux_endpoint1_source_first;
+assign maccore_ethphy_liteethphygmiimiitx_sink_sink_last1 = maccore_ethphy_liteethphygmiimiitx_demux_endpoint1_source_last;
+assign maccore_ethphy_liteethphygmiimiitx_sink_sink_payload_data1 = maccore_ethphy_liteethphygmiimiitx_demux_endpoint1_source_payload_data;
+assign maccore_ethphy_liteethphygmiimiitx_sink_sink_payload_last_be1 = maccore_ethphy_liteethphygmiimiitx_demux_endpoint1_source_payload_last_be;
+assign maccore_ethphy_liteethphygmiimiitx_sink_sink_payload_error1 = maccore_ethphy_liteethphygmiimiitx_demux_endpoint1_source_payload_error;
+assign gmii_eth_tx_er = 1'd0;
+assign maccore_ethphy_liteethphygmiimiitx_converter_sink_valid = maccore_ethphy_liteethphygmiimiitx_sink_sink_valid1;
+assign maccore_ethphy_liteethphygmiimiitx_converter_sink_payload_data = maccore_ethphy_liteethphygmiimiitx_sink_sink_payload_data1;
+assign maccore_ethphy_liteethphygmiimiitx_sink_sink_ready1 = maccore_ethphy_liteethphygmiimiitx_converter_sink_ready;
+assign maccore_ethphy_liteethphygmiimiitx_converter_source_ready = 1'd1;
+assign maccore_ethphy_liteethphygmiimiitx_converter_converter_sink_valid = maccore_ethphy_liteethphygmiimiitx_converter_sink_valid;
+assign maccore_ethphy_liteethphygmiimiitx_converter_converter_sink_first = maccore_ethphy_liteethphygmiimiitx_converter_sink_first;
+assign maccore_ethphy_liteethphygmiimiitx_converter_converter_sink_last = maccore_ethphy_liteethphygmiimiitx_converter_sink_last;
+assign maccore_ethphy_liteethphygmiimiitx_converter_sink_ready = maccore_ethphy_liteethphygmiimiitx_converter_converter_sink_ready;
+always @(*) begin
+	maccore_ethphy_liteethphygmiimiitx_converter_converter_sink_payload_data <= 8'd0;
+	maccore_ethphy_liteethphygmiimiitx_converter_converter_sink_payload_data[3:0] <= maccore_ethphy_liteethphygmiimiitx_converter_sink_payload_data[3:0];
+	maccore_ethphy_liteethphygmiimiitx_converter_converter_sink_payload_data[7:4] <= maccore_ethphy_liteethphygmiimiitx_converter_sink_payload_data[7:4];
+end
+assign maccore_ethphy_liteethphygmiimiitx_converter_source_valid = maccore_ethphy_liteethphygmiimiitx_converter_source_source_valid;
+assign maccore_ethphy_liteethphygmiimiitx_converter_source_first = maccore_ethphy_liteethphygmiimiitx_converter_source_source_first;
+assign maccore_ethphy_liteethphygmiimiitx_converter_source_last = maccore_ethphy_liteethphygmiimiitx_converter_source_source_last;
+assign maccore_ethphy_liteethphygmiimiitx_converter_source_source_ready = maccore_ethphy_liteethphygmiimiitx_converter_source_ready;
+assign {maccore_ethphy_liteethphygmiimiitx_converter_source_payload_data} = maccore_ethphy_liteethphygmiimiitx_converter_source_source_payload_data;
+assign maccore_ethphy_liteethphygmiimiitx_converter_source_source_valid = maccore_ethphy_liteethphygmiimiitx_converter_converter_source_valid;
+assign maccore_ethphy_liteethphygmiimiitx_converter_converter_source_ready = maccore_ethphy_liteethphygmiimiitx_converter_source_source_ready;
+assign maccore_ethphy_liteethphygmiimiitx_converter_source_source_first = maccore_ethphy_liteethphygmiimiitx_converter_converter_source_first;
+assign maccore_ethphy_liteethphygmiimiitx_converter_source_source_last = maccore_ethphy_liteethphygmiimiitx_converter_converter_source_last;
+assign maccore_ethphy_liteethphygmiimiitx_converter_source_source_payload_data = maccore_ethphy_liteethphygmiimiitx_converter_converter_source_payload_data;
+assign maccore_ethphy_liteethphygmiimiitx_converter_converter_first = (maccore_ethphy_liteethphygmiimiitx_converter_converter_mux == 1'd0);
+assign maccore_ethphy_liteethphygmiimiitx_converter_converter_last = (maccore_ethphy_liteethphygmiimiitx_converter_converter_mux == 1'd1);
+assign maccore_ethphy_liteethphygmiimiitx_converter_converter_source_valid = maccore_ethphy_liteethphygmiimiitx_converter_converter_sink_valid;
+assign maccore_ethphy_liteethphygmiimiitx_converter_converter_source_first = (maccore_ethphy_liteethphygmiimiitx_converter_converter_sink_first & maccore_ethphy_liteethphygmiimiitx_converter_converter_first);
+assign maccore_ethphy_liteethphygmiimiitx_converter_converter_source_last = (maccore_ethphy_liteethphygmiimiitx_converter_converter_sink_last & maccore_ethphy_liteethphygmiimiitx_converter_converter_last);
+assign maccore_ethphy_liteethphygmiimiitx_converter_converter_sink_ready = (maccore_ethphy_liteethphygmiimiitx_converter_converter_last & maccore_ethphy_liteethphygmiimiitx_converter_converter_source_ready);
+always @(*) begin
+	maccore_ethphy_liteethphygmiimiitx_converter_converter_source_payload_data <= 4'd0;
+	case (maccore_ethphy_liteethphygmiimiitx_converter_converter_mux)
+		1'd0: begin
+			maccore_ethphy_liteethphygmiimiitx_converter_converter_source_payload_data <= maccore_ethphy_liteethphygmiimiitx_converter_converter_sink_payload_data[3:0];
+		end
+		default: begin
+			maccore_ethphy_liteethphygmiimiitx_converter_converter_source_payload_data <= maccore_ethphy_liteethphygmiimiitx_converter_converter_sink_payload_data[7:4];
+		end
+	endcase
+end
+assign maccore_ethphy_liteethphygmiimiitx_converter_converter_source_payload_valid_token_count = maccore_ethphy_liteethphygmiimiitx_converter_converter_last;
+always @(*) begin
+	maccore_ethphy_liteethphygmiimiitx_demux_endpoint1_source_payload_data <= 8'd0;
+	maccore_ethphy_liteethphygmiimiitx_demux_endpoint1_source_last <= 1'd0;
+	maccore_ethphy_liteethphygmiimiitx_demux_endpoint1_source_payload_last_be <= 1'd0;
+	maccore_ethphy_liteethphygmiimiitx_demux_endpoint1_source_payload_error <= 1'd0;
+	maccore_ethphy_liteethphygmiimiitx_demux_endpoint0_source_valid <= 1'd0;
+	maccore_ethphy_liteethphygmiimiitx_demux_endpoint0_source_first <= 1'd0;
+	maccore_ethphy_liteethphygmiimiitx_demux_endpoint0_source_last <= 1'd0;
+	maccore_ethphy_liteethphygmiimiitx_demux_endpoint0_source_payload_data <= 8'd0;
+	maccore_ethphy_liteethphygmiimiitx_demux_endpoint0_source_payload_last_be <= 1'd0;
+	maccore_ethphy_liteethphygmiimiitx_demux_endpoint0_source_payload_error <= 1'd0;
+	maccore_ethphy_liteethphygmiimiitx_demux_endpoint1_source_valid <= 1'd0;
+	maccore_ethphy_liteethphygmiimiitx_demux_endpoint1_source_first <= 1'd0;
+	maccore_ethphy_liteethphygmiimiitx_demux_sink_ready <= 1'd0;
+	case (maccore_ethphy_liteethphygmiimiitx_demux_sel)
+		1'd0: begin
+			maccore_ethphy_liteethphygmiimiitx_demux_endpoint0_source_valid <= maccore_ethphy_liteethphygmiimiitx_demux_sink_valid;
+			maccore_ethphy_liteethphygmiimiitx_demux_sink_ready <= maccore_ethphy_liteethphygmiimiitx_demux_endpoint0_source_ready;
+			maccore_ethphy_liteethphygmiimiitx_demux_endpoint0_source_first <= maccore_ethphy_liteethphygmiimiitx_demux_sink_first;
+			maccore_ethphy_liteethphygmiimiitx_demux_endpoint0_source_last <= maccore_ethphy_liteethphygmiimiitx_demux_sink_last;
+			maccore_ethphy_liteethphygmiimiitx_demux_endpoint0_source_payload_data <= maccore_ethphy_liteethphygmiimiitx_demux_sink_payload_data;
+			maccore_ethphy_liteethphygmiimiitx_demux_endpoint0_source_payload_last_be <= maccore_ethphy_liteethphygmiimiitx_demux_sink_payload_last_be;
+			maccore_ethphy_liteethphygmiimiitx_demux_endpoint0_source_payload_error <= maccore_ethphy_liteethphygmiimiitx_demux_sink_payload_error;
+		end
+		1'd1: begin
+			maccore_ethphy_liteethphygmiimiitx_demux_endpoint1_source_valid <= maccore_ethphy_liteethphygmiimiitx_demux_sink_valid;
+			maccore_ethphy_liteethphygmiimiitx_demux_sink_ready <= maccore_ethphy_liteethphygmiimiitx_demux_endpoint1_source_ready;
+			maccore_ethphy_liteethphygmiimiitx_demux_endpoint1_source_first <= maccore_ethphy_liteethphygmiimiitx_demux_sink_first;
+			maccore_ethphy_liteethphygmiimiitx_demux_endpoint1_source_last <= maccore_ethphy_liteethphygmiimiitx_demux_sink_last;
+			maccore_ethphy_liteethphygmiimiitx_demux_endpoint1_source_payload_data <= maccore_ethphy_liteethphygmiimiitx_demux_sink_payload_data;
+			maccore_ethphy_liteethphygmiimiitx_demux_endpoint1_source_payload_last_be <= maccore_ethphy_liteethphygmiimiitx_demux_sink_payload_last_be;
+			maccore_ethphy_liteethphygmiimiitx_demux_endpoint1_source_payload_error <= maccore_ethphy_liteethphygmiimiitx_demux_sink_payload_error;
+		end
+	endcase
+end
+assign maccore_ethphy_liteethphygmiimiirx_mux_sel = (maccore_ethphy_mode0 == 1'd1);
+assign maccore_ethphy_liteethphygmiimiirx_mux_endpoint0_sink_valid = maccore_ethphy_liteethphygmiimiirx_gmii_rx_source_valid;
+assign maccore_ethphy_liteethphygmiimiirx_gmii_rx_source_ready = maccore_ethphy_liteethphygmiimiirx_mux_endpoint0_sink_ready;
+assign maccore_ethphy_liteethphygmiimiirx_mux_endpoint0_sink_first = maccore_ethphy_liteethphygmiimiirx_gmii_rx_source_first;
+assign maccore_ethphy_liteethphygmiimiirx_mux_endpoint0_sink_last = maccore_ethphy_liteethphygmiimiirx_gmii_rx_source_last;
+assign maccore_ethphy_liteethphygmiimiirx_mux_endpoint0_sink_payload_data = maccore_ethphy_liteethphygmiimiirx_gmii_rx_source_payload_data;
+assign maccore_ethphy_liteethphygmiimiirx_mux_endpoint0_sink_payload_last_be = maccore_ethphy_liteethphygmiimiirx_gmii_rx_source_payload_last_be;
+assign maccore_ethphy_liteethphygmiimiirx_mux_endpoint0_sink_payload_error = maccore_ethphy_liteethphygmiimiirx_gmii_rx_source_payload_error;
+assign maccore_ethphy_liteethphygmiimiirx_mux_endpoint1_sink_valid = maccore_ethphy_liteethphygmiimiirx_source_source_valid1;
+assign maccore_ethphy_liteethphygmiimiirx_source_source_ready1 = maccore_ethphy_liteethphygmiimiirx_mux_endpoint1_sink_ready;
+assign maccore_ethphy_liteethphygmiimiirx_mux_endpoint1_sink_first = maccore_ethphy_liteethphygmiimiirx_source_source_first1;
+assign maccore_ethphy_liteethphygmiimiirx_mux_endpoint1_sink_last = maccore_ethphy_liteethphygmiimiirx_source_source_last1;
+assign maccore_ethphy_liteethphygmiimiirx_mux_endpoint1_sink_payload_data = maccore_ethphy_liteethphygmiimiirx_source_source_payload_data1;
+assign maccore_ethphy_liteethphygmiimiirx_mux_endpoint1_sink_payload_last_be = maccore_ethphy_liteethphygmiimiirx_source_source_payload_last_be1;
+assign maccore_ethphy_liteethphygmiimiirx_mux_endpoint1_sink_payload_error = maccore_ethphy_liteethphygmiimiirx_source_source_payload_error1;
+assign maccore_ethphy_liteethphygmiimiirx_source_source_valid0 = maccore_ethphy_liteethphygmiimiirx_mux_source_valid;
+assign maccore_ethphy_liteethphygmiimiirx_mux_source_ready = maccore_ethphy_liteethphygmiimiirx_source_source_ready0;
+assign maccore_ethphy_liteethphygmiimiirx_source_source_first0 = maccore_ethphy_liteethphygmiimiirx_mux_source_first;
+assign maccore_ethphy_liteethphygmiimiirx_source_source_last0 = maccore_ethphy_liteethphygmiimiirx_mux_source_last;
+assign maccore_ethphy_liteethphygmiimiirx_source_source_payload_data0 = maccore_ethphy_liteethphygmiimiirx_mux_source_payload_data;
+assign maccore_ethphy_liteethphygmiimiirx_source_source_payload_last_be0 = maccore_ethphy_liteethphygmiimiirx_mux_source_payload_last_be;
+assign maccore_ethphy_liteethphygmiimiirx_source_source_payload_error0 = maccore_ethphy_liteethphygmiimiirx_mux_source_payload_error;
+assign maccore_ethphy_liteethphygmiimiirx_gmii_rx_source_last = ((~maccore_ethphy_liteethphygmiimiirx_pads_d_rx_dv) & maccore_ethphy_liteethphygmiimiirx_gmii_rx_dv_d);
+assign maccore_ethphy_liteethphygmiimiirx_converter_sink_last = (~maccore_ethphy_liteethphygmiimiirx_pads_d_rx_dv);
+assign maccore_ethphy_liteethphygmiimiirx_source_source_valid1 = maccore_ethphy_liteethphygmiimiirx_converter_source_valid;
+assign maccore_ethphy_liteethphygmiimiirx_converter_source_ready = maccore_ethphy_liteethphygmiimiirx_source_source_ready1;
+assign maccore_ethphy_liteethphygmiimiirx_source_source_first1 = maccore_ethphy_liteethphygmiimiirx_converter_source_first;
+assign maccore_ethphy_liteethphygmiimiirx_source_source_last1 = maccore_ethphy_liteethphygmiimiirx_converter_source_last;
+assign maccore_ethphy_liteethphygmiimiirx_source_source_payload_data1 = maccore_ethphy_liteethphygmiimiirx_converter_source_payload_data;
+assign maccore_ethphy_liteethphygmiimiirx_converter_converter_sink_valid = maccore_ethphy_liteethphygmiimiirx_converter_sink_valid;
+assign maccore_ethphy_liteethphygmiimiirx_converter_converter_sink_first = maccore_ethphy_liteethphygmiimiirx_converter_sink_first;
+assign maccore_ethphy_liteethphygmiimiirx_converter_converter_sink_last = maccore_ethphy_liteethphygmiimiirx_converter_sink_last;
+assign maccore_ethphy_liteethphygmiimiirx_converter_sink_ready = maccore_ethphy_liteethphygmiimiirx_converter_converter_sink_ready;
+assign maccore_ethphy_liteethphygmiimiirx_converter_converter_sink_payload_data = {maccore_ethphy_liteethphygmiimiirx_converter_sink_payload_data};
+assign maccore_ethphy_liteethphygmiimiirx_converter_source_valid = maccore_ethphy_liteethphygmiimiirx_converter_source_source_valid;
+assign maccore_ethphy_liteethphygmiimiirx_converter_source_first = maccore_ethphy_liteethphygmiimiirx_converter_source_source_first;
+assign maccore_ethphy_liteethphygmiimiirx_converter_source_last = maccore_ethphy_liteethphygmiimiirx_converter_source_source_last;
+assign maccore_ethphy_liteethphygmiimiirx_converter_source_source_ready = maccore_ethphy_liteethphygmiimiirx_converter_source_ready;
+always @(*) begin
+	maccore_ethphy_liteethphygmiimiirx_converter_source_payload_data <= 8'd0;
+	maccore_ethphy_liteethphygmiimiirx_converter_source_payload_data[3:0] <= maccore_ethphy_liteethphygmiimiirx_converter_source_source_payload_data[3:0];
+	maccore_ethphy_liteethphygmiimiirx_converter_source_payload_data[7:4] <= maccore_ethphy_liteethphygmiimiirx_converter_source_source_payload_data[7:4];
+end
+assign maccore_ethphy_liteethphygmiimiirx_converter_source_source_valid = maccore_ethphy_liteethphygmiimiirx_converter_converter_source_valid;
+assign maccore_ethphy_liteethphygmiimiirx_converter_converter_source_ready = maccore_ethphy_liteethphygmiimiirx_converter_source_source_ready;
+assign maccore_ethphy_liteethphygmiimiirx_converter_source_source_first = maccore_ethphy_liteethphygmiimiirx_converter_converter_source_first;
+assign maccore_ethphy_liteethphygmiimiirx_converter_source_source_last = maccore_ethphy_liteethphygmiimiirx_converter_converter_source_last;
+assign maccore_ethphy_liteethphygmiimiirx_converter_source_source_payload_data = maccore_ethphy_liteethphygmiimiirx_converter_converter_source_payload_data;
+assign maccore_ethphy_liteethphygmiimiirx_converter_converter_sink_ready = ((~maccore_ethphy_liteethphygmiimiirx_converter_converter_strobe_all) | maccore_ethphy_liteethphygmiimiirx_converter_converter_source_ready);
+assign maccore_ethphy_liteethphygmiimiirx_converter_converter_source_valid = maccore_ethphy_liteethphygmiimiirx_converter_converter_strobe_all;
+assign maccore_ethphy_liteethphygmiimiirx_converter_converter_load_part = (maccore_ethphy_liteethphygmiimiirx_converter_converter_sink_valid & maccore_ethphy_liteethphygmiimiirx_converter_converter_sink_ready);
+always @(*) begin
+	maccore_ethphy_liteethphygmiimiirx_mux_source_valid <= 1'd0;
+	maccore_ethphy_liteethphygmiimiirx_mux_source_first <= 1'd0;
+	maccore_ethphy_liteethphygmiimiirx_mux_source_last <= 1'd0;
+	maccore_ethphy_liteethphygmiimiirx_mux_source_payload_data <= 8'd0;
+	maccore_ethphy_liteethphygmiimiirx_mux_source_payload_last_be <= 1'd0;
+	maccore_ethphy_liteethphygmiimiirx_mux_source_payload_error <= 1'd0;
+	maccore_ethphy_liteethphygmiimiirx_mux_endpoint0_sink_ready <= 1'd0;
+	maccore_ethphy_liteethphygmiimiirx_mux_endpoint1_sink_ready <= 1'd0;
+	case (maccore_ethphy_liteethphygmiimiirx_mux_sel)
+		1'd0: begin
+			maccore_ethphy_liteethphygmiimiirx_mux_source_valid <= maccore_ethphy_liteethphygmiimiirx_mux_endpoint0_sink_valid;
+			maccore_ethphy_liteethphygmiimiirx_mux_endpoint0_sink_ready <= maccore_ethphy_liteethphygmiimiirx_mux_source_ready;
+			maccore_ethphy_liteethphygmiimiirx_mux_source_first <= maccore_ethphy_liteethphygmiimiirx_mux_endpoint0_sink_first;
+			maccore_ethphy_liteethphygmiimiirx_mux_source_last <= maccore_ethphy_liteethphygmiimiirx_mux_endpoint0_sink_last;
+			maccore_ethphy_liteethphygmiimiirx_mux_source_payload_data <= maccore_ethphy_liteethphygmiimiirx_mux_endpoint0_sink_payload_data;
+			maccore_ethphy_liteethphygmiimiirx_mux_source_payload_last_be <= maccore_ethphy_liteethphygmiimiirx_mux_endpoint0_sink_payload_last_be;
+			maccore_ethphy_liteethphygmiimiirx_mux_source_payload_error <= maccore_ethphy_liteethphygmiimiirx_mux_endpoint0_sink_payload_error;
+		end
+		1'd1: begin
+			maccore_ethphy_liteethphygmiimiirx_mux_source_valid <= maccore_ethphy_liteethphygmiimiirx_mux_endpoint1_sink_valid;
+			maccore_ethphy_liteethphygmiimiirx_mux_endpoint1_sink_ready <= maccore_ethphy_liteethphygmiimiirx_mux_source_ready;
+			maccore_ethphy_liteethphygmiimiirx_mux_source_first <= maccore_ethphy_liteethphygmiimiirx_mux_endpoint1_sink_first;
+			maccore_ethphy_liteethphygmiimiirx_mux_source_last <= maccore_ethphy_liteethphygmiimiirx_mux_endpoint1_sink_last;
+			maccore_ethphy_liteethphygmiimiirx_mux_source_payload_data <= maccore_ethphy_liteethphygmiimiirx_mux_endpoint1_sink_payload_data;
+			maccore_ethphy_liteethphygmiimiirx_mux_source_payload_last_be <= maccore_ethphy_liteethphygmiimiirx_mux_endpoint1_sink_payload_last_be;
+			maccore_ethphy_liteethphygmiimiirx_mux_source_payload_error <= maccore_ethphy_liteethphygmiimiirx_mux_endpoint1_sink_payload_error;
+		end
+	endcase
+end
+assign gmii_eth_mdc = maccore_ethphy__w_storage[0];
+assign maccore_ethphy_data_oe = maccore_ethphy__w_storage[1];
+assign maccore_ethphy_data_w = maccore_ethphy__w_storage[2];
+assign tx_cdc_sink_sink_valid = source_valid;
+assign source_ready = tx_cdc_sink_sink_ready;
+assign tx_cdc_sink_sink_first = source_first;
+assign tx_cdc_sink_sink_last = source_last;
+assign tx_cdc_sink_sink_payload_data = source_payload_data;
+assign tx_cdc_sink_sink_payload_last_be = source_payload_last_be;
+assign tx_cdc_sink_sink_payload_error = source_payload_error;
+assign sink_valid = rx_cdc_source_source_valid;
+assign rx_cdc_source_source_ready = sink_ready;
+assign sink_first = rx_cdc_source_source_first;
+assign sink_last = rx_cdc_source_source_last;
+assign sink_payload_data = rx_cdc_source_source_payload_data;
+assign sink_payload_last_be = rx_cdc_source_source_payload_last_be;
+assign sink_payload_error = rx_cdc_source_source_payload_error;
+assign ps_preamble_error_i = preamble_checker_error;
+assign ps_crc_error_i = liteethmaccrc32checker_error;
+always @(*) begin
+	tx_gap_inserter_source_valid <= 1'd0;
+	tx_gap_inserter_source_first <= 1'd0;
+	tx_gap_inserter_source_last <= 1'd0;
+	tx_gap_inserter_source_payload_data <= 8'd0;
+	tx_gap_inserter_source_payload_last_be <= 1'd0;
+	tx_gap_inserter_source_payload_error <= 1'd0;
+	subfragments_liteethmacgap_next_state <= 1'd0;
+	tx_gap_inserter_counter_liteethmacgap_next_value <= 4'd0;
+	tx_gap_inserter_counter_liteethmacgap_next_value_ce <= 1'd0;
+	tx_gap_inserter_sink_ready <= 1'd0;
+	subfragments_liteethmacgap_next_state <= subfragments_liteethmacgap_state;
+	case (subfragments_liteethmacgap_state)
+		1'd1: begin
+			tx_gap_inserter_counter_liteethmacgap_next_value <= (tx_gap_inserter_counter + 1'd1);
+			tx_gap_inserter_counter_liteethmacgap_next_value_ce <= 1'd1;
+			if ((tx_gap_inserter_counter == 4'd11)) begin
+				subfragments_liteethmacgap_next_state <= 1'd0;
+			end
+		end
+		default: begin
+			tx_gap_inserter_counter_liteethmacgap_next_value <= 1'd0;
+			tx_gap_inserter_counter_liteethmacgap_next_value_ce <= 1'd1;
+			tx_gap_inserter_source_valid <= tx_gap_inserter_sink_valid;
+			tx_gap_inserter_sink_ready <= tx_gap_inserter_source_ready;
+			tx_gap_inserter_source_first <= tx_gap_inserter_sink_first;
+			tx_gap_inserter_source_last <= tx_gap_inserter_sink_last;
+			tx_gap_inserter_source_payload_data <= tx_gap_inserter_sink_payload_data;
+			tx_gap_inserter_source_payload_last_be <= tx_gap_inserter_sink_payload_last_be;
+			tx_gap_inserter_source_payload_error <= tx_gap_inserter_sink_payload_error;
+			if (((tx_gap_inserter_sink_valid & tx_gap_inserter_sink_last) & tx_gap_inserter_sink_ready)) begin
+				subfragments_liteethmacgap_next_state <= 1'd1;
+			end
+		end
+	endcase
+end
+assign preamble_inserter_source_payload_last_be = preamble_inserter_sink_payload_last_be;
+always @(*) begin
+	preamble_inserter_source_first <= 1'd0;
+	preamble_inserter_source_last <= 1'd0;
+	preamble_inserter_source_payload_data <= 8'd0;
+	subfragments_liteethmacpreambleinserter_next_state <= 2'd0;
+	preamble_inserter_source_payload_error <= 1'd0;
+	preamble_inserter_count_liteethmacpreambleinserter_next_value <= 3'd0;
+	preamble_inserter_count_liteethmacpreambleinserter_next_value_ce <= 1'd0;
+	preamble_inserter_sink_ready <= 1'd0;
+	preamble_inserter_source_valid <= 1'd0;
+	preamble_inserter_source_payload_data <= preamble_inserter_sink_payload_data;
+	subfragments_liteethmacpreambleinserter_next_state <= subfragments_liteethmacpreambleinserter_state;
+	case (subfragments_liteethmacpreambleinserter_state)
+		1'd1: begin
+			preamble_inserter_source_valid <= 1'd1;
+			case (preamble_inserter_count)
+				1'd0: begin
+					preamble_inserter_source_payload_data <= preamble_inserter_preamble[7:0];
+				end
+				1'd1: begin
+					preamble_inserter_source_payload_data <= preamble_inserter_preamble[15:8];
+				end
+				2'd2: begin
+					preamble_inserter_source_payload_data <= preamble_inserter_preamble[23:16];
+				end
+				2'd3: begin
+					preamble_inserter_source_payload_data <= preamble_inserter_preamble[31:24];
+				end
+				3'd4: begin
+					preamble_inserter_source_payload_data <= preamble_inserter_preamble[39:32];
+				end
+				3'd5: begin
+					preamble_inserter_source_payload_data <= preamble_inserter_preamble[47:40];
+				end
+				3'd6: begin
+					preamble_inserter_source_payload_data <= preamble_inserter_preamble[55:48];
+				end
+				default: begin
+					preamble_inserter_source_payload_data <= preamble_inserter_preamble[63:56];
+				end
+			endcase
+			if (preamble_inserter_source_ready) begin
+				if ((preamble_inserter_count == 3'd7)) begin
+					subfragments_liteethmacpreambleinserter_next_state <= 2'd2;
+				end else begin
+					preamble_inserter_count_liteethmacpreambleinserter_next_value <= (preamble_inserter_count + 1'd1);
+					preamble_inserter_count_liteethmacpreambleinserter_next_value_ce <= 1'd1;
+				end
+			end
+		end
+		2'd2: begin
+			preamble_inserter_source_valid <= preamble_inserter_sink_valid;
+			preamble_inserter_sink_ready <= preamble_inserter_source_ready;
+			preamble_inserter_source_first <= preamble_inserter_sink_first;
+			preamble_inserter_source_last <= preamble_inserter_sink_last;
+			preamble_inserter_source_payload_error <= preamble_inserter_sink_payload_error;
+			if (((preamble_inserter_sink_valid & preamble_inserter_sink_last) & preamble_inserter_source_ready)) begin
+				subfragments_liteethmacpreambleinserter_next_state <= 1'd0;
+			end
+		end
+		default: begin
+			preamble_inserter_sink_ready <= 1'd1;
+			preamble_inserter_count_liteethmacpreambleinserter_next_value <= 1'd0;
+			preamble_inserter_count_liteethmacpreambleinserter_next_value_ce <= 1'd1;
+			if (preamble_inserter_sink_valid) begin
+				preamble_inserter_sink_ready <= 1'd0;
+				subfragments_liteethmacpreambleinserter_next_state <= 1'd1;
+			end
+		end
+	endcase
+end
+assign preamble_checker_source_payload_data = preamble_checker_sink_payload_data;
+assign preamble_checker_source_payload_last_be = preamble_checker_sink_payload_last_be;
+always @(*) begin
+	preamble_checker_source_payload_error <= 1'd0;
+	preamble_checker_error <= 1'd0;
+	preamble_checker_source_first <= 1'd0;
+	preamble_checker_source_valid <= 1'd0;
+	subfragments_liteethmacpreamblechecker_next_state <= 1'd0;
+	preamble_checker_sink_ready <= 1'd0;
+	preamble_checker_source_last <= 1'd0;
+	subfragments_liteethmacpreamblechecker_next_state <= subfragments_liteethmacpreamblechecker_state;
+	case (subfragments_liteethmacpreamblechecker_state)
+		1'd1: begin
+			preamble_checker_source_valid <= preamble_checker_sink_valid;
+			preamble_checker_sink_ready <= preamble_checker_source_ready;
+			preamble_checker_source_first <= preamble_checker_sink_first;
+			preamble_checker_source_last <= preamble_checker_sink_last;
+			preamble_checker_source_payload_error <= preamble_checker_sink_payload_error;
+			if (((preamble_checker_source_valid & preamble_checker_source_last) & preamble_checker_source_ready)) begin
+				subfragments_liteethmacpreamblechecker_next_state <= 1'd0;
+			end
+		end
+		default: begin
+			preamble_checker_sink_ready <= 1'd1;
+			if (((preamble_checker_sink_valid & (~preamble_checker_sink_last)) & (preamble_checker_sink_payload_data == 8'd213))) begin
+				subfragments_liteethmacpreamblechecker_next_state <= 1'd1;
+			end
+			if ((preamble_checker_sink_valid & preamble_checker_sink_last)) begin
+				preamble_checker_error <= 1'd1;
+			end
+		end
+	endcase
+end
+assign liteethmaccrc32inserter_cnt_done = (liteethmaccrc32inserter_cnt == 1'd0);
+assign liteethmaccrc32inserter_sink_valid = crc32_inserter_source_valid;
+assign crc32_inserter_source_ready = liteethmaccrc32inserter_sink_ready;
+assign liteethmaccrc32inserter_sink_first = crc32_inserter_source_first;
+assign liteethmaccrc32inserter_sink_last = crc32_inserter_source_last;
+assign liteethmaccrc32inserter_sink_payload_data = crc32_inserter_source_payload_data;
+assign liteethmaccrc32inserter_sink_payload_last_be = crc32_inserter_source_payload_last_be;
+assign liteethmaccrc32inserter_sink_payload_error = crc32_inserter_source_payload_error;
+assign liteethmaccrc32inserter_data1 = liteethmaccrc32inserter_data0;
+assign liteethmaccrc32inserter_last = liteethmaccrc32inserter_reg;
+assign liteethmaccrc32inserter_value = (~{liteethmaccrc32inserter_reg[0], liteethmaccrc32inserter_reg[1], liteethmaccrc32inserter_reg[2], liteethmaccrc32inserter_reg[3], liteethmaccrc32inserter_reg[4], liteethmaccrc32inserter_reg[5], liteethmaccrc32inserter_reg[6], liteethmaccrc32inserter_reg[7], liteethmaccrc32inserter_reg[8], liteethmaccrc32inserter_reg[9], liteethmaccrc32inserter_reg[10], liteethmaccrc32inserter_reg[11], liteethmaccrc32inserter_reg[12], liteethmaccrc32inserter_reg[13], liteethmaccrc32inserter_reg[14], liteethmaccrc32inserter_reg[15], liteethmaccrc32inserter_reg[16], liteethmaccrc32inserter_reg[17], liteethmaccrc32inserter_reg[18], liteethmaccrc32inserter_reg[19], liteethmaccrc32inserter_reg[20], liteethmaccrc32inserter_reg[21], liteethmaccrc32inserter_reg[22], liteethmaccrc32inserter_reg[23], liteethmaccrc32inserter_reg[24], liteethmaccrc32inserter_reg[25], liteethmaccrc32inserter_reg[26], liteethmaccrc32inserter_reg[27], liteethmaccrc32inserter_reg[28], liteethmaccrc32inserter_reg[29], liteethmaccrc32inserter_reg[30], liteethmaccrc32inserter_reg[31]});
+assign liteethmaccrc32inserter_error = (liteethmaccrc32inserter_next != 32'd3338984827);
+always @(*) begin
+	liteethmaccrc32inserter_next <= 32'd0;
+	liteethmaccrc32inserter_next[0] <= (((liteethmaccrc32inserter_last[24] ^ liteethmaccrc32inserter_last[30]) ^ liteethmaccrc32inserter_data1[1]) ^ liteethmaccrc32inserter_data1[7]);
+	liteethmaccrc32inserter_next[1] <= (((((((liteethmaccrc32inserter_last[25] ^ liteethmaccrc32inserter_last[31]) ^ liteethmaccrc32inserter_data1[0]) ^ liteethmaccrc32inserter_data1[6]) ^ liteethmaccrc32inserter_last[24]) ^ liteethmaccrc32inserter_last[30]) ^ liteethmaccrc32inserter_data1[1]) ^ liteethmaccrc32inserter_data1[7]);
+	liteethmaccrc32inserter_next[2] <= (((((((((liteethmaccrc32inserter_last[26] ^ liteethmaccrc32inserter_data1[5]) ^ liteethmaccrc32inserter_last[25]) ^ liteethmaccrc32inserter_last[31]) ^ liteethmaccrc32inserter_data1[0]) ^ liteethmaccrc32inserter_data1[6]) ^ liteethmaccrc32inserter_last[24]) ^ liteethmaccrc32inserter_last[30]) ^ liteethmaccrc32inserter_data1[1]) ^ liteethmaccrc32inserter_data1[7]);
+	liteethmaccrc32inserter_next[3] <= (((((((liteethmaccrc32inserter_last[27] ^ liteethmaccrc32inserter_data1[4]) ^ liteethmaccrc32inserter_last[26]) ^ liteethmaccrc32inserter_data1[5]) ^ liteethmaccrc32inserter_last[25]) ^ liteethmaccrc32inserter_last[31]) ^ liteethmaccrc32inserter_data1[0]) ^ liteethmaccrc32inserter_data1[6]);
+	liteethmaccrc32inserter_next[4] <= (((((((((liteethmaccrc32inserter_last[28] ^ liteethmaccrc32inserter_data1[3]) ^ liteethmaccrc32inserter_last[27]) ^ liteethmaccrc32inserter_data1[4]) ^ liteethmaccrc32inserter_last[26]) ^ liteethmaccrc32inserter_data1[5]) ^ liteethmaccrc32inserter_last[24]) ^ liteethmaccrc32inserter_last[30]) ^ liteethmaccrc32inserter_data1[1]) ^ liteethmaccrc32inserter_data1[7]);
+	liteethmaccrc32inserter_next[5] <= (((((((((((((liteethmaccrc32inserter_last[29] ^ liteethmaccrc32inserter_data1[2]) ^ liteethmaccrc32inserter_last[28]) ^ liteethmaccrc32inserter_data1[3]) ^ liteethmaccrc32inserter_last[27]) ^ liteethmaccrc32inserter_data1[4]) ^ liteethmaccrc32inserter_last[25]) ^ liteethmaccrc32inserter_last[31]) ^ liteethmaccrc32inserter_data1[0]) ^ liteethmaccrc32inserter_data1[6]) ^ liteethmaccrc32inserter_last[24]) ^ liteethmaccrc32inserter_last[30]) ^ liteethmaccrc32inserter_data1[1]) ^ liteethmaccrc32inserter_data1[7]);
+	liteethmaccrc32inserter_next[6] <= (((((((((((liteethmaccrc32inserter_last[30] ^ liteethmaccrc32inserter_data1[1]) ^ liteethmaccrc32inserter_last[29]) ^ liteethmaccrc32inserter_data1[2]) ^ liteethmaccrc32inserter_last[28]) ^ liteethmaccrc32inserter_data1[3]) ^ liteethmaccrc32inserter_last[26]) ^ liteethmaccrc32inserter_data1[5]) ^ liteethmaccrc32inserter_last[25]) ^ liteethmaccrc32inserter_last[31]) ^ liteethmaccrc32inserter_data1[0]) ^ liteethmaccrc32inserter_data1[6]);
+	liteethmaccrc32inserter_next[7] <= (((((((((liteethmaccrc32inserter_last[31] ^ liteethmaccrc32inserter_data1[0]) ^ liteethmaccrc32inserter_last[29]) ^ liteethmaccrc32inserter_data1[2]) ^ liteethmaccrc32inserter_last[27]) ^ liteethmaccrc32inserter_data1[4]) ^ liteethmaccrc32inserter_last[26]) ^ liteethmaccrc32inserter_data1[5]) ^ liteethmaccrc32inserter_last[24]) ^ liteethmaccrc32inserter_data1[7]);
+	liteethmaccrc32inserter_next[8] <= ((((((((liteethmaccrc32inserter_last[0] ^ liteethmaccrc32inserter_last[28]) ^ liteethmaccrc32inserter_data1[3]) ^ liteethmaccrc32inserter_last[27]) ^ liteethmaccrc32inserter_data1[4]) ^ liteethmaccrc32inserter_last[25]) ^ liteethmaccrc32inserter_data1[6]) ^ liteethmaccrc32inserter_last[24]) ^ liteethmaccrc32inserter_data1[7]);
+	liteethmaccrc32inserter_next[9] <= ((((((((liteethmaccrc32inserter_last[1] ^ liteethmaccrc32inserter_last[29]) ^ liteethmaccrc32inserter_data1[2]) ^ liteethmaccrc32inserter_last[28]) ^ liteethmaccrc32inserter_data1[3]) ^ liteethmaccrc32inserter_last[26]) ^ liteethmaccrc32inserter_data1[5]) ^ liteethmaccrc32inserter_last[25]) ^ liteethmaccrc32inserter_data1[6]);
+	liteethmaccrc32inserter_next[10] <= ((((((((liteethmaccrc32inserter_last[2] ^ liteethmaccrc32inserter_last[29]) ^ liteethmaccrc32inserter_data1[2]) ^ liteethmaccrc32inserter_last[27]) ^ liteethmaccrc32inserter_data1[4]) ^ liteethmaccrc32inserter_last[26]) ^ liteethmaccrc32inserter_data1[5]) ^ liteethmaccrc32inserter_last[24]) ^ liteethmaccrc32inserter_data1[7]);
+	liteethmaccrc32inserter_next[11] <= ((((((((liteethmaccrc32inserter_last[3] ^ liteethmaccrc32inserter_last[28]) ^ liteethmaccrc32inserter_data1[3]) ^ liteethmaccrc32inserter_last[27]) ^ liteethmaccrc32inserter_data1[4]) ^ liteethmaccrc32inserter_last[25]) ^ liteethmaccrc32inserter_data1[6]) ^ liteethmaccrc32inserter_last[24]) ^ liteethmaccrc32inserter_data1[7]);
+	liteethmaccrc32inserter_next[12] <= ((((((((((((liteethmaccrc32inserter_last[4] ^ liteethmaccrc32inserter_last[29]) ^ liteethmaccrc32inserter_data1[2]) ^ liteethmaccrc32inserter_last[28]) ^ liteethmaccrc32inserter_data1[3]) ^ liteethmaccrc32inserter_last[26]) ^ liteethmaccrc32inserter_data1[5]) ^ liteethmaccrc32inserter_last[25]) ^ liteethmaccrc32inserter_data1[6]) ^ liteethmaccrc32inserter_last[24]) ^ liteethmaccrc32inserter_last[30]) ^ liteethmaccrc32inserter_data1[1]) ^ liteethmaccrc32inserter_data1[7]);
+	liteethmaccrc32inserter_next[13] <= ((((((((((((liteethmaccrc32inserter_last[5] ^ liteethmaccrc32inserter_last[30]) ^ liteethmaccrc32inserter_data1[1]) ^ liteethmaccrc32inserter_last[29]) ^ liteethmaccrc32inserter_data1[2]) ^ liteethmaccrc32inserter_last[27]) ^ liteethmaccrc32inserter_data1[4]) ^ liteethmaccrc32inserter_last[26]) ^ liteethmaccrc32inserter_data1[5]) ^ liteethmaccrc32inserter_last[25]) ^ liteethmaccrc32inserter_last[31]) ^ liteethmaccrc32inserter_data1[0]) ^ liteethmaccrc32inserter_data1[6]);
+	liteethmaccrc32inserter_next[14] <= ((((((((((liteethmaccrc32inserter_last[6] ^ liteethmaccrc32inserter_last[31]) ^ liteethmaccrc32inserter_data1[0]) ^ liteethmaccrc32inserter_last[30]) ^ liteethmaccrc32inserter_data1[1]) ^ liteethmaccrc32inserter_last[28]) ^ liteethmaccrc32inserter_data1[3]) ^ liteethmaccrc32inserter_last[27]) ^ liteethmaccrc32inserter_data1[4]) ^ liteethmaccrc32inserter_last[26]) ^ liteethmaccrc32inserter_data1[5]);
+	liteethmaccrc32inserter_next[15] <= ((((((((liteethmaccrc32inserter_last[7] ^ liteethmaccrc32inserter_last[31]) ^ liteethmaccrc32inserter_data1[0]) ^ liteethmaccrc32inserter_last[29]) ^ liteethmaccrc32inserter_data1[2]) ^ liteethmaccrc32inserter_last[28]) ^ liteethmaccrc32inserter_data1[3]) ^ liteethmaccrc32inserter_last[27]) ^ liteethmaccrc32inserter_data1[4]);
+	liteethmaccrc32inserter_next[16] <= ((((((liteethmaccrc32inserter_last[8] ^ liteethmaccrc32inserter_last[29]) ^ liteethmaccrc32inserter_data1[2]) ^ liteethmaccrc32inserter_last[28]) ^ liteethmaccrc32inserter_data1[3]) ^ liteethmaccrc32inserter_last[24]) ^ liteethmaccrc32inserter_data1[7]);
+	liteethmaccrc32inserter_next[17] <= ((((((liteethmaccrc32inserter_last[9] ^ liteethmaccrc32inserter_last[30]) ^ liteethmaccrc32inserter_data1[1]) ^ liteethmaccrc32inserter_last[29]) ^ liteethmaccrc32inserter_data1[2]) ^ liteethmaccrc32inserter_last[25]) ^ liteethmaccrc32inserter_data1[6]);
+	liteethmaccrc32inserter_next[18] <= ((((((liteethmaccrc32inserter_last[10] ^ liteethmaccrc32inserter_last[31]) ^ liteethmaccrc32inserter_data1[0]) ^ liteethmaccrc32inserter_last[30]) ^ liteethmaccrc32inserter_data1[1]) ^ liteethmaccrc32inserter_last[26]) ^ liteethmaccrc32inserter_data1[5]);
+	liteethmaccrc32inserter_next[19] <= ((((liteethmaccrc32inserter_last[11] ^ liteethmaccrc32inserter_last[31]) ^ liteethmaccrc32inserter_data1[0]) ^ liteethmaccrc32inserter_last[27]) ^ liteethmaccrc32inserter_data1[4]);
+	liteethmaccrc32inserter_next[20] <= ((liteethmaccrc32inserter_last[12] ^ liteethmaccrc32inserter_last[28]) ^ liteethmaccrc32inserter_data1[3]);
+	liteethmaccrc32inserter_next[21] <= ((liteethmaccrc32inserter_last[13] ^ liteethmaccrc32inserter_last[29]) ^ liteethmaccrc32inserter_data1[2]);
+	liteethmaccrc32inserter_next[22] <= ((liteethmaccrc32inserter_last[14] ^ liteethmaccrc32inserter_last[24]) ^ liteethmaccrc32inserter_data1[7]);
+	liteethmaccrc32inserter_next[23] <= ((((((liteethmaccrc32inserter_last[15] ^ liteethmaccrc32inserter_last[25]) ^ liteethmaccrc32inserter_data1[6]) ^ liteethmaccrc32inserter_last[24]) ^ liteethmaccrc32inserter_last[30]) ^ liteethmaccrc32inserter_data1[1]) ^ liteethmaccrc32inserter_data1[7]);
+	liteethmaccrc32inserter_next[24] <= ((((((liteethmaccrc32inserter_last[16] ^ liteethmaccrc32inserter_last[26]) ^ liteethmaccrc32inserter_data1[5]) ^ liteethmaccrc32inserter_last[25]) ^ liteethmaccrc32inserter_last[31]) ^ liteethmaccrc32inserter_data1[0]) ^ liteethmaccrc32inserter_data1[6]);
+	liteethmaccrc32inserter_next[25] <= ((((liteethmaccrc32inserter_last[17] ^ liteethmaccrc32inserter_last[27]) ^ liteethmaccrc32inserter_data1[4]) ^ liteethmaccrc32inserter_last[26]) ^ liteethmaccrc32inserter_data1[5]);
+	liteethmaccrc32inserter_next[26] <= ((((((((liteethmaccrc32inserter_last[18] ^ liteethmaccrc32inserter_last[28]) ^ liteethmaccrc32inserter_data1[3]) ^ liteethmaccrc32inserter_last[27]) ^ liteethmaccrc32inserter_data1[4]) ^ liteethmaccrc32inserter_last[24]) ^ liteethmaccrc32inserter_last[30]) ^ liteethmaccrc32inserter_data1[1]) ^ liteethmaccrc32inserter_data1[7]);
+	liteethmaccrc32inserter_next[27] <= ((((((((liteethmaccrc32inserter_last[19] ^ liteethmaccrc32inserter_last[29]) ^ liteethmaccrc32inserter_data1[2]) ^ liteethmaccrc32inserter_last[28]) ^ liteethmaccrc32inserter_data1[3]) ^ liteethmaccrc32inserter_last[25]) ^ liteethmaccrc32inserter_last[31]) ^ liteethmaccrc32inserter_data1[0]) ^ liteethmaccrc32inserter_data1[6]);
+	liteethmaccrc32inserter_next[28] <= ((((((liteethmaccrc32inserter_last[20] ^ liteethmaccrc32inserter_last[30]) ^ liteethmaccrc32inserter_data1[1]) ^ liteethmaccrc32inserter_last[29]) ^ liteethmaccrc32inserter_data1[2]) ^ liteethmaccrc32inserter_last[26]) ^ liteethmaccrc32inserter_data1[5]);
+	liteethmaccrc32inserter_next[29] <= ((((((liteethmaccrc32inserter_last[21] ^ liteethmaccrc32inserter_last[31]) ^ liteethmaccrc32inserter_data1[0]) ^ liteethmaccrc32inserter_last[30]) ^ liteethmaccrc32inserter_data1[1]) ^ liteethmaccrc32inserter_last[27]) ^ liteethmaccrc32inserter_data1[4]);
+	liteethmaccrc32inserter_next[30] <= ((((liteethmaccrc32inserter_last[22] ^ liteethmaccrc32inserter_last[31]) ^ liteethmaccrc32inserter_data1[0]) ^ liteethmaccrc32inserter_last[28]) ^ liteethmaccrc32inserter_data1[3]);
+	liteethmaccrc32inserter_next[31] <= ((liteethmaccrc32inserter_last[23] ^ liteethmaccrc32inserter_last[29]) ^ liteethmaccrc32inserter_data1[2]);
+end
+always @(*) begin
+	liteethmaccrc32inserter_source_first <= 1'd0;
+	liteethmaccrc32inserter_source_last <= 1'd0;
+	liteethmaccrc32inserter_source_payload_data <= 8'd0;
+	liteethmaccrc32inserter_source_payload_last_be <= 1'd0;
+	liteethmaccrc32inserter_source_payload_error <= 1'd0;
+	liteethmaccrc32inserter_data0 <= 8'd0;
+	liteethmaccrc32inserter_is_ongoing0 <= 1'd0;
+	liteethmaccrc32inserter_sink_ready <= 1'd0;
+	liteethmaccrc32inserter_is_ongoing1 <= 1'd0;
+	liteethmaccrc32inserter_ce <= 1'd0;
+	liteethmaccrc32inserter_reset <= 1'd0;
+	subfragments_liteethmaccrc32inserter_next_state <= 2'd0;
+	liteethmaccrc32inserter_source_valid <= 1'd0;
+	subfragments_liteethmaccrc32inserter_next_state <= subfragments_liteethmaccrc32inserter_state;
+	case (subfragments_liteethmaccrc32inserter_state)
+		1'd1: begin
+			liteethmaccrc32inserter_ce <= (liteethmaccrc32inserter_sink_valid & liteethmaccrc32inserter_source_ready);
+			liteethmaccrc32inserter_data0 <= liteethmaccrc32inserter_sink_payload_data;
+			liteethmaccrc32inserter_source_valid <= liteethmaccrc32inserter_sink_valid;
+			liteethmaccrc32inserter_sink_ready <= liteethmaccrc32inserter_source_ready;
+			liteethmaccrc32inserter_source_first <= liteethmaccrc32inserter_sink_first;
+			liteethmaccrc32inserter_source_last <= liteethmaccrc32inserter_sink_last;
+			liteethmaccrc32inserter_source_payload_data <= liteethmaccrc32inserter_sink_payload_data;
+			liteethmaccrc32inserter_source_payload_last_be <= liteethmaccrc32inserter_sink_payload_last_be;
+			liteethmaccrc32inserter_source_payload_error <= liteethmaccrc32inserter_sink_payload_error;
+			liteethmaccrc32inserter_source_last <= 1'd0;
+			if (((liteethmaccrc32inserter_sink_valid & liteethmaccrc32inserter_sink_last) & liteethmaccrc32inserter_source_ready)) begin
+				subfragments_liteethmaccrc32inserter_next_state <= 2'd2;
+			end
+		end
+		2'd2: begin
+			liteethmaccrc32inserter_source_valid <= 1'd1;
+			case (liteethmaccrc32inserter_cnt)
+				1'd0: begin
+					liteethmaccrc32inserter_source_payload_data <= liteethmaccrc32inserter_value[31:24];
+				end
+				1'd1: begin
+					liteethmaccrc32inserter_source_payload_data <= liteethmaccrc32inserter_value[23:16];
+				end
+				2'd2: begin
+					liteethmaccrc32inserter_source_payload_data <= liteethmaccrc32inserter_value[15:8];
+				end
+				default: begin
+					liteethmaccrc32inserter_source_payload_data <= liteethmaccrc32inserter_value[7:0];
+				end
+			endcase
+			if (liteethmaccrc32inserter_cnt_done) begin
+				liteethmaccrc32inserter_source_last <= 1'd1;
+				if (liteethmaccrc32inserter_source_ready) begin
+					subfragments_liteethmaccrc32inserter_next_state <= 1'd0;
+				end
+			end
+			liteethmaccrc32inserter_is_ongoing1 <= 1'd1;
+		end
+		default: begin
+			liteethmaccrc32inserter_reset <= 1'd1;
+			liteethmaccrc32inserter_sink_ready <= 1'd1;
+			if (liteethmaccrc32inserter_sink_valid) begin
+				liteethmaccrc32inserter_sink_ready <= 1'd0;
+				subfragments_liteethmaccrc32inserter_next_state <= 1'd1;
+			end
+			liteethmaccrc32inserter_is_ongoing0 <= 1'd1;
+		end
+	endcase
+end
+assign crc32_inserter_sink_ready = ((~crc32_inserter_source_valid) | crc32_inserter_source_ready);
+assign liteethmaccrc32checker_fifo_full = (liteethmaccrc32checker_syncfifo_level == 3'd4);
+assign liteethmaccrc32checker_fifo_in = (liteethmaccrc32checker_sink_sink_valid & ((~liteethmaccrc32checker_fifo_full) | liteethmaccrc32checker_fifo_out));
+assign liteethmaccrc32checker_fifo_out = (liteethmaccrc32checker_source_source_valid & liteethmaccrc32checker_source_source_ready);
+assign liteethmaccrc32checker_syncfifo_sink_first = liteethmaccrc32checker_sink_sink_first;
+assign liteethmaccrc32checker_syncfifo_sink_last = liteethmaccrc32checker_sink_sink_last;
+assign liteethmaccrc32checker_syncfifo_sink_payload_data = liteethmaccrc32checker_sink_sink_payload_data;
+assign liteethmaccrc32checker_syncfifo_sink_payload_last_be = liteethmaccrc32checker_sink_sink_payload_last_be;
+assign liteethmaccrc32checker_syncfifo_sink_payload_error = liteethmaccrc32checker_sink_sink_payload_error;
+always @(*) begin
+	liteethmaccrc32checker_syncfifo_sink_valid <= 1'd0;
+	liteethmaccrc32checker_syncfifo_sink_valid <= liteethmaccrc32checker_sink_sink_valid;
+	liteethmaccrc32checker_syncfifo_sink_valid <= liteethmaccrc32checker_fifo_in;
+end
+always @(*) begin
+	liteethmaccrc32checker_sink_sink_ready <= 1'd0;
+	liteethmaccrc32checker_sink_sink_ready <= liteethmaccrc32checker_syncfifo_sink_ready;
+	liteethmaccrc32checker_sink_sink_ready <= liteethmaccrc32checker_fifo_in;
+end
+assign liteethmaccrc32checker_source_source_valid = (liteethmaccrc32checker_sink_sink_valid & liteethmaccrc32checker_fifo_full);
+assign liteethmaccrc32checker_source_source_last = liteethmaccrc32checker_sink_sink_last;
+assign liteethmaccrc32checker_syncfifo_source_ready = liteethmaccrc32checker_fifo_out;
+assign liteethmaccrc32checker_source_source_payload_data = liteethmaccrc32checker_syncfifo_source_payload_data;
+assign liteethmaccrc32checker_source_source_payload_last_be = liteethmaccrc32checker_syncfifo_source_payload_last_be;
+always @(*) begin
+	liteethmaccrc32checker_source_source_payload_error <= 1'd0;
+	liteethmaccrc32checker_source_source_payload_error <= liteethmaccrc32checker_syncfifo_source_payload_error;
+	liteethmaccrc32checker_source_source_payload_error <= (liteethmaccrc32checker_sink_sink_payload_error | liteethmaccrc32checker_crc_error);
+end
+assign liteethmaccrc32checker_error = ((liteethmaccrc32checker_source_source_valid & liteethmaccrc32checker_source_source_last) & liteethmaccrc32checker_crc_error);
+assign liteethmaccrc32checker_crc_data0 = liteethmaccrc32checker_sink_sink_payload_data;
+assign liteethmaccrc32checker_sink_sink_valid = crc32_checker_source_valid;
+assign crc32_checker_source_ready = liteethmaccrc32checker_sink_sink_ready;
+assign liteethmaccrc32checker_sink_sink_first = crc32_checker_source_first;
+assign liteethmaccrc32checker_sink_sink_last = crc32_checker_source_last;
+assign liteethmaccrc32checker_sink_sink_payload_data = crc32_checker_source_payload_data;
+assign liteethmaccrc32checker_sink_sink_payload_last_be = crc32_checker_source_payload_last_be;
+assign liteethmaccrc32checker_sink_sink_payload_error = crc32_checker_source_payload_error;
+assign liteethmaccrc32checker_crc_data1 = liteethmaccrc32checker_crc_data0;
+assign liteethmaccrc32checker_crc_last = liteethmaccrc32checker_crc_reg;
+assign liteethmaccrc32checker_crc_value = (~{liteethmaccrc32checker_crc_reg[0], liteethmaccrc32checker_crc_reg[1], liteethmaccrc32checker_crc_reg[2], liteethmaccrc32checker_crc_reg[3], liteethmaccrc32checker_crc_reg[4], liteethmaccrc32checker_crc_reg[5], liteethmaccrc32checker_crc_reg[6], liteethmaccrc32checker_crc_reg[7], liteethmaccrc32checker_crc_reg[8], liteethmaccrc32checker_crc_reg[9], liteethmaccrc32checker_crc_reg[10], liteethmaccrc32checker_crc_reg[11], liteethmaccrc32checker_crc_reg[12], liteethmaccrc32checker_crc_reg[13], liteethmaccrc32checker_crc_reg[14], liteethmaccrc32checker_crc_reg[15], liteethmaccrc32checker_crc_reg[16], liteethmaccrc32checker_crc_reg[17], liteethmaccrc32checker_crc_reg[18], liteethmaccrc32checker_crc_reg[19], liteethmaccrc32checker_crc_reg[20], liteethmaccrc32checker_crc_reg[21], liteethmaccrc32checker_crc_reg[22], liteethmaccrc32checker_crc_reg[23], liteethmaccrc32checker_crc_reg[24], liteethmaccrc32checker_crc_reg[25], liteethmaccrc32checker_crc_reg[26], liteethmaccrc32checker_crc_reg[27], liteethmaccrc32checker_crc_reg[28], liteethmaccrc32checker_crc_reg[29], liteethmaccrc32checker_crc_reg[30], liteethmaccrc32checker_crc_reg[31]});
+assign liteethmaccrc32checker_crc_error = (liteethmaccrc32checker_crc_next != 32'd3338984827);
+always @(*) begin
+	liteethmaccrc32checker_crc_next <= 32'd0;
+	liteethmaccrc32checker_crc_next[0] <= (((liteethmaccrc32checker_crc_last[24] ^ liteethmaccrc32checker_crc_last[30]) ^ liteethmaccrc32checker_crc_data1[1]) ^ liteethmaccrc32checker_crc_data1[7]);
+	liteethmaccrc32checker_crc_next[1] <= (((((((liteethmaccrc32checker_crc_last[25] ^ liteethmaccrc32checker_crc_last[31]) ^ liteethmaccrc32checker_crc_data1[0]) ^ liteethmaccrc32checker_crc_data1[6]) ^ liteethmaccrc32checker_crc_last[24]) ^ liteethmaccrc32checker_crc_last[30]) ^ liteethmaccrc32checker_crc_data1[1]) ^ liteethmaccrc32checker_crc_data1[7]);
+	liteethmaccrc32checker_crc_next[2] <= (((((((((liteethmaccrc32checker_crc_last[26] ^ liteethmaccrc32checker_crc_data1[5]) ^ liteethmaccrc32checker_crc_last[25]) ^ liteethmaccrc32checker_crc_last[31]) ^ liteethmaccrc32checker_crc_data1[0]) ^ liteethmaccrc32checker_crc_data1[6]) ^ liteethmaccrc32checker_crc_last[24]) ^ liteethmaccrc32checker_crc_last[30]) ^ liteethmaccrc32checker_crc_data1[1]) ^ liteethmaccrc32checker_crc_data1[7]);
+	liteethmaccrc32checker_crc_next[3] <= (((((((liteethmaccrc32checker_crc_last[27] ^ liteethmaccrc32checker_crc_data1[4]) ^ liteethmaccrc32checker_crc_last[26]) ^ liteethmaccrc32checker_crc_data1[5]) ^ liteethmaccrc32checker_crc_last[25]) ^ liteethmaccrc32checker_crc_last[31]) ^ liteethmaccrc32checker_crc_data1[0]) ^ liteethmaccrc32checker_crc_data1[6]);
+	liteethmaccrc32checker_crc_next[4] <= (((((((((liteethmaccrc32checker_crc_last[28] ^ liteethmaccrc32checker_crc_data1[3]) ^ liteethmaccrc32checker_crc_last[27]) ^ liteethmaccrc32checker_crc_data1[4]) ^ liteethmaccrc32checker_crc_last[26]) ^ liteethmaccrc32checker_crc_data1[5]) ^ liteethmaccrc32checker_crc_last[24]) ^ liteethmaccrc32checker_crc_last[30]) ^ liteethmaccrc32checker_crc_data1[1]) ^ liteethmaccrc32checker_crc_data1[7]);
+	liteethmaccrc32checker_crc_next[5] <= (((((((((((((liteethmaccrc32checker_crc_last[29] ^ liteethmaccrc32checker_crc_data1[2]) ^ liteethmaccrc32checker_crc_last[28]) ^ liteethmaccrc32checker_crc_data1[3]) ^ liteethmaccrc32checker_crc_last[27]) ^ liteethmaccrc32checker_crc_data1[4]) ^ liteethmaccrc32checker_crc_last[25]) ^ liteethmaccrc32checker_crc_last[31]) ^ liteethmaccrc32checker_crc_data1[0]) ^ liteethmaccrc32checker_crc_data1[6]) ^ liteethmaccrc32checker_crc_last[24]) ^ liteethmaccrc32checker_crc_last[30]) ^ liteethmaccrc32checker_crc_data1[1]) ^ liteethmaccrc32checker_crc_data1[7]);
+	liteethmaccrc32checker_crc_next[6] <= (((((((((((liteethmaccrc32checker_crc_last[30] ^ liteethmaccrc32checker_crc_data1[1]) ^ liteethmaccrc32checker_crc_last[29]) ^ liteethmaccrc32checker_crc_data1[2]) ^ liteethmaccrc32checker_crc_last[28]) ^ liteethmaccrc32checker_crc_data1[3]) ^ liteethmaccrc32checker_crc_last[26]) ^ liteethmaccrc32checker_crc_data1[5]) ^ liteethmaccrc32checker_crc_last[25]) ^ liteethmaccrc32checker_crc_last[31]) ^ liteethmaccrc32checker_crc_data1[0]) ^ liteethmaccrc32checker_crc_data1[6]);
+	liteethmaccrc32checker_crc_next[7] <= (((((((((liteethmaccrc32checker_crc_last[31] ^ liteethmaccrc32checker_crc_data1[0]) ^ liteethmaccrc32checker_crc_last[29]) ^ liteethmaccrc32checker_crc_data1[2]) ^ liteethmaccrc32checker_crc_last[27]) ^ liteethmaccrc32checker_crc_data1[4]) ^ liteethmaccrc32checker_crc_last[26]) ^ liteethmaccrc32checker_crc_data1[5]) ^ liteethmaccrc32checker_crc_last[24]) ^ liteethmaccrc32checker_crc_data1[7]);
+	liteethmaccrc32checker_crc_next[8] <= ((((((((liteethmaccrc32checker_crc_last[0] ^ liteethmaccrc32checker_crc_last[28]) ^ liteethmaccrc32checker_crc_data1[3]) ^ liteethmaccrc32checker_crc_last[27]) ^ liteethmaccrc32checker_crc_data1[4]) ^ liteethmaccrc32checker_crc_last[25]) ^ liteethmaccrc32checker_crc_data1[6]) ^ liteethmaccrc32checker_crc_last[24]) ^ liteethmaccrc32checker_crc_data1[7]);
+	liteethmaccrc32checker_crc_next[9] <= ((((((((liteethmaccrc32checker_crc_last[1] ^ liteethmaccrc32checker_crc_last[29]) ^ liteethmaccrc32checker_crc_data1[2]) ^ liteethmaccrc32checker_crc_last[28]) ^ liteethmaccrc32checker_crc_data1[3]) ^ liteethmaccrc32checker_crc_last[26]) ^ liteethmaccrc32checker_crc_data1[5]) ^ liteethmaccrc32checker_crc_last[25]) ^ liteethmaccrc32checker_crc_data1[6]);
+	liteethmaccrc32checker_crc_next[10] <= ((((((((liteethmaccrc32checker_crc_last[2] ^ liteethmaccrc32checker_crc_last[29]) ^ liteethmaccrc32checker_crc_data1[2]) ^ liteethmaccrc32checker_crc_last[27]) ^ liteethmaccrc32checker_crc_data1[4]) ^ liteethmaccrc32checker_crc_last[26]) ^ liteethmaccrc32checker_crc_data1[5]) ^ liteethmaccrc32checker_crc_last[24]) ^ liteethmaccrc32checker_crc_data1[7]);
+	liteethmaccrc32checker_crc_next[11] <= ((((((((liteethmaccrc32checker_crc_last[3] ^ liteethmaccrc32checker_crc_last[28]) ^ liteethmaccrc32checker_crc_data1[3]) ^ liteethmaccrc32checker_crc_last[27]) ^ liteethmaccrc32checker_crc_data1[4]) ^ liteethmaccrc32checker_crc_last[25]) ^ liteethmaccrc32checker_crc_data1[6]) ^ liteethmaccrc32checker_crc_last[24]) ^ liteethmaccrc32checker_crc_data1[7]);
+	liteethmaccrc32checker_crc_next[12] <= ((((((((((((liteethmaccrc32checker_crc_last[4] ^ liteethmaccrc32checker_crc_last[29]) ^ liteethmaccrc32checker_crc_data1[2]) ^ liteethmaccrc32checker_crc_last[28]) ^ liteethmaccrc32checker_crc_data1[3]) ^ liteethmaccrc32checker_crc_last[26]) ^ liteethmaccrc32checker_crc_data1[5]) ^ liteethmaccrc32checker_crc_last[25]) ^ liteethmaccrc32checker_crc_data1[6]) ^ liteethmaccrc32checker_crc_last[24]) ^ liteethmaccrc32checker_crc_last[30]) ^ liteethmaccrc32checker_crc_data1[1]) ^ liteethmaccrc32checker_crc_data1[7]);
+	liteethmaccrc32checker_crc_next[13] <= ((((((((((((liteethmaccrc32checker_crc_last[5] ^ liteethmaccrc32checker_crc_last[30]) ^ liteethmaccrc32checker_crc_data1[1]) ^ liteethmaccrc32checker_crc_last[29]) ^ liteethmaccrc32checker_crc_data1[2]) ^ liteethmaccrc32checker_crc_last[27]) ^ liteethmaccrc32checker_crc_data1[4]) ^ liteethmaccrc32checker_crc_last[26]) ^ liteethmaccrc32checker_crc_data1[5]) ^ liteethmaccrc32checker_crc_last[25]) ^ liteethmaccrc32checker_crc_last[31]) ^ liteethmaccrc32checker_crc_data1[0]) ^ liteethmaccrc32checker_crc_data1[6]);
+	liteethmaccrc32checker_crc_next[14] <= ((((((((((liteethmaccrc32checker_crc_last[6] ^ liteethmaccrc32checker_crc_last[31]) ^ liteethmaccrc32checker_crc_data1[0]) ^ liteethmaccrc32checker_crc_last[30]) ^ liteethmaccrc32checker_crc_data1[1]) ^ liteethmaccrc32checker_crc_last[28]) ^ liteethmaccrc32checker_crc_data1[3]) ^ liteethmaccrc32checker_crc_last[27]) ^ liteethmaccrc32checker_crc_data1[4]) ^ liteethmaccrc32checker_crc_last[26]) ^ liteethmaccrc32checker_crc_data1[5]);
+	liteethmaccrc32checker_crc_next[15] <= ((((((((liteethmaccrc32checker_crc_last[7] ^ liteethmaccrc32checker_crc_last[31]) ^ liteethmaccrc32checker_crc_data1[0]) ^ liteethmaccrc32checker_crc_last[29]) ^ liteethmaccrc32checker_crc_data1[2]) ^ liteethmaccrc32checker_crc_last[28]) ^ liteethmaccrc32checker_crc_data1[3]) ^ liteethmaccrc32checker_crc_last[27]) ^ liteethmaccrc32checker_crc_data1[4]);
+	liteethmaccrc32checker_crc_next[16] <= ((((((liteethmaccrc32checker_crc_last[8] ^ liteethmaccrc32checker_crc_last[29]) ^ liteethmaccrc32checker_crc_data1[2]) ^ liteethmaccrc32checker_crc_last[28]) ^ liteethmaccrc32checker_crc_data1[3]) ^ liteethmaccrc32checker_crc_last[24]) ^ liteethmaccrc32checker_crc_data1[7]);
+	liteethmaccrc32checker_crc_next[17] <= ((((((liteethmaccrc32checker_crc_last[9] ^ liteethmaccrc32checker_crc_last[30]) ^ liteethmaccrc32checker_crc_data1[1]) ^ liteethmaccrc32checker_crc_last[29]) ^ liteethmaccrc32checker_crc_data1[2]) ^ liteethmaccrc32checker_crc_last[25]) ^ liteethmaccrc32checker_crc_data1[6]);
+	liteethmaccrc32checker_crc_next[18] <= ((((((liteethmaccrc32checker_crc_last[10] ^ liteethmaccrc32checker_crc_last[31]) ^ liteethmaccrc32checker_crc_data1[0]) ^ liteethmaccrc32checker_crc_last[30]) ^ liteethmaccrc32checker_crc_data1[1]) ^ liteethmaccrc32checker_crc_last[26]) ^ liteethmaccrc32checker_crc_data1[5]);
+	liteethmaccrc32checker_crc_next[19] <= ((((liteethmaccrc32checker_crc_last[11] ^ liteethmaccrc32checker_crc_last[31]) ^ liteethmaccrc32checker_crc_data1[0]) ^ liteethmaccrc32checker_crc_last[27]) ^ liteethmaccrc32checker_crc_data1[4]);
+	liteethmaccrc32checker_crc_next[20] <= ((liteethmaccrc32checker_crc_last[12] ^ liteethmaccrc32checker_crc_last[28]) ^ liteethmaccrc32checker_crc_data1[3]);
+	liteethmaccrc32checker_crc_next[21] <= ((liteethmaccrc32checker_crc_last[13] ^ liteethmaccrc32checker_crc_last[29]) ^ liteethmaccrc32checker_crc_data1[2]);
+	liteethmaccrc32checker_crc_next[22] <= ((liteethmaccrc32checker_crc_last[14] ^ liteethmaccrc32checker_crc_last[24]) ^ liteethmaccrc32checker_crc_data1[7]);
+	liteethmaccrc32checker_crc_next[23] <= ((((((liteethmaccrc32checker_crc_last[15] ^ liteethmaccrc32checker_crc_last[25]) ^ liteethmaccrc32checker_crc_data1[6]) ^ liteethmaccrc32checker_crc_last[24]) ^ liteethmaccrc32checker_crc_last[30]) ^ liteethmaccrc32checker_crc_data1[1]) ^ liteethmaccrc32checker_crc_data1[7]);
+	liteethmaccrc32checker_crc_next[24] <= ((((((liteethmaccrc32checker_crc_last[16] ^ liteethmaccrc32checker_crc_last[26]) ^ liteethmaccrc32checker_crc_data1[5]) ^ liteethmaccrc32checker_crc_last[25]) ^ liteethmaccrc32checker_crc_last[31]) ^ liteethmaccrc32checker_crc_data1[0]) ^ liteethmaccrc32checker_crc_data1[6]);
+	liteethmaccrc32checker_crc_next[25] <= ((((liteethmaccrc32checker_crc_last[17] ^ liteethmaccrc32checker_crc_last[27]) ^ liteethmaccrc32checker_crc_data1[4]) ^ liteethmaccrc32checker_crc_last[26]) ^ liteethmaccrc32checker_crc_data1[5]);
+	liteethmaccrc32checker_crc_next[26] <= ((((((((liteethmaccrc32checker_crc_last[18] ^ liteethmaccrc32checker_crc_last[28]) ^ liteethmaccrc32checker_crc_data1[3]) ^ liteethmaccrc32checker_crc_last[27]) ^ liteethmaccrc32checker_crc_data1[4]) ^ liteethmaccrc32checker_crc_last[24]) ^ liteethmaccrc32checker_crc_last[30]) ^ liteethmaccrc32checker_crc_data1[1]) ^ liteethmaccrc32checker_crc_data1[7]);
+	liteethmaccrc32checker_crc_next[27] <= ((((((((liteethmaccrc32checker_crc_last[19] ^ liteethmaccrc32checker_crc_last[29]) ^ liteethmaccrc32checker_crc_data1[2]) ^ liteethmaccrc32checker_crc_last[28]) ^ liteethmaccrc32checker_crc_data1[3]) ^ liteethmaccrc32checker_crc_last[25]) ^ liteethmaccrc32checker_crc_last[31]) ^ liteethmaccrc32checker_crc_data1[0]) ^ liteethmaccrc32checker_crc_data1[6]);
+	liteethmaccrc32checker_crc_next[28] <= ((((((liteethmaccrc32checker_crc_last[20] ^ liteethmaccrc32checker_crc_last[30]) ^ liteethmaccrc32checker_crc_data1[1]) ^ liteethmaccrc32checker_crc_last[29]) ^ liteethmaccrc32checker_crc_data1[2]) ^ liteethmaccrc32checker_crc_last[26]) ^ liteethmaccrc32checker_crc_data1[5]);
+	liteethmaccrc32checker_crc_next[29] <= ((((((liteethmaccrc32checker_crc_last[21] ^ liteethmaccrc32checker_crc_last[31]) ^ liteethmaccrc32checker_crc_data1[0]) ^ liteethmaccrc32checker_crc_last[30]) ^ liteethmaccrc32checker_crc_data1[1]) ^ liteethmaccrc32checker_crc_last[27]) ^ liteethmaccrc32checker_crc_data1[4]);
+	liteethmaccrc32checker_crc_next[30] <= ((((liteethmaccrc32checker_crc_last[22] ^ liteethmaccrc32checker_crc_last[31]) ^ liteethmaccrc32checker_crc_data1[0]) ^ liteethmaccrc32checker_crc_last[28]) ^ liteethmaccrc32checker_crc_data1[3]);
+	liteethmaccrc32checker_crc_next[31] <= ((liteethmaccrc32checker_crc_last[23] ^ liteethmaccrc32checker_crc_last[29]) ^ liteethmaccrc32checker_crc_data1[2]);
+end
+assign liteethmaccrc32checker_syncfifo_syncfifo_din = {liteethmaccrc32checker_syncfifo_fifo_in_last, liteethmaccrc32checker_syncfifo_fifo_in_first, liteethmaccrc32checker_syncfifo_fifo_in_payload_error, liteethmaccrc32checker_syncfifo_fifo_in_payload_last_be, liteethmaccrc32checker_syncfifo_fifo_in_payload_data};
+assign {liteethmaccrc32checker_syncfifo_fifo_out_last, liteethmaccrc32checker_syncfifo_fifo_out_first, liteethmaccrc32checker_syncfifo_fifo_out_payload_error, liteethmaccrc32checker_syncfifo_fifo_out_payload_last_be, liteethmaccrc32checker_syncfifo_fifo_out_payload_data} = liteethmaccrc32checker_syncfifo_syncfifo_dout;
+assign liteethmaccrc32checker_syncfifo_sink_ready = liteethmaccrc32checker_syncfifo_syncfifo_writable;
+assign liteethmaccrc32checker_syncfifo_syncfifo_we = liteethmaccrc32checker_syncfifo_sink_valid;
+assign liteethmaccrc32checker_syncfifo_fifo_in_first = liteethmaccrc32checker_syncfifo_sink_first;
+assign liteethmaccrc32checker_syncfifo_fifo_in_last = liteethmaccrc32checker_syncfifo_sink_last;
+assign liteethmaccrc32checker_syncfifo_fifo_in_payload_data = liteethmaccrc32checker_syncfifo_sink_payload_data;
+assign liteethmaccrc32checker_syncfifo_fifo_in_payload_last_be = liteethmaccrc32checker_syncfifo_sink_payload_last_be;
+assign liteethmaccrc32checker_syncfifo_fifo_in_payload_error = liteethmaccrc32checker_syncfifo_sink_payload_error;
+assign liteethmaccrc32checker_syncfifo_source_valid = liteethmaccrc32checker_syncfifo_syncfifo_readable;
+assign liteethmaccrc32checker_syncfifo_source_first = liteethmaccrc32checker_syncfifo_fifo_out_first;
+assign liteethmaccrc32checker_syncfifo_source_last = liteethmaccrc32checker_syncfifo_fifo_out_last;
+assign liteethmaccrc32checker_syncfifo_source_payload_data = liteethmaccrc32checker_syncfifo_fifo_out_payload_data;
+assign liteethmaccrc32checker_syncfifo_source_payload_last_be = liteethmaccrc32checker_syncfifo_fifo_out_payload_last_be;
+assign liteethmaccrc32checker_syncfifo_source_payload_error = liteethmaccrc32checker_syncfifo_fifo_out_payload_error;
+assign liteethmaccrc32checker_syncfifo_syncfifo_re = liteethmaccrc32checker_syncfifo_source_ready;
+always @(*) begin
+	liteethmaccrc32checker_syncfifo_wrport_adr <= 3'd0;
+	if (liteethmaccrc32checker_syncfifo_replace) begin
+		liteethmaccrc32checker_syncfifo_wrport_adr <= (liteethmaccrc32checker_syncfifo_produce - 1'd1);
+	end else begin
+		liteethmaccrc32checker_syncfifo_wrport_adr <= liteethmaccrc32checker_syncfifo_produce;
+	end
+end
+assign liteethmaccrc32checker_syncfifo_wrport_dat_w = liteethmaccrc32checker_syncfifo_syncfifo_din;
+assign liteethmaccrc32checker_syncfifo_wrport_we = (liteethmaccrc32checker_syncfifo_syncfifo_we & (liteethmaccrc32checker_syncfifo_syncfifo_writable | liteethmaccrc32checker_syncfifo_replace));
+assign liteethmaccrc32checker_syncfifo_do_read = (liteethmaccrc32checker_syncfifo_syncfifo_readable & liteethmaccrc32checker_syncfifo_syncfifo_re);
+assign liteethmaccrc32checker_syncfifo_rdport_adr = liteethmaccrc32checker_syncfifo_consume;
+assign liteethmaccrc32checker_syncfifo_syncfifo_dout = liteethmaccrc32checker_syncfifo_rdport_dat_r;
+assign liteethmaccrc32checker_syncfifo_syncfifo_writable = (liteethmaccrc32checker_syncfifo_level != 3'd5);
+assign liteethmaccrc32checker_syncfifo_syncfifo_readable = (liteethmaccrc32checker_syncfifo_level != 1'd0);
+always @(*) begin
+	liteethmaccrc32checker_crc_ce <= 1'd0;
+	liteethmaccrc32checker_crc_reset <= 1'd0;
+	subfragments_liteethmaccrc32checker_next_state <= 2'd0;
+	liteethmaccrc32checker_fifo_reset <= 1'd0;
+	subfragments_liteethmaccrc32checker_next_state <= subfragments_liteethmaccrc32checker_state;
+	case (subfragments_liteethmaccrc32checker_state)
+		1'd1: begin
+			if ((liteethmaccrc32checker_sink_sink_valid & liteethmaccrc32checker_sink_sink_ready)) begin
+				liteethmaccrc32checker_crc_ce <= 1'd1;
+				subfragments_liteethmaccrc32checker_next_state <= 2'd2;
+			end
+		end
+		2'd2: begin
+			if ((liteethmaccrc32checker_sink_sink_valid & liteethmaccrc32checker_sink_sink_ready)) begin
+				liteethmaccrc32checker_crc_ce <= 1'd1;
+				if (liteethmaccrc32checker_sink_sink_last) begin
+					subfragments_liteethmaccrc32checker_next_state <= 1'd0;
+				end
+			end
+		end
+		default: begin
+			liteethmaccrc32checker_crc_reset <= 1'd1;
+			liteethmaccrc32checker_fifo_reset <= 1'd1;
+			subfragments_liteethmaccrc32checker_next_state <= 1'd1;
+		end
+	endcase
+end
+assign crc32_checker_sink_ready = ((~crc32_checker_source_valid) | crc32_checker_source_ready);
+assign ps_preamble_error_o = (ps_preamble_error_toggle_o ^ ps_preamble_error_toggle_o_r);
+assign ps_crc_error_o = (ps_crc_error_toggle_o ^ ps_crc_error_toggle_o_r);
+assign padding_inserter_counter_done = (padding_inserter_counter >= 6'd59);
+always @(*) begin
+	padding_inserter_source_valid <= 1'd0;
+	padding_inserter_counter_liteethmacpaddinginserter_next_value_ce <= 1'd0;
+	padding_inserter_source_first <= 1'd0;
+	padding_inserter_source_last <= 1'd0;
+	padding_inserter_source_payload_data <= 8'd0;
+	padding_inserter_source_payload_last_be <= 1'd0;
+	padding_inserter_source_payload_error <= 1'd0;
+	padding_inserter_sink_ready <= 1'd0;
+	subfragments_liteethmacpaddinginserter_next_state <= 1'd0;
+	padding_inserter_counter_liteethmacpaddinginserter_next_value <= 16'd0;
+	subfragments_liteethmacpaddinginserter_next_state <= subfragments_liteethmacpaddinginserter_state;
+	case (subfragments_liteethmacpaddinginserter_state)
+		1'd1: begin
+			padding_inserter_source_valid <= 1'd1;
+			padding_inserter_source_last <= padding_inserter_counter_done;
+			padding_inserter_source_payload_data <= 1'd0;
+			if ((padding_inserter_source_valid & padding_inserter_source_ready)) begin
+				padding_inserter_counter_liteethmacpaddinginserter_next_value <= (padding_inserter_counter + 1'd1);
+				padding_inserter_counter_liteethmacpaddinginserter_next_value_ce <= 1'd1;
+				if (padding_inserter_counter_done) begin
+					padding_inserter_counter_liteethmacpaddinginserter_next_value <= 1'd0;
+					padding_inserter_counter_liteethmacpaddinginserter_next_value_ce <= 1'd1;
+					subfragments_liteethmacpaddinginserter_next_state <= 1'd0;
+				end
+			end
+		end
+		default: begin
+			padding_inserter_source_valid <= padding_inserter_sink_valid;
+			padding_inserter_sink_ready <= padding_inserter_source_ready;
+			padding_inserter_source_first <= padding_inserter_sink_first;
+			padding_inserter_source_last <= padding_inserter_sink_last;
+			padding_inserter_source_payload_data <= padding_inserter_sink_payload_data;
+			padding_inserter_source_payload_last_be <= padding_inserter_sink_payload_last_be;
+			padding_inserter_source_payload_error <= padding_inserter_sink_payload_error;
+			if ((padding_inserter_source_valid & padding_inserter_source_ready)) begin
+				padding_inserter_counter_liteethmacpaddinginserter_next_value <= (padding_inserter_counter + 1'd1);
+				padding_inserter_counter_liteethmacpaddinginserter_next_value_ce <= 1'd1;
+				if (padding_inserter_sink_last) begin
+					if ((~padding_inserter_counter_done)) begin
+						padding_inserter_source_last <= 1'd0;
+						subfragments_liteethmacpaddinginserter_next_state <= 1'd1;
+					end else begin
+						padding_inserter_counter_liteethmacpaddinginserter_next_value <= 1'd0;
+						padding_inserter_counter_liteethmacpaddinginserter_next_value_ce <= 1'd1;
+					end
+				end
+			end
+		end
+	endcase
+end
+assign padding_checker_source_valid = padding_checker_sink_valid;
+assign padding_checker_sink_ready = padding_checker_source_ready;
+assign padding_checker_source_first = padding_checker_sink_first;
+assign padding_checker_source_last = padding_checker_sink_last;
+assign padding_checker_source_payload_data = padding_checker_sink_payload_data;
+assign padding_checker_source_payload_last_be = padding_checker_sink_payload_last_be;
+assign padding_checker_source_payload_error = padding_checker_sink_payload_error;
+always @(*) begin
+	tx_last_be_source_payload_data <= 8'd0;
+	subfragments_liteethmactxlastbe_next_state <= 1'd0;
+	tx_last_be_source_payload_error <= 1'd0;
+	tx_last_be_sink_ready <= 1'd0;
+	tx_last_be_source_valid <= 1'd0;
+	tx_last_be_source_first <= 1'd0;
+	tx_last_be_source_last <= 1'd0;
+	subfragments_liteethmactxlastbe_next_state <= subfragments_liteethmactxlastbe_state;
+	case (subfragments_liteethmactxlastbe_state)
+		1'd1: begin
+			tx_last_be_sink_ready <= 1'd1;
+			if ((tx_last_be_sink_valid & tx_last_be_sink_last)) begin
+				subfragments_liteethmactxlastbe_next_state <= 1'd0;
+			end
+		end
+		default: begin
+			tx_last_be_source_valid <= tx_last_be_sink_valid;
+			tx_last_be_sink_ready <= tx_last_be_source_ready;
+			tx_last_be_source_first <= tx_last_be_sink_first;
+			tx_last_be_source_payload_data <= tx_last_be_sink_payload_data;
+			tx_last_be_source_payload_error <= tx_last_be_sink_payload_error;
+			tx_last_be_source_last <= tx_last_be_sink_payload_last_be;
+			if ((tx_last_be_sink_valid & tx_last_be_sink_ready)) begin
+				if ((tx_last_be_sink_payload_last_be & (~tx_last_be_sink_last))) begin
+					subfragments_liteethmactxlastbe_next_state <= 1'd1;
+				end
+			end
+		end
+	endcase
+end
+assign rx_last_be_source_valid = rx_last_be_sink_valid;
+assign rx_last_be_sink_ready = rx_last_be_source_ready;
+assign rx_last_be_source_first = rx_last_be_sink_first;
+assign rx_last_be_source_last = rx_last_be_sink_last;
+assign rx_last_be_source_payload_data = rx_last_be_sink_payload_data;
+assign rx_last_be_source_payload_error = rx_last_be_sink_payload_error;
+always @(*) begin
+	rx_last_be_source_payload_last_be <= 1'd0;
+	rx_last_be_source_payload_last_be <= rx_last_be_sink_payload_last_be;
+	rx_last_be_source_payload_last_be <= rx_last_be_sink_last;
+end
+assign tx_converter_converter_sink_valid = tx_converter_sink_valid;
+assign tx_converter_converter_sink_first = tx_converter_sink_first;
+assign tx_converter_converter_sink_last = tx_converter_sink_last;
+assign tx_converter_sink_ready = tx_converter_converter_sink_ready;
+always @(*) begin
+	tx_converter_converter_sink_payload_data <= 40'd0;
+	tx_converter_converter_sink_payload_data[7:0] <= tx_converter_sink_payload_data[7:0];
+	tx_converter_converter_sink_payload_data[8] <= tx_converter_sink_payload_last_be[0];
+	tx_converter_converter_sink_payload_data[9] <= tx_converter_sink_payload_error[0];
+	tx_converter_converter_sink_payload_data[17:10] <= tx_converter_sink_payload_data[15:8];
+	tx_converter_converter_sink_payload_data[18] <= tx_converter_sink_payload_last_be[1];
+	tx_converter_converter_sink_payload_data[19] <= tx_converter_sink_payload_error[1];
+	tx_converter_converter_sink_payload_data[27:20] <= tx_converter_sink_payload_data[23:16];
+	tx_converter_converter_sink_payload_data[28] <= tx_converter_sink_payload_last_be[2];
+	tx_converter_converter_sink_payload_data[29] <= tx_converter_sink_payload_error[2];
+	tx_converter_converter_sink_payload_data[37:30] <= tx_converter_sink_payload_data[31:24];
+	tx_converter_converter_sink_payload_data[38] <= tx_converter_sink_payload_last_be[3];
+	tx_converter_converter_sink_payload_data[39] <= tx_converter_sink_payload_error[3];
+end
+assign tx_converter_source_valid = tx_converter_source_source_valid;
+assign tx_converter_source_first = tx_converter_source_source_first;
+assign tx_converter_source_last = tx_converter_source_source_last;
+assign tx_converter_source_source_ready = tx_converter_source_ready;
+assign {tx_converter_source_payload_error, tx_converter_source_payload_last_be, tx_converter_source_payload_data} = tx_converter_source_source_payload_data;
+assign tx_converter_source_source_valid = tx_converter_converter_source_valid;
+assign tx_converter_converter_source_ready = tx_converter_source_source_ready;
+assign tx_converter_source_source_first = tx_converter_converter_source_first;
+assign tx_converter_source_source_last = tx_converter_converter_source_last;
+assign tx_converter_source_source_payload_data = tx_converter_converter_source_payload_data;
+assign tx_converter_converter_first = (tx_converter_converter_mux == 1'd0);
+assign tx_converter_converter_last = (tx_converter_converter_mux == 2'd3);
+assign tx_converter_converter_source_valid = tx_converter_converter_sink_valid;
+assign tx_converter_converter_source_first = (tx_converter_converter_sink_first & tx_converter_converter_first);
+assign tx_converter_converter_source_last = (tx_converter_converter_sink_last & tx_converter_converter_last);
+assign tx_converter_converter_sink_ready = (tx_converter_converter_last & tx_converter_converter_source_ready);
+always @(*) begin
+	tx_converter_converter_source_payload_data <= 10'd0;
+	case (tx_converter_converter_mux)
+		1'd0: begin
+			tx_converter_converter_source_payload_data <= tx_converter_converter_sink_payload_data[9:0];
+		end
+		1'd1: begin
+			tx_converter_converter_source_payload_data <= tx_converter_converter_sink_payload_data[19:10];
+		end
+		2'd2: begin
+			tx_converter_converter_source_payload_data <= tx_converter_converter_sink_payload_data[29:20];
+		end
+		default: begin
+			tx_converter_converter_source_payload_data <= tx_converter_converter_sink_payload_data[39:30];
+		end
+	endcase
+end
+assign tx_converter_converter_source_payload_valid_token_count = tx_converter_converter_last;
+assign rx_converter_converter_sink_valid = rx_converter_sink_valid;
+assign rx_converter_converter_sink_first = rx_converter_sink_first;
+assign rx_converter_converter_sink_last = rx_converter_sink_last;
+assign rx_converter_sink_ready = rx_converter_converter_sink_ready;
+assign rx_converter_converter_sink_payload_data = {rx_converter_sink_payload_error, rx_converter_sink_payload_last_be, rx_converter_sink_payload_data};
+assign rx_converter_source_valid = rx_converter_source_source_valid;
+assign rx_converter_source_first = rx_converter_source_source_first;
+assign rx_converter_source_last = rx_converter_source_source_last;
+assign rx_converter_source_source_ready = rx_converter_source_ready;
+always @(*) begin
+	rx_converter_source_payload_data <= 32'd0;
+	rx_converter_source_payload_data[7:0] <= rx_converter_source_source_payload_data[7:0];
+	rx_converter_source_payload_data[15:8] <= rx_converter_source_source_payload_data[17:10];
+	rx_converter_source_payload_data[23:16] <= rx_converter_source_source_payload_data[27:20];
+	rx_converter_source_payload_data[31:24] <= rx_converter_source_source_payload_data[37:30];
+end
+always @(*) begin
+	rx_converter_source_payload_last_be <= 4'd0;
+	rx_converter_source_payload_last_be[0] <= rx_converter_source_source_payload_data[8];
+	rx_converter_source_payload_last_be[1] <= rx_converter_source_source_payload_data[18];
+	rx_converter_source_payload_last_be[2] <= rx_converter_source_source_payload_data[28];
+	rx_converter_source_payload_last_be[3] <= rx_converter_source_source_payload_data[38];
+end
+always @(*) begin
+	rx_converter_source_payload_error <= 4'd0;
+	rx_converter_source_payload_error[0] <= rx_converter_source_source_payload_data[9];
+	rx_converter_source_payload_error[1] <= rx_converter_source_source_payload_data[19];
+	rx_converter_source_payload_error[2] <= rx_converter_source_source_payload_data[29];
+	rx_converter_source_payload_error[3] <= rx_converter_source_source_payload_data[39];
+end
+assign rx_converter_source_source_valid = rx_converter_converter_source_valid;
+assign rx_converter_converter_source_ready = rx_converter_source_source_ready;
+assign rx_converter_source_source_first = rx_converter_converter_source_first;
+assign rx_converter_source_source_last = rx_converter_converter_source_last;
+assign rx_converter_source_source_payload_data = rx_converter_converter_source_payload_data;
+assign rx_converter_converter_sink_ready = ((~rx_converter_converter_strobe_all) | rx_converter_converter_source_ready);
+assign rx_converter_converter_source_valid = rx_converter_converter_strobe_all;
+assign rx_converter_converter_load_part = (rx_converter_converter_sink_valid & rx_converter_converter_sink_ready);
+assign tx_cdc_cdc_sink_valid = tx_cdc_sink_sink_valid;
+assign tx_cdc_sink_sink_ready = tx_cdc_cdc_sink_ready;
+assign tx_cdc_cdc_sink_first = tx_cdc_sink_sink_first;
+assign tx_cdc_cdc_sink_last = tx_cdc_sink_sink_last;
+assign tx_cdc_cdc_sink_payload_data = tx_cdc_sink_sink_payload_data;
+assign tx_cdc_cdc_sink_payload_last_be = tx_cdc_sink_sink_payload_last_be;
+assign tx_cdc_cdc_sink_payload_error = tx_cdc_sink_sink_payload_error;
+assign tx_cdc_source_source_valid = tx_cdc_cdc_source_valid;
+assign tx_cdc_cdc_source_ready = tx_cdc_source_source_ready;
+assign tx_cdc_source_source_first = tx_cdc_cdc_source_first;
+assign tx_cdc_source_source_last = tx_cdc_cdc_source_last;
+assign tx_cdc_source_source_payload_data = tx_cdc_cdc_source_payload_data;
+assign tx_cdc_source_source_payload_last_be = tx_cdc_cdc_source_payload_last_be;
+assign tx_cdc_source_source_payload_error = tx_cdc_cdc_source_payload_error;
+assign tx_cdc_cdc_asyncfifo_din = {tx_cdc_cdc_fifo_in_last, tx_cdc_cdc_fifo_in_first, tx_cdc_cdc_fifo_in_payload_error, tx_cdc_cdc_fifo_in_payload_last_be, tx_cdc_cdc_fifo_in_payload_data};
+assign {tx_cdc_cdc_fifo_out_last, tx_cdc_cdc_fifo_out_first, tx_cdc_cdc_fifo_out_payload_error, tx_cdc_cdc_fifo_out_payload_last_be, tx_cdc_cdc_fifo_out_payload_data} = tx_cdc_cdc_asyncfifo_dout;
+assign tx_cdc_cdc_sink_ready = tx_cdc_cdc_asyncfifo_writable;
+assign tx_cdc_cdc_asyncfifo_we = tx_cdc_cdc_sink_valid;
+assign tx_cdc_cdc_fifo_in_first = tx_cdc_cdc_sink_first;
+assign tx_cdc_cdc_fifo_in_last = tx_cdc_cdc_sink_last;
+assign tx_cdc_cdc_fifo_in_payload_data = tx_cdc_cdc_sink_payload_data;
+assign tx_cdc_cdc_fifo_in_payload_last_be = tx_cdc_cdc_sink_payload_last_be;
+assign tx_cdc_cdc_fifo_in_payload_error = tx_cdc_cdc_sink_payload_error;
+assign tx_cdc_cdc_source_valid = tx_cdc_cdc_asyncfifo_readable;
+assign tx_cdc_cdc_source_first = tx_cdc_cdc_fifo_out_first;
+assign tx_cdc_cdc_source_last = tx_cdc_cdc_fifo_out_last;
+assign tx_cdc_cdc_source_payload_data = tx_cdc_cdc_fifo_out_payload_data;
+assign tx_cdc_cdc_source_payload_last_be = tx_cdc_cdc_fifo_out_payload_last_be;
+assign tx_cdc_cdc_source_payload_error = tx_cdc_cdc_fifo_out_payload_error;
+assign tx_cdc_cdc_asyncfifo_re = tx_cdc_cdc_source_ready;
+assign tx_cdc_cdc_graycounter0_ce = (tx_cdc_cdc_asyncfifo_writable & tx_cdc_cdc_asyncfifo_we);
+assign tx_cdc_cdc_graycounter1_ce = (tx_cdc_cdc_asyncfifo_readable & tx_cdc_cdc_asyncfifo_re);
+assign tx_cdc_cdc_asyncfifo_writable = (((tx_cdc_cdc_graycounter0_q[5] == tx_cdc_cdc_consume_wdomain[5]) | (tx_cdc_cdc_graycounter0_q[4] == tx_cdc_cdc_consume_wdomain[4])) | (tx_cdc_cdc_graycounter0_q[3:0] != tx_cdc_cdc_consume_wdomain[3:0]));
+assign tx_cdc_cdc_asyncfifo_readable = (tx_cdc_cdc_graycounter1_q != tx_cdc_cdc_produce_rdomain);
+assign tx_cdc_cdc_wrport_adr = tx_cdc_cdc_graycounter0_q_binary[4:0];
+assign tx_cdc_cdc_wrport_dat_w = tx_cdc_cdc_asyncfifo_din;
+assign tx_cdc_cdc_wrport_we = tx_cdc_cdc_graycounter0_ce;
+assign tx_cdc_cdc_rdport_adr = tx_cdc_cdc_graycounter1_q_next_binary[4:0];
+assign tx_cdc_cdc_asyncfifo_dout = tx_cdc_cdc_rdport_dat_r;
+always @(*) begin
+	tx_cdc_cdc_graycounter0_q_next_binary <= 6'd0;
+	if (tx_cdc_cdc_graycounter0_ce) begin
+		tx_cdc_cdc_graycounter0_q_next_binary <= (tx_cdc_cdc_graycounter0_q_binary + 1'd1);
+	end else begin
+		tx_cdc_cdc_graycounter0_q_next_binary <= tx_cdc_cdc_graycounter0_q_binary;
+	end
+end
+assign tx_cdc_cdc_graycounter0_q_next = (tx_cdc_cdc_graycounter0_q_next_binary ^ tx_cdc_cdc_graycounter0_q_next_binary[5:1]);
+always @(*) begin
+	tx_cdc_cdc_graycounter1_q_next_binary <= 6'd0;
+	if (tx_cdc_cdc_graycounter1_ce) begin
+		tx_cdc_cdc_graycounter1_q_next_binary <= (tx_cdc_cdc_graycounter1_q_binary + 1'd1);
+	end else begin
+		tx_cdc_cdc_graycounter1_q_next_binary <= tx_cdc_cdc_graycounter1_q_binary;
+	end
+end
+assign tx_cdc_cdc_graycounter1_q_next = (tx_cdc_cdc_graycounter1_q_next_binary ^ tx_cdc_cdc_graycounter1_q_next_binary[5:1]);
+assign rx_cdc_cdc_sink_valid = rx_cdc_sink_sink_valid;
+assign rx_cdc_sink_sink_ready = rx_cdc_cdc_sink_ready;
+assign rx_cdc_cdc_sink_first = rx_cdc_sink_sink_first;
+assign rx_cdc_cdc_sink_last = rx_cdc_sink_sink_last;
+assign rx_cdc_cdc_sink_payload_data = rx_cdc_sink_sink_payload_data;
+assign rx_cdc_cdc_sink_payload_last_be = rx_cdc_sink_sink_payload_last_be;
+assign rx_cdc_cdc_sink_payload_error = rx_cdc_sink_sink_payload_error;
+assign rx_cdc_source_source_valid = rx_cdc_cdc_source_valid;
+assign rx_cdc_cdc_source_ready = rx_cdc_source_source_ready;
+assign rx_cdc_source_source_first = rx_cdc_cdc_source_first;
+assign rx_cdc_source_source_last = rx_cdc_cdc_source_last;
+assign rx_cdc_source_source_payload_data = rx_cdc_cdc_source_payload_data;
+assign rx_cdc_source_source_payload_last_be = rx_cdc_cdc_source_payload_last_be;
+assign rx_cdc_source_source_payload_error = rx_cdc_cdc_source_payload_error;
+assign rx_cdc_cdc_asyncfifo_din = {rx_cdc_cdc_fifo_in_last, rx_cdc_cdc_fifo_in_first, rx_cdc_cdc_fifo_in_payload_error, rx_cdc_cdc_fifo_in_payload_last_be, rx_cdc_cdc_fifo_in_payload_data};
+assign {rx_cdc_cdc_fifo_out_last, rx_cdc_cdc_fifo_out_first, rx_cdc_cdc_fifo_out_payload_error, rx_cdc_cdc_fifo_out_payload_last_be, rx_cdc_cdc_fifo_out_payload_data} = rx_cdc_cdc_asyncfifo_dout;
+assign rx_cdc_cdc_sink_ready = rx_cdc_cdc_asyncfifo_writable;
+assign rx_cdc_cdc_asyncfifo_we = rx_cdc_cdc_sink_valid;
+assign rx_cdc_cdc_fifo_in_first = rx_cdc_cdc_sink_first;
+assign rx_cdc_cdc_fifo_in_last = rx_cdc_cdc_sink_last;
+assign rx_cdc_cdc_fifo_in_payload_data = rx_cdc_cdc_sink_payload_data;
+assign rx_cdc_cdc_fifo_in_payload_last_be = rx_cdc_cdc_sink_payload_last_be;
+assign rx_cdc_cdc_fifo_in_payload_error = rx_cdc_cdc_sink_payload_error;
+assign rx_cdc_cdc_source_valid = rx_cdc_cdc_asyncfifo_readable;
+assign rx_cdc_cdc_source_first = rx_cdc_cdc_fifo_out_first;
+assign rx_cdc_cdc_source_last = rx_cdc_cdc_fifo_out_last;
+assign rx_cdc_cdc_source_payload_data = rx_cdc_cdc_fifo_out_payload_data;
+assign rx_cdc_cdc_source_payload_last_be = rx_cdc_cdc_fifo_out_payload_last_be;
+assign rx_cdc_cdc_source_payload_error = rx_cdc_cdc_fifo_out_payload_error;
+assign rx_cdc_cdc_asyncfifo_re = rx_cdc_cdc_source_ready;
+assign rx_cdc_cdc_graycounter0_ce = (rx_cdc_cdc_asyncfifo_writable & rx_cdc_cdc_asyncfifo_we);
+assign rx_cdc_cdc_graycounter1_ce = (rx_cdc_cdc_asyncfifo_readable & rx_cdc_cdc_asyncfifo_re);
+assign rx_cdc_cdc_asyncfifo_writable = (((rx_cdc_cdc_graycounter0_q[5] == rx_cdc_cdc_consume_wdomain[5]) | (rx_cdc_cdc_graycounter0_q[4] == rx_cdc_cdc_consume_wdomain[4])) | (rx_cdc_cdc_graycounter0_q[3:0] != rx_cdc_cdc_consume_wdomain[3:0]));
+assign rx_cdc_cdc_asyncfifo_readable = (rx_cdc_cdc_graycounter1_q != rx_cdc_cdc_produce_rdomain);
+assign rx_cdc_cdc_wrport_adr = rx_cdc_cdc_graycounter0_q_binary[4:0];
+assign rx_cdc_cdc_wrport_dat_w = rx_cdc_cdc_asyncfifo_din;
+assign rx_cdc_cdc_wrport_we = rx_cdc_cdc_graycounter0_ce;
+assign rx_cdc_cdc_rdport_adr = rx_cdc_cdc_graycounter1_q_next_binary[4:0];
+assign rx_cdc_cdc_asyncfifo_dout = rx_cdc_cdc_rdport_dat_r;
+always @(*) begin
+	rx_cdc_cdc_graycounter0_q_next_binary <= 6'd0;
+	if (rx_cdc_cdc_graycounter0_ce) begin
+		rx_cdc_cdc_graycounter0_q_next_binary <= (rx_cdc_cdc_graycounter0_q_binary + 1'd1);
+	end else begin
+		rx_cdc_cdc_graycounter0_q_next_binary <= rx_cdc_cdc_graycounter0_q_binary;
+	end
+end
+assign rx_cdc_cdc_graycounter0_q_next = (rx_cdc_cdc_graycounter0_q_next_binary ^ rx_cdc_cdc_graycounter0_q_next_binary[5:1]);
+always @(*) begin
+	rx_cdc_cdc_graycounter1_q_next_binary <= 6'd0;
+	if (rx_cdc_cdc_graycounter1_ce) begin
+		rx_cdc_cdc_graycounter1_q_next_binary <= (rx_cdc_cdc_graycounter1_q_binary + 1'd1);
+	end else begin
+		rx_cdc_cdc_graycounter1_q_next_binary <= rx_cdc_cdc_graycounter1_q_binary;
+	end
+end
+assign rx_cdc_cdc_graycounter1_q_next = (rx_cdc_cdc_graycounter1_q_next_binary ^ rx_cdc_cdc_graycounter1_q_next_binary[5:1]);
+assign tx_converter_sink_valid = tx_cdc_source_source_valid;
+assign tx_cdc_source_source_ready = tx_converter_sink_ready;
+assign tx_converter_sink_first = tx_cdc_source_source_first;
+assign tx_converter_sink_last = tx_cdc_source_source_last;
+assign tx_converter_sink_payload_data = tx_cdc_source_source_payload_data;
+assign tx_converter_sink_payload_last_be = tx_cdc_source_source_payload_last_be;
+assign tx_converter_sink_payload_error = tx_cdc_source_source_payload_error;
+assign tx_last_be_sink_valid = tx_converter_source_valid;
+assign tx_converter_source_ready = tx_last_be_sink_ready;
+assign tx_last_be_sink_first = tx_converter_source_first;
+assign tx_last_be_sink_last = tx_converter_source_last;
+assign tx_last_be_sink_payload_data = tx_converter_source_payload_data;
+assign tx_last_be_sink_payload_last_be = tx_converter_source_payload_last_be;
+assign tx_last_be_sink_payload_error = tx_converter_source_payload_error;
+assign padding_inserter_sink_valid = tx_last_be_source_valid;
+assign tx_last_be_source_ready = padding_inserter_sink_ready;
+assign padding_inserter_sink_first = tx_last_be_source_first;
+assign padding_inserter_sink_last = tx_last_be_source_last;
+assign padding_inserter_sink_payload_data = tx_last_be_source_payload_data;
+assign padding_inserter_sink_payload_last_be = tx_last_be_source_payload_last_be;
+assign padding_inserter_sink_payload_error = tx_last_be_source_payload_error;
+assign crc32_inserter_sink_valid = padding_inserter_source_valid;
+assign padding_inserter_source_ready = crc32_inserter_sink_ready;
+assign crc32_inserter_sink_first = padding_inserter_source_first;
+assign crc32_inserter_sink_last = padding_inserter_source_last;
+assign crc32_inserter_sink_payload_data = padding_inserter_source_payload_data;
+assign crc32_inserter_sink_payload_last_be = padding_inserter_source_payload_last_be;
+assign crc32_inserter_sink_payload_error = padding_inserter_source_payload_error;
+assign preamble_inserter_sink_valid = liteethmaccrc32inserter_source_valid;
+assign liteethmaccrc32inserter_source_ready = preamble_inserter_sink_ready;
+assign preamble_inserter_sink_first = liteethmaccrc32inserter_source_first;
+assign preamble_inserter_sink_last = liteethmaccrc32inserter_source_last;
+assign preamble_inserter_sink_payload_data = liteethmaccrc32inserter_source_payload_data;
+assign preamble_inserter_sink_payload_last_be = liteethmaccrc32inserter_source_payload_last_be;
+assign preamble_inserter_sink_payload_error = liteethmaccrc32inserter_source_payload_error;
+assign tx_gap_inserter_sink_valid = preamble_inserter_source_valid;
+assign preamble_inserter_source_ready = tx_gap_inserter_sink_ready;
+assign tx_gap_inserter_sink_first = preamble_inserter_source_first;
+assign tx_gap_inserter_sink_last = preamble_inserter_source_last;
+assign tx_gap_inserter_sink_payload_data = preamble_inserter_source_payload_data;
+assign tx_gap_inserter_sink_payload_last_be = preamble_inserter_source_payload_last_be;
+assign tx_gap_inserter_sink_payload_error = preamble_inserter_source_payload_error;
+assign maccore_ethphy_liteethphygmiimiitx_sink_sink_valid0 = tx_gap_inserter_source_valid;
+assign tx_gap_inserter_source_ready = maccore_ethphy_liteethphygmiimiitx_sink_sink_ready0;
+assign maccore_ethphy_liteethphygmiimiitx_sink_sink_first0 = tx_gap_inserter_source_first;
+assign maccore_ethphy_liteethphygmiimiitx_sink_sink_last0 = tx_gap_inserter_source_last;
+assign maccore_ethphy_liteethphygmiimiitx_sink_sink_payload_data0 = tx_gap_inserter_source_payload_data;
+assign maccore_ethphy_liteethphygmiimiitx_sink_sink_payload_last_be0 = tx_gap_inserter_source_payload_last_be;
+assign maccore_ethphy_liteethphygmiimiitx_sink_sink_payload_error0 = tx_gap_inserter_source_payload_error;
+assign preamble_checker_sink_valid = maccore_ethphy_liteethphygmiimiirx_source_source_valid0;
+assign maccore_ethphy_liteethphygmiimiirx_source_source_ready0 = preamble_checker_sink_ready;
+assign preamble_checker_sink_first = maccore_ethphy_liteethphygmiimiirx_source_source_first0;
+assign preamble_checker_sink_last = maccore_ethphy_liteethphygmiimiirx_source_source_last0;
+assign preamble_checker_sink_payload_data = maccore_ethphy_liteethphygmiimiirx_source_source_payload_data0;
+assign preamble_checker_sink_payload_last_be = maccore_ethphy_liteethphygmiimiirx_source_source_payload_last_be0;
+assign preamble_checker_sink_payload_error = maccore_ethphy_liteethphygmiimiirx_source_source_payload_error0;
+assign crc32_checker_sink_valid = preamble_checker_source_valid;
+assign preamble_checker_source_ready = crc32_checker_sink_ready;
+assign crc32_checker_sink_first = preamble_checker_source_first;
+assign crc32_checker_sink_last = preamble_checker_source_last;
+assign crc32_checker_sink_payload_data = preamble_checker_source_payload_data;
+assign crc32_checker_sink_payload_last_be = preamble_checker_source_payload_last_be;
+assign crc32_checker_sink_payload_error = preamble_checker_source_payload_error;
+assign padding_checker_sink_valid = liteethmaccrc32checker_source_source_valid;
+assign liteethmaccrc32checker_source_source_ready = padding_checker_sink_ready;
+assign padding_checker_sink_first = liteethmaccrc32checker_source_source_first;
+assign padding_checker_sink_last = liteethmaccrc32checker_source_source_last;
+assign padding_checker_sink_payload_data = liteethmaccrc32checker_source_source_payload_data;
+assign padding_checker_sink_payload_last_be = liteethmaccrc32checker_source_source_payload_last_be;
+assign padding_checker_sink_payload_error = liteethmaccrc32checker_source_source_payload_error;
+assign rx_last_be_sink_valid = padding_checker_source_valid;
+assign padding_checker_source_ready = rx_last_be_sink_ready;
+assign rx_last_be_sink_first = padding_checker_source_first;
+assign rx_last_be_sink_last = padding_checker_source_last;
+assign rx_last_be_sink_payload_data = padding_checker_source_payload_data;
+assign rx_last_be_sink_payload_last_be = padding_checker_source_payload_last_be;
+assign rx_last_be_sink_payload_error = padding_checker_source_payload_error;
+assign rx_converter_sink_valid = rx_last_be_source_valid;
+assign rx_last_be_source_ready = rx_converter_sink_ready;
+assign rx_converter_sink_first = rx_last_be_source_first;
+assign rx_converter_sink_last = rx_last_be_source_last;
+assign rx_converter_sink_payload_data = rx_last_be_source_payload_data;
+assign rx_converter_sink_payload_last_be = rx_last_be_source_payload_last_be;
+assign rx_converter_sink_payload_error = rx_last_be_source_payload_error;
+assign rx_cdc_sink_sink_valid = rx_converter_source_valid;
+assign rx_converter_source_ready = rx_cdc_sink_sink_ready;
+assign rx_cdc_sink_sink_first = rx_converter_source_first;
+assign rx_cdc_sink_sink_last = rx_converter_source_last;
+assign rx_cdc_sink_sink_payload_data = rx_converter_source_payload_data;
+assign rx_cdc_sink_sink_payload_last_be = rx_converter_source_payload_last_be;
+assign rx_cdc_sink_sink_payload_error = rx_converter_source_payload_error;
+assign writer_sink_sink_valid = sink_valid;
+assign sink_ready = writer_sink_sink_ready;
+assign writer_sink_sink_first = sink_first;
+assign writer_sink_sink_last = sink_last;
+assign writer_sink_sink_payload_data = sink_payload_data;
+assign writer_sink_sink_payload_last_be = sink_payload_last_be;
+assign writer_sink_sink_payload_error = sink_payload_error;
+assign source_valid = reader_source_source_valid;
+assign reader_source_source_ready = source_ready;
+assign source_first = reader_source_source_first;
+assign source_last = reader_source_source_last;
+assign source_payload_data = reader_source_source_payload_data;
+assign source_payload_last_be = reader_source_source_payload_last_be;
+assign source_payload_error = reader_source_source_payload_error;
+always @(*) begin
+	writer_inc <= 3'd0;
+	case (writer_sink_sink_payload_last_be)
+		1'd1: begin
+			writer_inc <= 1'd1;
+		end
+		2'd2: begin
+			writer_inc <= 2'd2;
+		end
+		3'd4: begin
+			writer_inc <= 2'd3;
+		end
+		default: begin
+			writer_inc <= 3'd4;
+		end
+	endcase
+end
+assign writer_stat_fifo_sink_payload_slot = writer_slot;
+assign writer_stat_fifo_sink_payload_length = writer_counter;
+assign writer_stat_fifo_source_ready = writer_available_clear;
+assign writer_available_trigger = writer_stat_fifo_source_valid;
+assign writer_slot_status = writer_stat_fifo_source_payload_slot;
+assign writer_length_status = writer_stat_fifo_source_payload_length;
+always @(*) begin
+	writer_memory1_adr <= 9'd0;
+	writer_memory1_we <= 1'd0;
+	writer_memory0_adr <= 9'd0;
+	writer_memory1_dat_w <= 32'd0;
+	writer_memory0_we <= 1'd0;
+	writer_memory0_dat_w <= 32'd0;
+	case (writer_slot)
+		1'd0: begin
+			writer_memory0_adr <= writer_counter[31:2];
+			writer_memory0_dat_w <= writer_sink_sink_payload_data;
+			if ((writer_sink_sink_valid & writer_ongoing)) begin
+				writer_memory0_we <= 4'd15;
+			end
+		end
+		1'd1: begin
+			writer_memory1_adr <= writer_counter[31:2];
+			writer_memory1_dat_w <= writer_sink_sink_payload_data;
+			if ((writer_sink_sink_valid & writer_ongoing)) begin
+				writer_memory1_we <= 4'd15;
+			end
+		end
+	endcase
+end
+assign writer_available0 = writer_available_status;
+assign writer_available1 = writer_available_pending;
+always @(*) begin
+	writer_available_clear <= 1'd0;
+	if ((writer_pending_re & writer_pending_r)) begin
+		writer_available_clear <= 1'd1;
+	end
+end
+assign writer_irq = (writer_pending_status & writer_enable_storage);
+assign writer_available_status = writer_available_trigger;
+assign writer_available_pending = writer_available_trigger;
+assign writer_stat_fifo_syncfifo_din = {writer_stat_fifo_fifo_in_last, writer_stat_fifo_fifo_in_first, writer_stat_fifo_fifo_in_payload_length, writer_stat_fifo_fifo_in_payload_slot};
+assign {writer_stat_fifo_fifo_out_last, writer_stat_fifo_fifo_out_first, writer_stat_fifo_fifo_out_payload_length, writer_stat_fifo_fifo_out_payload_slot} = writer_stat_fifo_syncfifo_dout;
+assign writer_stat_fifo_sink_ready = writer_stat_fifo_syncfifo_writable;
+assign writer_stat_fifo_syncfifo_we = writer_stat_fifo_sink_valid;
+assign writer_stat_fifo_fifo_in_first = writer_stat_fifo_sink_first;
+assign writer_stat_fifo_fifo_in_last = writer_stat_fifo_sink_last;
+assign writer_stat_fifo_fifo_in_payload_slot = writer_stat_fifo_sink_payload_slot;
+assign writer_stat_fifo_fifo_in_payload_length = writer_stat_fifo_sink_payload_length;
+assign writer_stat_fifo_source_valid = writer_stat_fifo_syncfifo_readable;
+assign writer_stat_fifo_source_first = writer_stat_fifo_fifo_out_first;
+assign writer_stat_fifo_source_last = writer_stat_fifo_fifo_out_last;
+assign writer_stat_fifo_source_payload_slot = writer_stat_fifo_fifo_out_payload_slot;
+assign writer_stat_fifo_source_payload_length = writer_stat_fifo_fifo_out_payload_length;
+assign writer_stat_fifo_syncfifo_re = writer_stat_fifo_source_ready;
+always @(*) begin
+	writer_stat_fifo_wrport_adr <= 1'd0;
+	if (writer_stat_fifo_replace) begin
+		writer_stat_fifo_wrport_adr <= (writer_stat_fifo_produce - 1'd1);
+	end else begin
+		writer_stat_fifo_wrport_adr <= writer_stat_fifo_produce;
+	end
+end
+assign writer_stat_fifo_wrport_dat_w = writer_stat_fifo_syncfifo_din;
+assign writer_stat_fifo_wrport_we = (writer_stat_fifo_syncfifo_we & (writer_stat_fifo_syncfifo_writable | writer_stat_fifo_replace));
+assign writer_stat_fifo_do_read = (writer_stat_fifo_syncfifo_readable & writer_stat_fifo_syncfifo_re);
+assign writer_stat_fifo_rdport_adr = writer_stat_fifo_consume;
+assign writer_stat_fifo_syncfifo_dout = writer_stat_fifo_rdport_dat_r;
+assign writer_stat_fifo_syncfifo_writable = (writer_stat_fifo_level != 2'd2);
+assign writer_stat_fifo_syncfifo_readable = (writer_stat_fifo_level != 1'd0);
+always @(*) begin
+	subfragments_liteethmacsramwriter_next_state <= 3'd0;
+	writer_counter_t_next_value <= 32'd0;
+	writer_counter_t_next_value_ce <= 1'd0;
+	writer_errors_status_f_next_value <= 32'd0;
+	writer_errors_status_f_next_value_ce <= 1'd0;
+	writer_slot_ce <= 1'd0;
+	writer_start <= 1'd0;
+	writer_ongoing <= 1'd0;
+	writer_stat_fifo_sink_valid <= 1'd0;
+	subfragments_liteethmacsramwriter_next_state <= subfragments_liteethmacsramwriter_state;
+	case (subfragments_liteethmacsramwriter_state)
+		1'd1: begin
+			if (writer_sink_sink_valid) begin
+				if ((writer_counter == 11'd1530)) begin
+					subfragments_liteethmacsramwriter_next_state <= 2'd3;
+				end else begin
+					writer_counter_t_next_value <= (writer_counter + writer_inc);
+					writer_counter_t_next_value_ce <= 1'd1;
+					writer_ongoing <= 1'd1;
+				end
+				if (writer_sink_sink_last) begin
+					if (((writer_sink_sink_payload_error & writer_sink_sink_payload_last_be) != 1'd0)) begin
+						subfragments_liteethmacsramwriter_next_state <= 2'd2;
+					end else begin
+						subfragments_liteethmacsramwriter_next_state <= 3'd4;
+					end
+				end
+			end
+		end
+		2'd2: begin
+			writer_counter_t_next_value <= 1'd0;
+			writer_counter_t_next_value_ce <= 1'd1;
+			subfragments_liteethmacsramwriter_next_state <= 1'd0;
+		end
+		2'd3: begin
+			if ((writer_sink_sink_valid & writer_sink_sink_last)) begin
+				subfragments_liteethmacsramwriter_next_state <= 3'd4;
+			end
+		end
+		3'd4: begin
+			writer_counter_t_next_value <= 1'd0;
+			writer_counter_t_next_value_ce <= 1'd1;
+			writer_slot_ce <= 1'd1;
+			writer_stat_fifo_sink_valid <= 1'd1;
+			subfragments_liteethmacsramwriter_next_state <= 1'd0;
+		end
+		default: begin
+			if (writer_sink_sink_valid) begin
+				if (writer_stat_fifo_sink_ready) begin
+					writer_start <= 1'd1;
+					writer_ongoing <= 1'd1;
+					writer_counter_t_next_value <= (writer_counter + writer_inc);
+					writer_counter_t_next_value_ce <= 1'd1;
+					subfragments_liteethmacsramwriter_next_state <= 1'd1;
+				end else begin
+					writer_errors_status_f_next_value <= (writer_errors_status + 1'd1);
+					writer_errors_status_f_next_value_ce <= 1'd1;
+					subfragments_liteethmacsramwriter_next_state <= 2'd3;
+				end
+			end
+		end
+	endcase
+end
+assign reader_cmd_fifo_sink_valid = reader_start_start_re;
+assign reader_cmd_fifo_sink_payload_slot = reader_slot_storage;
+assign reader_cmd_fifo_sink_payload_length = reader_length_storage;
+assign reader_ready_status = reader_cmd_fifo_sink_ready;
+assign reader_level_status = reader_cmd_fifo_level;
+always @(*) begin
+	reader_source_source_payload_last_be <= 4'd0;
+	if (reader_source_source_last) begin
+		case (reader_cmd_fifo_source_payload_length[1:0])
+			1'd0: begin
+				reader_source_source_payload_last_be <= 4'd8;
+			end
+			1'd1: begin
+				reader_source_source_payload_last_be <= 1'd1;
+			end
+			2'd2: begin
+				reader_source_source_payload_last_be <= 2'd2;
+			end
+			2'd3: begin
+				reader_source_source_payload_last_be <= 3'd4;
+			end
+		endcase
+	end
+end
+assign reader_memory0_adr = reader_read_address[10:2];
+assign reader_memory1_adr = reader_read_address[10:2];
+always @(*) begin
+	reader_source_source_payload_data <= 32'd0;
+	case (reader_cmd_fifo_source_payload_slot)
+		1'd0: begin
+			reader_source_source_payload_data <= reader_memory0_dat_r;
+		end
+		1'd1: begin
+			reader_source_source_payload_data <= reader_memory1_dat_r;
+		end
+	endcase
+end
+assign reader_event00 = reader_eventsourcepulse_status;
+assign reader_event01 = reader_eventsourcepulse_pending;
+always @(*) begin
+	reader_eventsourcepulse_clear <= 1'd0;
+	if ((reader_pending_re & reader_pending_r)) begin
+		reader_eventsourcepulse_clear <= 1'd1;
+	end
+end
+assign reader_irq = (reader_pending_status & reader_enable_storage);
+assign reader_eventsourcepulse_status = 1'd0;
+assign reader_cmd_fifo_syncfifo_din = {reader_cmd_fifo_fifo_in_last, reader_cmd_fifo_fifo_in_first, reader_cmd_fifo_fifo_in_payload_length, reader_cmd_fifo_fifo_in_payload_slot};
+assign {reader_cmd_fifo_fifo_out_last, reader_cmd_fifo_fifo_out_first, reader_cmd_fifo_fifo_out_payload_length, reader_cmd_fifo_fifo_out_payload_slot} = reader_cmd_fifo_syncfifo_dout;
+assign reader_cmd_fifo_sink_ready = reader_cmd_fifo_syncfifo_writable;
+assign reader_cmd_fifo_syncfifo_we = reader_cmd_fifo_sink_valid;
+assign reader_cmd_fifo_fifo_in_first = reader_cmd_fifo_sink_first;
+assign reader_cmd_fifo_fifo_in_last = reader_cmd_fifo_sink_last;
+assign reader_cmd_fifo_fifo_in_payload_slot = reader_cmd_fifo_sink_payload_slot;
+assign reader_cmd_fifo_fifo_in_payload_length = reader_cmd_fifo_sink_payload_length;
+assign reader_cmd_fifo_source_valid = reader_cmd_fifo_syncfifo_readable;
+assign reader_cmd_fifo_source_first = reader_cmd_fifo_fifo_out_first;
+assign reader_cmd_fifo_source_last = reader_cmd_fifo_fifo_out_last;
+assign reader_cmd_fifo_source_payload_slot = reader_cmd_fifo_fifo_out_payload_slot;
+assign reader_cmd_fifo_source_payload_length = reader_cmd_fifo_fifo_out_payload_length;
+assign reader_cmd_fifo_syncfifo_re = reader_cmd_fifo_source_ready;
+always @(*) begin
+	reader_cmd_fifo_wrport_adr <= 1'd0;
+	if (reader_cmd_fifo_replace) begin
+		reader_cmd_fifo_wrport_adr <= (reader_cmd_fifo_produce - 1'd1);
+	end else begin
+		reader_cmd_fifo_wrport_adr <= reader_cmd_fifo_produce;
+	end
+end
+assign reader_cmd_fifo_wrport_dat_w = reader_cmd_fifo_syncfifo_din;
+assign reader_cmd_fifo_wrport_we = (reader_cmd_fifo_syncfifo_we & (reader_cmd_fifo_syncfifo_writable | reader_cmd_fifo_replace));
+assign reader_cmd_fifo_do_read = (reader_cmd_fifo_syncfifo_readable & reader_cmd_fifo_syncfifo_re);
+assign reader_cmd_fifo_rdport_adr = reader_cmd_fifo_consume;
+assign reader_cmd_fifo_syncfifo_dout = reader_cmd_fifo_rdport_dat_r;
+assign reader_cmd_fifo_syncfifo_writable = (reader_cmd_fifo_level != 2'd2);
+assign reader_cmd_fifo_syncfifo_readable = (reader_cmd_fifo_level != 1'd0);
+always @(*) begin
+	reader_cmd_fifo_source_ready <= 1'd0;
+	reader_eventsourcepulse_trigger <= 1'd0;
+	subfragments_liteethmacsramreader_next_state <= 2'd0;
+	reader_counter_next_value <= 11'd0;
+	reader_counter_next_value_ce <= 1'd0;
+	reader_source_source_valid <= 1'd0;
+	reader_start <= 1'd0;
+	reader_source_source_last <= 1'd0;
+	reader_read_address <= 11'd0;
+	subfragments_liteethmacsramreader_next_state <= subfragments_liteethmacsramreader_state;
+	case (subfragments_liteethmacsramreader_state)
+		1'd1: begin
+			reader_source_source_valid <= 1'd1;
+			reader_source_source_last <= (reader_counter >= (reader_cmd_fifo_source_payload_length - 3'd4));
+			reader_read_address <= reader_counter;
+			if (reader_source_source_ready) begin
+				reader_read_address <= (reader_counter + 3'd4);
+				reader_counter_next_value <= (reader_counter + 3'd4);
+				reader_counter_next_value_ce <= 1'd1;
+				if (reader_source_source_last) begin
+					subfragments_liteethmacsramreader_next_state <= 2'd2;
+				end
+			end
+		end
+		2'd2: begin
+			reader_eventsourcepulse_trigger <= 1'd1;
+			reader_cmd_fifo_source_ready <= 1'd1;
+			subfragments_liteethmacsramreader_next_state <= 1'd0;
+		end
+		default: begin
+			reader_counter_next_value <= 1'd0;
+			reader_counter_next_value_ce <= 1'd1;
+			if (reader_cmd_fifo_source_valid) begin
+				reader_start <= 1'd1;
+				subfragments_liteethmacsramreader_next_state <= 1'd1;
+			end
+		end
+	endcase
+end
+assign ev_irq = (writer_irq | reader_irq);
+assign sram0_adr0 = sram0_bus_adr0[8:0];
+assign sram0_bus_dat_r0 = sram0_dat_r0;
+assign sram1_adr0 = sram1_bus_adr0[8:0];
+assign sram1_bus_dat_r0 = sram1_dat_r0;
+always @(*) begin
+	sram0_we <= 4'd0;
+	sram0_we[0] <= (((sram0_bus_cyc1 & sram0_bus_stb1) & sram0_bus_we1) & sram0_bus_sel1[0]);
+	sram0_we[1] <= (((sram0_bus_cyc1 & sram0_bus_stb1) & sram0_bus_we1) & sram0_bus_sel1[1]);
+	sram0_we[2] <= (((sram0_bus_cyc1 & sram0_bus_stb1) & sram0_bus_we1) & sram0_bus_sel1[2]);
+	sram0_we[3] <= (((sram0_bus_cyc1 & sram0_bus_stb1) & sram0_bus_we1) & sram0_bus_sel1[3]);
+end
+assign sram0_adr1 = sram0_bus_adr1[8:0];
+assign sram0_bus_dat_r1 = sram0_dat_r1;
+assign sram0_dat_w = sram0_bus_dat_w1;
+always @(*) begin
+	sram1_we <= 4'd0;
+	sram1_we[0] <= (((sram1_bus_cyc1 & sram1_bus_stb1) & sram1_bus_we1) & sram1_bus_sel1[0]);
+	sram1_we[1] <= (((sram1_bus_cyc1 & sram1_bus_stb1) & sram1_bus_we1) & sram1_bus_sel1[1]);
+	sram1_we[2] <= (((sram1_bus_cyc1 & sram1_bus_stb1) & sram1_bus_we1) & sram1_bus_sel1[2]);
+	sram1_we[3] <= (((sram1_bus_cyc1 & sram1_bus_stb1) & sram1_bus_we1) & sram1_bus_sel1[3]);
+end
+assign sram1_adr1 = sram1_bus_adr1[8:0];
+assign sram1_bus_dat_r1 = sram1_dat_r1;
+assign sram1_dat_w = sram1_bus_dat_w1;
+always @(*) begin
+	slave_sel <= 4'd0;
+	slave_sel[0] <= (bus_adr[10:9] == 1'd0);
+	slave_sel[1] <= (bus_adr[10:9] == 1'd1);
+	slave_sel[2] <= (bus_adr[10:9] == 2'd2);
+	slave_sel[3] <= (bus_adr[10:9] == 2'd3);
+end
+assign sram0_bus_adr0 = bus_adr;
+assign sram0_bus_dat_w0 = bus_dat_w;
+assign sram0_bus_sel0 = bus_sel;
+assign sram0_bus_stb0 = bus_stb;
+assign sram0_bus_we0 = bus_we;
+assign sram0_bus_cti0 = bus_cti;
+assign sram0_bus_bte0 = bus_bte;
+assign sram1_bus_adr0 = bus_adr;
+assign sram1_bus_dat_w0 = bus_dat_w;
+assign sram1_bus_sel0 = bus_sel;
+assign sram1_bus_stb0 = bus_stb;
+assign sram1_bus_we0 = bus_we;
+assign sram1_bus_cti0 = bus_cti;
+assign sram1_bus_bte0 = bus_bte;
+assign sram0_bus_adr1 = bus_adr;
+assign sram0_bus_dat_w1 = bus_dat_w;
+assign sram0_bus_sel1 = bus_sel;
+assign sram0_bus_stb1 = bus_stb;
+assign sram0_bus_we1 = bus_we;
+assign sram0_bus_cti1 = bus_cti;
+assign sram0_bus_bte1 = bus_bte;
+assign sram1_bus_adr1 = bus_adr;
+assign sram1_bus_dat_w1 = bus_dat_w;
+assign sram1_bus_sel1 = bus_sel;
+assign sram1_bus_stb1 = bus_stb;
+assign sram1_bus_we1 = bus_we;
+assign sram1_bus_cti1 = bus_cti;
+assign sram1_bus_bte1 = bus_bte;
+assign sram0_bus_cyc0 = (bus_cyc & slave_sel[0]);
+assign sram1_bus_cyc0 = (bus_cyc & slave_sel[1]);
+assign sram0_bus_cyc1 = (bus_cyc & slave_sel[2]);
+assign sram1_bus_cyc1 = (bus_cyc & slave_sel[3]);
+assign bus_ack = (((sram0_bus_ack0 | sram1_bus_ack0) | sram0_bus_ack1) | sram1_bus_ack1);
+assign bus_err = (((sram0_bus_err0 | sram1_bus_err0) | sram0_bus_err1) | sram1_bus_err1);
+assign bus_dat_r = (((({32{slave_sel_r[0]}} & sram0_bus_dat_r0) | ({32{slave_sel_r[1]}} & sram1_bus_dat_r0)) | ({32{slave_sel_r[2]}} & sram0_bus_dat_r1)) | ({32{slave_sel_r[3]}} & sram1_bus_dat_r1));
+always @(*) begin
+	maccore_maccore_we <= 1'd0;
+	maccore_maccore_dat_w <= 32'd0;
+	maccore_maccore_wishbone_ack <= 1'd0;
+	maccore_next_state <= 1'd0;
+	maccore_maccore_wishbone_dat_r <= 32'd0;
+	maccore_maccore_adr <= 14'd0;
+	maccore_next_state <= maccore_state;
+	case (maccore_state)
+		1'd1: begin
+			maccore_maccore_wishbone_ack <= 1'd1;
+			maccore_maccore_wishbone_dat_r <= maccore_maccore_dat_r;
+			maccore_next_state <= 1'd0;
+		end
+		default: begin
+			maccore_maccore_dat_w <= maccore_maccore_wishbone_dat_w;
+			if ((maccore_maccore_wishbone_cyc & maccore_maccore_wishbone_stb)) begin
+				maccore_maccore_adr <= maccore_maccore_wishbone_adr;
+				maccore_maccore_we <= (maccore_maccore_wishbone_we & (maccore_maccore_wishbone_sel != 1'd0));
+				maccore_next_state <= 1'd1;
+			end
+		end
+	endcase
+end
+assign maccore_shared_adr = array_muxed0;
+assign maccore_shared_dat_w = array_muxed1;
+assign maccore_shared_sel = array_muxed2;
+assign maccore_shared_cyc = array_muxed3;
+assign maccore_shared_stb = array_muxed4;
+assign maccore_shared_we = array_muxed5;
+assign maccore_shared_cti = array_muxed6;
+assign maccore_shared_bte = array_muxed7;
+assign wb_bus_dat_r = maccore_shared_dat_r;
+assign wb_bus_ack = (maccore_shared_ack & (maccore_grant == 1'd0));
+assign wb_bus_err = (maccore_shared_err & (maccore_grant == 1'd0));
+assign maccore_request = {wb_bus_cyc};
+assign maccore_grant = 1'd0;
+always @(*) begin
+	maccore_slave_sel <= 2'd0;
+	maccore_slave_sel[0] <= (maccore_shared_adr[29:11] == 4'd8);
+	maccore_slave_sel[1] <= (maccore_shared_adr[29:14] == 1'd0);
+end
+assign bus_adr = maccore_shared_adr;
+assign bus_dat_w = maccore_shared_dat_w;
+assign bus_sel = maccore_shared_sel;
+assign bus_stb = maccore_shared_stb;
+assign bus_we = maccore_shared_we;
+assign bus_cti = maccore_shared_cti;
+assign bus_bte = maccore_shared_bte;
+assign maccore_maccore_wishbone_adr = maccore_shared_adr;
+assign maccore_maccore_wishbone_dat_w = maccore_shared_dat_w;
+assign maccore_maccore_wishbone_sel = maccore_shared_sel;
+assign maccore_maccore_wishbone_stb = maccore_shared_stb;
+assign maccore_maccore_wishbone_we = maccore_shared_we;
+assign maccore_maccore_wishbone_cti = maccore_shared_cti;
+assign maccore_maccore_wishbone_bte = maccore_shared_bte;
+assign bus_cyc = (maccore_shared_cyc & maccore_slave_sel[0]);
+assign maccore_maccore_wishbone_cyc = (maccore_shared_cyc & maccore_slave_sel[1]);
+assign maccore_shared_err = (bus_err | maccore_maccore_wishbone_err);
+assign maccore_wait = ((maccore_shared_stb & maccore_shared_cyc) & (~maccore_shared_ack));
+always @(*) begin
+	maccore_error <= 1'd0;
+	maccore_shared_dat_r <= 32'd0;
+	maccore_shared_ack <= 1'd0;
+	maccore_shared_ack <= (bus_ack | maccore_maccore_wishbone_ack);
+	maccore_shared_dat_r <= (({32{maccore_slave_sel_r[0]}} & bus_dat_r) | ({32{maccore_slave_sel_r[1]}} & maccore_maccore_wishbone_dat_r));
+	if (maccore_done) begin
+		maccore_shared_dat_r <= 32'd4294967295;
+		maccore_shared_ack <= 1'd1;
+		maccore_error <= 1'd1;
+	end
+end
+assign maccore_done = (maccore_count == 1'd0);
+assign maccore_csrbank0_sel = (maccore_interface0_bank_bus_adr[13:9] == 1'd0);
+assign maccore_csrbank0_reset0_r = maccore_interface0_bank_bus_dat_w[1:0];
+always @(*) begin
+	maccore_csrbank0_reset0_re <= 1'd0;
+	maccore_csrbank0_reset0_we <= 1'd0;
+	if ((maccore_csrbank0_sel & (maccore_interface0_bank_bus_adr[8:0] == 1'd0))) begin
+		maccore_csrbank0_reset0_re <= maccore_interface0_bank_bus_we;
+		maccore_csrbank0_reset0_we <= (~maccore_interface0_bank_bus_we);
+	end
+end
+assign maccore_csrbank0_scratch0_r = maccore_interface0_bank_bus_dat_w[31:0];
+always @(*) begin
+	maccore_csrbank0_scratch0_re <= 1'd0;
+	maccore_csrbank0_scratch0_we <= 1'd0;
+	if ((maccore_csrbank0_sel & (maccore_interface0_bank_bus_adr[8:0] == 1'd1))) begin
+		maccore_csrbank0_scratch0_re <= maccore_interface0_bank_bus_we;
+		maccore_csrbank0_scratch0_we <= (~maccore_interface0_bank_bus_we);
+	end
+end
+assign maccore_csrbank0_bus_errors_r = maccore_interface0_bank_bus_dat_w[31:0];
+always @(*) begin
+	maccore_csrbank0_bus_errors_we <= 1'd0;
+	maccore_csrbank0_bus_errors_re <= 1'd0;
+	if ((maccore_csrbank0_sel & (maccore_interface0_bank_bus_adr[8:0] == 2'd2))) begin
+		maccore_csrbank0_bus_errors_re <= maccore_interface0_bank_bus_we;
+		maccore_csrbank0_bus_errors_we <= (~maccore_interface0_bank_bus_we);
+	end
+end
+always @(*) begin
+	maccore_maccore_soc_rst <= 1'd0;
+	if (maccore_maccore_reset_re) begin
+		maccore_maccore_soc_rst <= maccore_maccore_reset_storage[0];
+	end
+end
+assign maccore_maccore_cpu_rst = maccore_maccore_reset_storage[1];
+assign maccore_csrbank0_reset0_w = maccore_maccore_reset_storage[1:0];
+assign maccore_csrbank0_scratch0_w = maccore_maccore_scratch_storage[31:0];
+assign maccore_csrbank0_bus_errors_w = maccore_maccore_bus_errors_status[31:0];
+assign maccore_maccore_bus_errors_we = maccore_csrbank0_bus_errors_we;
+assign maccore_csrbank1_sel = (maccore_interface1_bank_bus_adr[13:9] == 2'd2);
+assign maccore_csrbank1_sram_writer_slot_r = maccore_interface1_bank_bus_dat_w[0];
+always @(*) begin
+	maccore_csrbank1_sram_writer_slot_we <= 1'd0;
+	maccore_csrbank1_sram_writer_slot_re <= 1'd0;
+	if ((maccore_csrbank1_sel & (maccore_interface1_bank_bus_adr[8:0] == 1'd0))) begin
+		maccore_csrbank1_sram_writer_slot_re <= maccore_interface1_bank_bus_we;
+		maccore_csrbank1_sram_writer_slot_we <= (~maccore_interface1_bank_bus_we);
+	end
+end
+assign maccore_csrbank1_sram_writer_length_r = maccore_interface1_bank_bus_dat_w[31:0];
+always @(*) begin
+	maccore_csrbank1_sram_writer_length_we <= 1'd0;
+	maccore_csrbank1_sram_writer_length_re <= 1'd0;
+	if ((maccore_csrbank1_sel & (maccore_interface1_bank_bus_adr[8:0] == 1'd1))) begin
+		maccore_csrbank1_sram_writer_length_re <= maccore_interface1_bank_bus_we;
+		maccore_csrbank1_sram_writer_length_we <= (~maccore_interface1_bank_bus_we);
+	end
+end
+assign maccore_csrbank1_sram_writer_errors_r = maccore_interface1_bank_bus_dat_w[31:0];
+always @(*) begin
+	maccore_csrbank1_sram_writer_errors_re <= 1'd0;
+	maccore_csrbank1_sram_writer_errors_we <= 1'd0;
+	if ((maccore_csrbank1_sel & (maccore_interface1_bank_bus_adr[8:0] == 2'd2))) begin
+		maccore_csrbank1_sram_writer_errors_re <= maccore_interface1_bank_bus_we;
+		maccore_csrbank1_sram_writer_errors_we <= (~maccore_interface1_bank_bus_we);
+	end
+end
+assign maccore_csrbank1_sram_writer_ev_status_r = maccore_interface1_bank_bus_dat_w[0];
+always @(*) begin
+	maccore_csrbank1_sram_writer_ev_status_re <= 1'd0;
+	maccore_csrbank1_sram_writer_ev_status_we <= 1'd0;
+	if ((maccore_csrbank1_sel & (maccore_interface1_bank_bus_adr[8:0] == 2'd3))) begin
+		maccore_csrbank1_sram_writer_ev_status_re <= maccore_interface1_bank_bus_we;
+		maccore_csrbank1_sram_writer_ev_status_we <= (~maccore_interface1_bank_bus_we);
+	end
+end
+assign maccore_csrbank1_sram_writer_ev_pending_r = maccore_interface1_bank_bus_dat_w[0];
+always @(*) begin
+	maccore_csrbank1_sram_writer_ev_pending_we <= 1'd0;
+	maccore_csrbank1_sram_writer_ev_pending_re <= 1'd0;
+	if ((maccore_csrbank1_sel & (maccore_interface1_bank_bus_adr[8:0] == 3'd4))) begin
+		maccore_csrbank1_sram_writer_ev_pending_re <= maccore_interface1_bank_bus_we;
+		maccore_csrbank1_sram_writer_ev_pending_we <= (~maccore_interface1_bank_bus_we);
+	end
+end
+assign maccore_csrbank1_sram_writer_ev_enable0_r = maccore_interface1_bank_bus_dat_w[0];
+always @(*) begin
+	maccore_csrbank1_sram_writer_ev_enable0_we <= 1'd0;
+	maccore_csrbank1_sram_writer_ev_enable0_re <= 1'd0;
+	if ((maccore_csrbank1_sel & (maccore_interface1_bank_bus_adr[8:0] == 3'd5))) begin
+		maccore_csrbank1_sram_writer_ev_enable0_re <= maccore_interface1_bank_bus_we;
+		maccore_csrbank1_sram_writer_ev_enable0_we <= (~maccore_interface1_bank_bus_we);
+	end
+end
+assign reader_start_start_r = maccore_interface1_bank_bus_dat_w[0];
+always @(*) begin
+	reader_start_start_re <= 1'd0;
+	reader_start_start_we <= 1'd0;
+	if ((maccore_csrbank1_sel & (maccore_interface1_bank_bus_adr[8:0] == 3'd6))) begin
+		reader_start_start_re <= maccore_interface1_bank_bus_we;
+		reader_start_start_we <= (~maccore_interface1_bank_bus_we);
+	end
+end
+assign maccore_csrbank1_sram_reader_ready_r = maccore_interface1_bank_bus_dat_w[0];
+always @(*) begin
+	maccore_csrbank1_sram_reader_ready_re <= 1'd0;
+	maccore_csrbank1_sram_reader_ready_we <= 1'd0;
+	if ((maccore_csrbank1_sel & (maccore_interface1_bank_bus_adr[8:0] == 3'd7))) begin
+		maccore_csrbank1_sram_reader_ready_re <= maccore_interface1_bank_bus_we;
+		maccore_csrbank1_sram_reader_ready_we <= (~maccore_interface1_bank_bus_we);
+	end
+end
+assign maccore_csrbank1_sram_reader_level_r = maccore_interface1_bank_bus_dat_w[1:0];
+always @(*) begin
+	maccore_csrbank1_sram_reader_level_we <= 1'd0;
+	maccore_csrbank1_sram_reader_level_re <= 1'd0;
+	if ((maccore_csrbank1_sel & (maccore_interface1_bank_bus_adr[8:0] == 4'd8))) begin
+		maccore_csrbank1_sram_reader_level_re <= maccore_interface1_bank_bus_we;
+		maccore_csrbank1_sram_reader_level_we <= (~maccore_interface1_bank_bus_we);
+	end
+end
+assign maccore_csrbank1_sram_reader_slot0_r = maccore_interface1_bank_bus_dat_w[0];
+always @(*) begin
+	maccore_csrbank1_sram_reader_slot0_we <= 1'd0;
+	maccore_csrbank1_sram_reader_slot0_re <= 1'd0;
+	if ((maccore_csrbank1_sel & (maccore_interface1_bank_bus_adr[8:0] == 4'd9))) begin
+		maccore_csrbank1_sram_reader_slot0_re <= maccore_interface1_bank_bus_we;
+		maccore_csrbank1_sram_reader_slot0_we <= (~maccore_interface1_bank_bus_we);
+	end
+end
+assign maccore_csrbank1_sram_reader_length0_r = maccore_interface1_bank_bus_dat_w[10:0];
+always @(*) begin
+	maccore_csrbank1_sram_reader_length0_re <= 1'd0;
+	maccore_csrbank1_sram_reader_length0_we <= 1'd0;
+	if ((maccore_csrbank1_sel & (maccore_interface1_bank_bus_adr[8:0] == 4'd10))) begin
+		maccore_csrbank1_sram_reader_length0_re <= maccore_interface1_bank_bus_we;
+		maccore_csrbank1_sram_reader_length0_we <= (~maccore_interface1_bank_bus_we);
+	end
+end
+assign maccore_csrbank1_sram_reader_ev_status_r = maccore_interface1_bank_bus_dat_w[0];
+always @(*) begin
+	maccore_csrbank1_sram_reader_ev_status_we <= 1'd0;
+	maccore_csrbank1_sram_reader_ev_status_re <= 1'd0;
+	if ((maccore_csrbank1_sel & (maccore_interface1_bank_bus_adr[8:0] == 4'd11))) begin
+		maccore_csrbank1_sram_reader_ev_status_re <= maccore_interface1_bank_bus_we;
+		maccore_csrbank1_sram_reader_ev_status_we <= (~maccore_interface1_bank_bus_we);
+	end
+end
+assign maccore_csrbank1_sram_reader_ev_pending_r = maccore_interface1_bank_bus_dat_w[0];
+always @(*) begin
+	maccore_csrbank1_sram_reader_ev_pending_we <= 1'd0;
+	maccore_csrbank1_sram_reader_ev_pending_re <= 1'd0;
+	if ((maccore_csrbank1_sel & (maccore_interface1_bank_bus_adr[8:0] == 4'd12))) begin
+		maccore_csrbank1_sram_reader_ev_pending_re <= maccore_interface1_bank_bus_we;
+		maccore_csrbank1_sram_reader_ev_pending_we <= (~maccore_interface1_bank_bus_we);
+	end
+end
+assign maccore_csrbank1_sram_reader_ev_enable0_r = maccore_interface1_bank_bus_dat_w[0];
+always @(*) begin
+	maccore_csrbank1_sram_reader_ev_enable0_re <= 1'd0;
+	maccore_csrbank1_sram_reader_ev_enable0_we <= 1'd0;
+	if ((maccore_csrbank1_sel & (maccore_interface1_bank_bus_adr[8:0] == 4'd13))) begin
+		maccore_csrbank1_sram_reader_ev_enable0_re <= maccore_interface1_bank_bus_we;
+		maccore_csrbank1_sram_reader_ev_enable0_we <= (~maccore_interface1_bank_bus_we);
+	end
+end
+assign maccore_csrbank1_preamble_crc_r = maccore_interface1_bank_bus_dat_w[0];
+always @(*) begin
+	maccore_csrbank1_preamble_crc_we <= 1'd0;
+	maccore_csrbank1_preamble_crc_re <= 1'd0;
+	if ((maccore_csrbank1_sel & (maccore_interface1_bank_bus_adr[8:0] == 4'd14))) begin
+		maccore_csrbank1_preamble_crc_re <= maccore_interface1_bank_bus_we;
+		maccore_csrbank1_preamble_crc_we <= (~maccore_interface1_bank_bus_we);
+	end
+end
+assign maccore_csrbank1_preamble_errors_r = maccore_interface1_bank_bus_dat_w[31:0];
+always @(*) begin
+	maccore_csrbank1_preamble_errors_we <= 1'd0;
+	maccore_csrbank1_preamble_errors_re <= 1'd0;
+	if ((maccore_csrbank1_sel & (maccore_interface1_bank_bus_adr[8:0] == 4'd15))) begin
+		maccore_csrbank1_preamble_errors_re <= maccore_interface1_bank_bus_we;
+		maccore_csrbank1_preamble_errors_we <= (~maccore_interface1_bank_bus_we);
+	end
+end
+assign maccore_csrbank1_crc_errors_r = maccore_interface1_bank_bus_dat_w[31:0];
+always @(*) begin
+	maccore_csrbank1_crc_errors_re <= 1'd0;
+	maccore_csrbank1_crc_errors_we <= 1'd0;
+	if ((maccore_csrbank1_sel & (maccore_interface1_bank_bus_adr[8:0] == 5'd16))) begin
+		maccore_csrbank1_crc_errors_re <= maccore_interface1_bank_bus_we;
+		maccore_csrbank1_crc_errors_we <= (~maccore_interface1_bank_bus_we);
+	end
+end
+assign maccore_csrbank1_sram_writer_slot_w = writer_slot_status;
+assign writer_slot_we = maccore_csrbank1_sram_writer_slot_we;
+assign maccore_csrbank1_sram_writer_length_w = writer_length_status[31:0];
+assign writer_length_we = maccore_csrbank1_sram_writer_length_we;
+assign maccore_csrbank1_sram_writer_errors_w = writer_errors_status[31:0];
+assign writer_errors_we = maccore_csrbank1_sram_writer_errors_we;
+assign writer_status_status = writer_available0;
+assign maccore_csrbank1_sram_writer_ev_status_w = writer_status_status;
+assign writer_status_we = maccore_csrbank1_sram_writer_ev_status_we;
+assign writer_pending_status = writer_available1;
+assign maccore_csrbank1_sram_writer_ev_pending_w = writer_pending_status;
+assign writer_pending_we = maccore_csrbank1_sram_writer_ev_pending_we;
+assign writer_available2 = writer_enable_storage;
+assign maccore_csrbank1_sram_writer_ev_enable0_w = writer_enable_storage;
+assign maccore_csrbank1_sram_reader_ready_w = reader_ready_status;
+assign reader_ready_we = maccore_csrbank1_sram_reader_ready_we;
+assign maccore_csrbank1_sram_reader_level_w = reader_level_status[1:0];
+assign reader_level_we = maccore_csrbank1_sram_reader_level_we;
+assign maccore_csrbank1_sram_reader_slot0_w = reader_slot_storage;
+assign maccore_csrbank1_sram_reader_length0_w = reader_length_storage[10:0];
+assign reader_status_status = reader_event00;
+assign maccore_csrbank1_sram_reader_ev_status_w = reader_status_status;
+assign reader_status_we = maccore_csrbank1_sram_reader_ev_status_we;
+assign reader_pending_status = reader_event01;
+assign maccore_csrbank1_sram_reader_ev_pending_w = reader_pending_status;
+assign reader_pending_we = maccore_csrbank1_sram_reader_ev_pending_we;
+assign reader_event02 = reader_enable_storage;
+assign maccore_csrbank1_sram_reader_ev_enable0_w = reader_enable_storage;
+assign maccore_csrbank1_preamble_crc_w = preamble_crc_status;
+assign preamble_crc_we = maccore_csrbank1_preamble_crc_we;
+assign maccore_csrbank1_preamble_errors_w = preamble_errors_status[31:0];
+assign preamble_errors_we = maccore_csrbank1_preamble_errors_we;
+assign maccore_csrbank1_crc_errors_w = crc_errors_status[31:0];
+assign crc_errors_we = maccore_csrbank1_crc_errors_we;
+assign maccore_csrbank2_sel = (maccore_interface2_bank_bus_adr[13:9] == 1'd1);
+assign maccore_csrbank2_mode_detection_mode_r = maccore_interface2_bank_bus_dat_w[0];
+always @(*) begin
+	maccore_csrbank2_mode_detection_mode_re <= 1'd0;
+	maccore_csrbank2_mode_detection_mode_we <= 1'd0;
+	if ((maccore_csrbank2_sel & (maccore_interface2_bank_bus_adr[8:0] == 1'd0))) begin
+		maccore_csrbank2_mode_detection_mode_re <= maccore_interface2_bank_bus_we;
+		maccore_csrbank2_mode_detection_mode_we <= (~maccore_interface2_bank_bus_we);
+	end
+end
+assign maccore_csrbank2_crg_reset0_r = maccore_interface2_bank_bus_dat_w[0];
+always @(*) begin
+	maccore_csrbank2_crg_reset0_re <= 1'd0;
+	maccore_csrbank2_crg_reset0_we <= 1'd0;
+	if ((maccore_csrbank2_sel & (maccore_interface2_bank_bus_adr[8:0] == 1'd1))) begin
+		maccore_csrbank2_crg_reset0_re <= maccore_interface2_bank_bus_we;
+		maccore_csrbank2_crg_reset0_we <= (~maccore_interface2_bank_bus_we);
+	end
+end
+assign maccore_csrbank2_mdio_w0_r = maccore_interface2_bank_bus_dat_w[2:0];
+always @(*) begin
+	maccore_csrbank2_mdio_w0_we <= 1'd0;
+	maccore_csrbank2_mdio_w0_re <= 1'd0;
+	if ((maccore_csrbank2_sel & (maccore_interface2_bank_bus_adr[8:0] == 2'd2))) begin
+		maccore_csrbank2_mdio_w0_re <= maccore_interface2_bank_bus_we;
+		maccore_csrbank2_mdio_w0_we <= (~maccore_interface2_bank_bus_we);
+	end
+end
+assign maccore_csrbank2_mdio_r_r = maccore_interface2_bank_bus_dat_w[0];
+always @(*) begin
+	maccore_csrbank2_mdio_r_re <= 1'd0;
+	maccore_csrbank2_mdio_r_we <= 1'd0;
+	if ((maccore_csrbank2_sel & (maccore_interface2_bank_bus_adr[8:0] == 2'd3))) begin
+		maccore_csrbank2_mdio_r_re <= maccore_interface2_bank_bus_we;
+		maccore_csrbank2_mdio_r_we <= (~maccore_interface2_bank_bus_we);
+	end
+end
+assign maccore_csrbank2_mode_detection_mode_w = maccore_ethphy_mode_status;
+assign maccore_ethphy_mode_we = maccore_csrbank2_mode_detection_mode_we;
+assign maccore_csrbank2_crg_reset0_w = maccore_ethphy_reset_storage;
+assign maccore_ethphy_mdc = maccore_ethphy__w_storage[0];
+assign maccore_ethphy_oe = maccore_ethphy__w_storage[1];
+assign maccore_ethphy_w = maccore_ethphy__w_storage[2];
+assign maccore_csrbank2_mdio_w0_w = maccore_ethphy__w_storage[2:0];
+assign maccore_csrbank2_mdio_r_w = maccore_ethphy__r_status;
+assign maccore_ethphy__r_we = maccore_csrbank2_mdio_r_we;
+assign maccore_csr_interconnect_adr = maccore_maccore_adr;
+assign maccore_csr_interconnect_we = maccore_maccore_we;
+assign maccore_csr_interconnect_dat_w = maccore_maccore_dat_w;
+assign maccore_maccore_dat_r = maccore_csr_interconnect_dat_r;
+assign maccore_interface0_bank_bus_adr = maccore_csr_interconnect_adr;
+assign maccore_interface1_bank_bus_adr = maccore_csr_interconnect_adr;
+assign maccore_interface2_bank_bus_adr = maccore_csr_interconnect_adr;
+assign maccore_interface0_bank_bus_we = maccore_csr_interconnect_we;
+assign maccore_interface1_bank_bus_we = maccore_csr_interconnect_we;
+assign maccore_interface2_bank_bus_we = maccore_csr_interconnect_we;
+assign maccore_interface0_bank_bus_dat_w = maccore_csr_interconnect_dat_w;
+assign maccore_interface1_bank_bus_dat_w = maccore_csr_interconnect_dat_w;
+assign maccore_interface2_bank_bus_dat_w = maccore_csr_interconnect_dat_w;
+assign maccore_csr_interconnect_dat_r = ((maccore_interface0_bank_bus_dat_r | maccore_interface1_bank_bus_dat_r) | maccore_interface2_bank_bus_dat_r);
+always @(*) begin
+	array_muxed0 <= 30'd0;
+	case (maccore_grant)
+		default: begin
+			array_muxed0 <= wb_bus_adr;
+		end
+	endcase
+end
+always @(*) begin
+	array_muxed1 <= 32'd0;
+	case (maccore_grant)
+		default: begin
+			array_muxed1 <= wb_bus_dat_w;
+		end
+	endcase
+end
+always @(*) begin
+	array_muxed2 <= 4'd0;
+	case (maccore_grant)
+		default: begin
+			array_muxed2 <= wb_bus_sel;
+		end
+	endcase
+end
+always @(*) begin
+	array_muxed3 <= 1'd0;
+	case (maccore_grant)
+		default: begin
+			array_muxed3 <= wb_bus_cyc;
+		end
+	endcase
+end
+always @(*) begin
+	array_muxed4 <= 1'd0;
+	case (maccore_grant)
+		default: begin
+			array_muxed4 <= wb_bus_stb;
+		end
+	endcase
+end
+always @(*) begin
+	array_muxed5 <= 1'd0;
+	case (maccore_grant)
+		default: begin
+			array_muxed5 <= wb_bus_we;
+		end
+	endcase
+end
+always @(*) begin
+	array_muxed6 <= 3'd0;
+	case (maccore_grant)
+		default: begin
+			array_muxed6 <= wb_bus_cti;
+		end
+	endcase
+end
+always @(*) begin
+	array_muxed7 <= 2'd0;
+	case (maccore_grant)
+		default: begin
+			array_muxed7 <= wb_bus_bte;
+		end
+	endcase
+end
+assign maccore_ethphy_toggle_o = xilinxmultiregimpl0_regs1;
+always @(*) begin
+	maccore_ethphy__r_status <= 1'd0;
+	maccore_ethphy__r_status <= maccore_ethphy_r;
+	maccore_ethphy__r_status <= xilinxmultiregimpl1_regs1;
+end
+assign ps_preamble_error_toggle_o = xilinxmultiregimpl2_regs1;
+assign ps_crc_error_toggle_o = xilinxmultiregimpl3_regs1;
+assign tx_cdc_cdc_produce_rdomain = xilinxmultiregimpl4_regs1;
+assign tx_cdc_cdc_consume_wdomain = xilinxmultiregimpl5_regs1;
+assign rx_cdc_cdc_produce_rdomain = xilinxmultiregimpl6_regs1;
+assign rx_cdc_cdc_consume_wdomain = xilinxmultiregimpl7_regs1;
+
+always @(posedge eth_rx_clk) begin
+	maccore_ethphy_eth_counter <= (maccore_ethphy_eth_counter + 1'd1);
+	if (maccore_ethphy_i) begin
+		maccore_ethphy_toggle_i <= (~maccore_ethphy_toggle_i);
+	end
+	maccore_ethphy_liteethphygmiimiirx_pads_d_rx_dv <= gmii_eth_rx_dv;
+	maccore_ethphy_liteethphygmiimiirx_pads_d_rx_data <= gmii_eth_rx_data;
+	maccore_ethphy_liteethphygmiimiirx_gmii_rx_dv_d <= maccore_ethphy_liteethphygmiimiirx_pads_d_rx_dv;
+	maccore_ethphy_liteethphygmiimiirx_gmii_rx_source_valid <= maccore_ethphy_liteethphygmiimiirx_pads_d_rx_dv;
+	maccore_ethphy_liteethphygmiimiirx_gmii_rx_source_payload_data <= maccore_ethphy_liteethphygmiimiirx_pads_d_rx_data;
+	maccore_ethphy_liteethphygmiimiirx_converter_reset <= (~maccore_ethphy_liteethphygmiimiirx_pads_d_rx_dv);
+	maccore_ethphy_liteethphygmiimiirx_converter_sink_valid <= 1'd1;
+	maccore_ethphy_liteethphygmiimiirx_converter_sink_payload_data <= maccore_ethphy_liteethphygmiimiirx_pads_d_rx_data;
+	if (maccore_ethphy_liteethphygmiimiirx_converter_converter_source_ready) begin
+		maccore_ethphy_liteethphygmiimiirx_converter_converter_strobe_all <= 1'd0;
+	end
+	if (maccore_ethphy_liteethphygmiimiirx_converter_converter_load_part) begin
+		if (((maccore_ethphy_liteethphygmiimiirx_converter_converter_demux == 1'd1) | maccore_ethphy_liteethphygmiimiirx_converter_converter_sink_last)) begin
+			maccore_ethphy_liteethphygmiimiirx_converter_converter_demux <= 1'd0;
+			maccore_ethphy_liteethphygmiimiirx_converter_converter_strobe_all <= 1'd1;
+		end else begin
+			maccore_ethphy_liteethphygmiimiirx_converter_converter_demux <= (maccore_ethphy_liteethphygmiimiirx_converter_converter_demux + 1'd1);
+		end
+	end
+	if ((maccore_ethphy_liteethphygmiimiirx_converter_converter_source_valid & maccore_ethphy_liteethphygmiimiirx_converter_converter_source_ready)) begin
+		if ((maccore_ethphy_liteethphygmiimiirx_converter_converter_sink_valid & maccore_ethphy_liteethphygmiimiirx_converter_converter_sink_ready)) begin
+			maccore_ethphy_liteethphygmiimiirx_converter_converter_source_first <= maccore_ethphy_liteethphygmiimiirx_converter_converter_sink_first;
+			maccore_ethphy_liteethphygmiimiirx_converter_converter_source_last <= maccore_ethphy_liteethphygmiimiirx_converter_converter_sink_last;
+		end else begin
+			maccore_ethphy_liteethphygmiimiirx_converter_converter_source_first <= 1'd0;
+			maccore_ethphy_liteethphygmiimiirx_converter_converter_source_last <= 1'd0;
+		end
+	end else begin
+		if ((maccore_ethphy_liteethphygmiimiirx_converter_converter_sink_valid & maccore_ethphy_liteethphygmiimiirx_converter_converter_sink_ready)) begin
+			maccore_ethphy_liteethphygmiimiirx_converter_converter_source_first <= (maccore_ethphy_liteethphygmiimiirx_converter_converter_sink_first | maccore_ethphy_liteethphygmiimiirx_converter_converter_source_first);
+			maccore_ethphy_liteethphygmiimiirx_converter_converter_source_last <= (maccore_ethphy_liteethphygmiimiirx_converter_converter_sink_last | maccore_ethphy_liteethphygmiimiirx_converter_converter_source_last);
+		end
+	end
+	if (maccore_ethphy_liteethphygmiimiirx_converter_converter_load_part) begin
+		case (maccore_ethphy_liteethphygmiimiirx_converter_converter_demux)
+			1'd0: begin
+				maccore_ethphy_liteethphygmiimiirx_converter_converter_source_payload_data[3:0] <= maccore_ethphy_liteethphygmiimiirx_converter_converter_sink_payload_data;
+			end
+			1'd1: begin
+				maccore_ethphy_liteethphygmiimiirx_converter_converter_source_payload_data[7:4] <= maccore_ethphy_liteethphygmiimiirx_converter_converter_sink_payload_data;
+			end
+		endcase
+	end
+	if (maccore_ethphy_liteethphygmiimiirx_converter_converter_load_part) begin
+		maccore_ethphy_liteethphygmiimiirx_converter_converter_source_payload_valid_token_count <= (maccore_ethphy_liteethphygmiimiirx_converter_converter_demux + 1'd1);
+	end
+	if (maccore_ethphy_liteethphygmiimiirx_converter_reset) begin
+		maccore_ethphy_liteethphygmiimiirx_converter_converter_source_payload_data <= 8'd0;
+		maccore_ethphy_liteethphygmiimiirx_converter_converter_source_payload_valid_token_count <= 2'd0;
+		maccore_ethphy_liteethphygmiimiirx_converter_converter_demux <= 1'd0;
+		maccore_ethphy_liteethphygmiimiirx_converter_converter_strobe_all <= 1'd0;
+	end
+	subfragments_liteethmacpreamblechecker_state <= subfragments_liteethmacpreamblechecker_next_state;
+	if (liteethmaccrc32checker_crc_ce) begin
+		liteethmaccrc32checker_crc_reg <= liteethmaccrc32checker_crc_next;
+	end
+	if (liteethmaccrc32checker_crc_reset) begin
+		liteethmaccrc32checker_crc_reg <= 32'd4294967295;
+	end
+	if (((liteethmaccrc32checker_syncfifo_syncfifo_we & liteethmaccrc32checker_syncfifo_syncfifo_writable) & (~liteethmaccrc32checker_syncfifo_replace))) begin
+		if ((liteethmaccrc32checker_syncfifo_produce == 3'd4)) begin
+			liteethmaccrc32checker_syncfifo_produce <= 1'd0;
+		end else begin
+			liteethmaccrc32checker_syncfifo_produce <= (liteethmaccrc32checker_syncfifo_produce + 1'd1);
+		end
+	end
+	if (liteethmaccrc32checker_syncfifo_do_read) begin
+		if ((liteethmaccrc32checker_syncfifo_consume == 3'd4)) begin
+			liteethmaccrc32checker_syncfifo_consume <= 1'd0;
+		end else begin
+			liteethmaccrc32checker_syncfifo_consume <= (liteethmaccrc32checker_syncfifo_consume + 1'd1);
+		end
+	end
+	if (((liteethmaccrc32checker_syncfifo_syncfifo_we & liteethmaccrc32checker_syncfifo_syncfifo_writable) & (~liteethmaccrc32checker_syncfifo_replace))) begin
+		if ((~liteethmaccrc32checker_syncfifo_do_read)) begin
+			liteethmaccrc32checker_syncfifo_level <= (liteethmaccrc32checker_syncfifo_level + 1'd1);
+		end
+	end else begin
+		if (liteethmaccrc32checker_syncfifo_do_read) begin
+			liteethmaccrc32checker_syncfifo_level <= (liteethmaccrc32checker_syncfifo_level - 1'd1);
+		end
+	end
+	if (liteethmaccrc32checker_fifo_reset) begin
+		liteethmaccrc32checker_syncfifo_level <= 3'd0;
+		liteethmaccrc32checker_syncfifo_produce <= 3'd0;
+		liteethmaccrc32checker_syncfifo_consume <= 3'd0;
+	end
+	subfragments_liteethmaccrc32checker_state <= subfragments_liteethmaccrc32checker_next_state;
+	if (((~crc32_checker_source_valid) | crc32_checker_source_ready)) begin
+		crc32_checker_source_valid <= crc32_checker_sink_valid;
+		crc32_checker_source_first <= crc32_checker_sink_first;
+		crc32_checker_source_last <= crc32_checker_sink_last;
+		crc32_checker_source_payload_data <= crc32_checker_sink_payload_data;
+		crc32_checker_source_payload_last_be <= crc32_checker_sink_payload_last_be;
+		crc32_checker_source_payload_error <= crc32_checker_sink_payload_error;
+	end
+	if (ps_preamble_error_i) begin
+		ps_preamble_error_toggle_i <= (~ps_preamble_error_toggle_i);
+	end
+	if (ps_crc_error_i) begin
+		ps_crc_error_toggle_i <= (~ps_crc_error_toggle_i);
+	end
+	if (rx_converter_converter_source_ready) begin
+		rx_converter_converter_strobe_all <= 1'd0;
+	end
+	if (rx_converter_converter_load_part) begin
+		if (((rx_converter_converter_demux == 2'd3) | rx_converter_converter_sink_last)) begin
+			rx_converter_converter_demux <= 1'd0;
+			rx_converter_converter_strobe_all <= 1'd1;
+		end else begin
+			rx_converter_converter_demux <= (rx_converter_converter_demux + 1'd1);
+		end
+	end
+	if ((rx_converter_converter_source_valid & rx_converter_converter_source_ready)) begin
+		if ((rx_converter_converter_sink_valid & rx_converter_converter_sink_ready)) begin
+			rx_converter_converter_source_first <= rx_converter_converter_sink_first;
+			rx_converter_converter_source_last <= rx_converter_converter_sink_last;
+		end else begin
+			rx_converter_converter_source_first <= 1'd0;
+			rx_converter_converter_source_last <= 1'd0;
+		end
+	end else begin
+		if ((rx_converter_converter_sink_valid & rx_converter_converter_sink_ready)) begin
+			rx_converter_converter_source_first <= (rx_converter_converter_sink_first | rx_converter_converter_source_first);
+			rx_converter_converter_source_last <= (rx_converter_converter_sink_last | rx_converter_converter_source_last);
+		end
+	end
+	if (rx_converter_converter_load_part) begin
+		case (rx_converter_converter_demux)
+			1'd0: begin
+				rx_converter_converter_source_payload_data[9:0] <= rx_converter_converter_sink_payload_data;
+			end
+			1'd1: begin
+				rx_converter_converter_source_payload_data[19:10] <= rx_converter_converter_sink_payload_data;
+			end
+			2'd2: begin
+				rx_converter_converter_source_payload_data[29:20] <= rx_converter_converter_sink_payload_data;
+			end
+			2'd3: begin
+				rx_converter_converter_source_payload_data[39:30] <= rx_converter_converter_sink_payload_data;
+			end
+		endcase
+	end
+	if (rx_converter_converter_load_part) begin
+		rx_converter_converter_source_payload_valid_token_count <= (rx_converter_converter_demux + 1'd1);
+	end
+	rx_cdc_cdc_graycounter0_q_binary <= rx_cdc_cdc_graycounter0_q_next_binary;
+	rx_cdc_cdc_graycounter0_q <= rx_cdc_cdc_graycounter0_q_next;
+	if (eth_rx_rst) begin
+		maccore_ethphy_liteethphygmiimiirx_gmii_rx_source_valid <= 1'd0;
+		maccore_ethphy_liteethphygmiimiirx_gmii_rx_source_payload_data <= 8'd0;
+		maccore_ethphy_liteethphygmiimiirx_gmii_rx_dv_d <= 1'd0;
+		maccore_ethphy_liteethphygmiimiirx_converter_sink_valid <= 1'd0;
+		maccore_ethphy_liteethphygmiimiirx_converter_sink_payload_data <= 4'd0;
+		maccore_ethphy_liteethphygmiimiirx_converter_converter_source_payload_data <= 8'd0;
+		maccore_ethphy_liteethphygmiimiirx_converter_converter_source_payload_valid_token_count <= 2'd0;
+		maccore_ethphy_liteethphygmiimiirx_converter_converter_demux <= 1'd0;
+		maccore_ethphy_liteethphygmiimiirx_converter_converter_strobe_all <= 1'd0;
+		maccore_ethphy_liteethphygmiimiirx_converter_reset <= 1'd0;
+		liteethmaccrc32checker_crc_reg <= 32'd4294967295;
+		liteethmaccrc32checker_syncfifo_level <= 3'd0;
+		liteethmaccrc32checker_syncfifo_produce <= 3'd0;
+		liteethmaccrc32checker_syncfifo_consume <= 3'd0;
+		crc32_checker_source_valid <= 1'd0;
+		crc32_checker_source_payload_data <= 8'd0;
+		crc32_checker_source_payload_last_be <= 1'd0;
+		crc32_checker_source_payload_error <= 1'd0;
+		rx_converter_converter_source_payload_data <= 40'd0;
+		rx_converter_converter_source_payload_valid_token_count <= 3'd0;
+		rx_converter_converter_demux <= 2'd0;
+		rx_converter_converter_strobe_all <= 1'd0;
+		rx_cdc_cdc_graycounter0_q <= 6'd0;
+		rx_cdc_cdc_graycounter0_q_binary <= 6'd0;
+		subfragments_liteethmacpreamblechecker_state <= 1'd0;
+		subfragments_liteethmaccrc32checker_state <= 2'd0;
+	end
+	xilinxmultiregimpl7_regs0 <= rx_cdc_cdc_graycounter1_q;
+	xilinxmultiregimpl7_regs1 <= xilinxmultiregimpl7_regs0;
+end
+
+always @(posedge eth_tx_clk) begin
+	if ((maccore_ethphy_mode0 == 1'd1)) begin
+		gmii_eth_tx_en <= maccore_ethphy_liteethphygmiimiitx_mii_tx_pads_tx_en;
+		gmii_eth_tx_data <= maccore_ethphy_liteethphygmiimiitx_mii_tx_pads_tx_data;
+	end else begin
+		gmii_eth_tx_en <= maccore_ethphy_liteethphygmiimiitx_gmii_tx_pads_tx_en;
+		gmii_eth_tx_data <= maccore_ethphy_liteethphygmiimiitx_gmii_tx_pads_tx_data;
+	end
+	maccore_ethphy_liteethphygmiimiitx_gmii_tx_pads_tx_er <= 1'd0;
+	maccore_ethphy_liteethphygmiimiitx_gmii_tx_pads_tx_en <= maccore_ethphy_liteethphygmiimiitx_gmii_tx_sink_valid;
+	maccore_ethphy_liteethphygmiimiitx_gmii_tx_pads_tx_data <= maccore_ethphy_liteethphygmiimiitx_gmii_tx_sink_payload_data;
+	maccore_ethphy_liteethphygmiimiitx_gmii_tx_sink_ready <= 1'd1;
+	maccore_ethphy_liteethphygmiimiitx_mii_tx_pads_tx_er <= 1'd0;
+	maccore_ethphy_liteethphygmiimiitx_mii_tx_pads_tx_en <= maccore_ethphy_liteethphygmiimiitx_converter_source_valid;
+	maccore_ethphy_liteethphygmiimiitx_mii_tx_pads_tx_data <= maccore_ethphy_liteethphygmiimiitx_converter_source_payload_data;
+	if ((maccore_ethphy_liteethphygmiimiitx_converter_converter_source_valid & maccore_ethphy_liteethphygmiimiitx_converter_converter_source_ready)) begin
+		if (maccore_ethphy_liteethphygmiimiitx_converter_converter_last) begin
+			maccore_ethphy_liteethphygmiimiitx_converter_converter_mux <= 1'd0;
+		end else begin
+			maccore_ethphy_liteethphygmiimiitx_converter_converter_mux <= (maccore_ethphy_liteethphygmiimiitx_converter_converter_mux + 1'd1);
+		end
+	end
+	subfragments_liteethmacgap_state <= subfragments_liteethmacgap_next_state;
+	if (tx_gap_inserter_counter_liteethmacgap_next_value_ce) begin
+		tx_gap_inserter_counter <= tx_gap_inserter_counter_liteethmacgap_next_value;
+	end
+	subfragments_liteethmacpreambleinserter_state <= subfragments_liteethmacpreambleinserter_next_state;
+	if (preamble_inserter_count_liteethmacpreambleinserter_next_value_ce) begin
+		preamble_inserter_count <= preamble_inserter_count_liteethmacpreambleinserter_next_value;
+	end
+	if (liteethmaccrc32inserter_is_ongoing0) begin
+		liteethmaccrc32inserter_cnt <= 2'd3;
+	end else begin
+		if ((liteethmaccrc32inserter_is_ongoing1 & (~liteethmaccrc32inserter_cnt_done))) begin
+			liteethmaccrc32inserter_cnt <= (liteethmaccrc32inserter_cnt - liteethmaccrc32inserter_source_ready);
+		end
+	end
+	if (liteethmaccrc32inserter_ce) begin
+		liteethmaccrc32inserter_reg <= liteethmaccrc32inserter_next;
+	end
+	if (liteethmaccrc32inserter_reset) begin
+		liteethmaccrc32inserter_reg <= 32'd4294967295;
+	end
+	subfragments_liteethmaccrc32inserter_state <= subfragments_liteethmaccrc32inserter_next_state;
+	if (((~crc32_inserter_source_valid) | crc32_inserter_source_ready)) begin
+		crc32_inserter_source_valid <= crc32_inserter_sink_valid;
+		crc32_inserter_source_first <= crc32_inserter_sink_first;
+		crc32_inserter_source_last <= crc32_inserter_sink_last;
+		crc32_inserter_source_payload_data <= crc32_inserter_sink_payload_data;
+		crc32_inserter_source_payload_last_be <= crc32_inserter_sink_payload_last_be;
+		crc32_inserter_source_payload_error <= crc32_inserter_sink_payload_error;
+	end
+	subfragments_liteethmacpaddinginserter_state <= subfragments_liteethmacpaddinginserter_next_state;
+	if (padding_inserter_counter_liteethmacpaddinginserter_next_value_ce) begin
+		padding_inserter_counter <= padding_inserter_counter_liteethmacpaddinginserter_next_value;
+	end
+	subfragments_liteethmactxlastbe_state <= subfragments_liteethmactxlastbe_next_state;
+	if ((tx_converter_converter_source_valid & tx_converter_converter_source_ready)) begin
+		if (tx_converter_converter_last) begin
+			tx_converter_converter_mux <= 1'd0;
+		end else begin
+			tx_converter_converter_mux <= (tx_converter_converter_mux + 1'd1);
+		end
+	end
+	tx_cdc_cdc_graycounter1_q_binary <= tx_cdc_cdc_graycounter1_q_next_binary;
+	tx_cdc_cdc_graycounter1_q <= tx_cdc_cdc_graycounter1_q_next;
+	if (eth_tx_rst) begin
+		maccore_ethphy_liteethphygmiimiitx_gmii_tx_sink_ready <= 1'd0;
+		maccore_ethphy_liteethphygmiimiitx_converter_converter_mux <= 1'd0;
+		liteethmaccrc32inserter_reg <= 32'd4294967295;
+		liteethmaccrc32inserter_cnt <= 2'd3;
+		crc32_inserter_source_valid <= 1'd0;
+		crc32_inserter_source_payload_data <= 8'd0;
+		crc32_inserter_source_payload_last_be <= 1'd0;
+		crc32_inserter_source_payload_error <= 1'd0;
+		padding_inserter_counter <= 16'd0;
+		tx_converter_converter_mux <= 2'd0;
+		tx_cdc_cdc_graycounter1_q <= 6'd0;
+		tx_cdc_cdc_graycounter1_q_binary <= 6'd0;
+		subfragments_liteethmacgap_state <= 1'd0;
+		subfragments_liteethmacpreambleinserter_state <= 2'd0;
+		subfragments_liteethmaccrc32inserter_state <= 2'd0;
+		subfragments_liteethmacpaddinginserter_state <= 1'd0;
+		subfragments_liteethmactxlastbe_state <= 1'd0;
+	end
+	xilinxmultiregimpl4_regs0 <= tx_cdc_cdc_graycounter0_q;
+	xilinxmultiregimpl4_regs1 <= xilinxmultiregimpl4_regs0;
+end
+
+always @(posedge por_clk) begin
+	maccore_int_rst <= sys_reset;
+end
+
+always @(posedge sys_clk) begin
+	if ((maccore_maccore_bus_errors != 32'd4294967295)) begin
+		if (maccore_maccore_bus_error) begin
+			maccore_maccore_bus_errors <= (maccore_maccore_bus_errors + 1'd1);
+		end
+	end
+	if (maccore_ethphy_update_mode) begin
+		maccore_ethphy_mode0 <= maccore_ethphy_mode1;
+	end
+	if (maccore_ethphy_sys_counter_reset) begin
+		maccore_ethphy_sys_counter <= 1'd0;
+	end else begin
+		if (maccore_ethphy_sys_counter_ce) begin
+			maccore_ethphy_sys_counter <= (maccore_ethphy_sys_counter + 1'd1);
+		end
+	end
+	maccore_ethphy_toggle_o_r <= maccore_ethphy_toggle_o;
+	subfragments_state <= subfragments_next_state;
+	if (maccore_ethphy_counter_ce) begin
+		maccore_ethphy_counter <= (maccore_ethphy_counter + 1'd1);
+	end
+	if (ps_preamble_error_o) begin
+		preamble_errors_status <= (preamble_errors_status + 1'd1);
+	end
+	if (ps_crc_error_o) begin
+		crc_errors_status <= (crc_errors_status + 1'd1);
+	end
+	ps_preamble_error_toggle_o_r <= ps_preamble_error_toggle_o;
+	ps_crc_error_toggle_o_r <= ps_crc_error_toggle_o;
+	tx_cdc_cdc_graycounter0_q_binary <= tx_cdc_cdc_graycounter0_q_next_binary;
+	tx_cdc_cdc_graycounter0_q <= tx_cdc_cdc_graycounter0_q_next;
+	rx_cdc_cdc_graycounter1_q_binary <= rx_cdc_cdc_graycounter1_q_next_binary;
+	rx_cdc_cdc_graycounter1_q <= rx_cdc_cdc_graycounter1_q_next;
+	if (writer_slot_ce) begin
+		writer_slot <= (writer_slot + 1'd1);
+	end
+	if (((writer_stat_fifo_syncfifo_we & writer_stat_fifo_syncfifo_writable) & (~writer_stat_fifo_replace))) begin
+		writer_stat_fifo_produce <= (writer_stat_fifo_produce + 1'd1);
+	end
+	if (writer_stat_fifo_do_read) begin
+		writer_stat_fifo_consume <= (writer_stat_fifo_consume + 1'd1);
+	end
+	if (((writer_stat_fifo_syncfifo_we & writer_stat_fifo_syncfifo_writable) & (~writer_stat_fifo_replace))) begin
+		if ((~writer_stat_fifo_do_read)) begin
+			writer_stat_fifo_level <= (writer_stat_fifo_level + 1'd1);
+		end
+	end else begin
+		if (writer_stat_fifo_do_read) begin
+			writer_stat_fifo_level <= (writer_stat_fifo_level - 1'd1);
+		end
+	end
+	subfragments_liteethmacsramwriter_state <= subfragments_liteethmacsramwriter_next_state;
+	if (writer_counter_t_next_value_ce) begin
+		writer_counter <= writer_counter_t_next_value;
+	end
+	if (writer_errors_status_f_next_value_ce) begin
+		writer_errors_status <= writer_errors_status_f_next_value;
+	end
+	if (reader_eventsourcepulse_clear) begin
+		reader_eventsourcepulse_pending <= 1'd0;
+	end
+	if (reader_eventsourcepulse_trigger) begin
+		reader_eventsourcepulse_pending <= 1'd1;
+	end
+	if (((reader_cmd_fifo_syncfifo_we & reader_cmd_fifo_syncfifo_writable) & (~reader_cmd_fifo_replace))) begin
+		reader_cmd_fifo_produce <= (reader_cmd_fifo_produce + 1'd1);
+	end
+	if (reader_cmd_fifo_do_read) begin
+		reader_cmd_fifo_consume <= (reader_cmd_fifo_consume + 1'd1);
+	end
+	if (((reader_cmd_fifo_syncfifo_we & reader_cmd_fifo_syncfifo_writable) & (~reader_cmd_fifo_replace))) begin
+		if ((~reader_cmd_fifo_do_read)) begin
+			reader_cmd_fifo_level <= (reader_cmd_fifo_level + 1'd1);
+		end
+	end else begin
+		if (reader_cmd_fifo_do_read) begin
+			reader_cmd_fifo_level <= (reader_cmd_fifo_level - 1'd1);
+		end
+	end
+	subfragments_liteethmacsramreader_state <= subfragments_liteethmacsramreader_next_state;
+	if (reader_counter_next_value_ce) begin
+		reader_counter <= reader_counter_next_value;
+	end
+	sram0_bus_ack0 <= 1'd0;
+	if (((sram0_bus_cyc0 & sram0_bus_stb0) & (~sram0_bus_ack0))) begin
+		sram0_bus_ack0 <= 1'd1;
+	end
+	sram1_bus_ack0 <= 1'd0;
+	if (((sram1_bus_cyc0 & sram1_bus_stb0) & (~sram1_bus_ack0))) begin
+		sram1_bus_ack0 <= 1'd1;
+	end
+	sram0_bus_ack1 <= 1'd0;
+	if (((sram0_bus_cyc1 & sram0_bus_stb1) & (~sram0_bus_ack1))) begin
+		sram0_bus_ack1 <= 1'd1;
+	end
+	sram1_bus_ack1 <= 1'd0;
+	if (((sram1_bus_cyc1 & sram1_bus_stb1) & (~sram1_bus_ack1))) begin
+		sram1_bus_ack1 <= 1'd1;
+	end
+	slave_sel_r <= slave_sel;
+	maccore_state <= maccore_next_state;
+	maccore_slave_sel_r <= maccore_slave_sel;
+	if (maccore_wait) begin
+		if ((~maccore_done)) begin
+			maccore_count <= (maccore_count - 1'd1);
+		end
+	end else begin
+		maccore_count <= 20'd1000000;
+	end
+	maccore_interface0_bank_bus_dat_r <= 1'd0;
+	if (maccore_csrbank0_sel) begin
+		case (maccore_interface0_bank_bus_adr[8:0])
+			1'd0: begin
+				maccore_interface0_bank_bus_dat_r <= maccore_csrbank0_reset0_w;
+			end
+			1'd1: begin
+				maccore_interface0_bank_bus_dat_r <= maccore_csrbank0_scratch0_w;
+			end
+			2'd2: begin
+				maccore_interface0_bank_bus_dat_r <= maccore_csrbank0_bus_errors_w;
+			end
+		endcase
+	end
+	if (maccore_csrbank0_reset0_re) begin
+		maccore_maccore_reset_storage[1:0] <= maccore_csrbank0_reset0_r;
+	end
+	maccore_maccore_reset_re <= maccore_csrbank0_reset0_re;
+	if (maccore_csrbank0_scratch0_re) begin
+		maccore_maccore_scratch_storage[31:0] <= maccore_csrbank0_scratch0_r;
+	end
+	maccore_maccore_scratch_re <= maccore_csrbank0_scratch0_re;
+	maccore_maccore_bus_errors_re <= maccore_csrbank0_bus_errors_re;
+	maccore_interface1_bank_bus_dat_r <= 1'd0;
+	if (maccore_csrbank1_sel) begin
+		case (maccore_interface1_bank_bus_adr[8:0])
+			1'd0: begin
+				maccore_interface1_bank_bus_dat_r <= maccore_csrbank1_sram_writer_slot_w;
+			end
+			1'd1: begin
+				maccore_interface1_bank_bus_dat_r <= maccore_csrbank1_sram_writer_length_w;
+			end
+			2'd2: begin
+				maccore_interface1_bank_bus_dat_r <= maccore_csrbank1_sram_writer_errors_w;
+			end
+			2'd3: begin
+				maccore_interface1_bank_bus_dat_r <= maccore_csrbank1_sram_writer_ev_status_w;
+			end
+			3'd4: begin
+				maccore_interface1_bank_bus_dat_r <= maccore_csrbank1_sram_writer_ev_pending_w;
+			end
+			3'd5: begin
+				maccore_interface1_bank_bus_dat_r <= maccore_csrbank1_sram_writer_ev_enable0_w;
+			end
+			3'd6: begin
+				maccore_interface1_bank_bus_dat_r <= reader_start_start_w;
+			end
+			3'd7: begin
+				maccore_interface1_bank_bus_dat_r <= maccore_csrbank1_sram_reader_ready_w;
+			end
+			4'd8: begin
+				maccore_interface1_bank_bus_dat_r <= maccore_csrbank1_sram_reader_level_w;
+			end
+			4'd9: begin
+				maccore_interface1_bank_bus_dat_r <= maccore_csrbank1_sram_reader_slot0_w;
+			end
+			4'd10: begin
+				maccore_interface1_bank_bus_dat_r <= maccore_csrbank1_sram_reader_length0_w;
+			end
+			4'd11: begin
+				maccore_interface1_bank_bus_dat_r <= maccore_csrbank1_sram_reader_ev_status_w;
+			end
+			4'd12: begin
+				maccore_interface1_bank_bus_dat_r <= maccore_csrbank1_sram_reader_ev_pending_w;
+			end
+			4'd13: begin
+				maccore_interface1_bank_bus_dat_r <= maccore_csrbank1_sram_reader_ev_enable0_w;
+			end
+			4'd14: begin
+				maccore_interface1_bank_bus_dat_r <= maccore_csrbank1_preamble_crc_w;
+			end
+			4'd15: begin
+				maccore_interface1_bank_bus_dat_r <= maccore_csrbank1_preamble_errors_w;
+			end
+			5'd16: begin
+				maccore_interface1_bank_bus_dat_r <= maccore_csrbank1_crc_errors_w;
+			end
+		endcase
+	end
+	writer_slot_re <= maccore_csrbank1_sram_writer_slot_re;
+	writer_length_re <= maccore_csrbank1_sram_writer_length_re;
+	writer_errors_re <= maccore_csrbank1_sram_writer_errors_re;
+	writer_status_re <= maccore_csrbank1_sram_writer_ev_status_re;
+	if (maccore_csrbank1_sram_writer_ev_pending_re) begin
+		writer_pending_r <= maccore_csrbank1_sram_writer_ev_pending_r;
+	end
+	writer_pending_re <= maccore_csrbank1_sram_writer_ev_pending_re;
+	if (maccore_csrbank1_sram_writer_ev_enable0_re) begin
+		writer_enable_storage <= maccore_csrbank1_sram_writer_ev_enable0_r;
+	end
+	writer_enable_re <= maccore_csrbank1_sram_writer_ev_enable0_re;
+	reader_ready_re <= maccore_csrbank1_sram_reader_ready_re;
+	reader_level_re <= maccore_csrbank1_sram_reader_level_re;
+	if (maccore_csrbank1_sram_reader_slot0_re) begin
+		reader_slot_storage <= maccore_csrbank1_sram_reader_slot0_r;
+	end
+	reader_slot_re <= maccore_csrbank1_sram_reader_slot0_re;
+	if (maccore_csrbank1_sram_reader_length0_re) begin
+		reader_length_storage[10:0] <= maccore_csrbank1_sram_reader_length0_r;
+	end
+	reader_length_re <= maccore_csrbank1_sram_reader_length0_re;
+	reader_status_re <= maccore_csrbank1_sram_reader_ev_status_re;
+	if (maccore_csrbank1_sram_reader_ev_pending_re) begin
+		reader_pending_r <= maccore_csrbank1_sram_reader_ev_pending_r;
+	end
+	reader_pending_re <= maccore_csrbank1_sram_reader_ev_pending_re;
+	if (maccore_csrbank1_sram_reader_ev_enable0_re) begin
+		reader_enable_storage <= maccore_csrbank1_sram_reader_ev_enable0_r;
+	end
+	reader_enable_re <= maccore_csrbank1_sram_reader_ev_enable0_re;
+	preamble_crc_re <= maccore_csrbank1_preamble_crc_re;
+	preamble_errors_re <= maccore_csrbank1_preamble_errors_re;
+	crc_errors_re <= maccore_csrbank1_crc_errors_re;
+	maccore_interface2_bank_bus_dat_r <= 1'd0;
+	if (maccore_csrbank2_sel) begin
+		case (maccore_interface2_bank_bus_adr[8:0])
+			1'd0: begin
+				maccore_interface2_bank_bus_dat_r <= maccore_csrbank2_mode_detection_mode_w;
+			end
+			1'd1: begin
+				maccore_interface2_bank_bus_dat_r <= maccore_csrbank2_crg_reset0_w;
+			end
+			2'd2: begin
+				maccore_interface2_bank_bus_dat_r <= maccore_csrbank2_mdio_w0_w;
+			end
+			2'd3: begin
+				maccore_interface2_bank_bus_dat_r <= maccore_csrbank2_mdio_r_w;
+			end
+		endcase
+	end
+	maccore_ethphy_mode_re <= maccore_csrbank2_mode_detection_mode_re;
+	if (maccore_csrbank2_crg_reset0_re) begin
+		maccore_ethphy_reset_storage <= maccore_csrbank2_crg_reset0_r;
+	end
+	maccore_ethphy_reset_re <= maccore_csrbank2_crg_reset0_re;
+	if (maccore_csrbank2_mdio_w0_re) begin
+		maccore_ethphy__w_storage[2:0] <= maccore_csrbank2_mdio_w0_r;
+	end
+	maccore_ethphy__w_re <= maccore_csrbank2_mdio_w0_re;
+	maccore_ethphy__r_re <= maccore_csrbank2_mdio_r_re;
+	if (sys_rst) begin
+		maccore_maccore_reset_storage <= 2'd0;
+		maccore_maccore_reset_re <= 1'd0;
+		maccore_maccore_scratch_storage <= 32'd305419896;
+		maccore_maccore_scratch_re <= 1'd0;
+		maccore_maccore_bus_errors_re <= 1'd0;
+		maccore_maccore_bus_errors <= 32'd0;
+		maccore_ethphy_mode0 <= 1'd0;
+		maccore_ethphy_mode_re <= 1'd0;
+		maccore_ethphy_reset_storage <= 1'd0;
+		maccore_ethphy_reset_re <= 1'd0;
+		maccore_ethphy_counter <= 9'd0;
+		maccore_ethphy__w_storage <= 3'd0;
+		maccore_ethphy__w_re <= 1'd0;
+		maccore_ethphy__r_re <= 1'd0;
+		preamble_crc_re <= 1'd0;
+		preamble_errors_status <= 32'd0;
+		preamble_errors_re <= 1'd0;
+		crc_errors_status <= 32'd0;
+		crc_errors_re <= 1'd0;
+		tx_cdc_cdc_graycounter0_q <= 6'd0;
+		tx_cdc_cdc_graycounter0_q_binary <= 6'd0;
+		rx_cdc_cdc_graycounter1_q <= 6'd0;
+		rx_cdc_cdc_graycounter1_q_binary <= 6'd0;
+		writer_slot_re <= 1'd0;
+		writer_length_re <= 1'd0;
+		writer_errors_status <= 32'd0;
+		writer_errors_re <= 1'd0;
+		writer_status_re <= 1'd0;
+		writer_pending_re <= 1'd0;
+		writer_pending_r <= 1'd0;
+		writer_enable_storage <= 1'd0;
+		writer_enable_re <= 1'd0;
+		writer_counter <= 32'd0;
+		writer_slot <= 1'd0;
+		writer_stat_fifo_level <= 2'd0;
+		writer_stat_fifo_produce <= 1'd0;
+		writer_stat_fifo_consume <= 1'd0;
+		reader_ready_re <= 1'd0;
+		reader_level_re <= 1'd0;
+		reader_slot_re <= 1'd0;
+		reader_length_re <= 1'd0;
+		reader_eventsourcepulse_pending <= 1'd0;
+		reader_status_re <= 1'd0;
+		reader_pending_re <= 1'd0;
+		reader_pending_r <= 1'd0;
+		reader_enable_storage <= 1'd0;
+		reader_enable_re <= 1'd0;
+		reader_cmd_fifo_level <= 2'd0;
+		reader_cmd_fifo_produce <= 1'd0;
+		reader_cmd_fifo_consume <= 1'd0;
+		reader_counter <= 11'd0;
+		sram0_bus_ack0 <= 1'd0;
+		sram1_bus_ack0 <= 1'd0;
+		sram0_bus_ack1 <= 1'd0;
+		sram1_bus_ack1 <= 1'd0;
+		slave_sel_r <= 4'd0;
+		subfragments_state <= 2'd0;
+		subfragments_liteethmacsramwriter_state <= 3'd0;
+		subfragments_liteethmacsramreader_state <= 2'd0;
+		maccore_slave_sel_r <= 2'd0;
+		maccore_count <= 20'd1000000;
+		maccore_state <= 1'd0;
+	end
+	xilinxmultiregimpl0_regs0 <= maccore_ethphy_toggle_i;
+	xilinxmultiregimpl0_regs1 <= xilinxmultiregimpl0_regs0;
+	xilinxmultiregimpl1_regs0 <= maccore_ethphy_data_r;
+	xilinxmultiregimpl1_regs1 <= xilinxmultiregimpl1_regs0;
+	xilinxmultiregimpl2_regs0 <= ps_preamble_error_toggle_i;
+	xilinxmultiregimpl2_regs1 <= xilinxmultiregimpl2_regs0;
+	xilinxmultiregimpl3_regs0 <= ps_crc_error_toggle_i;
+	xilinxmultiregimpl3_regs1 <= xilinxmultiregimpl3_regs0;
+	xilinxmultiregimpl5_regs0 <= tx_cdc_cdc_graycounter1_q;
+	xilinxmultiregimpl5_regs1 <= xilinxmultiregimpl5_regs0;
+	xilinxmultiregimpl6_regs0 <= rx_cdc_cdc_graycounter0_q;
+	xilinxmultiregimpl6_regs1 <= xilinxmultiregimpl6_regs0;
+end
+
+BUFG BUFG(
+	.I(gmii_eth_clocks_rx),
+	.O(eth_rx_clk)
+);
+
+BUFG BUFG_1(
+	.I(maccore_ethphy_eth_tx_clk),
+	.O(eth_tx_clk)
+);
+
+assign gmii_eth_mdio = maccore_ethphy_data_oe ? maccore_ethphy_data_w : 1'bz;
+assign maccore_ethphy_data_r = gmii_eth_mdio;
+
+reg [11:0] storage[0:4];
+reg [11:0] memdat;
+always @(posedge eth_rx_clk) begin
+	if (liteethmaccrc32checker_syncfifo_wrport_we)
+		storage[liteethmaccrc32checker_syncfifo_wrport_adr] <= liteethmaccrc32checker_syncfifo_wrport_dat_w;
+	memdat <= storage[liteethmaccrc32checker_syncfifo_wrport_adr];
+end
+
+always @(posedge eth_rx_clk) begin
+end
+
+assign liteethmaccrc32checker_syncfifo_wrport_dat_r = memdat;
+assign liteethmaccrc32checker_syncfifo_rdport_dat_r = storage[liteethmaccrc32checker_syncfifo_rdport_adr];
+
+reg [41:0] storage_1[0:31];
+reg [4:0] memadr;
+reg [4:0] memadr_1;
+always @(posedge sys_clk) begin
+	if (tx_cdc_cdc_wrport_we)
+		storage_1[tx_cdc_cdc_wrport_adr] <= tx_cdc_cdc_wrport_dat_w;
+	memadr <= tx_cdc_cdc_wrport_adr;
+end
+
+always @(posedge eth_tx_clk) begin
+	memadr_1 <= tx_cdc_cdc_rdport_adr;
+end
+
+assign tx_cdc_cdc_wrport_dat_r = storage_1[memadr];
+assign tx_cdc_cdc_rdport_dat_r = storage_1[memadr_1];
+
+reg [41:0] storage_2[0:31];
+reg [4:0] memadr_2;
+reg [4:0] memadr_3;
+always @(posedge eth_rx_clk) begin
+	if (rx_cdc_cdc_wrport_we)
+		storage_2[rx_cdc_cdc_wrport_adr] <= rx_cdc_cdc_wrport_dat_w;
+	memadr_2 <= rx_cdc_cdc_wrport_adr;
+end
+
+always @(posedge sys_clk) begin
+	memadr_3 <= rx_cdc_cdc_rdport_adr;
+end
+
+assign rx_cdc_cdc_wrport_dat_r = storage_2[memadr_2];
+assign rx_cdc_cdc_rdport_dat_r = storage_2[memadr_3];
+
+reg [34:0] storage_3[0:1];
+reg [34:0] memdat_1;
+always @(posedge sys_clk) begin
+	if (writer_stat_fifo_wrport_we)
+		storage_3[writer_stat_fifo_wrport_adr] <= writer_stat_fifo_wrport_dat_w;
+	memdat_1 <= storage_3[writer_stat_fifo_wrport_adr];
+end
+
+always @(posedge sys_clk) begin
+end
+
+assign writer_stat_fifo_wrport_dat_r = memdat_1;
+assign writer_stat_fifo_rdport_dat_r = storage_3[writer_stat_fifo_rdport_adr];
+
+reg [31:0] mem[0:381];
+reg [8:0] memadr_4;
+reg [31:0] memdat_2;
+always @(posedge sys_clk) begin
+	if (writer_memory0_we)
+		mem[writer_memory0_adr] <= writer_memory0_dat_w;
+	memadr_4 <= writer_memory0_adr;
+end
+
+always @(posedge sys_clk) begin
+	memdat_2 <= mem[sram0_adr0];
+end
+
+assign writer_memory0_dat_r = mem[memadr_4];
+assign sram0_dat_r0 = memdat_2;
+
+reg [31:0] mem_1[0:381];
+reg [8:0] memadr_5;
+reg [31:0] memdat_3;
+always @(posedge sys_clk) begin
+	if (writer_memory1_we)
+		mem_1[writer_memory1_adr] <= writer_memory1_dat_w;
+	memadr_5 <= writer_memory1_adr;
+end
+
+always @(posedge sys_clk) begin
+	memdat_3 <= mem_1[sram1_adr0];
+end
+
+assign writer_memory1_dat_r = mem_1[memadr_5];
+assign sram1_dat_r0 = memdat_3;
+
+reg [13:0] storage_4[0:1];
+reg [13:0] memdat_4;
+always @(posedge sys_clk) begin
+	if (reader_cmd_fifo_wrport_we)
+		storage_4[reader_cmd_fifo_wrport_adr] <= reader_cmd_fifo_wrport_dat_w;
+	memdat_4 <= storage_4[reader_cmd_fifo_wrport_adr];
+end
+
+always @(posedge sys_clk) begin
+end
+
+assign reader_cmd_fifo_wrport_dat_r = memdat_4;
+assign reader_cmd_fifo_rdport_dat_r = storage_4[reader_cmd_fifo_rdport_adr];
+
+reg [31:0] mem_2[0:381];
+reg [8:0] memadr_6;
+reg [8:0] memadr_7;
+always @(posedge sys_clk) begin
+	memadr_6 <= reader_memory0_adr;
+end
+
+always @(posedge sys_clk) begin
+	if (sram0_we[0])
+		mem_2[sram0_adr1][7:0] <= sram0_dat_w[7:0];
+	if (sram0_we[1])
+		mem_2[sram0_adr1][15:8] <= sram0_dat_w[15:8];
+	if (sram0_we[2])
+		mem_2[sram0_adr1][23:16] <= sram0_dat_w[23:16];
+	if (sram0_we[3])
+		mem_2[sram0_adr1][31:24] <= sram0_dat_w[31:24];
+	memadr_7 <= sram0_adr1;
+end
+
+assign reader_memory0_dat_r = mem_2[memadr_6];
+assign sram0_dat_r1 = mem_2[memadr_7];
+
+reg [31:0] mem_3[0:381];
+reg [8:0] memadr_8;
+reg [8:0] memadr_9;
+always @(posedge sys_clk) begin
+	memadr_8 <= reader_memory1_adr;
+end
+
+always @(posedge sys_clk) begin
+	if (sram1_we[0])
+		mem_3[sram1_adr1][7:0] <= sram1_dat_w[7:0];
+	if (sram1_we[1])
+		mem_3[sram1_adr1][15:8] <= sram1_dat_w[15:8];
+	if (sram1_we[2])
+		mem_3[sram1_adr1][23:16] <= sram1_dat_w[23:16];
+	if (sram1_we[3])
+		mem_3[sram1_adr1][31:24] <= sram1_dat_w[31:24];
+	memadr_9 <= sram1_adr1;
+end
+
+assign reader_memory1_dat_r = mem_3[memadr_8];
+assign sram1_dat_r1 = mem_3[memadr_9];
+
+ODDR #(
+	.DDR_CLK_EDGE("SAME_EDGE")
+) ODDR (
+	.C(eth_tx_clk),
+	.CE(1'd1),
+	.D1(1'd1),
+	.D2((maccore_ethphy_mode0 == 1'd1)),
+	.R(1'd0),
+	.S(1'd0),
+	.Q(gmii_eth_clocks_gtx)
+);
+
+(* ars_ff1 = "true", async_reg = "true" *) FDPE #(
+	.INIT(1'd1)
+) FDPE (
+	.C(eth_tx_clk),
+	.CE(1'd1),
+	.D(1'd0),
+	.PRE(maccore_ethphy_reset0),
+	.Q(rst_meta0)
+);
+
+(* ars_ff2 = "true", async_reg = "true" *) FDPE #(
+	.INIT(1'd1)
+) FDPE_1 (
+	.C(eth_tx_clk),
+	.CE(1'd1),
+	.D(rst_meta0),
+	.PRE(maccore_ethphy_reset0),
+	.Q(eth_tx_rst)
+);
+
+(* ars_ff1 = "true", async_reg = "true" *) FDPE #(
+	.INIT(1'd1)
+) FDPE_2 (
+	.C(eth_rx_clk),
+	.CE(1'd1),
+	.D(1'd0),
+	.PRE(maccore_ethphy_reset0),
+	.Q(rst_meta1)
+);
+
+(* ars_ff2 = "true", async_reg = "true" *) FDPE #(
+	.INIT(1'd1)
+) FDPE_3 (
+	.C(eth_rx_clk),
+	.CE(1'd1),
+	.D(rst_meta1),
+	.PRE(maccore_ethphy_reset0),
+	.Q(eth_rx_rst)
+);
+
+endmodule