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Metavalue cleanup for common.vhdl

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This affects other files which have been included here.

Signed-off-by: Michael Neuling <mikey@neuling.org>
pull/378/head
Michael Neuling 2 years ago
parent 281a125f1f
commit caf458be37
5 changed files with 43 additions and 32 deletions
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35
common.vhdl
Unescape Escape View File

@ -115,28 +115,29 @@ package common is


-- Some SPRs are stored in a pair of small RAMs in execute1 -- Some SPRs are stored in a pair of small RAMs in execute1
-- Even half: -- Even half:
subtype ramspr_index is natural range 0 to 7; subtype ramspr_index_range is natural range 0 to 7;
constant RAMSPR_SRR0 : ramspr_index := 0; subtype ramspr_index is unsigned(2 downto 0);
constant RAMSPR_HSRR0 : ramspr_index := 1; constant RAMSPR_SRR0 : ramspr_index := to_unsigned(0,3);
constant RAMSPR_SPRG0 : ramspr_index := 2; constant RAMSPR_HSRR0 : ramspr_index := to_unsigned(1,3);
constant RAMSPR_SPRG2 : ramspr_index := 3; constant RAMSPR_SPRG0 : ramspr_index := to_unsigned(2,3);
constant RAMSPR_HSPRG0 : ramspr_index := 4; constant RAMSPR_SPRG2 : ramspr_index := to_unsigned(3,3);
constant RAMSPR_LR : ramspr_index := 5; -- must equal RAMSPR_CTR constant RAMSPR_HSPRG0 : ramspr_index := to_unsigned(4,3);
constant RAMSPR_TAR : ramspr_index := 6; constant RAMSPR_LR : ramspr_index := to_unsigned(5,3); -- must equal RAMSPR_CTR
constant RAMSPR_TAR : ramspr_index := to_unsigned(6,3);
-- Odd half: -- Odd half:
constant RAMSPR_SRR1 : ramspr_index := 0; constant RAMSPR_SRR1 : ramspr_index := to_unsigned(0,3);
constant RAMSPR_HSRR1 : ramspr_index := 1; constant RAMSPR_HSRR1 : ramspr_index := to_unsigned(1,3);
constant RAMSPR_SPRG1 : ramspr_index := 2; constant RAMSPR_SPRG1 : ramspr_index := to_unsigned(2,3);
constant RAMSPR_SPRG3 : ramspr_index := 3; constant RAMSPR_SPRG3 : ramspr_index := to_unsigned(3,3);
constant RAMSPR_HSPRG1 : ramspr_index := 4; constant RAMSPR_HSPRG1 : ramspr_index := to_unsigned(4,3);
constant RAMSPR_CTR : ramspr_index := 5; -- must equal RAMSPR_LR constant RAMSPR_CTR : ramspr_index := to_unsigned(5,3); -- must equal RAMSPR_LR


type ram_spr_info is record type ram_spr_info is record
index : ramspr_index; index : ramspr_index;
isodd : std_ulogic; isodd : std_ulogic;
valid : std_ulogic; valid : std_ulogic;
end record; end record;
constant ram_spr_info_init: ram_spr_info := (index => 0, others => '0'); constant ram_spr_info_init: ram_spr_info := (index => to_unsigned(0,3), others => '0');


subtype spr_selector is std_ulogic_vector(2 downto 0); subtype spr_selector is std_ulogic_vector(2 downto 0);
type spr_id is record type spr_id is record
@ -366,8 +367,8 @@ package common is
result_sel => "000", sub_select => "000", result_sel => "000", sub_select => "000",
repeat => '0', second => '0', spr_select => spr_id_init, repeat => '0', second => '0', spr_select => spr_id_init,
spr_is_ram => '0', spr_is_ram => '0',
ramspr_even_rdaddr => 0, ramspr_odd_rdaddr => 0, ramspr_rd_odd => '0', ramspr_even_rdaddr => (others => '0'), ramspr_odd_rdaddr => (others => '0'), ramspr_rd_odd => '0',
ramspr_wraddr => 0, ramspr_write_even => '0', ramspr_write_odd => '0', ramspr_wraddr => (others => '0'), ramspr_write_even => '0', ramspr_write_odd => '0',
dbg_spr_access => '0', dbg_spr_access => '0',
dec_ctr => '0', dec_ctr => '0',
others => (others => '0')); others => (others => '0'));

4
core_debug.vhdl
Unescape Escape View File

@ -273,7 +273,7 @@ begin
valid := '1'; valid := '1';
sel := "000"; sel := "000";
isram := '1'; isram := '1';
raddr := 0; raddr := (others => '0');
odd := '0'; odd := '0';
case gspr_index(4 downto 0) is case gspr_index(4 downto 0) is
when 5x"00" => when 5x"00" =>
@ -304,7 +304,7 @@ begin
when others => when others =>
valid := '0'; valid := '0';
end case; end case;
dbg_spr_addr <= isram & sel & std_ulogic_vector(to_unsigned(raddr, 3)) & odd; dbg_spr_addr <= isram & sel & std_ulogic_vector(raddr) & odd;
spr_index_valid <= valid; spr_index_valid <= valid;
end if; end if;
end process; end process;

2
decode1.vhdl
Unescape Escape View File

@ -530,7 +530,7 @@ architecture behaviour of decode1 is
function decode_ram_spr(sprn : spr_num_t) return ram_spr_info is function decode_ram_spr(sprn : spr_num_t) return ram_spr_info is
variable ret : ram_spr_info; variable ret : ram_spr_info;
begin begin
ret := (index => 0, isodd => '0', valid => '1'); ret := (index => (others => '0'), isodd => '0', valid => '1');
case sprn is case sprn is
when SPR_LR => when SPR_LR =>
ret.index := RAMSPR_LR; ret.index := RAMSPR_LR;

4
decode2.vhdl
Unescape Escape View File

@ -671,8 +671,8 @@ begin


v.e.dbg_spr_access := dbg_spr_req and not v.read_rspr; v.e.dbg_spr_access := dbg_spr_req and not v.read_rspr;
if v.e.dbg_spr_access = '1' then if v.e.dbg_spr_access = '1' then
v.e.ramspr_even_rdaddr := to_integer(unsigned(dbg_spr_addr(3 downto 1))); v.e.ramspr_even_rdaddr := unsigned(dbg_spr_addr(3 downto 1));
v.e.ramspr_odd_rdaddr := to_integer(unsigned(dbg_spr_addr(3 downto 1))); v.e.ramspr_odd_rdaddr := unsigned(dbg_spr_addr(3 downto 1));
v.e.ramspr_rd_odd := dbg_spr_addr(0); v.e.ramspr_rd_odd := dbg_spr_addr(0);
end if; end if;



30
execute1.vhdl
Unescape Escape View File

@ -147,7 +147,7 @@ architecture behaviour of execute1 is
taken_branch_event => '0', br_mispredict => '0', taken_branch_event => '0', br_mispredict => '0',
msr => 64x"0", msr => 64x"0",
xerc => xerc_init, xerc_valid => '0', xerc => xerc_init, xerc_valid => '0',
ramspr_wraddr => 0, ramspr_odd_data => 64x"0"); ramspr_wraddr => (others => '0'), ramspr_odd_data => 64x"0");


type reg_stage2_type is record type reg_stage2_type is record
e : Execute1ToWritebackType; e : Execute1ToWritebackType;
@ -221,7 +221,7 @@ architecture behaviour of execute1 is
signal irq_valid_log : std_ulogic; signal irq_valid_log : std_ulogic;


-- SPR-related signals -- SPR-related signals
type ramspr_half_t is array(ramspr_index) of std_ulogic_vector(63 downto 0); type ramspr_half_t is array(ramspr_index_range) of std_ulogic_vector(63 downto 0);
signal even_sprs : ramspr_half_t := (others => (others => '0')); signal even_sprs : ramspr_half_t := (others => (others => '0'));
signal odd_sprs : ramspr_half_t := (others => (others => '0')); signal odd_sprs : ramspr_half_t := (others => (others => '0'));
signal ramspr_even : std_ulogic_vector(63 downto 0); signal ramspr_even : std_ulogic_vector(63 downto 0);
@ -510,8 +510,16 @@ begin
variable doit : std_ulogic; variable doit : std_ulogic;
begin begin
-- Read address mux and async RAM reading -- Read address mux and async RAM reading
even_rd_data := even_sprs(e_in.ramspr_even_rdaddr); if is_X(e_in.ramspr_even_rdaddr) then
odd_rd_data := odd_sprs(e_in.ramspr_odd_rdaddr); even_rd_data := (others => 'X');
else
even_rd_data := even_sprs(to_integer(e_in.ramspr_even_rdaddr));
end if;
if is_X(e_in.ramspr_even_rdaddr) then
odd_rd_data := (others => 'X');
else
odd_rd_data := odd_sprs(to_integer(e_in.ramspr_odd_rdaddr));
end if;


-- Write address and data muxes -- Write address and data muxes
doit := ex1.e.valid and not stage2_stall and not flush_in; doit := ex1.e.valid and not stage2_stall and not flush_in;
@ -559,13 +567,15 @@ begin
begin begin
if rising_edge(clk) then if rising_edge(clk) then
if ramspr_even_wr_enab = '1' then if ramspr_even_wr_enab = '1' then
even_sprs(ramspr_wr_addr) <= ramspr_even_wr_data; assert not is_X(ramspr_wr_addr) report "Writing to unknown address" severity FAILURE;
report "writing even spr " & integer'image(ramspr_wr_addr) & " data=" & even_sprs(to_integer(ramspr_wr_addr)) <= ramspr_even_wr_data;
report "writing even spr " & integer'image(to_integer(ramspr_wr_addr)) & " data=" &
to_hstring(ramspr_even_wr_data); to_hstring(ramspr_even_wr_data);
end if; end if;
if ramspr_odd_wr_enab = '1' then if ramspr_odd_wr_enab = '1' then
odd_sprs(ramspr_wr_addr) <= ramspr_odd_wr_data; assert not is_X(ramspr_wr_addr) report "Writing to unknown address" severity FAILURE;
report "writing odd spr " & integer'image(ramspr_wr_addr) & " data=" & odd_sprs(to_integer(ramspr_wr_addr)) <= ramspr_odd_wr_data;
report "writing odd spr " & integer'image(to_integer(ramspr_wr_addr)) & " data=" &
to_hstring(ramspr_odd_wr_data); to_hstring(ramspr_odd_wr_data);
end if; end if;
end if; end if;
@ -1773,8 +1783,8 @@ begin
variable xer : std_ulogic_vector(63 downto 0); variable xer : std_ulogic_vector(63 downto 0);
begin begin
if sim_dump = '1' then if sim_dump = '1' then
report "LR " & to_hstring(even_sprs(RAMSPR_LR)); report "LR " & to_hstring(even_sprs(to_integer(RAMSPR_LR)));
report "CTR " & to_hstring(odd_sprs(RAMSPR_CTR)); report "CTR " & to_hstring(odd_sprs(to_integer(RAMSPR_CTR)));
sim_dump_done <= '1'; sim_dump_done <= '1';
else else
sim_dump_done <= '0'; sim_dump_done <= '0';

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