Wishbone debug module
This adds a debug module off the DMI (debug) bus which can act as a wishbone master to generate read and write cycles. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>pull/69/head
Benjamin Herrenschmidt
5 years ago
parent
ee52fd4d80
commit
b46f81fae4
@ -0,0 +1,167 @@
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.wishbone_types.all;
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entity wishbone_debug_master is
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port(clk : in std_ulogic;
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rst : in std_ulogic;
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-- Debug bus interface
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dmi_addr : in std_ulogic_vector(1 downto 0);
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dmi_din : in std_ulogic_vector(63 downto 0);
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dmi_dout : out std_ulogic_vector(63 downto 0);
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dmi_req : in std_ulogic;
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dmi_wr : in std_ulogic;
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dmi_ack : out std_ulogic;
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-- Wishbone master interface
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wb_out : out wishbone_master_out;
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wb_in : in wishbone_slave_out
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);
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end entity wishbone_debug_master;
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architecture behaviour of wishbone_debug_master is
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-- ** Register offsets definitions. All registers are 64-bit
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constant DBG_WB_ADDR : std_ulogic_vector(1 downto 0) := "00";
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constant DBG_WB_DATA : std_ulogic_vector(1 downto 0) := "01";
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constant DBG_WB_CTRL : std_ulogic_vector(1 downto 0) := "10";
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constant DBG_WB_RSVD : std_ulogic_vector(1 downto 0) := "11";
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-- CTRL register:
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--
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-- bit 0..7 : SEL bits (byte enables)
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-- bit 8 : address auto-increment
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-- bit 10..9 : auto-increment value:
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-- 00 - +1
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-- 01 - +2
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-- 10 - +4
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-- 11 - +8
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-- ** Address and control registers and read data
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signal reg_addr : std_ulogic_vector(63 downto 0);
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signal reg_ctrl_out : std_ulogic_vector(63 downto 0);
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signal reg_ctrl : std_ulogic_vector(10 downto 0);
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signal data_latch : std_ulogic_vector(63 downto 0);
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type state_t is (IDLE, WB_CYCLE, DMI_WAIT);
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signal state : state_t;
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begin
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-- Hard wire unused bits to 0
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reg_ctrl_out <= (63 downto 11 => '0',
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10 downto 0 => reg_ctrl);
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-- DMI read data mux
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with dmi_addr select dmi_dout <=
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reg_addr when DBG_WB_ADDR,
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data_latch when DBG_WB_DATA,
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reg_ctrl_out when DBG_WB_CTRL,
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(others => '0') when others;
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-- ADDR and CTRL register writes
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reg_write : process(clk)
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subtype autoinc_inc_t is integer range 1 to 8;
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function decode_autoinc(c : std_ulogic_vector(1 downto 0))
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return autoinc_inc_t is
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begin
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case c is
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when "00" => return 1;
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when "01" => return 2;
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when "10" => return 4;
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when "11" => return 8;
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-- Below shouldn't be necessary but GHDL complains
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when others => return 8;
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end case;
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end function decode_autoinc;
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begin
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if rising_edge(clk) then
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if (rst) then
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reg_addr <= (others => '0');
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reg_ctrl <= (others => '0');
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else -- Standard register writes
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if dmi_req and dmi_wr then
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if dmi_addr = DBG_WB_ADDR then
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reg_addr <= dmi_din;
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elsif dmi_addr = DBG_WB_CTRL then
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reg_ctrl <= dmi_din(10 downto 0);
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end if;
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end if;
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-- Address register auto-increment
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if state = WB_CYCLE and (wb_in.ack and reg_ctrl(8))= '1' then
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reg_addr <= std_ulogic_vector(unsigned(reg_addr) +
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decode_autoinc(reg_ctrl(10 downto 9)));
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end if;
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end if;
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end if;
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end process;
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-- ACK is hard wired to req for register writes. For data read/writes
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-- (aka commands), it's sent when the state machine got the WB ack.
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--
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-- Note: We never set it to 1, we just pass dmi_req back when acking.
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-- This fullfills two purposes:
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--
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-- * Avoids polluting the ack signal when another DMI slave is
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-- selected. This allows the decoder to just OR all the acks
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-- together rather than mux them.
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--
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-- * Makes ack go down on the same cycle as req goes down, thus
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-- saving a clock cycle. This is safe because we know that
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-- the state machine will no longer be in DMI_WAIT state on
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-- the next cycle, so we won't be bouncing the signal back up.
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--
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dmi_ack <= dmi_req when (dmi_addr /= DBG_WB_DATA or state = DMI_WAIT) else '0';
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-- Some WB signals are direct wires from registers or DMI
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wb_out.adr <= reg_addr;
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wb_out.dat <= dmi_din;
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wb_out.sel <= reg_ctrl(7 downto 0);
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wb_out.we <= dmi_wr;
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-- We always move WB cyc and stb simultaneously (no pipelining yet...)
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wb_out.cyc <= '1' when state = WB_CYCLE else '0';
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wb_out.stb <= '1' when state = WB_CYCLE else '0';
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-- Data latch. WB will take the read data away as soon as the cycle
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-- terminates but we must maintain it on DMI until req goes down, so
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-- we latch it. (Q: Should we move that latch to dmi_dtm itself ?)
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--
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latch_reads : process(clk)
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begin
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if rising_edge(clk) then
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if state = WB_CYCLE and wb_in.ack = '1' and dmi_wr = '0' then
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data_latch <= wb_in.dat;
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end if;
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end if;
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end process;
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-- Command state machine (generate wb_cyc)
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wb_trigger : process(clk)
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begin
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if rising_edge(clk) then
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if (rst) then
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state <= IDLE;
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else
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case state is
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when IDLE =>
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if dmi_req = '1' and dmi_addr = DBG_WB_DATA then
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state <= WB_CYCLE;
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end if;
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when WB_CYCLE =>
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if wb_in.ack then
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state <= DMI_WAIT;
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end if;
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when DMI_WAIT =>
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if dmi_req = '0' then
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state <= IDLE;
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end if;
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end case;
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end if;
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end if;
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end process;
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end architecture behaviour;
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