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execute1: Make it clear that divide logic is not included when HAS_FPU=true

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This adds a "not HAS_FPU" condition in a few places to make it obvious
that logic to interface to the divide unit is not included when we
have an FPU.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
pull/382/head
Paul Mackerras 2 years ago
parent d1e8e62fee
commit b0aa5340b8
1 changed files with 45 additions and 43 deletions
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88
execute1.vhdl
Unescape Escape View File

@ -699,54 +699,56 @@ begin
x_to_multiply.addend <= addend; x_to_multiply.addend <= addend;


-- Interface to divide unit -- Interface to divide unit
sign1 := '0'; if not HAS_FPU then
sign2 := '0'; sign1 := '0';
if e_in.is_signed = '1' then sign2 := '0';
if e_in.is_32bit = '1' then if e_in.is_signed = '1' then
sign1 := a_in(31); if e_in.is_32bit = '1' then
sign2 := b_in(31); sign1 := a_in(31);
sign2 := b_in(31);
else
sign1 := a_in(63);
sign2 := b_in(63);
end if;
end if;
-- take absolute values
if sign1 = '0' then
abs1 := signed(a_in);
else else
sign1 := a_in(63); abs1 := - signed(a_in);
sign2 := b_in(63);
end if; end if;
end if; if sign2 = '0' then
-- take absolute values abs2 := signed(b_in);
if sign1 = '0' then else
abs1 := signed(a_in); abs2 := - signed(b_in);
else
abs1 := - signed(a_in);
end if;
if sign2 = '0' then
abs2 := signed(b_in);
else
abs2 := - signed(b_in);
end if;

x_to_divider.is_signed <= e_in.is_signed;
x_to_divider.is_32bit <= e_in.is_32bit;
x_to_divider.is_extended <= '0';
x_to_divider.is_modulus <= '0';
if e_in.insn_type = OP_MOD then
x_to_divider.is_modulus <= '1';
end if;
x_to_divider.flush <= flush_in;
x_to_divider.neg_result <= sign1 xor (sign2 and not x_to_divider.is_modulus);
if e_in.is_32bit = '0' then
-- 64-bit forms
if e_in.insn_type = OP_DIVE then
x_to_divider.is_extended <= '1';
end if; end if;
x_to_divider.dividend <= std_ulogic_vector(abs1);
x_to_divider.divisor <= std_ulogic_vector(abs2); x_to_divider.is_signed <= e_in.is_signed;
else x_to_divider.is_32bit <= e_in.is_32bit;
-- 32-bit forms
x_to_divider.is_extended <= '0'; x_to_divider.is_extended <= '0';
if e_in.insn_type = OP_DIVE then -- extended forms x_to_divider.is_modulus <= '0';
x_to_divider.dividend <= std_ulogic_vector(abs1(31 downto 0)) & x"00000000"; if e_in.insn_type = OP_MOD then
x_to_divider.is_modulus <= '1';
end if;
x_to_divider.flush <= flush_in;
x_to_divider.neg_result <= sign1 xor (sign2 and not x_to_divider.is_modulus);
if e_in.is_32bit = '0' then
-- 64-bit forms
if e_in.insn_type = OP_DIVE then
x_to_divider.is_extended <= '1';
end if;
x_to_divider.dividend <= std_ulogic_vector(abs1);
x_to_divider.divisor <= std_ulogic_vector(abs2);
else else
x_to_divider.dividend <= x"00000000" & std_ulogic_vector(abs1(31 downto 0)); -- 32-bit forms
x_to_divider.is_extended <= '0';
if e_in.insn_type = OP_DIVE then -- extended forms
x_to_divider.dividend <= std_ulogic_vector(abs1(31 downto 0)) & x"00000000";
else
x_to_divider.dividend <= x"00000000" & std_ulogic_vector(abs1(31 downto 0));
end if;
x_to_divider.divisor <= x"00000000" & std_ulogic_vector(abs2(31 downto 0));
end if; end if;
x_to_divider.divisor <= x"00000000" & std_ulogic_vector(abs2(31 downto 0));
end if; end if;


-- signals to 32-bit multiplier -- signals to 32-bit multiplier
@ -1486,7 +1488,7 @@ begin
end if; end if;
end if; end if;


if ex1.div_in_progress = '1' then if not HAS_FPU and ex1.div_in_progress = '1' then
v.div_in_progress := not divider_to_x.valid; v.div_in_progress := not divider_to_x.valid;
v.busy := not divider_to_x.valid; v.busy := not divider_to_x.valid;
if divider_to_x.valid = '1' and ex1.oe = '1' then if divider_to_x.valid = '1' and ex1.oe = '1' then

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