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microwatt
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Merge pull request #445 from paulusmack/master

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Various improvements, including SMP support for the Acorn-CLE-215 board.
master
Paul Mackerras 4 days ago committed by GitHub
parent dc9d351833 8f6c727309
commit a764fd464e
No known key found for this signature in database
GPG Key ID: B5690EEEBB952194
14 changed files with 521 additions and 595 deletions
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6
common.vhdl
Unescape Escape View File

@ -469,8 +469,8 @@ package common is
update : std_ulogic; -- is this an update instruction?
reserve : std_ulogic; -- set for larx/stcx
br_pred : std_ulogic;
result_sel : std_ulogic_vector(2 downto 0); -- select source of result
sub_select : std_ulogic_vector(2 downto 0); -- sub-result selection
result_sel : result_sel_t; -- select source of result
sub_select : subresult_sel_t; -- sub-result selection
repeat : std_ulogic; -- set if instruction is cracked into two ops
second : std_ulogic; -- set if this is the second op
spr_select : spr_id;
@ -509,7 +509,7 @@ package common is
read_data1 => (others => '0'), read_data2 => (others => '0'), read_data3 => (others => '0'),
reg_valid1 => '0', reg_valid2 => '0', reg_valid3 => '0',
cr => (others => '0'), insn => (others => '0'), data_len => (others => '0'),
result_sel => "000", sub_select => "000",
result_sel => ADD, sub_select => "000",
repeat => '0', second => '0', spr_select => spr_id_init,
spr_is_ram => '0',
ramspr_even_rdaddr => (others => '0'), ramspr_odd_rdaddr => (others => '0'), ramspr_rd_odd => '0',

3
dcache.vhdl
Unescape Escape View File

@ -1158,12 +1158,11 @@ begin
-- If we're stalling then we need to keep reading the last
-- row requested.
if r0_stall = '0' then
early_rd_valid <= '1';
if m_in.valid = '1' then
early_req_row <= get_row(m_in.addr);
early_rd_valid <= '1';
else
early_req_row <= get_row(d_in.addr);
early_rd_valid <= d_in.valid and d_in.load;
end if;
else
early_req_row <= req_row;

648
decode1.vhdl
Unescape Escape View File

@ -73,328 +73,328 @@ architecture behaviour of decode1 is
type decoder_rom_t is array(insn_code) of decode_rom_t;

constant decode_rom : decoder_rom_t := (
-- unit fac internal in1 in2 const in3 out CR CR inv inv cry cry ldst BR sgn upd rsrv 32b sgn rc lk priv sgl rpt
-- unit fac internal in1 in2 const in3 out res subres CR CR inv inv cry cry ldst BR sgn upd rsrv 32b sgn rc lk priv sgl rpt
-- op in out A out in out len ext pipe
INSN_illegal => (ALU, NONE, OP_ILLEGAL, NONE, IMM, NONE, NONE, NONE, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_fetch_fail => (LDST, NONE, OP_FETCH_FAILED, CIA, IMM, NONE, NONE, NONE, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),

INSN_add => (ALU, NONE, OP_ADD, RA, RB, NONE, NONE, RT, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RCOE, '0', '0', '0', NONE),
INSN_addc => (ALU, NONE, OP_ADD, RA, RB, NONE, NONE, RT, '0', '0', '0', '0', ZERO, '1', NONE, '0', '0', '0', '0', '0', '0', RCOE, '0', '0', '0', NONE),
INSN_adde => (ALU, NONE, OP_ADD, RA, RB, NONE, NONE, RT, '0', '0', '0', '0', CA, '1', NONE, '0', '0', '0', '0', '0', '0', RCOE, '0', '0', '0', NONE),
INSN_addex => (ALU, NONE, OP_ADD, RA, RB, NONE, NONE, RT, '0', '0', '0', '0', OV, '1', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0', '0', NONE),
INSN_addg6s => (ALU, NONE, OP_ADDG6S, RA, RB, NONE, NONE, RT, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_addi => (ALU, NONE, OP_ADD, RA_OR_ZERO, IMM, CONST_SI, NONE, RT, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_addic => (ALU, NONE, OP_ADD, RA, IMM, CONST_SI, NONE, RT, '0', '0', '0', '0', ZERO, '1', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_addic_dot => (ALU, NONE, OP_ADD, RA, IMM, CONST_SI, NONE, RT, '0', '0', '0', '0', ZERO, '1', NONE, '0', '0', '0', '0', '0', '0', ONE, '0', '0', '0', NONE),
INSN_addis => (ALU, NONE, OP_ADD, RA_OR_ZERO, IMM, CONST_SI_HI, NONE, RT, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_addme => (ALU, NONE, OP_ADD, RA, IMM, CONST_M1, NONE, RT, '0', '0', '0', '0', CA, '1', NONE, '0', '0', '0', '0', '0', '0', RCOE, '0', '0', '0', NONE),
INSN_addpcis => (ALU, NONE, OP_ADD, CIA, IMM, CONST_DXHI4, NONE, RT, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_addze => (ALU, NONE, OP_ADD, RA, IMM, NONE, NONE, RT, '0', '0', '0', '0', CA, '1', NONE, '0', '0', '0', '0', '0', '0', RCOE, '0', '0', '0', NONE),
INSN_and => (ALU, NONE, OP_LOGIC, NONE, RB, NONE, RS, RA, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0', '0', NONE),
INSN_andc => (ALU, NONE, OP_LOGIC, NONE, RB, NONE, RS, RA, '0', '0', '1', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0', '0', NONE),
INSN_andi_dot => (ALU, NONE, OP_LOGIC, NONE, IMM, CONST_UI, RS, RA, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', ONE, '0', '0', '0', NONE),
INSN_andis_dot => (ALU, NONE, OP_LOGIC, NONE, IMM, CONST_UI_HI, RS, RA, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', ONE, '0', '0', '0', NONE),
INSN_attn => (ALU, NONE, OP_ATTN, NONE, IMM, NONE, NONE, NONE, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '1', '1', NONE),
INSN_brel => (ALU, NONE, OP_B, CIA, IMM, CONST_LI, NONE, NONE, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '1', '0', '0', NONE),
INSN_babs => (ALU, NONE, OP_B, NONE, IMM, CONST_LI, NONE, NONE, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '1', '0', '0', NONE),
INSN_bcrel => (ALU, NONE, OP_BC, CIA, IMM, CONST_BD, NONE, NONE, '1', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '1', '0', '0', NONE),
INSN_bcabs => (ALU, NONE, OP_BC, NONE, IMM, CONST_BD, NONE, NONE, '1', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '1', '0', '0', NONE),
INSN_bcctr => (ALU, NONE, OP_BCREG, NONE, IMM, NONE, NONE, NONE, '1', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '1', '0', '0', NONE),
INSN_bclr => (ALU, NONE, OP_BCREG, NONE, IMM, NONE, NONE, NONE, '1', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '1', '0', '0', NONE),
INSN_bctar => (ALU, NONE, OP_BCREG, NONE, IMM, NONE, NONE, NONE, '1', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '1', '0', '0', NONE),
INSN_bperm => (ALU, NONE, OP_BPERM, NONE, RB, NONE, RS, RA, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_brh => (ALU, NONE, OP_BREV, NONE, IMM, NONE, RS, RA, '0', '0', '0', '0', ZERO, '0', is2B, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_brw => (ALU, NONE, OP_BREV, NONE, IMM, NONE, RS, RA, '0', '0', '0', '0', ZERO, '0', is4B, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_brd => (ALU, NONE, OP_BREV, NONE, IMM, NONE, RS, RA, '0', '0', '0', '0', ZERO, '0', is8B, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_cbcdtd => (ALU, NONE, OP_BCD, NONE, IMM, NONE, RS, RA, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_cdtbcd => (ALU, NONE, OP_BCD, NONE, IMM, NONE, RS, RA, '0', '0', '1', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_cfuged => (ALU, NONE, OP_BSORT, NONE, RB, NONE, RS, RA, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_cmp => (ALU, NONE, OP_CMP, RA, RB, NONE, NONE, NONE, '0', '1', '1', '0', ONE, '0', NONE, '0', '0', '0', '0', '0', '1', NONE, '0', '0', '0', NONE),
INSN_cmpb => (ALU, NONE, OP_CMPB, NONE, RB, NONE, RS, RA, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_cmpeqb => (ALU, NONE, OP_CMPEQB, RA, RB, NONE, NONE, NONE, '0', '1', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_cmpi => (ALU, NONE, OP_CMP, RA, IMM, CONST_SI, NONE, NONE, '0', '1', '1', '0', ONE, '0', NONE, '0', '0', '0', '0', '0', '1', NONE, '0', '0', '0', NONE),
INSN_cmpl => (ALU, NONE, OP_CMP, RA, RB, NONE, NONE, NONE, '0', '1', '1', '0', ONE, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_cmpli => (ALU, NONE, OP_CMP, RA, IMM, CONST_UI, NONE, NONE, '0', '1', '1', '0', ONE, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_cmprb => (ALU, NONE, OP_CMPRB, RA, RB, NONE, NONE, NONE, '0', '1', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_cntlzd => (ALU, NONE, OP_COUNTB, NONE, IMM, NONE, RS, RA, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0', '0', NONE),
INSN_cntlzw => (ALU, NONE, OP_COUNTB, NONE, IMM, NONE, RS, RA, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '1', '0', RC, '0', '0', '0', NONE),
INSN_cnttzd => (ALU, NONE, OP_COUNTB, NONE, IMM, NONE, RS, RA, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0', '0', NONE),
INSN_cnttzw => (ALU, NONE, OP_COUNTB, NONE, IMM, NONE, RS, RA, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '1', '0', RC, '0', '0', '0', NONE),
INSN_crand => (ALU, NONE, OP_CROP, NONE, IMM, NONE, NONE, NONE, '1', '1', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_crandc => (ALU, NONE, OP_CROP, NONE, IMM, NONE, NONE, NONE, '1', '1', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_creqv => (ALU, NONE, OP_CROP, NONE, IMM, NONE, NONE, NONE, '1', '1', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_crnand => (ALU, NONE, OP_CROP, NONE, IMM, NONE, NONE, NONE, '1', '1', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_crnor => (ALU, NONE, OP_CROP, NONE, IMM, NONE, NONE, NONE, '1', '1', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_cror => (ALU, NONE, OP_CROP, NONE, IMM, NONE, NONE, NONE, '1', '1', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_crorc => (ALU, NONE, OP_CROP, NONE, IMM, NONE, NONE, NONE, '1', '1', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_crxor => (ALU, NONE, OP_CROP, NONE, IMM, NONE, NONE, NONE, '1', '1', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_darn => (ALU, NONE, OP_DARN, NONE, IMM, NONE, NONE, RT, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_dcbf => (LDST, NONE, OP_DCBF, RA_OR_ZERO, RB, NONE, NONE, NONE, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_dcbst => (ALU, NONE, OP_DCBST, NONE, IMM, NONE, NONE, NONE, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_dcbt => (LDST, NONE, OP_LOAD, RA_OR_ZERO, RB, NONE, NONE, NONE, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_dcbtst => (LDST, NONE, OP_STORE, RA_OR_ZERO, RB, NONE, NONE, NONE, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_dcbz => (LDST, NONE, OP_DCBZ, RA_OR_ZERO, RB, NONE, NONE, NONE, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_divd => (DVU, NONE, OP_DIV, RA, RB, NONE, NONE, RT, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '1', RCOE, '0', '0', '0', NONE),
INSN_divde => (DVU, NONE, OP_DIVE, RA, RB, NONE, NONE, RT, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '1', RCOE, '0', '0', '0', NONE),
INSN_divdeu => (DVU, NONE, OP_DIVE, RA, RB, NONE, NONE, RT, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RCOE, '0', '0', '0', NONE),
INSN_divdu => (DVU, NONE, OP_DIV, RA, RB, NONE, NONE, RT, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RCOE, '0', '0', '0', NONE),
INSN_divw => (DVU, NONE, OP_DIV, RA, RB, NONE, NONE, RT, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '1', '1', RCOE, '0', '0', '0', NONE),
INSN_divwe => (DVU, NONE, OP_DIVE, RA, RB, NONE, NONE, RT, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '1', '1', RCOE, '0', '0', '0', NONE),
INSN_divweu => (DVU, NONE, OP_DIVE, RA, RB, NONE, NONE, RT, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '1', '0', RCOE, '0', '0', '0', NONE),
INSN_divwu => (DVU, NONE, OP_DIV, RA, RB, NONE, NONE, RT, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '1', '0', RCOE, '0', '0', '0', NONE),
INSN_eieio => (ALU, NONE, OP_NOP, NONE, IMM, NONE, NONE, NONE, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_eqv => (ALU, NONE, OP_XOR, NONE, RB, NONE, RS, RA, '0', '0', '0', '1', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0', '0', NONE),
INSN_extsb => (ALU, NONE, OP_EXTS, NONE, IMM, NONE, RS, RA, '0', '0', '0', '0', ZERO, '0', is1B, '0', '0', '0', '0', '0', '0', RC, '0', '0', '0', NONE),
INSN_extsh => (ALU, NONE, OP_EXTS, NONE, IMM, NONE, RS, RA, '0', '0', '0', '0', ZERO, '0', is2B, '0', '0', '0', '0', '0', '0', RC, '0', '0', '0', NONE),
INSN_extsw => (ALU, NONE, OP_EXTS, NONE, IMM, NONE, RS, RA, '0', '0', '0', '0', ZERO, '0', is4B, '0', '0', '0', '0', '0', '0', RC, '0', '0', '0', NONE),
INSN_extswsli => (ALU, NONE, OP_EXTSWSLI, NONE, IMM, CONST_SH, RS, RA, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0', '0', NONE),
INSN_fabs => (FPU, FPU, OP_FP_MOVE, NONE, FRB, NONE, NONE, FRT, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0', '0', NONE),
INSN_fadd => (FPU, FPU, OP_FP_ARITH, FRA, FRB, NONE, NONE, FRT, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0', '0', NONE),
INSN_fadds => (FPU, FPU, OP_FP_ARITH, FRA, FRB, NONE, NONE, FRT, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '1', '0', RC, '0', '0', '0', NONE),
INSN_fcfid => (FPU, FPU, OP_FP_MISC, NONE, FRB, NONE, NONE, FRT, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '1', RC, '0', '0', '0', NONE),
INSN_fcfids => (FPU, FPU, OP_FP_MISC, NONE, FRB, NONE, NONE, FRT, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '1', '1', RC, '0', '0', '0', NONE),
INSN_fcfidu => (FPU, FPU, OP_FP_MISC, NONE, FRB, NONE, NONE, FRT, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0', '0', NONE),
INSN_fcfidus => (FPU, FPU, OP_FP_MISC, NONE, FRB, NONE, NONE, FRT, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '1', '0', RC, '0', '0', '0', NONE),
INSN_fcmpo => (FPU, FPU, OP_FP_CMP, FRA, FRB, NONE, NONE, NONE, '0', '1', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_fcmpu => (FPU, FPU, OP_FP_CMP, FRA, FRB, NONE, NONE, NONE, '0', '1', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_fcpsgn => (FPU, FPU, OP_FP_MOVE, FRA, FRB, NONE, NONE, FRT, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0', '0', NONE),
INSN_fctid => (FPU, FPU, OP_FP_ARITH, NONE, FRB, NONE, NONE, FRT, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0', '0', NONE),
INSN_fctidu => (FPU, FPU, OP_FP_ARITH, NONE, FRB, NONE, NONE, FRT, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0', '0', NONE),
INSN_fctiduz => (FPU, FPU, OP_FP_ARITH, NONE, FRB, NONE, NONE, FRT, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0', '0', NONE),
INSN_fctidz => (FPU, FPU, OP_FP_ARITH, NONE, FRB, NONE, NONE, FRT, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0', '0', NONE),
INSN_fctiw => (FPU, FPU, OP_FP_ARITH, NONE, FRB, NONE, NONE, FRT, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0', '0', NONE),
INSN_fctiwu => (FPU, FPU, OP_FP_ARITH, NONE, FRB, NONE, NONE, FRT, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0', '0', NONE),
INSN_fctiwuz => (FPU, FPU, OP_FP_ARITH, NONE, FRB, NONE, NONE, FRT, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0', '0', NONE),
INSN_fctiwz => (FPU, FPU, OP_FP_ARITH, NONE, FRB, NONE, NONE, FRT, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0', '0', NONE),
INSN_fdiv => (FPU, FPU, OP_FP_ARITH, FRA, FRB, NONE, NONE, FRT, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0', '0', NONE),
INSN_fdivs => (FPU, FPU, OP_FP_ARITH, FRA, FRB, NONE, NONE, FRT, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '1', '0', RC, '0', '0', '0', NONE),
INSN_fmadd => (FPU, FPU, OP_FP_ARITH, FRA, FRB, NONE, FRC, FRT, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0', '0', NONE),
INSN_fmadds => (FPU, FPU, OP_FP_ARITH, FRA, FRB, NONE, FRC, FRT, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '1', '0', RC, '0', '0', '0', NONE),
INSN_fmr => (FPU, FPU, OP_FP_MOVE, NONE, FRB, NONE, NONE, FRT, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0', '0', NONE),
INSN_fmrgew => (FPU, FPU, OP_FP_MISC, FRA, FRB, NONE, NONE, FRT, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_fmrgow => (FPU, FPU, OP_FP_MISC, FRA, FRB, NONE, NONE, FRT, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_fmsub => (FPU, FPU, OP_FP_ARITH, FRA, FRB, NONE, FRC, FRT, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0', '0', NONE),
INSN_fmsubs => (FPU, FPU, OP_FP_ARITH, FRA, FRB, NONE, FRC, FRT, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '1', '0', RC, '0', '0', '0', NONE),
INSN_fmul => (FPU, FPU, OP_FP_ARITH, FRA, IMM, NONE, FRC, FRT, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0', '0', NONE),
INSN_fmuls => (FPU, FPU, OP_FP_ARITH, FRA, IMM, NONE, FRC, FRT, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '1', '0', RC, '0', '0', '0', NONE),
INSN_fnabs => (FPU, FPU, OP_FP_MOVE, NONE, FRB, NONE, NONE, FRT, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0', '0', NONE),
INSN_fneg => (FPU, FPU, OP_FP_MOVE, NONE, FRB, NONE, NONE, FRT, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0', '0', NONE),
INSN_fnmadd => (FPU, FPU, OP_FP_ARITH, FRA, FRB, NONE, FRC, FRT, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0', '0', NONE),
INSN_fnmadds => (FPU, FPU, OP_FP_ARITH, FRA, FRB, NONE, FRC, FRT, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '1', '0', RC, '0', '0', '0', NONE),
INSN_fnmsub => (FPU, FPU, OP_FP_ARITH, FRA, FRB, NONE, FRC, FRT, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0', '0', NONE),
INSN_fnmsubs => (FPU, FPU, OP_FP_ARITH, FRA, FRB, NONE, FRC, FRT, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '1', '0', RC, '0', '0', '0', NONE),
INSN_fre => (FPU, FPU, OP_FP_ARITH, NONE, FRB, NONE, NONE, FRT, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0', '0', NONE),
INSN_fres => (FPU, FPU, OP_FP_ARITH, NONE, FRB, NONE, NONE, FRT, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '1', '0', RC, '0', '0', '0', NONE),
INSN_frim => (FPU, FPU, OP_FP_ARITH, NONE, FRB, NONE, NONE, FRT, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0', '0', NONE),
INSN_frin => (FPU, FPU, OP_FP_ARITH, NONE, FRB, NONE, NONE, FRT, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0', '0', NONE),
INSN_frip => (FPU, FPU, OP_FP_ARITH, NONE, FRB, NONE, NONE, FRT, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0', '0', NONE),
INSN_friz => (FPU, FPU, OP_FP_ARITH, NONE, FRB, NONE, NONE, FRT, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0', '0', NONE),
INSN_frsp => (FPU, FPU, OP_FP_ARITH, NONE, FRB, NONE, NONE, FRT, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '1', '0', RC, '0', '0', '0', NONE),
INSN_frsqrte => (FPU, FPU, OP_FP_ARITH, NONE, FRB, NONE, NONE, FRT, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0', '0', NONE),
INSN_frsqrtes => (FPU, FPU, OP_FP_ARITH, NONE, FRB, NONE, NONE, FRT, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '1', '0', RC, '0', '0', '0', NONE),
INSN_fsel => (FPU, FPU, OP_FP_MOVE, FRA, FRB, NONE, FRC, FRT, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0', '0', NONE),
INSN_fsqrt => (FPU, FPU, OP_FP_ARITH, NONE, FRB, NONE, NONE, FRT, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0', '0', NONE),
INSN_fsqrts => (FPU, FPU, OP_FP_ARITH, NONE, FRB, NONE, NONE, FRT, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '1', '0', RC, '0', '0', '0', NONE),
INSN_fsub => (FPU, FPU, OP_FP_ARITH, FRA, FRB, NONE, NONE, FRT, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0', '0', NONE),
INSN_fsubs => (FPU, FPU, OP_FP_ARITH, FRA, FRB, NONE, NONE, FRT, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '1', '0', RC, '0', '0', '0', NONE),
INSN_ftdiv => (FPU, FPU, OP_FP_CMP, FRA, FRB, NONE, NONE, NONE, '0', '1', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_ftsqrt => (FPU, FPU, OP_FP_CMP, NONE, FRB, NONE, NONE, NONE, '0', '1', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_hashchk => (LDST, NONE, OP_LOAD, RA, IMM, CONST_DSX, RBC, NONE, '0', '0', '0', '0', ZERO, '0', is8B, '0', '0', '0', '0', '0', '1', NONE, '0', '0', '0', NONE),
INSN_hashchkp => (LDST, NONE, OP_LOAD, RA, IMM, CONST_DSX, RBC, NONE, '0', '0', '0', '0', ZERO, '0', is8B, '0', '0', '0', '0', '0', '1', NONE, '0', '1', '0', NONE),
INSN_hashst => (LDST, NONE, OP_STORE, RA, IMM, CONST_DSX, RBC, NONE, '0', '0', '0', '0', ZERO, '0', is8B, '0', '0', '0', '0', '0', '1', NONE, '0', '0', '0', NONE),
INSN_hashstp => (LDST, NONE, OP_STORE, RA, IMM, CONST_DSX, RBC, NONE, '0', '0', '0', '0', ZERO, '0', is8B, '0', '0', '0', '0', '0', '1', NONE, '0', '1', '0', NONE),
INSN_icbi => (ALU, NONE, OP_ICBI, NONE, IMM, NONE, NONE, NONE, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '1', NONE),
INSN_icbt => (ALU, NONE, OP_ICBT, NONE, IMM, NONE, NONE, NONE, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_isel => (ALU, NONE, OP_ISEL, RA_OR_ZERO, RB, NONE, NONE, RT, '1', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_isync => (ALU, NONE, OP_ISYNC, NONE, IMM, NONE, NONE, NONE, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_lbarx => (LDST, NONE, OP_LOAD, RA_OR_ZERO, RB, NONE, NONE, RT, '0', '0', '0', '0', ZERO, '0', is1B, '0', '0', '0', '1', '0', '0', NONE, '0', '0', '0', NONE),
INSN_lbz => (LDST, NONE, OP_LOAD, RA_OR_ZERO, IMM, CONST_SI, NONE, RT, '0', '0', '0', '0', ZERO, '0', is1B, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_lbzcix => (LDST, NONE, OP_LOAD, RA_OR_ZERO, RB, NONE, NONE, RT, '0', '0', '1', '0', ZERO, '0', is1B, '0', '0', '0', '0', '0', '0', NONE, '0', '1', '0', NONE),
INSN_lbzu => (LDST, NONE, OP_LOAD, RA_OR_ZERO, IMM, CONST_SI, NONE, RT, '0', '0', '0', '0', ZERO, '0', is1B, '0', '0', '1', '0', '0', '0', NONE, '0', '0', '0', DUPD),
INSN_lbzux => (LDST, NONE, OP_LOAD, RA_OR_ZERO, RB, NONE, NONE, RT, '0', '0', '0', '0', ZERO, '0', is1B, '0', '0', '1', '0', '0', '0', NONE, '0', '0', '0', DUPD),
INSN_lbzx => (LDST, NONE, OP_LOAD, RA_OR_ZERO, RB, NONE, NONE, RT, '0', '0', '0', '0', ZERO, '0', is1B, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_ld => (LDST, NONE, OP_LOAD, RA_OR_ZERO, IMM, CONST_DS, NONE, RT, '0', '0', '0', '0', ZERO, '0', is8B, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_ldarx => (LDST, NONE, OP_LOAD, RA_OR_ZERO, RB, NONE, NONE, RT, '0', '0', '0', '0', ZERO, '0', is8B, '0', '0', '0', '1', '0', '0', NONE, '0', '0', '0', NONE),
INSN_ldbrx => (LDST, NONE, OP_LOAD, RA_OR_ZERO, RB, NONE, NONE, RT, '0', '0', '0', '0', ZERO, '0', is8B, '1', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_ldcix => (LDST, NONE, OP_LOAD, RA_OR_ZERO, RB, NONE, NONE, RT, '0', '0', '1', '0', ZERO, '0', is8B, '0', '0', '0', '0', '0', '0', NONE, '0', '1', '0', NONE),
INSN_ldu => (LDST, NONE, OP_LOAD, RA_OR_ZERO, IMM, CONST_DS, NONE, RT, '0', '0', '0', '0', ZERO, '0', is8B, '0', '0', '1', '0', '0', '0', NONE, '0', '0', '0', DUPD),
INSN_ldux => (LDST, NONE, OP_LOAD, RA_OR_ZERO, RB, NONE, NONE, RT, '0', '0', '0', '0', ZERO, '0', is8B, '0', '0', '1', '0', '0', '0', NONE, '0', '0', '0', DUPD),
INSN_ldx => (LDST, NONE, OP_LOAD, RA_OR_ZERO, RB, NONE, NONE, RT, '0', '0', '0', '0', ZERO, '0', is8B, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_lfd => (LDST, FPU, OP_LOAD, RA_OR_ZERO, IMM, CONST_SI, NONE, FRT, '0', '0', '0', '0', ZERO, '0', is8B, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_lfdu => (LDST, FPU, OP_LOAD, RA_OR_ZERO, IMM, CONST_SI, NONE, FRT, '0', '0', '0', '0', ZERO, '0', is8B, '0', '0', '1', '0', '0', '0', NONE, '0', '0', '0', DUPD),
INSN_lfdux => (LDST, FPU, OP_LOAD, RA_OR_ZERO, RB, NONE, NONE, FRT, '0', '0', '0', '0', ZERO, '0', is8B, '0', '0', '1', '0', '0', '0', NONE, '0', '0', '0', DUPD),
INSN_lfdx => (LDST, FPU, OP_LOAD, RA_OR_ZERO, RB, NONE, NONE, FRT, '0', '0', '0', '0', ZERO, '0', is8B, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_lfiwax => (LDST, FPU, OP_LOAD, RA_OR_ZERO, RB, NONE, NONE, FRT, '0', '0', '0', '0', ZERO, '0', is4B, '0', '1', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_lfiwzx => (LDST, FPU, OP_LOAD, RA_OR_ZERO, RB, NONE, NONE, FRT, '0', '0', '0', '0', ZERO, '0', is4B, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_lfs => (LDST, FPU, OP_LOAD, RA_OR_ZERO, IMM, CONST_SI, NONE, FRT, '0', '0', '0', '0', ZERO, '0', is4B, '0', '0', '0', '0', '1', '0', NONE, '0', '0', '0', NONE),
INSN_lfsu => (LDST, FPU, OP_LOAD, RA_OR_ZERO, IMM, CONST_SI, NONE, FRT, '0', '0', '0', '0', ZERO, '0', is4B, '0', '0', '1', '0', '1', '0', NONE, '0', '0', '0', DUPD),
INSN_lfsux => (LDST, FPU, OP_LOAD, RA_OR_ZERO, RB, NONE, NONE, FRT, '0', '0', '0', '0', ZERO, '0', is4B, '0', '0', '1', '0', '1', '0', NONE, '0', '0', '0', DUPD),
INSN_lfsx => (LDST, FPU, OP_LOAD, RA_OR_ZERO, RB, NONE, NONE, FRT, '0', '0', '0', '0', ZERO, '0', is4B, '0', '0', '0', '0', '1', '0', NONE, '0', '0', '0', NONE),
INSN_lha => (LDST, NONE, OP_LOAD, RA_OR_ZERO, IMM, CONST_SI, NONE, RT, '0', '0', '0', '0', ZERO, '0', is2B, '0', '1', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_lharx => (LDST, NONE, OP_LOAD, RA_OR_ZERO, RB, NONE, NONE, RT, '0', '0', '0', '0', ZERO, '0', is2B, '0', '0', '0', '1', '0', '0', NONE, '0', '0', '0', NONE),
INSN_lhau => (LDST, NONE, OP_LOAD, RA_OR_ZERO, IMM, CONST_SI, NONE, RT, '0', '0', '0', '0', ZERO, '0', is2B, '0', '1', '1', '0', '0', '0', NONE, '0', '0', '0', DUPD),
INSN_lhaux => (LDST, NONE, OP_LOAD, RA_OR_ZERO, RB, NONE, NONE, RT, '0', '0', '0', '0', ZERO, '0', is2B, '0', '1', '1', '0', '0', '0', NONE, '0', '0', '0', DUPD),
INSN_lhax => (LDST, NONE, OP_LOAD, RA_OR_ZERO, RB, NONE, NONE, RT, '0', '0', '0', '0', ZERO, '0', is2B, '0', '1', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_lhbrx => (LDST, NONE, OP_LOAD, RA_OR_ZERO, RB, NONE, NONE, RT, '0', '0', '0', '0', ZERO, '0', is2B, '1', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_lhz => (LDST, NONE, OP_LOAD, RA_OR_ZERO, IMM, CONST_SI, NONE, RT, '0', '0', '0', '0', ZERO, '0', is2B, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_lhzcix => (LDST, NONE, OP_LOAD, RA_OR_ZERO, RB, NONE, NONE, RT, '0', '0', '1', '0', ZERO, '0', is2B, '0', '0', '0', '0', '0', '0', NONE, '0', '1', '0', NONE),
INSN_lhzu => (LDST, NONE, OP_LOAD, RA_OR_ZERO, IMM, CONST_SI, NONE, RT, '0', '0', '0', '0', ZERO, '0', is2B, '0', '0', '1', '0', '0', '0', NONE, '0', '0', '0', DUPD),
INSN_lhzux => (LDST, NONE, OP_LOAD, RA_OR_ZERO, RB, NONE, NONE, RT, '0', '0', '0', '0', ZERO, '0', is2B, '0', '0', '1', '0', '0', '0', NONE, '0', '0', '0', DUPD),
INSN_lhzx => (LDST, NONE, OP_LOAD, RA_OR_ZERO, RB, NONE, NONE, RT, '0', '0', '0', '0', ZERO, '0', is2B, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_lq => (LDST, NONE, OP_LOAD, RA_OR_ZERO, IMM, CONST_DQ, NONE, RT, '0', '0', '0', '0', ZERO, '0', is8B, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', DRTP),
INSN_lqarx => (LDST, NONE, OP_LOAD, RA_OR_ZERO, RB, NONE, NONE, RT, '0', '0', '0', '0', ZERO, '0', is8B, '0', '0', '0', '1', '0', '0', NONE, '0', '0', '0', DRTP),
INSN_lwa => (LDST, NONE, OP_LOAD, RA_OR_ZERO, IMM, CONST_DS, NONE, RT, '0', '0', '0', '0', ZERO, '0', is4B, '0', '1', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_lwarx => (LDST, NONE, OP_LOAD, RA_OR_ZERO, RB, NONE, NONE, RT, '0', '0', '0', '0', ZERO, '0', is4B, '0', '0', '0', '1', '0', '0', NONE, '0', '0', '0', NONE),
INSN_lwaux => (LDST, NONE, OP_LOAD, RA_OR_ZERO, RB, NONE, NONE, RT, '0', '0', '0', '0', ZERO, '0', is4B, '0', '1', '1', '0', '0', '0', NONE, '0', '0', '0', DUPD),
INSN_lwax => (LDST, NONE, OP_LOAD, RA_OR_ZERO, RB, NONE, NONE, RT, '0', '0', '0', '0', ZERO, '0', is4B, '0', '1', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_lwbrx => (LDST, NONE, OP_LOAD, RA_OR_ZERO, RB, NONE, NONE, RT, '0', '0', '0', '0', ZERO, '0', is4B, '1', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_lwz => (LDST, NONE, OP_LOAD, RA_OR_ZERO, IMM, CONST_SI, NONE, RT, '0', '0', '0', '0', ZERO, '0', is4B, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_lwzcix => (LDST, NONE, OP_LOAD, RA_OR_ZERO, RB, NONE, NONE, RT, '0', '0', '1', '0', ZERO, '0', is4B, '0', '0', '0', '0', '0', '0', NONE, '0', '1', '0', NONE),
INSN_lwzu => (LDST, NONE, OP_LOAD, RA_OR_ZERO, IMM, CONST_SI, NONE, RT, '0', '0', '0', '0', ZERO, '0', is4B, '0', '0', '1', '0', '0', '0', NONE, '0', '0', '0', DUPD),
INSN_lwzux => (LDST, NONE, OP_LOAD, RA_OR_ZERO, RB, NONE, NONE, RT, '0', '0', '0', '0', ZERO, '0', is4B, '0', '0', '1', '0', '0', '0', NONE, '0', '0', '0', DUPD),
INSN_lwzx => (LDST, NONE, OP_LOAD, RA_OR_ZERO, RB, NONE, NONE, RT, '0', '0', '0', '0', ZERO, '0', is4B, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_maddhd => (ALU, NONE, OP_MUL_H64, RA, RB, NONE, RCR, RT, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '1', NONE, '0', '0', '0', NONE),
INSN_maddhdu => (ALU, NONE, OP_MUL_H64, RA, RB, NONE, RCR, RT, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_maddld => (ALU, NONE, OP_MUL_L64, RA, RB, NONE, RCR, RT, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '1', NONE, '0', '0', '0', NONE),
INSN_mcrf => (ALU, NONE, OP_CROP, NONE, IMM, NONE, NONE, NONE, '1', '1', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_mcrfs => (FPU, FPU, OP_FP_CMP, NONE, IMM, NONE, NONE, NONE, '0', '1', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_mcrxrx => (ALU, NONE, OP_MCRXRX, NONE, IMM, NONE, NONE, NONE, '0', '1', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_mfcr => (ALU, NONE, OP_MFCR, NONE, IMM, NONE, NONE, RT, '1', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_mffs => (FPU, FPU, OP_FP_MISC, NONE, FRB, NONE, NONE, FRT, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0', '0', NONE),
INSN_mfmsr => (ALU, NONE, OP_MFMSR, NONE, IMM, NONE, NONE, RT, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '1', '1', NONE),
INSN_mfspr => (ALU, NONE, OP_MFSPR, NONE, IMM, NONE, RS, RT, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_modsd => (DVU, NONE, OP_MOD, RA, RB, NONE, NONE, RT, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '1', NONE, '0', '0', '0', NONE),
INSN_modsw => (DVU, NONE, OP_MOD, RA, RB, NONE, NONE, RT, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '1', '1', NONE, '0', '0', '0', NONE),
INSN_modud => (DVU, NONE, OP_MOD, RA, RB, NONE, NONE, RT, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_moduw => (DVU, NONE, OP_MOD, RA, RB, NONE, NONE, RT, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '1', '0', NONE, '0', '0', '0', NONE),
INSN_mtcrf => (ALU, NONE, OP_MTCRF, NONE, IMM, NONE, RS, NONE, '0', '1', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_mtfsb => (FPU, FPU, OP_FP_MISC, NONE, IMM, NONE, NONE, NONE, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0', '0', NONE),
INSN_mtfsf => (FPU, FPU, OP_FP_MISC, NONE, FRB, NONE, NONE, NONE, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0', '0', NONE),
INSN_mtfsfi => (FPU, FPU, OP_FP_MISC, NONE, IMM, NONE, NONE, NONE, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0', '0', NONE),
INSN_mtmsr => (ALU, NONE, OP_MTMSRD, NONE, IMM, NONE, RS, NONE, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '1', '0', NONE, '0', '1', '0', NONE),
INSN_mtmsrd => (ALU, NONE, OP_MTMSRD, NONE, IMM, NONE, RS, NONE, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '1', '0', NONE),
INSN_mtspr => (ALU, NONE, OP_MTSPR, NONE, IMM, NONE, RS, NONE, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_mulhd => (ALU, NONE, OP_MUL_H64, RA, RB, NONE, NONE, RT, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '1', RC, '0', '0', '0', NONE),
INSN_mulhdu => (ALU, NONE, OP_MUL_H64, RA, RB, NONE, NONE, RT, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0', '0', NONE),
INSN_mulhw => (ALU, NONE, OP_MUL_H32, RA, RB, NONE, NONE, RT, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '1', '1', RC, '0', '0', '0', NONE),
INSN_mulhwu => (ALU, NONE, OP_MUL_H32, RA, RB, NONE, NONE, RT, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '1', '0', RC, '0', '0', '0', NONE),
INSN_mulld => (ALU, NONE, OP_MUL_L64, RA, RB, NONE, NONE, RT, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '1', RCOE, '0', '0', '0', NONE),
INSN_mulli => (ALU, NONE, OP_MUL_L64, RA, IMM, CONST_SI, NONE, RT, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '1', NONE, '0', '0', '0', NONE),
INSN_mullw => (ALU, NONE, OP_MUL_L64, RA, RB, NONE, NONE, RT, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '1', '1', RCOE, '0', '0', '0', NONE),
INSN_nand => (ALU, NONE, OP_LOGIC, NONE, RB, NONE, RS, RA, '0', '0', '0', '1', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0', '0', NONE),
INSN_neg => (ALU, NONE, OP_ADD, RA, IMM, NONE, NONE, RT, '0', '0', '1', '0', ONE, '0', NONE, '0', '0', '0', '0', '0', '0', RCOE, '0', '0', '0', NONE),
INSN_nop => (ALU, NONE, OP_NOP, NONE, IMM, NONE, NONE, NONE, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_nor => (ALU, NONE, OP_LOGIC, NONE, RB, NONE, RS, RA, '0', '0', '1', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '1', RC, '0', '0', '0', NONE),
INSN_or => (ALU, NONE, OP_LOGIC, NONE, RB, NONE, RS, RA, '0', '0', '1', '1', ZERO, '0', NONE, '0', '0', '0', '0', '0', '1', RC, '0', '0', '0', NONE),
INSN_orc => (ALU, NONE, OP_LOGIC, NONE, RB, NONE, RS, RA, '0', '0', '0', '1', ZERO, '0', NONE, '0', '0', '0', '0', '0', '1', RC, '0', '0', '0', NONE),
INSN_ori => (ALU, NONE, OP_LOGIC, NONE, IMM, CONST_UI, RS, RA, '0', '0', '1', '1', ZERO, '0', NONE, '0', '0', '0', '0', '0', '1', NONE, '0', '0', '0', NONE),
INSN_oris => (ALU, NONE, OP_LOGIC, NONE, IMM, CONST_UI_HI, RS, RA, '0', '0', '1', '1', ZERO, '0', NONE, '0', '0', '0', '0', '0', '1', NONE, '0', '0', '0', NONE),
INSN_paddi => (ALU, NONE, OP_ADD, RA0_OR_CIA, IMM, CONST_PSI, NONE, RT, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_pdepd => (ALU, NONE, OP_BSORT, NONE, RB, NONE, RS, RA, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_pextd => (ALU, NONE, OP_BSORT, NONE, RB, NONE, RS, RA, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_plbz => (LDST, NONE, OP_LOAD, RA0_OR_CIA, IMM, CONST_PSI, NONE, RT, '0', '0', '0', '0', ZERO, '0', is1B, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_pld => (LDST, NONE, OP_LOAD, RA0_OR_CIA, IMM, CONST_PSI, NONE, RT, '0', '0', '0', '0', ZERO, '0', is8B, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_plfd => (LDST, FPU, OP_LOAD, RA0_OR_CIA, IMM, CONST_PSI, NONE, FRT, '0', '0', '0', '0', ZERO, '0', is8B, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_plfs => (LDST, FPU, OP_LOAD, RA0_OR_CIA, IMM, CONST_PSI, NONE, FRT, '0', '0', '0', '0', ZERO, '0', is4B, '0', '0', '0', '0', '1', '0', NONE, '0', '0', '0', NONE),
INSN_plha => (LDST, NONE, OP_LOAD, RA0_OR_CIA, IMM, CONST_PSI, NONE, RT, '0', '0', '0', '0', ZERO, '0', is2B, '0', '1', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_plhz => (LDST, NONE, OP_LOAD, RA0_OR_CIA, IMM, CONST_PSI, NONE, RT, '0', '0', '0', '0', ZERO, '0', is2B, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_plq => (LDST, NONE, OP_LOAD, RA0_OR_CIA, IMM, CONST_PSI, NONE, RT, '0', '0', '0', '0', ZERO, '0', is8B, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', DRTP),
INSN_plwa => (LDST, NONE, OP_LOAD, RA0_OR_CIA, IMM, CONST_PSI, NONE, RT, '0', '0', '0', '0', ZERO, '0', is4B, '0', '1', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_plwz => (LDST, NONE, OP_LOAD, RA0_OR_CIA, IMM, CONST_PSI, NONE, RT, '0', '0', '0', '0', ZERO, '0', is4B, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_pnop => (ALU, NONE, OP_NOP, NONE, IMM, NONE, NONE, NONE, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_pstb => (LDST, NONE, OP_STORE, RA0_OR_CIA, IMM, CONST_PSI, RS, NONE, '0', '0', '0', '0', ZERO, '0', is1B, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_pstd => (LDST, NONE, OP_STORE, RA0_OR_CIA, IMM, CONST_PSI, RS, NONE, '0', '0', '0', '0', ZERO, '0', is8B, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_pstfd => (LDST, FPU, OP_STORE, RA0_OR_CIA, IMM, CONST_PSI, FRS, NONE, '0', '0', '0', '0', ZERO, '0', is8B, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_pstfs => (LDST, FPU, OP_STORE, RA0_OR_CIA, IMM, CONST_PSI, FRS, NONE, '0', '0', '0', '0', ZERO, '0', is4B, '0', '0', '0', '0', '1', '0', NONE, '0', '0', '0', NONE),
INSN_psth => (LDST, NONE, OP_STORE, RA0_OR_CIA, IMM, CONST_PSI, RS, NONE, '0', '0', '0', '0', ZERO, '0', is2B, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_pstq => (LDST, NONE, OP_STORE, RA0_OR_CIA, IMM, CONST_PSI, RS, NONE, '0', '0', '0', '0', ZERO, '0', is8B, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', DRSP),
INSN_pstw => (LDST, NONE, OP_STORE, RA0_OR_CIA, IMM, CONST_PSI, RS, NONE, '0', '0', '0', '0', ZERO, '0', is4B, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_popcntb => (ALU, NONE, OP_COUNTB, NONE, IMM, NONE, RS, RA, '0', '0', '0', '0', ZERO, '0', is1B, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_popcntd => (ALU, NONE, OP_COUNTB, NONE, IMM, NONE, RS, RA, '0', '0', '0', '0', ZERO, '0', is8B, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_popcntw => (ALU, NONE, OP_COUNTB, NONE, IMM, NONE, RS, RA, '0', '0', '0', '0', ZERO, '0', is4B, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_prtyd => (ALU, NONE, OP_PRTY, NONE, IMM, NONE, RS, RA, '0', '0', '0', '0', ZERO, '0', is8B, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_prtyw => (ALU, NONE, OP_PRTY, NONE, IMM, NONE, RS, RA, '0', '0', '0', '0', ZERO, '0', is4B, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_rfid => (ALU, NONE, OP_RFID, NONE, IMM, NONE, NONE, NONE, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '1', '0', NONE),
INSN_rfscv => (ALU, NONE, OP_RFID, NONE, IMM, NONE, NONE, NONE, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '1', '0', NONE),
INSN_rldcl => (ALU, NONE, OP_RLCL, NONE, RB, NONE, RS, RA, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0', '0', NONE),
INSN_rldcr => (ALU, NONE, OP_RLCR, NONE, RB, NONE, RS, RA, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0', '0', NONE),
INSN_rldic => (ALU, NONE, OP_RLC, NONE, IMM, CONST_SH, RS, RA, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0', '0', NONE),
INSN_rldicl => (ALU, NONE, OP_RLCL, NONE, IMM, CONST_SH, RS, RA, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0', '0', NONE),
INSN_rldicr => (ALU, NONE, OP_RLCR, NONE, IMM, CONST_SH, RS, RA, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0', '0', NONE),
INSN_rldimi => (ALU, NONE, OP_RLC, RA, IMM, CONST_SH, RS, RA, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0', '0', NONE),
INSN_rlwimi => (ALU, NONE, OP_RLC, RA, IMM, CONST_SH32, RS, RA, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '1', '0', RC, '0', '0', '0', NONE),
INSN_rlwinm => (ALU, NONE, OP_RLC, NONE, IMM, CONST_SH32, RS, RA, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '1', '0', RC, '0', '0', '0', NONE),
INSN_rlwnm => (ALU, NONE, OP_RLC, NONE, RB, NONE, RS, RA, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '1', '0', RC, '0', '0', '0', NONE),
INSN_rnop => (ALU, NONE, OP_NOP, NONE, IMM, NONE, NONE, NONE, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_sc => (ALU, NONE, OP_SC, NONE, IMM, NONE, NONE, NONE, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_setb => (ALU, NONE, OP_SETB, NONE, IMM, NONE, NONE, RT, '1', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_slbia => (LDST, NONE, OP_TLBIE, NONE, IMM, NONE, NONE, NONE, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '1', '0', NONE),
INSN_sld => (ALU, NONE, OP_SHL, NONE, RB, NONE, RS, RA, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0', '0', NONE),
INSN_slw => (ALU, NONE, OP_SHL, NONE, RB, NONE, RS, RA, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '1', '0', RC, '0', '0', '0', NONE),
INSN_srad => (ALU, NONE, OP_SHR, NONE, RB, NONE, RS, RA, '0', '0', '0', '0', ZERO, '1', NONE, '0', '0', '0', '0', '0', '1', RC, '0', '0', '0', NONE),
INSN_sradi => (ALU, NONE, OP_SHR, NONE, IMM, CONST_SH, RS, RA, '0', '0', '0', '0', ZERO, '1', NONE, '0', '0', '0', '0', '0', '1', RC, '0', '0', '0', NONE),
INSN_sraw => (ALU, NONE, OP_SHR, NONE, RB, NONE, RS, RA, '0', '0', '0', '0', ZERO, '1', NONE, '0', '0', '0', '0', '1', '1', RC, '0', '0', '0', NONE),
INSN_srawi => (ALU, NONE, OP_SHR, NONE, IMM, CONST_SH32, RS, RA, '0', '0', '0', '0', ZERO, '1', NONE, '0', '0', '0', '0', '1', '1', RC, '0', '0', '0', NONE),
INSN_srd => (ALU, NONE, OP_SHR, NONE, RB, NONE, RS, RA, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0', '0', NONE),
INSN_srw => (ALU, NONE, OP_SHR, NONE, RB, NONE, RS, RA, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '1', '0', RC, '0', '0', '0', NONE),
INSN_stb => (LDST, NONE, OP_STORE, RA_OR_ZERO, IMM, CONST_SI, RS, NONE, '0', '0', '0', '0', ZERO, '0', is1B, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_stbcix => (LDST, NONE, OP_STORE, RA_OR_ZERO, RB, NONE, RS, NONE, '0', '0', '1', '0', ZERO, '0', is1B, '0', '0', '0', '0', '0', '0', NONE, '0', '1', '0', NONE),
INSN_stbcx => (LDST, NONE, OP_STORE, RA_OR_ZERO, RB, NONE, RS, NONE, '0', '0', '0', '0', ZERO, '0', is1B, '0', '0', '0', '1', '0', '0', ONE, '0', '0', '0', NONE),
INSN_stbu => (LDST, NONE, OP_STORE, RA_OR_ZERO, IMM, CONST_SI, RS, RA, '0', '0', '0', '0', ZERO, '0', is1B, '0', '0', '1', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_stbux => (LDST, NONE, OP_STORE, RA_OR_ZERO, RB, NONE, RS, RA, '0', '0', '0', '0', ZERO, '0', is1B, '0', '0', '1', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_stbx => (LDST, NONE, OP_STORE, RA_OR_ZERO, RB, NONE, RS, NONE, '0', '0', '0', '0', ZERO, '0', is1B, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_std => (LDST, NONE, OP_STORE, RA_OR_ZERO, IMM, CONST_DS, RS, NONE, '0', '0', '0', '0', ZERO, '0', is8B, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_stdbrx => (LDST, NONE, OP_STORE, RA_OR_ZERO, RB, NONE, RS, NONE, '0', '0', '0', '0', ZERO, '0', is8B, '1', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_stdcix => (LDST, NONE, OP_STORE, RA_OR_ZERO, RB, NONE, RS, NONE, '0', '0', '1', '0', ZERO, '0', is8B, '0', '0', '0', '0', '0', '0', NONE, '0', '1', '0', NONE),
INSN_stdcx => (LDST, NONE, OP_STORE, RA_OR_ZERO, RB, NONE, RS, NONE, '0', '0', '0', '0', ZERO, '0', is8B, '0', '0', '0', '1', '0', '0', ONE, '0', '0', '0', NONE),
INSN_stdu => (LDST, NONE, OP_STORE, RA_OR_ZERO, IMM, CONST_DS, RS, RA, '0', '0', '0', '0', ZERO, '0', is8B, '0', '0', '1', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_stdux => (LDST, NONE, OP_STORE, RA_OR_ZERO, RB, NONE, RS, RA, '0', '0', '0', '0', ZERO, '0', is8B, '0', '0', '1', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_stdx => (LDST, NONE, OP_STORE, RA_OR_ZERO, RB, NONE, RS, NONE, '0', '0', '0', '0', ZERO, '0', is8B, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_stfd => (LDST, FPU, OP_STORE, RA_OR_ZERO, IMM, CONST_SI, FRS, NONE, '0', '0', '0', '0', ZERO, '0', is8B, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_stfdu => (LDST, FPU, OP_STORE, RA_OR_ZERO, IMM, CONST_SI, FRS, RA, '0', '0', '0', '0', ZERO, '0', is8B, '0', '0', '1', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_stfdux => (LDST, FPU, OP_STORE, RA_OR_ZERO, RB, NONE, FRS, RA, '0', '0', '0', '0', ZERO, '0', is8B, '0', '0', '1', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_stfdx => (LDST, FPU, OP_STORE, RA_OR_ZERO, RB, NONE, FRS, NONE, '0', '0', '0', '0', ZERO, '0', is8B, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_stfiwx => (LDST, FPU, OP_STORE, RA_OR_ZERO, RB, NONE, FRS, NONE, '0', '0', '0', '0', ZERO, '0', is4B, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_stfs => (LDST, FPU, OP_STORE, RA_OR_ZERO, IMM, CONST_SI, FRS, NONE, '0', '0', '0', '0', ZERO, '0', is4B, '0', '0', '0', '0', '1', '0', NONE, '0', '0', '0', NONE),
INSN_stfsu => (LDST, FPU, OP_STORE, RA_OR_ZERO, IMM, CONST_SI, FRS, RA, '0', '0', '0', '0', ZERO, '0', is4B, '0', '0', '1', '0', '1', '0', NONE, '0', '0', '0', NONE),
INSN_stfsux => (LDST, FPU, OP_STORE, RA_OR_ZERO, RB, NONE, FRS, RA, '0', '0', '0', '0', ZERO, '0', is4B, '0', '0', '1', '0', '1', '0', NONE, '0', '0', '0', NONE),
INSN_stfsx => (LDST, FPU, OP_STORE, RA_OR_ZERO, RB, NONE, FRS, NONE, '0', '0', '0', '0', ZERO, '0', is4B, '0', '0', '0', '0', '1', '0', NONE, '0', '0', '0', NONE),
INSN_sth => (LDST, NONE, OP_STORE, RA_OR_ZERO, IMM, CONST_SI, RS, NONE, '0', '0', '0', '0', ZERO, '0', is2B, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_sthbrx => (LDST, NONE, OP_STORE, RA_OR_ZERO, RB, NONE, RS, NONE, '0', '0', '0', '0', ZERO, '0', is2B, '1', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_sthcix => (LDST, NONE, OP_STORE, RA_OR_ZERO, RB, NONE, RS, NONE, '0', '0', '1', '0', ZERO, '0', is2B, '0', '0', '0', '0', '0', '0', NONE, '0', '1', '0', NONE),
INSN_sthcx => (LDST, NONE, OP_STORE, RA_OR_ZERO, RB, NONE, RS, NONE, '0', '0', '0', '0', ZERO, '0', is2B, '0', '0', '0', '1', '0', '0', ONE, '0', '0', '0', NONE),
INSN_sthu => (LDST, NONE, OP_STORE, RA_OR_ZERO, IMM, CONST_SI, RS, RA, '0', '0', '0', '0', ZERO, '0', is2B, '0', '0', '1', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_sthux => (LDST, NONE, OP_STORE, RA_OR_ZERO, RB, NONE, RS, RA, '0', '0', '0', '0', ZERO, '0', is2B, '0', '0', '1', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_sthx => (LDST, NONE, OP_STORE, RA_OR_ZERO, RB, NONE, RS, NONE, '0', '0', '0', '0', ZERO, '0', is2B, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_stq => (LDST, NONE, OP_STORE, RA_OR_ZERO, IMM, CONST_DS, RS, NONE, '0', '0', '0', '0', ZERO, '0', is8B, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', DRSP),
INSN_stqcx => (LDST, NONE, OP_STORE, RA_OR_ZERO, RB, NONE, RS, NONE, '0', '0', '0', '0', ZERO, '0', is8B, '0', '0', '0', '1', '0', '0', ONE, '0', '0', '0', DRSP),
INSN_stw => (LDST, NONE, OP_STORE, RA_OR_ZERO, IMM, CONST_SI, RS, NONE, '0', '0', '0', '0', ZERO, '0', is4B, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_stwbrx => (LDST, NONE, OP_STORE, RA_OR_ZERO, RB, NONE, RS, NONE, '0', '0', '0', '0', ZERO, '0', is4B, '1', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_stwcix => (LDST, NONE, OP_STORE, RA_OR_ZERO, RB, NONE, RS, NONE, '0', '0', '1', '0', ZERO, '0', is4B, '0', '0', '0', '0', '0', '0', NONE, '0', '1', '0', NONE),
INSN_stwcx => (LDST, NONE, OP_STORE, RA_OR_ZERO, RB, NONE, RS, NONE, '0', '0', '0', '0', ZERO, '0', is4B, '0', '0', '0', '1', '0', '0', ONE, '0', '0', '0', NONE),
INSN_stwu => (LDST, NONE, OP_STORE, RA_OR_ZERO, IMM, CONST_SI, RS, RA, '0', '0', '0', '0', ZERO, '0', is4B, '0', '0', '1', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_stwux => (LDST, NONE, OP_STORE, RA_OR_ZERO, RB, NONE, RS, RA, '0', '0', '0', '0', ZERO, '0', is4B, '0', '0', '1', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_stwx => (LDST, NONE, OP_STORE, RA_OR_ZERO, RB, NONE, RS, NONE, '0', '0', '0', '0', ZERO, '0', is4B, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_subf => (ALU, NONE, OP_ADD, RA, RB, NONE, NONE, RT, '0', '0', '1', '0', ONE, '0', NONE, '0', '0', '0', '0', '0', '0', RCOE, '0', '0', '0', NONE),
INSN_subfc => (ALU, NONE, OP_ADD, RA, RB, NONE, NONE, RT, '0', '0', '1', '0', ONE, '1', NONE, '0', '0', '0', '0', '0', '0', RCOE, '0', '0', '0', NONE),
INSN_subfe => (ALU, NONE, OP_ADD, RA, RB, NONE, NONE, RT, '0', '0', '1', '0', CA, '1', NONE, '0', '0', '0', '0', '0', '0', RCOE, '0', '0', '0', NONE),
INSN_subfic => (ALU, NONE, OP_ADD, RA, IMM, CONST_SI, NONE, RT, '0', '0', '1', '0', ONE, '1', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_subfme => (ALU, NONE, OP_ADD, RA, IMM, CONST_M1, NONE, RT, '0', '0', '1', '0', CA, '1', NONE, '0', '0', '0', '0', '0', '0', RCOE, '0', '0', '0', NONE),
INSN_subfze => (ALU, NONE, OP_ADD, RA, IMM, NONE, NONE, RT, '0', '0', '1', '0', CA, '1', NONE, '0', '0', '0', '0', '0', '0', RCOE, '0', '0', '0', NONE),
INSN_sync => (LDST, NONE, OP_SYNC, NONE, IMM, NONE, NONE, NONE, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '1', NONE),
INSN_td => (ALU, NONE, OP_TRAP, RA, RB, NONE, NONE, NONE, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_tdi => (ALU, NONE, OP_TRAP, RA, IMM, CONST_SI, NONE, NONE, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_tlbie => (LDST, NONE, OP_TLBIE, NONE, RB, NONE, RS, NONE, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '1', '0', NONE),
INSN_tlbiel => (LDST, NONE, OP_TLBIE, NONE, RB, NONE, RS, NONE, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '1', '0', NONE),
INSN_tlbsync => (ALU, NONE, OP_NOP, NONE, IMM, NONE, NONE, NONE, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '1', '0', NONE),
INSN_tw => (ALU, NONE, OP_TRAP, RA, RB, NONE, NONE, NONE, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '1', '0', NONE, '0', '0', '0', NONE),
INSN_twi => (ALU, NONE, OP_TRAP, RA, IMM, CONST_SI, NONE, NONE, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '1', '0', NONE, '0', '0', '0', NONE),
INSN_wait => (ALU, NONE, OP_WAIT, NONE, IMM, NONE, NONE, NONE, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '1', NONE),
INSN_xor => (ALU, NONE, OP_XOR, NONE, RB, NONE, RS, RA, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0', '0', NONE),
INSN_xori => (ALU, NONE, OP_XOR, NONE, IMM, CONST_UI, RS, RA, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_xoris => (ALU, NONE, OP_XOR, NONE, IMM, CONST_UI_HI, RS, RA, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),

others => (ALU, NONE, OP_ILLEGAL, NONE, IMM, NONE, NONE, NONE, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE)
INSN_illegal => (ALU, NONE, OP_ILLEGAL, NONE, IMM, NONE, NONE, NONE, ADD, "000", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_fetch_fail => (LDST, NONE, OP_FETCH_FAILED, CIA, IMM, NONE, NONE, NONE, ADD, "000", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),

INSN_add => (ALU, NONE, OP_ADD, RA, RB, NONE, NONE, RT, ADD, "000", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RCOE, '0', '0', '0', NONE),
INSN_addc => (ALU, NONE, OP_ADD, RA, RB, NONE, NONE, RT, ADD, "000", '0', '0', '0', '0', ZERO, '1', NONE, '0', '0', '0', '0', '0', '0', RCOE, '0', '0', '0', NONE),
INSN_adde => (ALU, NONE, OP_ADD, RA, RB, NONE, NONE, RT, ADD, "000", '0', '0', '0', '0', CA, '1', NONE, '0', '0', '0', '0', '0', '0', RCOE, '0', '0', '0', NONE),
INSN_addex => (ALU, NONE, OP_ADD, RA, RB, NONE, NONE, RT, ADD, "000", '0', '0', '0', '0', OV, '1', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0', '0', NONE),
INSN_addg6s => (ALU, NONE, OP_ADDG6S, RA, RB, NONE, NONE, RT, MSC, "001", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_addi => (ALU, NONE, OP_ADD, RA_OR_ZERO, IMM, CONST_SI, NONE, RT, ADD, "000", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_addic => (ALU, NONE, OP_ADD, RA, IMM, CONST_SI, NONE, RT, ADD, "000", '0', '0', '0', '0', ZERO, '1', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_addic_dot => (ALU, NONE, OP_ADD, RA, IMM, CONST_SI, NONE, RT, ADD, "000", '0', '0', '0', '0', ZERO, '1', NONE, '0', '0', '0', '0', '0', '0', ONE, '0', '0', '0', NONE),
INSN_addis => (ALU, NONE, OP_ADD, RA_OR_ZERO, IMM, CONST_SI_HI, NONE, RT, ADD, "000", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_addme => (ALU, NONE, OP_ADD, RA, IMM, CONST_M1, NONE, RT, ADD, "000", '0', '0', '0', '0', CA, '1', NONE, '0', '0', '0', '0', '0', '0', RCOE, '0', '0', '0', NONE),
INSN_addpcis => (ALU, NONE, OP_ADD, CIA, IMM, CONST_DXHI4, NONE, RT, ADD, "000", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_addze => (ALU, NONE, OP_ADD, RA, IMM, NONE, NONE, RT, ADD, "000", '0', '0', '0', '0', CA, '1', NONE, '0', '0', '0', '0', '0', '0', RCOE, '0', '0', '0', NONE),
INSN_and => (ALU, NONE, OP_LOGIC, NONE, RB, NONE, RS, RA, LOG, "000", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0', '0', NONE),
INSN_andc => (ALU, NONE, OP_LOGIC, NONE, RB, NONE, RS, RA, LOG, "000", '0', '0', '1', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0', '0', NONE),
INSN_andi_dot => (ALU, NONE, OP_LOGIC, NONE, IMM, CONST_UI, RS, RA, LOG, "000", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', ONE, '0', '0', '0', NONE),
INSN_andis_dot => (ALU, NONE, OP_LOGIC, NONE, IMM, CONST_UI_HI, RS, RA, LOG, "000", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', ONE, '0', '0', '0', NONE),
INSN_attn => (ALU, NONE, OP_ATTN, NONE, IMM, NONE, NONE, NONE, ADD, "000", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '1', '1', NONE),
INSN_brel => (ALU, NONE, OP_B, CIA, IMM, CONST_LI, NONE, NONE, ADD, "000", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '1', '0', '0', NONE),
INSN_babs => (ALU, NONE, OP_B, NONE, IMM, CONST_LI, NONE, NONE, ADD, "000", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '1', '0', '0', NONE),
INSN_bcrel => (ALU, NONE, OP_BC, CIA, IMM, CONST_BD, NONE, NONE, ADD, "000", '1', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '1', '0', '0', NONE),
INSN_bcabs => (ALU, NONE, OP_BC, NONE, IMM, CONST_BD, NONE, NONE, ADD, "000", '1', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '1', '0', '0', NONE),
INSN_bcctr => (ALU, NONE, OP_BCREG, NONE, IMM, NONE, NONE, NONE, SPR, "000", '1', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '1', '0', '0', NONE),
INSN_bclr => (ALU, NONE, OP_BCREG, NONE, IMM, NONE, NONE, NONE, SPR, "000", '1', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '1', '0', '0', NONE),
INSN_bctar => (ALU, NONE, OP_BCREG, NONE, IMM, NONE, NONE, NONE, SPR, "000", '1', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '1', '0', '0', NONE),
INSN_bperm => (ALU, NONE, OP_BPERM, NONE, RB, NONE, RS, RA, ADD, "100", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_brh => (ALU, NONE, OP_BREV, NONE, IMM, NONE, RS, RA, LOG, "010", '0', '0', '0', '0', ZERO, '0', is2B, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_brw => (ALU, NONE, OP_BREV, NONE, IMM, NONE, RS, RA, LOG, "010", '0', '0', '0', '0', ZERO, '0', is4B, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_brd => (ALU, NONE, OP_BREV, NONE, IMM, NONE, RS, RA, LOG, "010", '0', '0', '0', '0', ZERO, '0', is8B, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_cbcdtd => (ALU, NONE, OP_BCD, NONE, IMM, NONE, RS, RA, LOG, "101", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_cdtbcd => (ALU, NONE, OP_BCD, NONE, IMM, NONE, RS, RA, LOG, "101", '0', '0', '1', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_cfuged => (ALU, NONE, OP_BSORT, NONE, RB, NONE, RS, RA, ADD, "000", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_cmp => (ALU, NONE, OP_CMP, RA, RB, NONE, NONE, NONE, ADD, "000", '0', '1', '1', '0', ONE, '0', NONE, '0', '0', '0', '0', '0', '1', NONE, '0', '0', '0', NONE),
INSN_cmpb => (ALU, NONE, OP_CMPB, NONE, RB, NONE, RS, RA, LOG, "100", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_cmpeqb => (ALU, NONE, OP_CMPEQB, RA, RB, NONE, NONE, NONE, ADD, "010", '0', '1', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_cmpi => (ALU, NONE, OP_CMP, RA, IMM, CONST_SI, NONE, NONE, ADD, "000", '0', '1', '1', '0', ONE, '0', NONE, '0', '0', '0', '0', '0', '1', NONE, '0', '0', '0', NONE),
INSN_cmpl => (ALU, NONE, OP_CMP, RA, RB, NONE, NONE, NONE, ADD, "000", '0', '1', '1', '0', ONE, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_cmpli => (ALU, NONE, OP_CMP, RA, IMM, CONST_UI, NONE, NONE, ADD, "000", '0', '1', '1', '0', ONE, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_cmprb => (ALU, NONE, OP_CMPRB, RA, RB, NONE, NONE, NONE, ADD, "001", '0', '1', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_cntlzd => (ALU, NONE, OP_COUNTB, NONE, IMM, NONE, RS, RA, ADD, "000", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0', '0', NONE),
INSN_cntlzw => (ALU, NONE, OP_COUNTB, NONE, IMM, NONE, RS, RA, ADD, "000", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '1', '0', RC, '0', '0', '0', NONE),
INSN_cnttzd => (ALU, NONE, OP_COUNTB, NONE, IMM, NONE, RS, RA, ADD, "000", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0', '0', NONE),
INSN_cnttzw => (ALU, NONE, OP_COUNTB, NONE, IMM, NONE, RS, RA, ADD, "000", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '1', '0', RC, '0', '0', '0', NONE),
INSN_crand => (ALU, NONE, OP_CROP, NONE, IMM, NONE, NONE, NONE, ADD, "011", '1', '1', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_crandc => (ALU, NONE, OP_CROP, NONE, IMM, NONE, NONE, NONE, ADD, "011", '1', '1', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_creqv => (ALU, NONE, OP_CROP, NONE, IMM, NONE, NONE, NONE, ADD, "011", '1', '1', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_crnand => (ALU, NONE, OP_CROP, NONE, IMM, NONE, NONE, NONE, ADD, "011", '1', '1', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_crnor => (ALU, NONE, OP_CROP, NONE, IMM, NONE, NONE, NONE, ADD, "011", '1', '1', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_cror => (ALU, NONE, OP_CROP, NONE, IMM, NONE, NONE, NONE, ADD, "011", '1', '1', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_crorc => (ALU, NONE, OP_CROP, NONE, IMM, NONE, NONE, NONE, ADD, "011", '1', '1', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_crxor => (ALU, NONE, OP_CROP, NONE, IMM, NONE, NONE, NONE, ADD, "011", '1', '1', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_darn => (ALU, NONE, OP_DARN, NONE, IMM, NONE, NONE, RT, MSC, "011", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_dcbf => (LDST, NONE, OP_DCBF, RA_OR_ZERO, RB, NONE, NONE, NONE, ADD, "000", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_dcbst => (ALU, NONE, OP_DCBST, NONE, IMM, NONE, NONE, NONE, ADD, "000", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_dcbt => (LDST, NONE, OP_LOAD, RA_OR_ZERO, RB, NONE, NONE, NONE, ADD, "000", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_dcbtst => (LDST, NONE, OP_STORE, RA_OR_ZERO, RB, NONE, NONE, NONE, ADD, "000", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_dcbz => (LDST, NONE, OP_DCBZ, RA_OR_ZERO, RB, NONE, NONE, NONE, ADD, "000", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_divd => (DVU, NONE, OP_DIV, RA, RB, NONE, NONE, RT, ADD, "101", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '1', RCOE, '0', '0', '0', NONE),
INSN_divde => (DVU, NONE, OP_DIVE, RA, RB, NONE, NONE, RT, ADD, "101", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '1', RCOE, '0', '0', '0', NONE),
INSN_divdeu => (DVU, NONE, OP_DIVE, RA, RB, NONE, NONE, RT, ADD, "101", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RCOE, '0', '0', '0', NONE),
INSN_divdu => (DVU, NONE, OP_DIV, RA, RB, NONE, NONE, RT, ADD, "101", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RCOE, '0', '0', '0', NONE),
INSN_divw => (DVU, NONE, OP_DIV, RA, RB, NONE, NONE, RT, ADD, "101", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '1', '1', RCOE, '0', '0', '0', NONE),
INSN_divwe => (DVU, NONE, OP_DIVE, RA, RB, NONE, NONE, RT, ADD, "101", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '1', '1', RCOE, '0', '0', '0', NONE),
INSN_divweu => (DVU, NONE, OP_DIVE, RA, RB, NONE, NONE, RT, ADD, "101", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '1', '0', RCOE, '0', '0', '0', NONE),
INSN_divwu => (DVU, NONE, OP_DIV, RA, RB, NONE, NONE, RT, ADD, "101", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '1', '0', RCOE, '0', '0', '0', NONE),
INSN_eieio => (ALU, NONE, OP_NOP, NONE, IMM, NONE, NONE, NONE, ADD, "000", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_eqv => (ALU, NONE, OP_XOR, NONE, RB, NONE, RS, RA, LOG, "001", '0', '0', '0', '1', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0', '0', NONE),
INSN_extsb => (ALU, NONE, OP_EXTS, NONE, IMM, NONE, RS, RA, LOG, "110", '0', '0', '0', '0', ZERO, '0', is1B, '0', '0', '0', '0', '0', '0', RC, '0', '0', '0', NONE),
INSN_extsh => (ALU, NONE, OP_EXTS, NONE, IMM, NONE, RS, RA, LOG, "110", '0', '0', '0', '0', ZERO, '0', is2B, '0', '0', '0', '0', '0', '0', RC, '0', '0', '0', NONE),
INSN_extsw => (ALU, NONE, OP_EXTS, NONE, IMM, NONE, RS, RA, LOG, "110", '0', '0', '0', '0', ZERO, '0', is4B, '0', '0', '0', '0', '0', '0', RC, '0', '0', '0', NONE),
INSN_extswsli => (ALU, NONE, OP_EXTSWSLI, NONE, IMM, CONST_SH, RS, RA, ROT, "000", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0', '0', NONE),
INSN_fabs => (FPU, FPU, OP_FP_MOVE, NONE, FRB, NONE, NONE, FRT, ADD, "000", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0', '0', NONE),
INSN_fadd => (FPU, FPU, OP_FP_ARITH, FRA, FRB, NONE, NONE, FRT, ADD, "000", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0', '0', NONE),
INSN_fadds => (FPU, FPU, OP_FP_ARITH, FRA, FRB, NONE, NONE, FRT, ADD, "000", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '1', '0', RC, '0', '0', '0', NONE),
INSN_fcfid => (FPU, FPU, OP_FP_MISC, NONE, FRB, NONE, NONE, FRT, ADD, "000", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '1', RC, '0', '0', '0', NONE),
INSN_fcfids => (FPU, FPU, OP_FP_MISC, NONE, FRB, NONE, NONE, FRT, ADD, "000", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '1', '1', RC, '0', '0', '0', NONE),
INSN_fcfidu => (FPU, FPU, OP_FP_MISC, NONE, FRB, NONE, NONE, FRT, ADD, "000", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0', '0', NONE),
INSN_fcfidus => (FPU, FPU, OP_FP_MISC, NONE, FRB, NONE, NONE, FRT, ADD, "000", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '1', '0', RC, '0', '0', '0', NONE),
INSN_fcmpo => (FPU, FPU, OP_FP_CMP, FRA, FRB, NONE, NONE, NONE, ADD, "000", '0', '1', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_fcmpu => (FPU, FPU, OP_FP_CMP, FRA, FRB, NONE, NONE, NONE, ADD, "000", '0', '1', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_fcpsgn => (FPU, FPU, OP_FP_MOVE, FRA, FRB, NONE, NONE, FRT, ADD, "000", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0', '0', NONE),
INSN_fctid => (FPU, FPU, OP_FP_ARITH, NONE, FRB, NONE, NONE, FRT, ADD, "000", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0', '0', NONE),
INSN_fctidu => (FPU, FPU, OP_FP_ARITH, NONE, FRB, NONE, NONE, FRT, ADD, "000", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0', '0', NONE),
INSN_fctiduz => (FPU, FPU, OP_FP_ARITH, NONE, FRB, NONE, NONE, FRT, ADD, "000", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0', '0', NONE),
INSN_fctidz => (FPU, FPU, OP_FP_ARITH, NONE, FRB, NONE, NONE, FRT, ADD, "000", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0', '0', NONE),
INSN_fctiw => (FPU, FPU, OP_FP_ARITH, NONE, FRB, NONE, NONE, FRT, ADD, "000", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0', '0', NONE),
INSN_fctiwu => (FPU, FPU, OP_FP_ARITH, NONE, FRB, NONE, NONE, FRT, ADD, "000", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0', '0', NONE),
INSN_fctiwuz => (FPU, FPU, OP_FP_ARITH, NONE, FRB, NONE, NONE, FRT, ADD, "000", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0', '0', NONE),
INSN_fctiwz => (FPU, FPU, OP_FP_ARITH, NONE, FRB, NONE, NONE, FRT, ADD, "000", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0', '0', NONE),
INSN_fdiv => (FPU, FPU, OP_FP_ARITH, FRA, FRB, NONE, NONE, FRT, ADD, "000", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0', '0', NONE),
INSN_fdivs => (FPU, FPU, OP_FP_ARITH, FRA, FRB, NONE, NONE, FRT, ADD, "000", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '1', '0', RC, '0', '0', '0', NONE),
INSN_fmadd => (FPU, FPU, OP_FP_ARITH, FRA, FRB, NONE, FRC, FRT, ADD, "000", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0', '0', NONE),
INSN_fmadds => (FPU, FPU, OP_FP_ARITH, FRA, FRB, NONE, FRC, FRT, ADD, "000", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '1', '0', RC, '0', '0', '0', NONE),
INSN_fmr => (FPU, FPU, OP_FP_MOVE, NONE, FRB, NONE, NONE, FRT, ADD, "000", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0', '0', NONE),
INSN_fmrgew => (FPU, FPU, OP_FP_MISC, FRA, FRB, NONE, NONE, FRT, ADD, "000", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_fmrgow => (FPU, FPU, OP_FP_MISC, FRA, FRB, NONE, NONE, FRT, ADD, "000", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_fmsub => (FPU, FPU, OP_FP_ARITH, FRA, FRB, NONE, FRC, FRT, ADD, "000", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0', '0', NONE),
INSN_fmsubs => (FPU, FPU, OP_FP_ARITH, FRA, FRB, NONE, FRC, FRT, ADD, "000", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '1', '0', RC, '0', '0', '0', NONE),
INSN_fmul => (FPU, FPU, OP_FP_ARITH, FRA, IMM, NONE, FRC, FRT, ADD, "000", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0', '0', NONE),
INSN_fmuls => (FPU, FPU, OP_FP_ARITH, FRA, IMM, NONE, FRC, FRT, ADD, "000", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '1', '0', RC, '0', '0', '0', NONE),
INSN_fnabs => (FPU, FPU, OP_FP_MOVE, NONE, FRB, NONE, NONE, FRT, ADD, "000", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0', '0', NONE),
INSN_fneg => (FPU, FPU, OP_FP_MOVE, NONE, FRB, NONE, NONE, FRT, ADD, "000", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0', '0', NONE),
INSN_fnmadd => (FPU, FPU, OP_FP_ARITH, FRA, FRB, NONE, FRC, FRT, ADD, "000", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0', '0', NONE),
INSN_fnmadds => (FPU, FPU, OP_FP_ARITH, FRA, FRB, NONE, FRC, FRT, ADD, "000", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '1', '0', RC, '0', '0', '0', NONE),
INSN_fnmsub => (FPU, FPU, OP_FP_ARITH, FRA, FRB, NONE, FRC, FRT, ADD, "000", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0', '0', NONE),
INSN_fnmsubs => (FPU, FPU, OP_FP_ARITH, FRA, FRB, NONE, FRC, FRT, ADD, "000", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '1', '0', RC, '0', '0', '0', NONE),
INSN_fre => (FPU, FPU, OP_FP_ARITH, NONE, FRB, NONE, NONE, FRT, ADD, "000", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0', '0', NONE),
INSN_fres => (FPU, FPU, OP_FP_ARITH, NONE, FRB, NONE, NONE, FRT, ADD, "000", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '1', '0', RC, '0', '0', '0', NONE),
INSN_frim => (FPU, FPU, OP_FP_ARITH, NONE, FRB, NONE, NONE, FRT, ADD, "000", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0', '0', NONE),
INSN_frin => (FPU, FPU, OP_FP_ARITH, NONE, FRB, NONE, NONE, FRT, ADD, "000", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0', '0', NONE),
INSN_frip => (FPU, FPU, OP_FP_ARITH, NONE, FRB, NONE, NONE, FRT, ADD, "000", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0', '0', NONE),
INSN_friz => (FPU, FPU, OP_FP_ARITH, NONE, FRB, NONE, NONE, FRT, ADD, "000", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0', '0', NONE),
INSN_frsp => (FPU, FPU, OP_FP_ARITH, NONE, FRB, NONE, NONE, FRT, ADD, "000", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '1', '0', RC, '0', '0', '0', NONE),
INSN_frsqrte => (FPU, FPU, OP_FP_ARITH, NONE, FRB, NONE, NONE, FRT, ADD, "000", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0', '0', NONE),
INSN_frsqrtes => (FPU, FPU, OP_FP_ARITH, NONE, FRB, NONE, NONE, FRT, ADD, "000", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '1', '0', RC, '0', '0', '0', NONE),
INSN_fsel => (FPU, FPU, OP_FP_MOVE, FRA, FRB, NONE, FRC, FRT, ADD, "000", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0', '0', NONE),
INSN_fsqrt => (FPU, FPU, OP_FP_ARITH, NONE, FRB, NONE, NONE, FRT, ADD, "000", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0', '0', NONE),
INSN_fsqrts => (FPU, FPU, OP_FP_ARITH, NONE, FRB, NONE, NONE, FRT, ADD, "000", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '1', '0', RC, '0', '0', '0', NONE),
INSN_fsub => (FPU, FPU, OP_FP_ARITH, FRA, FRB, NONE, NONE, FRT, ADD, "000", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0', '0', NONE),
INSN_fsubs => (FPU, FPU, OP_FP_ARITH, FRA, FRB, NONE, NONE, FRT, ADD, "000", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '1', '0', RC, '0', '0', '0', NONE),
INSN_ftdiv => (FPU, FPU, OP_FP_CMP, FRA, FRB, NONE, NONE, NONE, ADD, "000", '0', '1', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_ftsqrt => (FPU, FPU, OP_FP_CMP, NONE, FRB, NONE, NONE, NONE, ADD, "000", '0', '1', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_hashchk => (LDST, NONE, OP_LOAD, RA, RB, NONE, NONE, NONE, ADD, "000", '0', '0', '0', '0', ZERO, '0', is8B, '0', '0', '0', '0', '0', '1', NONE, '0', '0', '0', NONE),
INSN_hashchkp => (LDST, NONE, OP_LOAD, RA, RB, NONE, NONE, NONE, ADD, "000", '0', '0', '0', '0', ZERO, '0', is8B, '0', '0', '0', '0', '0', '1', NONE, '0', '1', '0', NONE),
INSN_hashst => (LDST, NONE, OP_STORE, RA, RB, NONE, NONE, NONE, ADD, "000", '0', '0', '0', '0', ZERO, '0', is8B, '0', '0', '0', '0', '0', '1', NONE, '0', '0', '0', NONE),
INSN_hashstp => (LDST, NONE, OP_STORE, RA, RB, NONE, NONE, NONE, ADD, "000", '0', '0', '0', '0', ZERO, '0', is8B, '0', '0', '0', '0', '0', '1', NONE, '0', '1', '0', NONE),
INSN_icbi => (ALU, NONE, OP_ICBI, NONE, IMM, NONE, NONE, NONE, ADD, "000", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '1', NONE),
INSN_icbt => (ALU, NONE, OP_ICBT, NONE, IMM, NONE, NONE, NONE, ADD, "000", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_isel => (ALU, NONE, OP_ISEL, RA_OR_ZERO, RB, NONE, NONE, RT, MSC, "010", '1', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_isync => (ALU, NONE, OP_ISYNC, NONE, IMM, NONE, NONE, NONE, ADD, "000", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_lbarx => (LDST, NONE, OP_LOAD, RA_OR_ZERO, RB, NONE, NONE, RT, ADD, "000", '0', '0', '0', '0', ZERO, '0', is1B, '0', '0', '0', '1', '0', '0', NONE, '0', '0', '0', NONE),
INSN_lbz => (LDST, NONE, OP_LOAD, RA_OR_ZERO, IMM, CONST_SI, NONE, RT, ADD, "000", '0', '0', '0', '0', ZERO, '0', is1B, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_lbzcix => (LDST, NONE, OP_LOAD, RA_OR_ZERO, RB, NONE, NONE, RT, ADD, "000", '0', '0', '1', '0', ZERO, '0', is1B, '0', '0', '0', '0', '0', '0', NONE, '0', '1', '0', NONE),
INSN_lbzu => (LDST, NONE, OP_LOAD, RA_OR_ZERO, IMM, CONST_SI, NONE, RT, ADD, "000", '0', '0', '0', '0', ZERO, '0', is1B, '0', '0', '1', '0', '0', '0', NONE, '0', '0', '0', DUPD),
INSN_lbzux => (LDST, NONE, OP_LOAD, RA_OR_ZERO, RB, NONE, NONE, RT, ADD, "000", '0', '0', '0', '0', ZERO, '0', is1B, '0', '0', '1', '0', '0', '0', NONE, '0', '0', '0', DUPD),
INSN_lbzx => (LDST, NONE, OP_LOAD, RA_OR_ZERO, RB, NONE, NONE, RT, ADD, "000", '0', '0', '0', '0', ZERO, '0', is1B, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_ld => (LDST, NONE, OP_LOAD, RA_OR_ZERO, IMM, CONST_DS, NONE, RT, ADD, "000", '0', '0', '0', '0', ZERO, '0', is8B, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_ldarx => (LDST, NONE, OP_LOAD, RA_OR_ZERO, RB, NONE, NONE, RT, ADD, "000", '0', '0', '0', '0', ZERO, '0', is8B, '0', '0', '0', '1', '0', '0', NONE, '0', '0', '0', NONE),
INSN_ldbrx => (LDST, NONE, OP_LOAD, RA_OR_ZERO, RB, NONE, NONE, RT, ADD, "000", '0', '0', '0', '0', ZERO, '0', is8B, '1', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_ldcix => (LDST, NONE, OP_LOAD, RA_OR_ZERO, RB, NONE, NONE, RT, ADD, "000", '0', '0', '1', '0', ZERO, '0', is8B, '0', '0', '0', '0', '0', '0', NONE, '0', '1', '0', NONE),
INSN_ldu => (LDST, NONE, OP_LOAD, RA_OR_ZERO, IMM, CONST_DS, NONE, RT, ADD, "000", '0', '0', '0', '0', ZERO, '0', is8B, '0', '0', '1', '0', '0', '0', NONE, '0', '0', '0', DUPD),
INSN_ldux => (LDST, NONE, OP_LOAD, RA_OR_ZERO, RB, NONE, NONE, RT, ADD, "000", '0', '0', '0', '0', ZERO, '0', is8B, '0', '0', '1', '0', '0', '0', NONE, '0', '0', '0', DUPD),
INSN_ldx => (LDST, NONE, OP_LOAD, RA_OR_ZERO, RB, NONE, NONE, RT, ADD, "000", '0', '0', '0', '0', ZERO, '0', is8B, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_lfd => (LDST, FPU, OP_LOAD, RA_OR_ZERO, IMM, CONST_SI, NONE, FRT, ADD, "000", '0', '0', '0', '0', ZERO, '0', is8B, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_lfdu => (LDST, FPU, OP_LOAD, RA_OR_ZERO, IMM, CONST_SI, NONE, FRT, ADD, "000", '0', '0', '0', '0', ZERO, '0', is8B, '0', '0', '1', '0', '0', '0', NONE, '0', '0', '0', DUPD),
INSN_lfdux => (LDST, FPU, OP_LOAD, RA_OR_ZERO, RB, NONE, NONE, FRT, ADD, "000", '0', '0', '0', '0', ZERO, '0', is8B, '0', '0', '1', '0', '0', '0', NONE, '0', '0', '0', DUPD),
INSN_lfdx => (LDST, FPU, OP_LOAD, RA_OR_ZERO, RB, NONE, NONE, FRT, ADD, "000", '0', '0', '0', '0', ZERO, '0', is8B, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_lfiwax => (LDST, FPU, OP_LOAD, RA_OR_ZERO, RB, NONE, NONE, FRT, ADD, "000", '0', '0', '0', '0', ZERO, '0', is4B, '0', '1', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_lfiwzx => (LDST, FPU, OP_LOAD, RA_OR_ZERO, RB, NONE, NONE, FRT, ADD, "000", '0', '0', '0', '0', ZERO, '0', is4B, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_lfs => (LDST, FPU, OP_LOAD, RA_OR_ZERO, IMM, CONST_SI, NONE, FRT, ADD, "000", '0', '0', '0', '0', ZERO, '0', is4B, '0', '0', '0', '0', '1', '0', NONE, '0', '0', '0', NONE),
INSN_lfsu => (LDST, FPU, OP_LOAD, RA_OR_ZERO, IMM, CONST_SI, NONE, FRT, ADD, "000", '0', '0', '0', '0', ZERO, '0', is4B, '0', '0', '1', '0', '1', '0', NONE, '0', '0', '0', DUPD),
INSN_lfsux => (LDST, FPU, OP_LOAD, RA_OR_ZERO, RB, NONE, NONE, FRT, ADD, "000", '0', '0', '0', '0', ZERO, '0', is4B, '0', '0', '1', '0', '1', '0', NONE, '0', '0', '0', DUPD),
INSN_lfsx => (LDST, FPU, OP_LOAD, RA_OR_ZERO, RB, NONE, NONE, FRT, ADD, "000", '0', '0', '0', '0', ZERO, '0', is4B, '0', '0', '0', '0', '1', '0', NONE, '0', '0', '0', NONE),
INSN_lha => (LDST, NONE, OP_LOAD, RA_OR_ZERO, IMM, CONST_SI, NONE, RT, ADD, "000", '0', '0', '0', '0', ZERO, '0', is2B, '0', '1', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_lharx => (LDST, NONE, OP_LOAD, RA_OR_ZERO, RB, NONE, NONE, RT, ADD, "000", '0', '0', '0', '0', ZERO, '0', is2B, '0', '0', '0', '1', '0', '0', NONE, '0', '0', '0', NONE),
INSN_lhau => (LDST, NONE, OP_LOAD, RA_OR_ZERO, IMM, CONST_SI, NONE, RT, ADD, "000", '0', '0', '0', '0', ZERO, '0', is2B, '0', '1', '1', '0', '0', '0', NONE, '0', '0', '0', DUPD),
INSN_lhaux => (LDST, NONE, OP_LOAD, RA_OR_ZERO, RB, NONE, NONE, RT, ADD, "000", '0', '0', '0', '0', ZERO, '0', is2B, '0', '1', '1', '0', '0', '0', NONE, '0', '0', '0', DUPD),
INSN_lhax => (LDST, NONE, OP_LOAD, RA_OR_ZERO, RB, NONE, NONE, RT, ADD, "000", '0', '0', '0', '0', ZERO, '0', is2B, '0', '1', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_lhbrx => (LDST, NONE, OP_LOAD, RA_OR_ZERO, RB, NONE, NONE, RT, ADD, "000", '0', '0', '0', '0', ZERO, '0', is2B, '1', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_lhz => (LDST, NONE, OP_LOAD, RA_OR_ZERO, IMM, CONST_SI, NONE, RT, ADD, "000", '0', '0', '0', '0', ZERO, '0', is2B, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_lhzcix => (LDST, NONE, OP_LOAD, RA_OR_ZERO, RB, NONE, NONE, RT, ADD, "000", '0', '0', '1', '0', ZERO, '0', is2B, '0', '0', '0', '0', '0', '0', NONE, '0', '1', '0', NONE),
INSN_lhzu => (LDST, NONE, OP_LOAD, RA_OR_ZERO, IMM, CONST_SI, NONE, RT, ADD, "000", '0', '0', '0', '0', ZERO, '0', is2B, '0', '0', '1', '0', '0', '0', NONE, '0', '0', '0', DUPD),
INSN_lhzux => (LDST, NONE, OP_LOAD, RA_OR_ZERO, RB, NONE, NONE, RT, ADD, "000", '0', '0', '0', '0', ZERO, '0', is2B, '0', '0', '1', '0', '0', '0', NONE, '0', '0', '0', DUPD),
INSN_lhzx => (LDST, NONE, OP_LOAD, RA_OR_ZERO, RB, NONE, NONE, RT, ADD, "000", '0', '0', '0', '0', ZERO, '0', is2B, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_lq => (LDST, NONE, OP_LOAD, RA_OR_ZERO, IMM, CONST_DQ, NONE, RT, ADD, "000", '0', '0', '0', '0', ZERO, '0', is8B, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', DRTP),
INSN_lqarx => (LDST, NONE, OP_LOAD, RA_OR_ZERO, RB, NONE, NONE, RT, ADD, "000", '0', '0', '0', '0', ZERO, '0', is8B, '0', '0', '0', '1', '0', '0', NONE, '0', '0', '0', DRTP),
INSN_lwa => (LDST, NONE, OP_LOAD, RA_OR_ZERO, IMM, CONST_DS, NONE, RT, ADD, "000", '0', '0', '0', '0', ZERO, '0', is4B, '0', '1', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_lwarx => (LDST, NONE, OP_LOAD, RA_OR_ZERO, RB, NONE, NONE, RT, ADD, "000", '0', '0', '0', '0', ZERO, '0', is4B, '0', '0', '0', '1', '0', '0', NONE, '0', '0', '0', NONE),
INSN_lwaux => (LDST, NONE, OP_LOAD, RA_OR_ZERO, RB, NONE, NONE, RT, ADD, "000", '0', '0', '0', '0', ZERO, '0', is4B, '0', '1', '1', '0', '0', '0', NONE, '0', '0', '0', DUPD),
INSN_lwax => (LDST, NONE, OP_LOAD, RA_OR_ZERO, RB, NONE, NONE, RT, ADD, "000", '0', '0', '0', '0', ZERO, '0', is4B, '0', '1', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_lwbrx => (LDST, NONE, OP_LOAD, RA_OR_ZERO, RB, NONE, NONE, RT, ADD, "000", '0', '0', '0', '0', ZERO, '0', is4B, '1', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_lwz => (LDST, NONE, OP_LOAD, RA_OR_ZERO, IMM, CONST_SI, NONE, RT, ADD, "000", '0', '0', '0', '0', ZERO, '0', is4B, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_lwzcix => (LDST, NONE, OP_LOAD, RA_OR_ZERO, RB, NONE, NONE, RT, ADD, "000", '0', '0', '1', '0', ZERO, '0', is4B, '0', '0', '0', '0', '0', '0', NONE, '0', '1', '0', NONE),
INSN_lwzu => (LDST, NONE, OP_LOAD, RA_OR_ZERO, IMM, CONST_SI, NONE, RT, ADD, "000", '0', '0', '0', '0', ZERO, '0', is4B, '0', '0', '1', '0', '0', '0', NONE, '0', '0', '0', DUPD),
INSN_lwzux => (LDST, NONE, OP_LOAD, RA_OR_ZERO, RB, NONE, NONE, RT, ADD, "000", '0', '0', '0', '0', ZERO, '0', is4B, '0', '0', '1', '0', '0', '0', NONE, '0', '0', '0', DUPD),
INSN_lwzx => (LDST, NONE, OP_LOAD, RA_OR_ZERO, RB, NONE, NONE, RT, ADD, "000", '0', '0', '0', '0', ZERO, '0', is4B, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_maddhd => (ALU, NONE, OP_MUL_H64, RA, RB, NONE, RCR, RT, ADD, "010", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '1', NONE, '0', '0', '0', NONE),
INSN_maddhdu => (ALU, NONE, OP_MUL_H64, RA, RB, NONE, RCR, RT, ADD, "010", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_maddld => (ALU, NONE, OP_MUL_L64, RA, RB, NONE, RCR, RT, ADD, "000", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '1', NONE, '0', '0', '0', NONE),
INSN_mcrf => (ALU, NONE, OP_CROP, NONE, IMM, NONE, NONE, NONE, ADD, "011", '1', '1', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_mcrfs => (FPU, FPU, OP_FP_CMP, NONE, IMM, NONE, NONE, NONE, ADD, "000", '0', '1', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_mcrxrx => (ALU, NONE, OP_MCRXRX, NONE, IMM, NONE, NONE, NONE, ADD, "100", '0', '1', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_mfcr => (ALU, NONE, OP_MFCR, NONE, IMM, NONE, NONE, RT, MSC, "101", '1', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_mffs => (FPU, FPU, OP_FP_MISC, NONE, FRB, NONE, NONE, FRT, ADD, "000", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0', '0', NONE),
INSN_mfmsr => (ALU, NONE, OP_MFMSR, NONE, IMM, NONE, NONE, RT, MSC, "100", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '1', '1', NONE),
INSN_mfspr => (ALU, NONE, OP_MFSPR, NONE, IMM, NONE, RS, RT, SPR, "000", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_modsd => (DVU, NONE, OP_MOD, RA, RB, NONE, NONE, RT, ADD, "101", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '1', NONE, '0', '0', '0', NONE),
INSN_modsw => (DVU, NONE, OP_MOD, RA, RB, NONE, NONE, RT, ADD, "101", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '1', '1', NONE, '0', '0', '0', NONE),
INSN_modud => (DVU, NONE, OP_MOD, RA, RB, NONE, NONE, RT, ADD, "101", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_moduw => (DVU, NONE, OP_MOD, RA, RB, NONE, NONE, RT, ADD, "101", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '1', '0', NONE, '0', '0', '0', NONE),
INSN_mtcrf => (ALU, NONE, OP_MTCRF, NONE, IMM, NONE, RS, NONE, ADD, "101", '0', '1', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_mtfsb => (FPU, FPU, OP_FP_MISC, NONE, IMM, NONE, NONE, NONE, ADD, "000", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0', '0', NONE),
INSN_mtfsf => (FPU, FPU, OP_FP_MISC, NONE, FRB, NONE, NONE, NONE, ADD, "000", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0', '0', NONE),
INSN_mtfsfi => (FPU, FPU, OP_FP_MISC, NONE, IMM, NONE, NONE, NONE, ADD, "000", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0', '0', NONE),
INSN_mtmsr => (ALU, NONE, OP_MTMSRD, NONE, IMM, NONE, RS, NONE, ADD, "000", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '1', '0', NONE, '0', '1', '0', NONE),
INSN_mtmsrd => (ALU, NONE, OP_MTMSRD, NONE, IMM, NONE, RS, NONE, ADD, "000", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '1', '0', NONE),
INSN_mtspr => (ALU, NONE, OP_MTSPR, NONE, IMM, NONE, RS, NONE, ADD, "000", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_mulhd => (ALU, NONE, OP_MUL_H64, RA, RB, NONE, NONE, RT, ADD, "010", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '1', RC, '0', '0', '0', NONE),
INSN_mulhdu => (ALU, NONE, OP_MUL_H64, RA, RB, NONE, NONE, RT, ADD, "010", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0', '0', NONE),
INSN_mulhw => (ALU, NONE, OP_MUL_H32, RA, RB, NONE, NONE, RT, ADD, "001", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '1', '1', RC, '0', '0', '0', NONE),
INSN_mulhwu => (ALU, NONE, OP_MUL_H32, RA, RB, NONE, NONE, RT, ADD, "001", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '1', '0', RC, '0', '0', '0', NONE),
INSN_mulld => (ALU, NONE, OP_MUL_L64, RA, RB, NONE, NONE, RT, ADD, "000", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '1', RCOE, '0', '0', '0', NONE),
INSN_mulli => (ALU, NONE, OP_MUL_L64, RA, IMM, CONST_SI, NONE, RT, ADD, "000", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '1', NONE, '0', '0', '0', NONE),
INSN_mullw => (ALU, NONE, OP_MUL_L64, RA, RB, NONE, NONE, RT, ADD, "000", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '1', '1', RCOE, '0', '0', '0', NONE),
INSN_nand => (ALU, NONE, OP_LOGIC, NONE, RB, NONE, RS, RA, LOG, "000", '0', '0', '0', '1', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0', '0', NONE),
INSN_neg => (ALU, NONE, OP_ADD, RA, IMM, NONE, NONE, RT, ADD, "000", '0', '0', '1', '0', ONE, '0', NONE, '0', '0', '0', '0', '0', '0', RCOE, '0', '0', '0', NONE),
INSN_nop => (ALU, NONE, OP_NOP, NONE, IMM, NONE, NONE, NONE, ADD, "000", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_nor => (ALU, NONE, OP_LOGIC, NONE, RB, NONE, RS, RA, LOG, "000", '0', '0', '1', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '1', RC, '0', '0', '0', NONE),
INSN_or => (ALU, NONE, OP_LOGIC, NONE, RB, NONE, RS, RA, LOG, "000", '0', '0', '1', '1', ZERO, '0', NONE, '0', '0', '0', '0', '0', '1', RC, '0', '0', '0', NONE),
INSN_orc => (ALU, NONE, OP_LOGIC, NONE, RB, NONE, RS, RA, LOG, "000", '0', '0', '0', '1', ZERO, '0', NONE, '0', '0', '0', '0', '0', '1', RC, '0', '0', '0', NONE),
INSN_ori => (ALU, NONE, OP_LOGIC, NONE, IMM, CONST_UI, RS, RA, LOG, "000", '0', '0', '1', '1', ZERO, '0', NONE, '0', '0', '0', '0', '0', '1', NONE, '0', '0', '0', NONE),
INSN_oris => (ALU, NONE, OP_LOGIC, NONE, IMM, CONST_UI_HI, RS, RA, LOG, "000", '0', '0', '1', '1', ZERO, '0', NONE, '0', '0', '0', '0', '0', '1', NONE, '0', '0', '0', NONE),
INSN_paddi => (ALU, NONE, OP_ADD, RA0_OR_CIA, IMM, CONST_PSI, NONE, RT, ADD, "000", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_pdepd => (ALU, NONE, OP_BSORT, NONE, RB, NONE, RS, RA, ADD, "100", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_pextd => (ALU, NONE, OP_BSORT, NONE, RB, NONE, RS, RA, ADD, "100", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_plbz => (LDST, NONE, OP_LOAD, RA0_OR_CIA, IMM, CONST_PSI, NONE, RT, ADD, "000", '0', '0', '0', '0', ZERO, '0', is1B, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_pld => (LDST, NONE, OP_LOAD, RA0_OR_CIA, IMM, CONST_PSI, NONE, RT, ADD, "000", '0', '0', '0', '0', ZERO, '0', is8B, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_plfd => (LDST, FPU, OP_LOAD, RA0_OR_CIA, IMM, CONST_PSI, NONE, FRT, ADD, "000", '0', '0', '0', '0', ZERO, '0', is8B, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_plfs => (LDST, FPU, OP_LOAD, RA0_OR_CIA, IMM, CONST_PSI, NONE, FRT, ADD, "000", '0', '0', '0', '0', ZERO, '0', is4B, '0', '0', '0', '0', '1', '0', NONE, '0', '0', '0', NONE),
INSN_plha => (LDST, NONE, OP_LOAD, RA0_OR_CIA, IMM, CONST_PSI, NONE, RT, ADD, "000", '0', '0', '0', '0', ZERO, '0', is2B, '0', '1', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_plhz => (LDST, NONE, OP_LOAD, RA0_OR_CIA, IMM, CONST_PSI, NONE, RT, ADD, "000", '0', '0', '0', '0', ZERO, '0', is2B, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_plq => (LDST, NONE, OP_LOAD, RA0_OR_CIA, IMM, CONST_PSI, NONE, RT, ADD, "000", '0', '0', '0', '0', ZERO, '0', is8B, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', DRTP),
INSN_plwa => (LDST, NONE, OP_LOAD, RA0_OR_CIA, IMM, CONST_PSI, NONE, RT, ADD, "000", '0', '0', '0', '0', ZERO, '0', is4B, '0', '1', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_plwz => (LDST, NONE, OP_LOAD, RA0_OR_CIA, IMM, CONST_PSI, NONE, RT, ADD, "000", '0', '0', '0', '0', ZERO, '0', is4B, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_pnop => (ALU, NONE, OP_NOP, NONE, IMM, NONE, NONE, NONE, ADD, "000", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_pstb => (LDST, NONE, OP_STORE, RA0_OR_CIA, IMM, CONST_PSI, RS, NONE, ADD, "000", '0', '0', '0', '0', ZERO, '0', is1B, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_pstd => (LDST, NONE, OP_STORE, RA0_OR_CIA, IMM, CONST_PSI, RS, NONE, ADD, "000", '0', '0', '0', '0', ZERO, '0', is8B, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_pstfd => (LDST, FPU, OP_STORE, RA0_OR_CIA, IMM, CONST_PSI, FRS, NONE, ADD, "000", '0', '0', '0', '0', ZERO, '0', is8B, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_pstfs => (LDST, FPU, OP_STORE, RA0_OR_CIA, IMM, CONST_PSI, FRS, NONE, ADD, "000", '0', '0', '0', '0', ZERO, '0', is4B, '0', '0', '0', '0', '1', '0', NONE, '0', '0', '0', NONE),
INSN_psth => (LDST, NONE, OP_STORE, RA0_OR_CIA, IMM, CONST_PSI, RS, NONE, ADD, "000", '0', '0', '0', '0', ZERO, '0', is2B, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_pstq => (LDST, NONE, OP_STORE, RA0_OR_CIA, IMM, CONST_PSI, RS, NONE, ADD, "000", '0', '0', '0', '0', ZERO, '0', is8B, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', DRSP),
INSN_pstw => (LDST, NONE, OP_STORE, RA0_OR_CIA, IMM, CONST_PSI, RS, NONE, ADD, "000", '0', '0', '0', '0', ZERO, '0', is4B, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_popcntb => (ALU, NONE, OP_COUNTB, NONE, IMM, NONE, RS, RA, ADD, "000", '0', '0', '0', '0', ZERO, '0', is1B, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_popcntd => (ALU, NONE, OP_COUNTB, NONE, IMM, NONE, RS, RA, ADD, "000", '0', '0', '0', '0', ZERO, '0', is8B, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_popcntw => (ALU, NONE, OP_COUNTB, NONE, IMM, NONE, RS, RA, ADD, "000", '0', '0', '0', '0', ZERO, '0', is4B, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_prtyd => (ALU, NONE, OP_PRTY, NONE, IMM, NONE, RS, RA, LOG, "011", '0', '0', '0', '0', ZERO, '0', is8B, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_prtyw => (ALU, NONE, OP_PRTY, NONE, IMM, NONE, RS, RA, LOG, "011", '0', '0', '0', '0', ZERO, '0', is4B, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_rfid => (ALU, NONE, OP_RFID, NONE, IMM, NONE, NONE, NONE, SPR, "000", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '1', '0', NONE),
INSN_rfscv => (ALU, NONE, OP_RFID, NONE, IMM, NONE, NONE, NONE, SPR, "000", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '1', '0', NONE),
INSN_rldcl => (ALU, NONE, OP_RLCL, NONE, RB, NONE, RS, RA, ROT, "000", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0', '0', NONE),
INSN_rldcr => (ALU, NONE, OP_RLCR, NONE, RB, NONE, RS, RA, ROT, "000", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0', '0', NONE),
INSN_rldic => (ALU, NONE, OP_RLC, NONE, IMM, CONST_SH, RS, RA, ROT, "000", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0', '0', NONE),
INSN_rldicl => (ALU, NONE, OP_RLCL, NONE, IMM, CONST_SH, RS, RA, ROT, "000", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0', '0', NONE),
INSN_rldicr => (ALU, NONE, OP_RLCR, NONE, IMM, CONST_SH, RS, RA, ROT, "000", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0', '0', NONE),
INSN_rldimi => (ALU, NONE, OP_RLC, RA, IMM, CONST_SH, RS, RA, ROT, "000", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0', '0', NONE),
INSN_rlwimi => (ALU, NONE, OP_RLC, RA, IMM, CONST_SH32, RS, RA, ROT, "000", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '1', '0', RC, '0', '0', '0', NONE),
INSN_rlwinm => (ALU, NONE, OP_RLC, NONE, IMM, CONST_SH32, RS, RA, ROT, "000", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '1', '0', RC, '0', '0', '0', NONE),
INSN_rlwnm => (ALU, NONE, OP_RLC, NONE, RB, NONE, RS, RA, ROT, "000", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '1', '0', RC, '0', '0', '0', NONE),
INSN_rnop => (ALU, NONE, OP_NOP, NONE, IMM, NONE, NONE, NONE, ADD, "000", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_sc => (ALU, NONE, OP_SC, NONE, IMM, NONE, NONE, NONE, ADD, "000", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_setb => (ALU, NONE, OP_SETB, NONE, IMM, NONE, NONE, RT, MSC, "110", '1', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_slbia => (LDST, NONE, OP_TLBIE, NONE, IMM, NONE, NONE, NONE, ADD, "000", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '1', '0', NONE),
INSN_sld => (ALU, NONE, OP_SHL, NONE, RB, NONE, RS, RA, ROT, "000", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0', '0', NONE),
INSN_slw => (ALU, NONE, OP_SHL, NONE, RB, NONE, RS, RA, ROT, "000", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '1', '0', RC, '0', '0', '0', NONE),
INSN_srad => (ALU, NONE, OP_SHR, NONE, RB, NONE, RS, RA, ROT, "000", '0', '0', '0', '0', ZERO, '1', NONE, '0', '0', '0', '0', '0', '1', RC, '0', '0', '0', NONE),
INSN_sradi => (ALU, NONE, OP_SHR, NONE, IMM, CONST_SH, RS, RA, ROT, "000", '0', '0', '0', '0', ZERO, '1', NONE, '0', '0', '0', '0', '0', '1', RC, '0', '0', '0', NONE),
INSN_sraw => (ALU, NONE, OP_SHR, NONE, RB, NONE, RS, RA, ROT, "000", '0', '0', '0', '0', ZERO, '1', NONE, '0', '0', '0', '0', '1', '1', RC, '0', '0', '0', NONE),
INSN_srawi => (ALU, NONE, OP_SHR, NONE, IMM, CONST_SH32, RS, RA, ROT, "000", '0', '0', '0', '0', ZERO, '1', NONE, '0', '0', '0', '0', '1', '1', RC, '0', '0', '0', NONE),
INSN_srd => (ALU, NONE, OP_SHR, NONE, RB, NONE, RS, RA, ROT, "000", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0', '0', NONE),
INSN_srw => (ALU, NONE, OP_SHR, NONE, RB, NONE, RS, RA, ROT, "000", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '1', '0', RC, '0', '0', '0', NONE),
INSN_stb => (LDST, NONE, OP_STORE, RA_OR_ZERO, IMM, CONST_SI, RS, NONE, ADD, "000", '0', '0', '0', '0', ZERO, '0', is1B, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_stbcix => (LDST, NONE, OP_STORE, RA_OR_ZERO, RB, NONE, RS, NONE, ADD, "000", '0', '0', '1', '0', ZERO, '0', is1B, '0', '0', '0', '0', '0', '0', NONE, '0', '1', '0', NONE),
INSN_stbcx => (LDST, NONE, OP_STORE, RA_OR_ZERO, RB, NONE, RS, NONE, ADD, "000", '0', '0', '0', '0', ZERO, '0', is1B, '0', '0', '0', '1', '0', '0', ONE, '0', '0', '0', NONE),
INSN_stbu => (LDST, NONE, OP_STORE, RA_OR_ZERO, IMM, CONST_SI, RS, RA, ADD, "000", '0', '0', '0', '0', ZERO, '0', is1B, '0', '0', '1', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_stbux => (LDST, NONE, OP_STORE, RA_OR_ZERO, RB, NONE, RS, RA, ADD, "000", '0', '0', '0', '0', ZERO, '0', is1B, '0', '0', '1', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_stbx => (LDST, NONE, OP_STORE, RA_OR_ZERO, RB, NONE, RS, NONE, ADD, "000", '0', '0', '0', '0', ZERO, '0', is1B, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_std => (LDST, NONE, OP_STORE, RA_OR_ZERO, IMM, CONST_DS, RS, NONE, ADD, "000", '0', '0', '0', '0', ZERO, '0', is8B, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_stdbrx => (LDST, NONE, OP_STORE, RA_OR_ZERO, RB, NONE, RS, NONE, ADD, "000", '0', '0', '0', '0', ZERO, '0', is8B, '1', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_stdcix => (LDST, NONE, OP_STORE, RA_OR_ZERO, RB, NONE, RS, NONE, ADD, "000", '0', '0', '1', '0', ZERO, '0', is8B, '0', '0', '0', '0', '0', '0', NONE, '0', '1', '0', NONE),
INSN_stdcx => (LDST, NONE, OP_STORE, RA_OR_ZERO, RB, NONE, RS, NONE, ADD, "000", '0', '0', '0', '0', ZERO, '0', is8B, '0', '0', '0', '1', '0', '0', ONE, '0', '0', '0', NONE),
INSN_stdu => (LDST, NONE, OP_STORE, RA_OR_ZERO, IMM, CONST_DS, RS, RA, ADD, "000", '0', '0', '0', '0', ZERO, '0', is8B, '0', '0', '1', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_stdux => (LDST, NONE, OP_STORE, RA_OR_ZERO, RB, NONE, RS, RA, ADD, "000", '0', '0', '0', '0', ZERO, '0', is8B, '0', '0', '1', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_stdx => (LDST, NONE, OP_STORE, RA_OR_ZERO, RB, NONE, RS, NONE, ADD, "000", '0', '0', '0', '0', ZERO, '0', is8B, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_stfd => (LDST, FPU, OP_STORE, RA_OR_ZERO, IMM, CONST_SI, FRS, NONE, ADD, "000", '0', '0', '0', '0', ZERO, '0', is8B, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_stfdu => (LDST, FPU, OP_STORE, RA_OR_ZERO, IMM, CONST_SI, FRS, RA, ADD, "000", '0', '0', '0', '0', ZERO, '0', is8B, '0', '0', '1', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_stfdux => (LDST, FPU, OP_STORE, RA_OR_ZERO, RB, NONE, FRS, RA, ADD, "000", '0', '0', '0', '0', ZERO, '0', is8B, '0', '0', '1', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_stfdx => (LDST, FPU, OP_STORE, RA_OR_ZERO, RB, NONE, FRS, NONE, ADD, "000", '0', '0', '0', '0', ZERO, '0', is8B, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_stfiwx => (LDST, FPU, OP_STORE, RA_OR_ZERO, RB, NONE, FRS, NONE, ADD, "000", '0', '0', '0', '0', ZERO, '0', is4B, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_stfs => (LDST, FPU, OP_STORE, RA_OR_ZERO, IMM, CONST_SI, FRS, NONE, ADD, "000", '0', '0', '0', '0', ZERO, '0', is4B, '0', '0', '0', '0', '1', '0', NONE, '0', '0', '0', NONE),
INSN_stfsu => (LDST, FPU, OP_STORE, RA_OR_ZERO, IMM, CONST_SI, FRS, RA, ADD, "000", '0', '0', '0', '0', ZERO, '0', is4B, '0', '0', '1', '0', '1', '0', NONE, '0', '0', '0', NONE),
INSN_stfsux => (LDST, FPU, OP_STORE, RA_OR_ZERO, RB, NONE, FRS, RA, ADD, "000", '0', '0', '0', '0', ZERO, '0', is4B, '0', '0', '1', '0', '1', '0', NONE, '0', '0', '0', NONE),
INSN_stfsx => (LDST, FPU, OP_STORE, RA_OR_ZERO, RB, NONE, FRS, NONE, ADD, "000", '0', '0', '0', '0', ZERO, '0', is4B, '0', '0', '0', '0', '1', '0', NONE, '0', '0', '0', NONE),
INSN_sth => (LDST, NONE, OP_STORE, RA_OR_ZERO, IMM, CONST_SI, RS, NONE, ADD, "000", '0', '0', '0', '0', ZERO, '0', is2B, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_sthbrx => (LDST, NONE, OP_STORE, RA_OR_ZERO, RB, NONE, RS, NONE, ADD, "000", '0', '0', '0', '0', ZERO, '0', is2B, '1', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_sthcix => (LDST, NONE, OP_STORE, RA_OR_ZERO, RB, NONE, RS, NONE, ADD, "000", '0', '0', '1', '0', ZERO, '0', is2B, '0', '0', '0', '0', '0', '0', NONE, '0', '1', '0', NONE),
INSN_sthcx => (LDST, NONE, OP_STORE, RA_OR_ZERO, RB, NONE, RS, NONE, ADD, "000", '0', '0', '0', '0', ZERO, '0', is2B, '0', '0', '0', '1', '0', '0', ONE, '0', '0', '0', NONE),
INSN_sthu => (LDST, NONE, OP_STORE, RA_OR_ZERO, IMM, CONST_SI, RS, RA, ADD, "000", '0', '0', '0', '0', ZERO, '0', is2B, '0', '0', '1', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_sthux => (LDST, NONE, OP_STORE, RA_OR_ZERO, RB, NONE, RS, RA, ADD, "000", '0', '0', '0', '0', ZERO, '0', is2B, '0', '0', '1', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_sthx => (LDST, NONE, OP_STORE, RA_OR_ZERO, RB, NONE, RS, NONE, ADD, "000", '0', '0', '0', '0', ZERO, '0', is2B, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_stq => (LDST, NONE, OP_STORE, RA_OR_ZERO, IMM, CONST_DS, RS, NONE, ADD, "000", '0', '0', '0', '0', ZERO, '0', is8B, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', DRSP),
INSN_stqcx => (LDST, NONE, OP_STORE, RA_OR_ZERO, RB, NONE, RS, NONE, ADD, "000", '0', '0', '0', '0', ZERO, '0', is8B, '0', '0', '0', '1', '0', '0', ONE, '0', '0', '0', DRSP),
INSN_stw => (LDST, NONE, OP_STORE, RA_OR_ZERO, IMM, CONST_SI, RS, NONE, ADD, "000", '0', '0', '0', '0', ZERO, '0', is4B, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_stwbrx => (LDST, NONE, OP_STORE, RA_OR_ZERO, RB, NONE, RS, NONE, ADD, "000", '0', '0', '0', '0', ZERO, '0', is4B, '1', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_stwcix => (LDST, NONE, OP_STORE, RA_OR_ZERO, RB, NONE, RS, NONE, ADD, "000", '0', '0', '1', '0', ZERO, '0', is4B, '0', '0', '0', '0', '0', '0', NONE, '0', '1', '0', NONE),
INSN_stwcx => (LDST, NONE, OP_STORE, RA_OR_ZERO, RB, NONE, RS, NONE, ADD, "000", '0', '0', '0', '0', ZERO, '0', is4B, '0', '0', '0', '1', '0', '0', ONE, '0', '0', '0', NONE),
INSN_stwu => (LDST, NONE, OP_STORE, RA_OR_ZERO, IMM, CONST_SI, RS, RA, ADD, "000", '0', '0', '0', '0', ZERO, '0', is4B, '0', '0', '1', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_stwux => (LDST, NONE, OP_STORE, RA_OR_ZERO, RB, NONE, RS, RA, ADD, "000", '0', '0', '0', '0', ZERO, '0', is4B, '0', '0', '1', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_stwx => (LDST, NONE, OP_STORE, RA_OR_ZERO, RB, NONE, RS, NONE, ADD, "000", '0', '0', '0', '0', ZERO, '0', is4B, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_subf => (ALU, NONE, OP_ADD, RA, RB, NONE, NONE, RT, ADD, "000", '0', '0', '1', '0', ONE, '0', NONE, '0', '0', '0', '0', '0', '0', RCOE, '0', '0', '0', NONE),
INSN_subfc => (ALU, NONE, OP_ADD, RA, RB, NONE, NONE, RT, ADD, "000", '0', '0', '1', '0', ONE, '1', NONE, '0', '0', '0', '0', '0', '0', RCOE, '0', '0', '0', NONE),
INSN_subfe => (ALU, NONE, OP_ADD, RA, RB, NONE, NONE, RT, ADD, "000", '0', '0', '1', '0', CA, '1', NONE, '0', '0', '0', '0', '0', '0', RCOE, '0', '0', '0', NONE),
INSN_subfic => (ALU, NONE, OP_ADD, RA, IMM, CONST_SI, NONE, RT, ADD, "000", '0', '0', '1', '0', ONE, '1', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_subfme => (ALU, NONE, OP_ADD, RA, IMM, CONST_M1, NONE, RT, ADD, "000", '0', '0', '1', '0', CA, '1', NONE, '0', '0', '0', '0', '0', '0', RCOE, '0', '0', '0', NONE),
INSN_subfze => (ALU, NONE, OP_ADD, RA, IMM, NONE, NONE, RT, ADD, "000", '0', '0', '1', '0', CA, '1', NONE, '0', '0', '0', '0', '0', '0', RCOE, '0', '0', '0', NONE),
INSN_sync => (LDST, NONE, OP_SYNC, NONE, IMM, NONE, NONE, NONE, ADD, "000", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '1', NONE),
INSN_td => (ALU, NONE, OP_TRAP, RA, RB, NONE, NONE, NONE, ADD, "000", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_tdi => (ALU, NONE, OP_TRAP, RA, IMM, CONST_SI, NONE, NONE, ADD, "000", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_tlbie => (LDST, NONE, OP_TLBIE, NONE, RB, NONE, RS, NONE, ADD, "000", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '1', '0', NONE),
INSN_tlbiel => (LDST, NONE, OP_TLBIE, NONE, RB, NONE, RS, NONE, ADD, "000", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '1', '0', NONE),
INSN_tlbsync => (ALU, NONE, OP_NOP, NONE, IMM, NONE, NONE, NONE, ADD, "000", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '1', '0', NONE),
INSN_tw => (ALU, NONE, OP_TRAP, RA, RB, NONE, NONE, NONE, ADD, "000", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '1', '0', NONE, '0', '0', '0', NONE),
INSN_twi => (ALU, NONE, OP_TRAP, RA, IMM, CONST_SI, NONE, NONE, ADD, "000", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '1', '0', NONE, '0', '0', '0', NONE),
INSN_wait => (ALU, NONE, OP_WAIT, NONE, IMM, NONE, NONE, NONE, ADD, "000", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '1', NONE),
INSN_xor => (ALU, NONE, OP_XOR, NONE, RB, NONE, RS, RA, LOG, "001", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0', '0', NONE),
INSN_xori => (ALU, NONE, OP_XOR, NONE, IMM, CONST_UI, RS, RA, LOG, "001", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),
INSN_xoris => (ALU, NONE, OP_XOR, NONE, IMM, CONST_UI_HI, RS, RA, LOG, "001", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE),

others => (ALU, NONE, OP_ILLEGAL, NONE, IMM, NONE, NONE, NONE, ADD, "000", '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0', '0', NONE)
);

function decode_ram_spr(sprn : spr_num_t) return ram_spr_info is
@ -726,12 +726,6 @@ begin
if (icode = INSN_stq or icode = INSN_stqcx) and f_in.big_endian = '0' then
vr.reg_3_addr(0) := '1';
end if;
-- See if this is an instruction where we need to use the RS/RC
-- read port to read the RB operand, because we want to get an
-- immediate operand to execute1 via read_data2.
if (icode = INSN_hashst or icode = INSN_hashchk or icode = INSN_hashstp or icode = INSN_hashchkp) then
vr.reg_3_addr := '0' & insn_rb(f_in.insn);
end if;
vr.read_1_enable := f_in.valid;
vr.read_2_enable := f_in.valid and maybe_rb;
vr.read_3_enable := f_in.valid;

140
decode2.vhdl
Unescape Escape View File

@ -85,16 +85,16 @@ architecture behaviour of decode2 is

function decode_input_reg_a (t : input_reg_a_t; insn_in : std_ulogic_vector(31 downto 0);
prefix : std_ulogic_vector(25 downto 0))
return decode_input_reg_t is
return std_ulogic is
begin
if t = RA or ((t = RA_OR_ZERO or t = RA0_OR_CIA) and insn_ra(insn_in) /= "00000") then
return ('1', gpr_to_gspr(insn_ra(insn_in)));
return '1';
elsif t = CIA or (t = RA0_OR_CIA and insn_prefix_r(prefix) = '1') then
return ('0', (others => '0'));
elsif HAS_FPU and t = FRA then
return ('1', fpr_to_gspr(insn_fra(insn_in)));
return '0';
elsif t = FRA then
return '1';
else
return ('0', (others => '0'));
return '0';
end if;
end;

@ -140,8 +140,6 @@ architecture behaviour of decode2 is
ret := x"00000000000000" & "00" & insn_in(1) & insn_in(15 downto 11);
when CONST_SH32 =>
ret := x"00000000000000" & "000" & insn_in(15 downto 11);
when CONST_DSX =>
ret := 55x"7FFFFFFFFFFFFF" & insn_in(0) & insn_in(25 downto 21) & "000";
when others =>
ret := (others => '0');
end case;
@ -149,49 +147,25 @@ architecture behaviour of decode2 is
return ret;
end;

function decode_input_reg_b (t : input_reg_b_t; insn_in : std_ulogic_vector(31 downto 0))
return decode_input_reg_t is
variable ret : decode_input_reg_t;
function decode_input_reg_b (t : input_reg_b_t)
return std_ulogic is
begin
case t is
when RB =>
ret := ('1', gpr_to_gspr(insn_rb(insn_in)));
when FRB =>
if HAS_FPU then
ret := ('1', fpr_to_gspr(insn_frb(insn_in)));
else
ret := ('0', (others => '0'));
end if;
when RB | FRB =>
return '1';
when IMM =>
ret := ('0', (others => '0'));
return '0';
end case;
return ret;
end;

function decode_input_reg_c (t : input_reg_c_t; insn_in : std_ulogic_vector(31 downto 0))
return decode_input_reg_t is
function decode_input_reg_c (t : input_reg_c_t)
return std_ulogic is
begin
case t is
when RS =>
return ('1', gpr_to_gspr(insn_rs(insn_in)));
when RCR =>
return ('1', gpr_to_gspr(insn_rcreg(insn_in)));
when FRS =>
if HAS_FPU then
return ('1', fpr_to_gspr(insn_frt(insn_in)));
else
return ('0', (others => '0'));
end if;
when FRC =>
if HAS_FPU then
return ('1', fpr_to_gspr(insn_frc(insn_in)));
else
return ('0', (others => '0'));
end if;
when RBC =>
return ('1', gpr_to_gspr(insn_rb(insn_in)));
when RS | RCR | FRS | FRC =>
return '1';
when NONE =>
return ('0', (others => '0'));
return '0';
end case;
end;

@ -243,59 +217,6 @@ architecture behaviour of decode2 is
return t;
end;

-- control signals that are derived from insn_type
type mux_select_array_t is array(insn_type_t) of std_ulogic_vector(2 downto 0);

constant result_select : mux_select_array_t := (
OP_LOGIC => "001", -- logical_result
OP_XOR => "001",
OP_PRTY => "001",
OP_CMPB => "001",
OP_EXTS => "001",
OP_BREV => "001",
OP_BCD => "001",
OP_MTSPR => "001",
OP_RLC => "010", -- rotator_result
OP_RLCL => "010",
OP_RLCR => "010",
OP_SHL => "010",
OP_SHR => "010",
OP_EXTSWSLI => "010",
OP_BCREG => "101", -- ramspr_result
OP_RFID => "101",
OP_ADDG6S => "111", -- misc_result
OP_ISEL => "111",
OP_DARN => "111",
OP_MFMSR => "111",
OP_MFCR => "111",
OP_SETB => "111",
others => "000" -- default to adder_result
);

constant subresult_select : mux_select_array_t := (
OP_MUL_L64 => "000", -- multicyc_result
OP_MUL_H64 => "010",
OP_MUL_H32 => "001",
OP_DIV => "101",
OP_DIVE => "101",
OP_MOD => "101",
OP_BSORT => "100",
OP_BPERM => "100",
OP_ADDG6S => "001", -- misc_result
OP_ISEL => "010",
OP_DARN => "011",
OP_MFMSR => "100",
OP_MFCR => "101",
OP_SETB => "110",
OP_CMP => "000", -- cr_result
OP_CMPRB => "001",
OP_CMPEQB => "010",
OP_CROP => "011",
OP_MCRXRX => "100",
OP_MTCRF => "101",
others => "000"
);

signal decoded_reg_a : decode_input_reg_t;
signal decoded_reg_b : decode_input_reg_t;
signal decoded_reg_c : decode_input_reg_t;
@ -402,11 +323,6 @@ begin
dc2.e.ramspr_odd_rdaddr <= dc2in.e.ramspr_odd_rdaddr;
dc2.e.ramspr_rd_odd <= dc2in.e.ramspr_rd_odd;
end if;
if d_in.valid = '1' then
assert decoded_reg_a.reg_valid = '0' or decoded_reg_a.reg = d_in.reg_a severity failure;
assert decoded_reg_b.reg_valid = '0' or decoded_reg_b.reg = d_in.reg_b severity failure;
assert decoded_reg_c.reg_valid = '0' or decoded_reg_c.reg = d_in.reg_c severity failure;
end if;
end if;
end process;

@ -416,9 +332,12 @@ begin
variable dec_a, dec_b, dec_c : decode_input_reg_t;
variable dec_o : decode_output_reg_t;
begin
dec_a := decode_input_reg_a (d_in.decode.input_reg_a, d_in.insn, d_in.prefix);
dec_b := decode_input_reg_b (d_in.decode.input_reg_b, d_in.insn);
dec_c := decode_input_reg_c (d_in.decode.input_reg_c, d_in.insn);
dec_a.reg_valid := decode_input_reg_a (d_in.decode.input_reg_a, d_in.insn, d_in.prefix);
dec_a.reg := d_in.reg_a;
dec_b.reg_valid := decode_input_reg_b (d_in.decode.input_reg_b);
dec_b.reg := d_in.reg_b;
dec_c.reg_valid := decode_input_reg_c (d_in.decode.input_reg_c);
dec_c.reg := d_in.reg_c;
dec_o := decode_output_reg (d_in.decode.output_reg_a, d_in.insn);
case d_in.decode.repeat is
when DUPD =>
@ -693,19 +612,8 @@ begin
v.e.update := d_in.decode.update;
v.e.reserve := d_in.decode.reserve;
v.e.br_pred := d_in.br_pred;
v.e.result_sel := result_select(op);
v.e.sub_select := subresult_select(op);
if op = OP_MFSPR then
if d_in.ram_spr.valid = '1' then
v.e.result_sel := "101"; -- ramspr_result
elsif d_in.spr_info.valid = '0' or d_in.spr_info.wonly = '1' or
d_in.spr_info.noop = '1' then
-- Privileged mfspr to invalid/unimplemented SPR numbers
-- writes the contents of RT back to RT (i.e. it's a no-op)
-- as does any mfspr from the reserved/noop SPR numbers
v.e.result_sel := "001"; -- logical_result
end if;
end if;
v.e.result_sel := d_in.decode.result;
v.e.sub_select := d_in.decode.subresult;
v.e.privileged := d_in.decode.privileged;
if (op = OP_MFSPR or op = OP_MTSPR) and d_in.insn(20) = '1' then
v.e.privileged := '1';

15
decode_types.vhdl
Unescape Escape View File

@ -420,9 +420,8 @@ package decode_types is
type input_reg_a_t is (NONE, RA, RA_OR_ZERO, RA0_OR_CIA, CIA, FRA);
type input_reg_b_t is (IMM, RB, FRB);
type const_sel_t is (NONE, CONST_UI, CONST_SI, CONST_SI_HI, CONST_UI_HI, CONST_LI, CONST_BD,
CONST_DXHI4, CONST_DS, CONST_DQ, CONST_M1, CONST_SH, CONST_SH32, CONST_PSI,
CONST_DSX);
type input_reg_c_t is (NONE, RS, RCR, RBC, FRC, FRS);
CONST_DXHI4, CONST_DS, CONST_DQ, CONST_M1, CONST_SH, CONST_SH32, CONST_PSI);
type input_reg_c_t is (NONE, RS, RCR, FRC, FRS);
type output_reg_a_t is (NONE, RT, RA, FRT);
type rc_t is (NONE, ONE, RC, RCOE);
type carry_in_t is (ZERO, CA, OV, ONE);
@ -449,6 +448,9 @@ package decode_types is
type facility_t is (NONE, FPU);
type length_t is (NONE, is1B, is2B, is4B, is8B);

type result_sel_t is (ADD, LOG, ROT, UN3, MCYC, SPR, UN6, MSC);
subtype subresult_sel_t is std_ulogic_vector(2 downto 0);

type repeat_t is (NONE, -- instruction is not repeated
DUPD, -- update-form load
DRSP, -- double RS (RS, RS+1)
@ -464,6 +466,10 @@ package decode_types is
input_reg_c : input_reg_c_t;
output_reg_a : output_reg_a_t;

-- Result multiplexor control
result : result_sel_t;
subresult : subresult_sel_t;

input_cr : std_ulogic;
output_cr : std_ulogic;

@ -493,7 +499,8 @@ package decode_types is
constant decode_rom_init : decode_rom_t := (unit => ALU, facility => NONE,
insn_type => OP_ILLEGAL, input_reg_a => NONE,
input_reg_b => IMM, const_sel => NONE, input_reg_c => NONE,
output_reg_a => NONE, input_cr => '0', output_cr => '0',
output_reg_a => NONE, result => ADD, subresult => "000",
input_cr => '0', output_cr => '0',
invert_a => '0', invert_out => '0', input_carry => ZERO, output_carry => '0',
length => NONE, byte_reverse => '0', sign_extend => '0',
update => '0', reserve => '0', is_32bit => '0',

93
execute1.vhdl
Unescape Escape View File

@ -102,6 +102,7 @@ architecture behaviour of execute1 is
scv_trap : std_ulogic;
write_tbl : std_ulogic;
write_tbu : std_ulogic;
noop_spr_read : std_ulogic;
end record;
constant side_effect_init : side_effect_type := (others => '0');

@ -125,13 +126,13 @@ architecture behaviour of execute1 is
fp_intr : std_ulogic;
res2_sel : std_ulogic_vector(1 downto 0);
bypass_valid : std_ulogic;
ramspr_odd_data : std_ulogic_vector(63 downto 0);
spr_write_data : std_ulogic_vector(63 downto 0);
ic : std_ulogic_vector(3 downto 0);
end record;
constant actions_type_init : actions_type :=
(e => Execute1ToWritebackInit, se => side_effect_init,
new_msr => (others => '0'), res2_sel => "00",
ramspr_odd_data => 64x"0", ic => x"0", others => '0');
spr_write_data => 64x"0", ic => x"0", others => '0');

type reg_stage1_type is record
e : Execute1ToWritebackType;
@ -164,7 +165,7 @@ architecture behaviour of execute1 is
xerc : xer_common_t;
xerc_valid : std_ulogic;
ramspr_wraddr : ramspr_index;
ramspr_odd_data : std_ulogic_vector(63 downto 0);
spr_write_data : std_ulogic_vector(63 downto 0);
ic : std_ulogic_vector(3 downto 0);
prefixed : std_ulogic;
insn : std_ulogic_vector(31 downto 0);
@ -184,7 +185,7 @@ architecture behaviour of execute1 is
taken_branch_event => '0', br_mispredict => '0',
msr => 64x"0",
xerc => xerc_init, xerc_valid => '0',
ramspr_wraddr => (others => '0'), ramspr_odd_data => 64x"0",
ramspr_wraddr => (others => '0'), spr_write_data => 64x"0",
ic => x"0",
prefixed => '0', insn => 32x"0", prefix => 26x"0");

@ -223,7 +224,7 @@ architecture behaviour of execute1 is
signal bsort_result: std_ulogic_vector(63 downto 0);
signal spr_result: std_ulogic_vector(63 downto 0);
signal next_nia : std_ulogic_vector(63 downto 0);
signal s1_sel : std_ulogic_vector(2 downto 0);
signal s1_sel : result_sel_t;
signal log_spr_data : std_ulogic_vector(63 downto 0);

signal carry_32 : std_ulogic;
@ -496,7 +497,7 @@ begin
port map (
rs => c_in,
rb => b_in,
op => e_in.insn_type,
op => e_in.sub_select,
invert_in => e_in.invert_a,
invert_out => e_in.invert_out,
is_signed => e_in.is_signed,
@ -595,13 +596,13 @@ begin
thi := timebase(63 downto 32);
carry := '0';
if stage2_stall = '0' and ex1.se.write_tbl = '1' then
tlo := ex1.e.write_data(31 downto 0);
tlo := ex1.spr_write_data(31 downto 0);
elsif tb_ctrl.freeze = '0' then
tlo := std_ulogic_vector(unsigned(tlo) + 1);
carry := tb_carry;
end if;
if stage2_stall = '0' and ex1.se.write_tbu = '1' then
thi := ex1.e.write_data(31 downto 0);
thi := ex1.spr_write_data(31 downto 0);
else
thi := std_ulogic_vector(unsigned(thi) + carry);
end if;
@ -640,7 +641,7 @@ begin
x_to_pmu.addr <= l_in.ea_for_pmu;
x_to_pmu.addr_v <= l_in.ea_valid;
x_to_pmu.spr_num <= ex1.pmu_spr_num;
x_to_pmu.spr_val <= ex1.e.write_data;
x_to_pmu.spr_val <= ex1.spr_write_data;
x_to_pmu.run <= ctrl.run;
x_to_pmu.trace <= pmu_trace;

@ -704,14 +705,14 @@ begin
if ex1.lr_from_next = '1' then
ramspr_even_data := next_nia;
else
ramspr_even_data := ex1.e.write_data;
ramspr_even_data := ex1.spr_write_data;
end if;
if interrupt_in.intr = '1' then
even_wr_data := ex2.e.last_nia;
odd_wr_data := intr_srr1(ctrl.msr, interrupt_in.srr1);
else
even_wr_data := ramspr_even_data;
odd_wr_data := ex1.ramspr_odd_data;
odd_wr_data := ex1.spr_write_data;
end if;
ramspr_wr_addr <= wr_addr;
ramspr_even_wr_data <= even_wr_data;
@ -728,7 +729,7 @@ begin
ramspr_even <= even_rd_data;
end if;
if ex1.se.ramspr_write_odd = '1' and e_in.ramspr_odd_rdaddr = ex1.ramspr_wraddr then
ramspr_odd <= ex1.ramspr_odd_data;
ramspr_odd <= ex1.spr_write_data;
else
ramspr_odd <= odd_rd_data;
end if;
@ -761,14 +762,15 @@ begin
end process;

-- First stage result mux
s1_sel <= e_in.result_sel when ex1.busy = '0' else "100";
s1_sel <= e_in.result_sel when ex1.busy = '0' else MCYC;
with s1_sel select alu_result <=
adder_result when "000",
logical_result when "001",
rotator_result when "010",
multicyc_result when "100",
ramspr_result when "101",
misc_result when others;
adder_result when ADD,
logical_result when LOG,
rotator_result when ROT,
multicyc_result when MCYC,
ramspr_result when SPR,
misc_result when MSC,
64x"0" when others;

execute1_0: process(clk)
begin
@ -1210,9 +1212,9 @@ begin

v.se.ramspr_write_even := e_in.ramspr_write_even;
v.se.ramspr_write_odd := e_in.ramspr_write_odd;
v.ramspr_odd_data := c_in;
v.spr_write_data := c_in;
if e_in.dec_ctr = '1' then
v.ramspr_odd_data := std_ulogic_vector(unsigned(ramspr_odd) - 1);
v.spr_write_data := std_ulogic_vector(unsigned(ramspr_odd) - 1);
end if;

-- Note the difference between v.exception and v.trap:
@ -1390,16 +1392,17 @@ begin
when OP_DARN =>
when OP_MFMSR =>
when OP_MFSPR =>
if e_in.spr_is_ram = '1' or e_in.spr_select.noop = '1' then
if e_in.spr_is_ram = '1' then
if e_in.valid = '1' and not is_X(e_in.insn) then
report "MFSPR to SPR " & integer'image(decode_spr_num(e_in.insn)) &
"=" & to_hstring(alu_result);
end if;
elsif e_in.spr_select.valid = '1' then
elsif e_in.spr_select.valid = '1' and e_in.spr_select.wonly = '0' then
if e_in.valid = '1' and not is_X(e_in.insn) then
report "MFSPR to slow SPR " & integer'image(decode_spr_num(e_in.insn));
end if;
slow_op := '1';
v.se.noop_spr_read := e_in.spr_select.noop;
if e_in.spr_select.ispmu = '0' then
case e_in.spr_select.sel is
when SPRSEL_LOGR =>
@ -1419,6 +1422,8 @@ begin
report "MFSPR to SPR " & integer'image(decode_spr_num(e_in.insn)) &
" invalid";
end if;
slow_op := '1';
v.se.noop_spr_read := '1';
if ex1.msr(MSR_PR) = '1' then
illegal := '1';
end if;
@ -1675,7 +1680,7 @@ begin
v.se := side_effect_init;
v.ramspr_wraddr := e_in.ramspr_wraddr;
v.lr_from_next := e_in.lr;
v.ramspr_odd_data := actions.ramspr_odd_data;
v.spr_write_data := actions.spr_write_data;
v.ic := actions.ic;
v.prefixed := e_in.prefixed;
v.insn := e_in.insn;
@ -2059,7 +2064,9 @@ begin
else
rcresult := countbits_result;
end if;
if ex1.res2_sel(0) = '0' then
if ex1.se.noop_spr_read = '1' then
sprres := ex1.spr_write_data;
elsif ex1.res2_sel(0) = '0' then
sprres := spr_result;
else
sprres := pmu_to_x.spr_val;
@ -2103,40 +2110,40 @@ begin
ctrl_tmp.msr <= ex1.msr;
end if;
if ex1.se.write_xerlow = '1' then
ctrl_tmp.xer_low <= ex1.e.write_data(17 downto 0);
ctrl_tmp.xer_low <= ex1.spr_write_data(17 downto 0);
end if;
if ex1.se.write_dec = '1' then
ctrl_tmp.dec <= ex1.e.write_data;
ctrl_tmp.dec <= ex1.spr_write_data;
end if;
if ex1.se.write_cfar = '1' then
ctrl_tmp.cfar <= ex1.e.write_data;
ctrl_tmp.cfar <= ex1.spr_write_data;
elsif ex1.se.set_cfar = '1' then
ctrl_tmp.cfar <= ex1.e.last_nia;
end if;
if ex1.se.write_loga = '1' then
v.log_addr_spr := ex1.e.write_data(31 downto 0);
v.log_addr_spr := ex1.spr_write_data(31 downto 0);
elsif ex1.se.inc_loga = '1' then
v.log_addr_spr := std_ulogic_vector(unsigned(ex2.log_addr_spr) + 1);
end if;
x_to_pmu.mtspr <= ex1.se.write_pmuspr;
if ex1.se.write_fscr = '1' then
ctrl_tmp.fscr_ic <= ex1.e.write_data(59 downto 56);
ctrl_tmp.fscr_pref <= ex1.e.write_data(FSCR_PREFIX);
ctrl_tmp.fscr_scv <= ex1.e.write_data(FSCR_SCV);
ctrl_tmp.fscr_tar <= ex1.e.write_data(FSCR_TAR);
ctrl_tmp.fscr_dscr <= ex1.e.write_data(FSCR_DSCR);
ctrl_tmp.fscr_ic <= ex1.spr_write_data(59 downto 56);
ctrl_tmp.fscr_pref <= ex1.spr_write_data(FSCR_PREFIX);
ctrl_tmp.fscr_scv <= ex1.spr_write_data(FSCR_SCV);
ctrl_tmp.fscr_tar <= ex1.spr_write_data(FSCR_TAR);
ctrl_tmp.fscr_dscr <= ex1.spr_write_data(FSCR_DSCR);
elsif ex1.se.write_ic = '1' then
ctrl_tmp.fscr_ic <= ex1.ic;
end if;
if ex1.se.write_lpcr = '1' then
ctrl_tmp.lpcr_hail <= ex1.e.write_data(LPCR_HAIL);
ctrl_tmp.lpcr_ld <= ex1.e.write_data(LPCR_LD);
ctrl_tmp.lpcr_heic <= ex1.e.write_data(LPCR_HEIC);
ctrl_tmp.lpcr_lpes <= ex1.e.write_data(LPCR_LPES);
ctrl_tmp.lpcr_hvice <= ex1.e.write_data(LPCR_HVICE);
ctrl_tmp.lpcr_hail <= ex1.spr_write_data(LPCR_HAIL);
ctrl_tmp.lpcr_ld <= ex1.spr_write_data(LPCR_LD);
ctrl_tmp.lpcr_heic <= ex1.spr_write_data(LPCR_HEIC);
ctrl_tmp.lpcr_lpes <= ex1.spr_write_data(LPCR_LPES);
ctrl_tmp.lpcr_hvice <= ex1.spr_write_data(LPCR_HVICE);
end if;
if ex1.se.write_heir = '1' then
ctrl_tmp.heir <= ex1.e.write_data;
ctrl_tmp.heir <= ex1.spr_write_data;
elsif ex1.se.set_heir = '1' then
ctrl_tmp.heir(31 downto 0) <= ex1.insn;
if ex1.prefixed = '1' then
@ -2147,13 +2154,13 @@ begin
end if;
end if;
if ex1.se.write_ctrl = '1' then
ctrl_tmp.run <= ex1.e.write_data(0);
ctrl_tmp.run <= ex1.spr_write_data(0);
end if;
if ex1.se.write_dscr = '1' then
ctrl_tmp.dscr <= ex1.e.write_data(24 downto 0);
ctrl_tmp.dscr <= ex1.spr_write_data(24 downto 0);
end if;
if ex1.se.write_ciabr = '1' then
ctrl_tmp.ciabr <= ex1.e.write_data;
ctrl_tmp.ciabr <= ex1.spr_write_data;
end if;
if ex1.se.enter_wait = '1' then
ctrl_tmp.wait_state <= '1';

14
fpga/top-acorn-cle-215.vhdl
Unescape Escape View File

@ -10,6 +10,7 @@ use work.wishbone_types.all;

entity toplevel is
generic (
CPUS : natural := 1;
MEMORY_SIZE : integer := 16384;
RAM_INIT_FILE : string := "firmware.hex";
CLK_FREQUENCY : positive := 100000000;
@ -66,6 +67,9 @@ architecture behaviour of toplevel is
-- Internal clock
signal ext_clk : std_ulogic;

-- Status
signal run_outs : std_ulogic_vector(CPUS-1 downto 0);

-- Reset signals:
signal soc_rst : std_ulogic;
signal pll_rst : std_ulogic;
@ -124,6 +128,7 @@ begin
MEMORY_SIZE => BRAM_SIZE,
RAM_INIT_FILE => RAM_INIT_FILE,
SIM => false,
NCPUS => CPUS,
CLK_FREQ => CLK_FREQUENCY,
HAS_DRAM => USE_LITEDRAM,
DRAM_SIZE => 1024 * 1024 * 1024,
@ -141,6 +146,7 @@ begin
-- System signals
system_clk => system_clk,
rst => soc_rst,
run_outs => run_outs,

-- UART signals
uart0_txd => uart_tx,
@ -223,10 +229,10 @@ begin
pll_locked_out => system_clk_locked
);

led0 <= soc_rst;
led1 <= pll_rst;
led2 <= not system_clk_locked;
led3 <= '0';
led0 <= run_outs(0);
led1 <= run_outs(1) when CPUS > 1 else pll_rst;
led2 <= run_outs(2) when CPUS > 2 else not system_clk_locked;
led3 <= run_outs(3) when CPUS > 3 else '0';

-- Vivado barfs on those differential signals if left
-- unconnected. So instanciate a diff. buffer and feed

55
fpu.vhdl
Unescape Escape View File

@ -582,26 +582,6 @@ architecture behaviour of fpu is
return shift_result;
end;

-- Generate a mask with 0-bits on the left and 1-bits on the right which
-- selects the bits will be lost in doing a right shift. The shift
-- parameter is the bottom 6 bits of a negative shift count,
-- indicating a right shift.
function right_mask(shift: unsigned(5 downto 0)) return std_ulogic_vector is
variable mask_result: std_ulogic_vector(63 downto 0);
begin
mask_result := (others => '0');
if is_X(shift) then
mask_result := (others => 'X');
return mask_result;
end if;
for i in 0 to 63 loop
if i >= shift then
mask_result(63 - i) := '1';
end if;
end loop;
return mask_result;
end;

-- Split a DP floating-point number into components and work out its class.
-- If is_int = 1, the input is considered an integer
function decode_dp(fpr: std_ulogic_vector(63 downto 0); is_fp: std_ulogic;
@ -1051,6 +1031,7 @@ begin
variable asign : std_ulogic;
variable bneg : std_ulogic;
variable ci : std_ulogic;
variable rormr : std_ulogic_vector(63 downto 0);
begin
v := r;
v.complete := '0';
@ -3258,22 +3239,26 @@ begin
-- Data path.
-- This has A and B input multiplexers, an adder, a shifter,
-- count-leading-zeroes logic, and a result mux.

-- If shifting right, test if bits of R will be shifted out of significance
if r.longmask = '1' then
mshift := r.shift + to_signed(-29, EXP_BITS);
else
mshift := r.shift;
end if;
if is_X(mshift) then
mask := (others => 'X');
elsif mshift < to_signed(-64, EXP_BITS) then
mask := (others => '1');
elsif mshift >= to_signed(0, EXP_BITS) then
mask := (others => '0');
else
mask := right_mask(unsigned(mshift(5 downto 0)));
end if;
if (or (mask and r.r)) = '1' and set_x = '1' then
v.x := '1';
mshift := to_signed(28, EXP_BITS);
else
mshift := to_signed(-1, EXP_BITS);
end if;
mshift := mshift - r.shift;
if set_x = '1' and not is_X(mshift) and mshift >= to_signed(0, EXP_BITS) then
-- Instead of computing (R & right_mask(63-mshift)) != 0,
-- we compute (R | -R), which has the form 111...10...0
-- where the rightmost 1 is in the same position as the
-- rightmost 1 in R. Then if bit (mshift) of that value
-- is 1, there must be a 1 in the rightmost (mshift + 1)
-- bits of R.
rormr := r.r or std_ulogic_vector(- signed(r.r));
if mshift >= to_signed(64, EXP_BITS) then
mshift := to_signed(63, EXP_BITS);
end if;
v.x := v.x or r.r(to_integer(unsigned(mshift(5 downto 0))));
end if;
asign := '0';
case opsel_a is

16
loadstore1.vhdl
Unescape Escape View File

@ -108,6 +108,7 @@ architecture behave of loadstore1 is
two_dwords : std_ulogic;
incomplete : std_ulogic;
ea_valid : std_ulogic;
hash_addr : std_ulogic_vector(63 downto 0);
end record;
constant request_init : request_t := (addr => (others => '0'),
byte_sel => x"00", second_bytes => x"00",
@ -116,6 +117,7 @@ architecture behave of loadstore1 is
elt_length => x"0", brev_mask => "000",
xerc => xerc_init,
sprsel => "0000", ric => "00",
hash_addr => 64x"0",
others => '0');

type reg_stage1_t is record
@ -529,7 +531,7 @@ begin
-- start a new hash process
hv.z0 := 31x"7D12B0E6"; -- 0xFA2561CD >> 1
ra := l_in.addr1;
rb := l_in.data;
rb := l_in.addr2;
key := l_in.hashkey;
for lane in 0 to 3 loop
j := lane * 16;
@ -566,6 +568,7 @@ begin
variable misaligned : std_ulogic;
variable addr_mask : std_ulogic_vector(2 downto 0);
variable hash_nop : std_ulogic;
variable disp : std_ulogic_vector(63 downto 0);
begin
v := request_init;
sprn := l_in.insn(15 downto 11) & l_in.insn(20 downto 16);
@ -598,6 +601,9 @@ begin
v.sprsel := "100" & sprn(8);
end if;

disp := l_in.addr2;
if l_in.hash = '1' then
end if;
lsu_sum := std_ulogic_vector(unsigned(l_in.addr1) + unsigned(l_in.addr2));

if HAS_FPU and l_in.is_32bit = '1' then
@ -615,8 +621,13 @@ begin
addr := std_ulogic_vector(unsigned(r1.addr0(63 downto 3)) + not l_in.update) &
r1.addr0(2 downto 0);
end if;
-- Hash instructions have a short immediate displacement field,
-- interpreted as a negative multiple of 8
disp := 55x"7FFFFFFFFFFFFF" & l_in.insn(0) & l_in.insn(25 downto 21) & "000";
v.hash_addr := std_ulogic_vector(unsigned(l_in.addr1) + unsigned(disp));
if l_in.mode_32bit = '1' then
addr(63 downto 32) := (others => '0');
v.hash_addr(63 downto 32) := (others => '0');
end if;
v.addr := addr;
v.ea_valid := l_in.valid;
@ -812,6 +823,9 @@ begin
-- need to initiate and then wait for the hash computation
hash_start <= not r1.busy;
v.busy := not hash_r.done;
if r1.busy = '1' then
v.req.addr := r1.req.hash_addr;
end if;
if hash_r.done = '0' then
issue := '0';
else

19
logical.vhdl
Unescape Escape View File

@ -10,7 +10,7 @@ entity logical is
port (
rs : in std_ulogic_vector(63 downto 0);
rb : in std_ulogic_vector(63 downto 0);
op : in insn_type_t;
op : in subresult_sel_t;
invert_in : in std_ulogic;
invert_out : in std_ulogic;
is_signed : in std_ulogic;
@ -114,7 +114,7 @@ begin
end if;

case op is
when OP_LOGIC =>
when "000" => -- OP_LOGIC
-- for now, abuse the 'is_signed' field to indicate inversion of RS
rs_adj := rs;
if is_signed = '1' then
@ -124,13 +124,13 @@ begin
if invert_out = '1' then
tmp := not tmp;
end if;
when OP_XOR =>
when "001" => -- OP_XOR
tmp := rs xor rb;
if invert_out = '1' then
tmp := not tmp;
end if;

when OP_BREV =>
when "010" => -- OP_BREV
if datalen(3) = '1' then
tmp := rs( 7 downto 0) & rs(15 downto 8) & rs(23 downto 16) & rs(31 downto 24) &
rs(39 downto 32) & rs(47 downto 40) & rs(55 downto 48) & rs(63 downto 56);
@ -142,11 +142,11 @@ begin
rs(23 downto 16) & rs(31 downto 24) & rs( 7 downto 0) & rs(15 downto 8);
end if;

when OP_PRTY =>
when "011" => -- OP_PRTY
tmp := parity;
when OP_CMPB =>
when "100" => -- OP_CMPB
tmp := ppc_cmpb(rs, rb);
when OP_BCD =>
when "101" => -- OP_BCD
-- invert_in is abused to indicate direction of conversion
if invert_in = '0' then
-- cbcdtd
@ -157,7 +157,7 @@ begin
tmp := x"00" & dpd_to_bcd(rs(51 downto 42)) & dpd_to_bcd(rs(41 downto 32)) &
x"00" & dpd_to_bcd(rs(19 downto 10)) & dpd_to_bcd(rs(9 downto 0));
end if;
when OP_EXTS =>
when "110" => -- OP_EXTS
-- note datalen is a 1-hot encoding
negative := (datalen(0) and rs(7)) or
(datalen(1) and rs(15)) or
@ -171,8 +171,7 @@ begin
end if;
tmp(7 downto 0) := rs(7 downto 0);
when others =>
-- e.g. OP_MFSPR
tmp := rs;
tmp := (others => '0');
end case;

result <= tmp;

3
microwatt.core
Unescape Escape View File

@ -197,6 +197,7 @@ targets:
default_tool: vivado
filesets: [core, acorn_cle_215, soc, fpga, debug_xilinx, litedram, uart16550, xilinx_specific]
parameters :
- cpus
- memory_size
- ram_init_file
- use_litedram=true
@ -205,6 +206,8 @@ targets:
- spi_flash_offset=10485760
- log_length=2048
- uart_is_16550
- has_fpu
- has_btc
generate: [litedram_acorn_cle_215, git_hash]
tools:
vivado: {part : xc7a200tsbg484-2}

10
openocd/arty.cfg
Unescape Escape View File

@ -1,6 +1,6 @@
interface ftdi
ftdi_vid_pid 0x0403 0x6010
ftdi_channel 0
ftdi_layout_init 0x00e8 0x60eb
adapter driver ftdi
ftdi vid_pid 0x0403 0x6010
ftdi channel 0
ftdi layout_init 0x00e8 0x60eb
reset_config none
adapter_khz 25000
adapter speed 25000

93
predecode.vhdl
Unescape Escape View File

@ -29,16 +29,17 @@ architecture behaviour of predecoder is

type predecoder_rom_t is array(0 to 2047) of insn_code;

-- indexed by instruction bits 31..26 and 4..0
constant major_predecode_rom : predecoder_rom_t := (
2#001100_00000# to 2#001100_11111# => INSN_addic,
2#001101_00000# to 2#001101_11111# => INSN_addic_dot,
2#001110_00000# to 2#001110_11111# => INSN_addi,
2#001111_00000# to 2#001111_11111# => INSN_addis,
2#010011_00100# to 2#010011_00101# => INSN_addpcis,
2#011100_00000# to 2#011100_11111# => INSN_andi_dot,
2#011101_00000# to 2#011101_11111# => INSN_andis_dot,
2#000000_00000# => INSN_attn,
2#010010_00000# to 2#010010_00001# => INSN_brel,
2#001100_00000# to 2#001100_11111# => INSN_addic, -- 12
2#001101_00000# to 2#001101_11111# => INSN_addic_dot, -- 13
2#001110_00000# to 2#001110_11111# => INSN_addi, -- 14
2#001111_00000# to 2#001111_11111# => INSN_addis, -- 15
2#010011_00100# to 2#010011_00101# => INSN_addpcis, -- 19
2#011100_00000# to 2#011100_11111# => INSN_andi_dot, -- 28
2#011101_00000# to 2#011101_11111# => INSN_andis_dot, -- 29
2#000000_00000# => INSN_attn, -- 0
2#010010_00000# to 2#010010_00001# => INSN_brel, -- 18
2#010010_00010# to 2#010010_00011# => INSN_babs,
2#010010_00100# to 2#010010_00101# => INSN_brel,
2#010010_00110# to 2#010010_00111# => INSN_babs,
@ -54,7 +55,7 @@ architecture behaviour of predecoder is
2#010010_11010# to 2#010010_11011# => INSN_babs,
2#010010_11100# to 2#010010_11101# => INSN_brel,
2#010010_11110# to 2#010010_11111# => INSN_babs,
2#010000_00000# to 2#010000_00001# => INSN_bcrel,
2#010000_00000# to 2#010000_00001# => INSN_bcrel, -- 16
2#010000_00010# to 2#010000_00011# => INSN_bcabs,
2#010000_00100# to 2#010000_00101# => INSN_bcrel,
2#010000_00110# to 2#010000_00111# => INSN_bcabs,
@ -70,42 +71,42 @@ architecture behaviour of predecoder is
2#010000_11010# to 2#010000_11011# => INSN_bcabs,
2#010000_11100# to 2#010000_11101# => INSN_bcrel,
2#010000_11110# to 2#010000_11111# => INSN_bcabs,
2#001011_00000# to 2#001011_11111# => INSN_cmpi,
2#001010_00000# to 2#001010_11111# => INSN_cmpli,
2#100010_00000# to 2#100010_11111# => INSN_lbz,
2#100011_00000# to 2#100011_11111# => INSN_lbzu,
2#110010_00000# to 2#110010_11111# => INSN_lfd,
2#110011_00000# to 2#110011_11111# => INSN_lfdu,
2#110000_00000# to 2#110000_11111# => INSN_lfs,
2#110001_00000# to 2#110001_11111# => INSN_lfsu,
2#101010_00000# to 2#101010_11111# => INSN_lha,
2#101011_00000# to 2#101011_11111# => INSN_lhau,
2#101000_00000# to 2#101000_11111# => INSN_lhz,
2#101001_00000# to 2#101001_11111# => INSN_lhzu,
2#100000_00000# to 2#100000_11111# => INSN_lwz,
2#100001_00000# to 2#100001_11111# => INSN_lwzu,
2#000111_00000# to 2#000111_11111# => INSN_mulli,
2#011000_00000# to 2#011000_11111# => INSN_ori,
2#011001_00000# to 2#011001_11111# => INSN_oris,
2#010100_00000# to 2#010100_11111# => INSN_rlwimi,
2#010101_00000# to 2#010101_11111# => INSN_rlwinm,
2#010111_00000# to 2#010111_11111# => INSN_rlwnm,
2#010001_00000# to 2#010001_11111# => INSN_sc,
2#100110_00000# to 2#100110_11111# => INSN_stb,
2#100111_00000# to 2#100111_11111# => INSN_stbu,
2#110110_00000# to 2#110110_11111# => INSN_stfd,
2#110111_00000# to 2#110111_11111# => INSN_stfdu,
2#110100_00000# to 2#110100_11111# => INSN_stfs,
2#110101_00000# to 2#110101_11111# => INSN_stfsu,
2#101100_00000# to 2#101100_11111# => INSN_sth,
2#101101_00000# to 2#101101_11111# => INSN_sthu,
2#100100_00000# to 2#100100_11111# => INSN_stw,
2#100101_00000# to 2#100101_11111# => INSN_stwu,
2#001000_00000# to 2#001000_11111# => INSN_subfic,
2#000010_00000# to 2#000010_11111# => INSN_tdi,
2#000011_00000# to 2#000011_11111# => INSN_twi,
2#011010_00000# to 2#011010_11111# => INSN_xori,
2#011011_00000# to 2#011011_11111# => INSN_xoris,
2#001011_00000# to 2#001011_11111# => INSN_cmpi, -- 11
2#001010_00000# to 2#001010_11111# => INSN_cmpli, -- 10
2#100010_00000# to 2#100010_11111# => INSN_lbz, -- 34
2#100011_00000# to 2#100011_11111# => INSN_lbzu, -- 35
2#110010_00000# to 2#110010_11111# => INSN_lfd, -- 50
2#110011_00000# to 2#110011_11111# => INSN_lfdu, -- 51
2#110000_00000# to 2#110000_11111# => INSN_lfs, -- 56
2#110001_00000# to 2#110001_11111# => INSN_lfsu, -- 57
2#101010_00000# to 2#101010_11111# => INSN_lha, -- 42
2#101011_00000# to 2#101011_11111# => INSN_lhau, -- 43
2#101000_00000# to 2#101000_11111# => INSN_lhz, -- 40
2#101001_00000# to 2#101001_11111# => INSN_lhzu, -- 41
2#100000_00000# to 2#100000_11111# => INSN_lwz, -- 32
2#100001_00000# to 2#100001_11111# => INSN_lwzu, -- 33
2#000111_00000# to 2#000111_11111# => INSN_mulli, -- 7
2#011000_00000# to 2#011000_11111# => INSN_ori, -- 24
2#011001_00000# to 2#011001_11111# => INSN_oris, -- 25
2#010100_00000# to 2#010100_11111# => INSN_rlwimi, -- 20
2#010101_00000# to 2#010101_11111# => INSN_rlwinm, -- 21
2#010111_00000# to 2#010111_11111# => INSN_rlwnm, -- 23
2#010001_00000# to 2#010001_11111# => INSN_sc, -- 17
2#100110_00000# to 2#100110_11111# => INSN_stb, -- 38
2#100111_00000# to 2#100111_11111# => INSN_stbu, -- 39
2#110110_00000# to 2#110110_11111# => INSN_stfd, -- 54
2#110111_00000# to 2#110111_11111# => INSN_stfdu, -- 55
2#110100_00000# to 2#110100_11111# => INSN_stfs, -- 52
2#110101_00000# to 2#110101_11111# => INSN_stfsu, -- 53
2#101100_00000# to 2#101100_11111# => INSN_sth, -- 44
2#101101_00000# to 2#101101_11111# => INSN_sthu, -- 45
2#100100_00000# to 2#100100_11111# => INSN_stw, -- 36
2#100101_00000# to 2#100101_11111# => INSN_stwu, -- 37
2#001000_00000# to 2#001000_11111# => INSN_subfic, -- 8
2#000010_00000# to 2#000010_11111# => INSN_tdi, -- 2
2#000011_00000# to 2#000011_11111# => INSN_twi, -- 3
2#011010_00000# to 2#011010_11111# => INSN_xori, -- 26
2#011011_00000# to 2#011011_11111# => INSN_xoris, -- 27
-- major opcode 4
2#000100_10000# => INSN_maddhd,
2#000100_10001# => INSN_maddhdu,

3
soc.vhdl
Unescape Escape View File

@ -431,6 +431,7 @@ begin
-- From CPU to BRAM, DRAM, IO, selected on top 3 bits and dram_at_0
-- 0000 - BRAM
-- 0001 - DRAM
-- 001x - DRAM
-- 01xx - DRAM
-- 10xx - BRAM
-- 11xx - IO
@ -449,6 +450,8 @@ begin
slave_top := SLAVE_TOP_BRAM;
elsif std_match(top_decode, "0001") then
slave_top := SLAVE_TOP_DRAM;
elsif std_match(top_decode, "001-") then
slave_top := SLAVE_TOP_DRAM;
elsif std_match(top_decode, "01--") then
slave_top := SLAVE_TOP_DRAM;
elsif std_match(top_decode, "10--") then

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