litedram: Add an L2 cache with store queue
This adds a cache between the wishbone and litedram with the following features (at this point, it's still evolving) - 128 bytes line width in order to have a reasonable amount of litedram pipelining on the 128-bit wide data port. - Configurable geometry otherwise - Stores are acked immediately on wishbone whether hit or miss (minus a 2 cycles delay if there's a previous load response in the way) and sent to LiteDRAM via 8 entries (configurable) store queue Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>pull/190/head
Benjamin Herrenschmidt
6 years ago
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bf1b98b958
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a3857aac94
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$ version 1.1
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# Signals in entities :
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/core_dram_tb/dram/rst
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/core_dram_tb/dram/system_clk
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/core_dram_tb/dram/system_reset
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/core_dram_tb/dram/wb_in
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/core_dram_tb/dram/wb_out
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/core_dram_tb/dram/user_port0_cmd_valid
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/core_dram_tb/dram/user_port0_cmd_ready
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/core_dram_tb/dram/user_port0_cmd_we
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/core_dram_tb/dram/user_port0_cmd_addr
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/core_dram_tb/dram/user_port0_wdata_valid
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/core_dram_tb/dram/user_port0_wdata_ready
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/core_dram_tb/dram/user_port0_wdata_we
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/core_dram_tb/dram/user_port0_wdata_data
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/core_dram_tb/dram/user_port0_rdata_valid
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/core_dram_tb/dram/user_port0_rdata_ready
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/core_dram_tb/dram/user_port0_rdata_data
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/core_dram_tb/dram/cache_tags
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/core_dram_tb/dram/cache_valids
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/core_dram_tb/dram/storeq_rd_ready
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/core_dram_tb/dram/storeq_rd_valid
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/core_dram_tb/dram/storeq_rd_data
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/core_dram_tb/dram/storeq_wr_ready
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/core_dram_tb/dram/storeq_wr_valid
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/core_dram_tb/dram/storeq_wr_data
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/core_dram_tb/dram/accept_store
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/core_dram_tb/dram/state
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/core_dram_tb/dram/wb_req
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/core_dram_tb/dram/store_queued
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/core_dram_tb/dram/read_ack_0
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/core_dram_tb/dram/read_ack_1
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/core_dram_tb/dram/read_ad3_0
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/core_dram_tb/dram/read_ad3_1
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/core_dram_tb/dram/read_way_0
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/core_dram_tb/dram/read_way_1
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/core_dram_tb/dram/req_index
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/core_dram_tb/dram/req_row
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/core_dram_tb/dram/req_hit_way
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/core_dram_tb/dram/req_tag
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/core_dram_tb/dram/req_op
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/core_dram_tb/dram/req_laddr
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/core_dram_tb/dram/req_ad3
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/core_dram_tb/dram/req_we
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/core_dram_tb/dram/req_wdata
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/core_dram_tb/dram/store_way
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/core_dram_tb/dram/store_index
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/core_dram_tb/dram/store_row
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/core_dram_tb/dram/cache_out
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/core_dram_tb/dram/plru_victim
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/core_dram_tb/dram/replace_way
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/core_dram_tb/dram/rams/do_read
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/core_dram_tb/dram/rams/do_write
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/core_dram_tb/dram/rams/rd_addr
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/core_dram_tb/dram/rams/wr_addr
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/core_dram_tb/dram/rams/wr_data
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/core_dram_tb/dram/rams/wr_sel
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/core_dram_tb/dram/rams/wr_sel_m
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/core_dram_tb/dram/rams/dout
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/core_dram_tb/dram/rams/way/clk
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/core_dram_tb/dram/rams/way/rd_en
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/core_dram_tb/dram/rams/way/rd_addr
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/core_dram_tb/dram/rams/way/rd_data
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/core_dram_tb/dram/rams/way/wr_sel
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/core_dram_tb/dram/rams/way/wr_addr
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/core_dram_tb/dram/rams/way/wr_data
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/core_dram_tb/dram/rams/way/rd_data0
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/core_dram_tb/dram/store_queue/wr_ready
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/core_dram_tb/dram/store_queue/wr_valid
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/core_dram_tb/dram/store_queue/wr_data
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/core_dram_tb/dram/store_queue/rd_ready
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/core_dram_tb/dram/store_queue/rd_valid
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/core_dram_tb/dram/store_queue/rd_data
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/core_dram_tb/dram/store_queue/rd_idx
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/core_dram_tb/dram/store_queue/rd_next
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/core_dram_tb/dram/store_queue/wr_idx
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/core_dram_tb/dram/store_queue/wr_next
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/core_dram_tb/dram/store_queue/op_prev
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/core_dram_tb/dram/store_queue/op_next
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/core_dram_tb/dram/store_queue/full
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/core_dram_tb/dram/store_queue/empty
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/core_dram_tb/dram/store_queue/push
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/core_dram_tb/dram/store_queue/pop
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File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
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-- Synchronous FIFO with a protocol similar to AXI
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--
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-- The outputs are generated combinationally from the inputs
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-- in order to allow for back-to-back transfers with the type
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-- of flow control used by busses lite AXI, pipelined WB or
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-- LiteDRAM native port when the FIFO is full.
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--
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-- That means that care needs to be taken by the user not to
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-- generate the inputs combinationally from the outputs otherwise
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-- it would create a logic loop.
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--
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-- If breaking that loop is required, a stash buffer could be
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-- added to break the flow control "loop" between the read and
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-- the write port.
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--
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library ieee;
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use ieee.std_logic_1164.all;
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library work;
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use work.utils.all;
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entity sync_fifo is
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generic(
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-- Fifo depth in entries
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DEPTH : natural := 64;
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-- Fifo width in bits
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WIDTH : natural := 32;
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-- When INIT_ZERO is set, the memory is pre-initialized to 0's
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INIT_ZERO : boolean := false
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);
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port(
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-- Control lines:
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clk : in std_ulogic;
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reset : in std_ulogic;
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-- Write port
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wr_ready : out std_ulogic;
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wr_valid : in std_ulogic;
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wr_data : in std_ulogic_vector(WIDTH - 1 downto 0);
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-- Read port
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rd_ready : in std_ulogic;
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rd_valid : out std_ulogic;
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rd_data : out std_ulogic_vector(WIDTH - 1 downto 0)
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);
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end entity sync_fifo;
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architecture behaviour of sync_fifo is
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subtype data_t is std_ulogic_vector(WIDTH - 1 downto 0);
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type memory_t is array(0 to DEPTH - 1) of data_t;
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function init_mem return memory_t is
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variable m : memory_t;
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begin
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if INIT_ZERO then
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for i in 0 to DEPTH - 1 loop
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m(i) := (others => '0');
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end loop;
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end if;
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return m;
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end function;
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signal memory : memory_t := init_mem;
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subtype index_t is integer range 0 to DEPTH - 1;
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signal rd_idx : index_t;
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signal rd_next : index_t;
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signal wr_idx : index_t;
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signal wr_next : index_t;
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function next_index(idx : index_t) return index_t is
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variable r : index_t;
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begin
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if ispow2(DEPTH) then
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r := (idx + 1) mod DEPTH;
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else
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r := idx + 1;
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if r = DEPTH then
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r := 0;
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end if;
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end if;
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return r;
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end function;
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type op_t is (OP_POP, OP_PUSH);
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signal op_prev : op_t := OP_POP;
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signal op_next : op_t;
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signal full, empty : std_ulogic;
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signal push, pop : std_ulogic;
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begin
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-- Current state at last clock edge
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empty <= '1' when rd_idx = wr_idx and op_prev = OP_POP else '0';
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full <= '1' when rd_idx = wr_idx and op_prev = OP_PUSH else '0';
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-- We can accept new data if we aren't full or we are but
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-- the read port is going to accept data this cycle
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wr_ready <= rd_ready or not full;
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-- We can provide data if we aren't empty or we are but
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-- the write port is going to provide data this cycle
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rd_valid <= wr_valid or not empty;
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-- Internal control signals
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push <= wr_ready and wr_valid;
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pop <= rd_ready and rd_valid;
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-- Next state
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rd_next <= next_index(rd_idx) when pop = '1' else rd_idx;
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wr_next <= next_index(wr_idx) when push = '1' else wr_idx;
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with push & pop select op_next <=
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OP_PUSH when "10",
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OP_POP when "01",
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op_prev when others;
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-- Read port output
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rd_data <= memory(rd_idx) when empty = '0' else wr_data;
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-- Read counter
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reader: process(clk)
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begin
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if rising_edge(clk) then
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if reset = '1' then
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rd_idx <= 0;
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else
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rd_idx <= rd_next;
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end if;
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end if;
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end process;
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-- Write counter and memory write
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producer: process(clk)
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begin
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if rising_edge(clk) then
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if reset = '1' then
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wr_idx <= 0;
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else
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wr_idx <= wr_next;
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if push = '1' then
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memory(wr_idx) <= wr_data;
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end if;
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end if;
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end if;
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end process;
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-- Previous op latch used for generating empty/full
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op: process(clk)
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begin
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if rising_edge(clk) then
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if reset = '1' then
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op_prev <= OP_POP;
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else
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op_prev <= op_next;
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end if;
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end if;
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end process;
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end architecture behaviour;
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