Add core debug module
This module adds some simple core controls: reset, stop, start, step along with icache clear and reading the NIA and core status bits Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.orgpull/69/head
Benjamin Herrenschmidt
5 years ago
parent
554b753172
commit
98f0994698
@ -0,0 +1,152 @@
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.common.all;
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entity core_debug is
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port (
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clk : in std_logic;
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rst : in std_logic;
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dmi_addr : in std_ulogic_vector(3 downto 0);
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dmi_din : in std_ulogic_vector(63 downto 0);
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dmi_dout : out std_ulogic_vector(63 downto 0);
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dmi_req : in std_ulogic;
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dmi_wr : in std_ulogic;
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dmi_ack : out std_ulogic;
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-- Debug actions
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core_stop : out std_ulogic;
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core_rst : out std_ulogic;
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icache_rst : out std_ulogic;
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-- Core status inputs
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terminate : in std_ulogic;
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core_stopped : in std_ulogic;
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nia : in std_ulogic_vector(63 downto 0);
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-- Misc
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terminated_out : out std_ulogic
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);
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end core_debug;
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architecture behave of core_debug is
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-- DMI needs fixing... make a one clock pulse
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signal dmi_req_1: std_ulogic;
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-- CTRL register (direct actions, write 1 to act, read back 0)
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-- bit 0 : Core stop
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-- bit 1 : Core reset (doesn't clear stop)
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-- bit 2 : Icache reset
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-- bit 3 : Single step
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-- bit 4 : Core start
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constant DBG_CORE_CTRL : std_ulogic_vector(3 downto 0) := "0000";
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constant DBG_CORE_CTRL_STOP : integer := 0;
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constant DBG_CORE_CTRL_RESET : integer := 1;
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constant DBG_CORE_CTRL_ICRESET : integer := 2;
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constant DBG_CORE_CTRL_STEP : integer := 3;
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constant DBG_CORE_CTRL_START : integer := 4;
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-- STAT register (read only)
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-- bit 0 : Core stopping (wait til bit 1 set)
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-- bit 1 : Core stopped
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-- bit 2 : Core terminated (clears with start or reset)
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constant DBG_CORE_STAT : std_ulogic_vector(3 downto 0) := "0001";
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constant DBG_CORE_STAT_STOPPING : integer := 0;
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constant DBG_CORE_STAT_STOPPED : integer := 1;
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constant DBG_CORE_STAT_TERM : integer := 2;
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-- NIA register (read only for now)
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constant DBG_CORE_NIA : std_ulogic_vector(3 downto 0) := "0010";
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-- Some internal wires
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signal stat_reg : std_ulogic_vector(63 downto 0);
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-- Some internal latches
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signal stopping : std_ulogic;
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signal do_step : std_ulogic;
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signal do_reset : std_ulogic;
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signal do_icreset : std_ulogic;
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signal terminated : std_ulogic;
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begin
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-- Single cycle register accesses on DMI
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dmi_ack <= dmi_req;
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-- Status register read composition
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stat_reg <= (2 => terminated,
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1 => core_stopped,
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0 => stopping,
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others => '0');
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-- DMI read data mux
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with dmi_addr select dmi_dout <=
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stat_reg when DBG_CORE_STAT,
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nia when DBG_CORE_NIA,
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(others => '0') when others;
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-- DMI writes
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reg_write: process(clk)
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begin
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if rising_edge(clk) then
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if (rst) then
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stopping <= '0';
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terminated <= '0';
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else
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-- Reset the 1-cycle "do" signals
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do_step <= '0';
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do_reset <= '0';
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do_icreset <= '0';
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-- Edge detect on dmi_req for 1-shot pulses
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dmi_req_1 <= dmi_req;
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if dmi_req = '1' and dmi_req_1 = '0' then
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if dmi_wr = '1' then
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report("DMI write to " & to_hstring(dmi_addr));
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-- Control register actions
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if dmi_addr = DBG_CORE_CTRL then
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if dmi_din(DBG_CORE_CTRL_RESET) = '1' then
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do_reset <= '1';
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terminated <= '0';
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end if;
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if dmi_din(DBG_CORE_CTRL_STOP) = '1' then
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stopping <= '1';
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end if;
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if dmi_din(DBG_CORE_CTRL_STEP) = '1' then
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do_step <= '1';
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terminated <= '0';
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end if;
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if dmi_din(DBG_CORE_CTRL_ICRESET) = '1' then
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do_icreset <= '1';
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end if;
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if dmi_din(DBG_CORE_CTRL_START) = '1' then
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stopping <= '0';
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terminated <= '0';
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end if;
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end if;
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else
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report("DMI read from " & to_string(dmi_addr));
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end if;
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end if;
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-- Set core stop on terminate. We'll be stopping some time *after*
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-- the offending instruction, at least until we can do back flushes
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-- that preserve NIA which we can't just yet.
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if terminate = '1' then
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stopping <= '1';
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terminated <= '1';
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end if;
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end if;
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end if;
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end process;
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-- Core control signals generated by the debug module
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core_stop <= stopping and not do_step;
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core_rst <= do_reset;
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icache_rst <= do_icreset;
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terminated_out <= terminated;
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end behave;
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