Merge pull request #360 from antonblanchard/log2ceil-issue

wishbone_bram_wrapper ram_addr_bits is 1 bit off
3 years ago · 8bf48ac094
parent 30fd936c12 b5accb78b2
commit 8bf48ac094
1 changed files with 1 additions and 1 deletions
--- a/wishbone_bram_wrapper.vhdl
+++ b/wishbone_bram_wrapper.vhdl
@ -24,7 +24,7 @@ entity wishbone_bram_wrapper is
 end entity wishbone_bram_wrapper;

 architecture behaviour of wishbone_bram_wrapper is
-    constant ram_addr_bits : integer := log2ceil(MEMORY_SIZE) - 3;
+    constant ram_addr_bits : integer := log2ceil(MEMORY_SIZE-1) - 3;

    -- RAM interface
    signal ram_addr : std_logic_vector(ram_addr_bits - 1 downto 0);