Reformat fetch2

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
pull/76/head
Benjamin Herrenschmidt 5 years ago
parent 41a4eb8271
commit 8b55fc4d9e

@ -7,60 +7,60 @@ use work.common.all;
use work.wishbone_types.all; use work.wishbone_types.all;


entity fetch2 is entity fetch2 is
port( port(
clk : in std_ulogic; clk : in std_ulogic;
rst : in std_ulogic; rst : in std_ulogic;


stall_in : in std_ulogic; stall_in : in std_ulogic;
stall_out : out std_ulogic; stall_out : out std_ulogic;


flush_in : in std_ulogic; flush_in : in std_ulogic;
stop_in : in std_ulogic; stop_in : in std_ulogic;


i_in : in IcacheToFetch2Type; i_in : in IcacheToFetch2Type;
i_out : out Fetch2ToIcacheType; i_out : out Fetch2ToIcacheType;


f_in : in Fetch1ToFetch2Type; f_in : in Fetch1ToFetch2Type;


f_out : out Fetch2ToDecode1Type f_out : out Fetch2ToDecode1Type
); );
end entity fetch2; end entity fetch2;


architecture behaviour of fetch2 is architecture behaviour of fetch2 is
signal r, rin : Fetch2ToDecode1Type; signal r, rin : Fetch2ToDecode1Type;
begin begin
regs : process(clk) regs : process(clk)
begin begin
if rising_edge(clk) then if rising_edge(clk) then
-- Output state remains unchanged on stall, unless we are flushing -- Output state remains unchanged on stall, unless we are flushing
if rst = '1' or flush_in = '1' or stall_in = '0' then if rst = '1' or flush_in = '1' or stall_in = '0' then
r <= rin; r <= rin;
end if; end if;
end if; end if;
end process; end process;


comb : process(all) comb : process(all)
variable v : Fetch2ToDecode1Type; variable v : Fetch2ToDecode1Type;
begin begin
v := r; v := r;


-- asynchronous icache lookup -- asynchronous icache lookup
i_out.req <= '1'; i_out.req <= '1';
i_out.addr <= f_in.nia; i_out.addr <= f_in.nia;
v.valid := i_in.ack; v.valid := i_in.ack;
v.nia := f_in.nia; v.nia := f_in.nia;
v.insn := i_in.insn; v.insn := i_in.insn;
stall_out <= stop_in or not i_in.ack; stall_out <= stop_in or not i_in.ack;


if flush_in = '1' or stop_in = '1' then if flush_in = '1' or stop_in = '1' then
v.valid := '0'; v.valid := '0';
end if; end if;
v.stop_mark := stop_in; v.stop_mark := stop_in;


-- Update registers -- Update registers
rin <= v; rin <= v;


-- Update outputs -- Update outputs
f_out <= r; f_out <= r;
end process; end process;
end architecture behaviour; end architecture behaviour;

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