Fix a few reset issues in flash controller

Our flash controller fails when simulating with iverilog. Looking
closer, both wb_stash and auto_last_addr are X state, and things
fall apart after they get used.

Initialise them both fixes the iverilog issue.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
pull/256/head
Anton Blanchard 4 years ago committed by Anton Blanchard
parent 081dc64d39
commit 7c8bc85e44

@ -232,6 +232,10 @@ begin
if rst = '1' then if rst = '1' then
wb_out.ack <= '0'; wb_out.ack <= '0';
wb_out.stall <= '0'; wb_out.stall <= '0';
wb_stash.cyc <= '0';
wb_stash.stb <= '0';
wb_stash.sel <= (others => '0');
wb_stash.we <= '0';
else else
-- Latch wb responses as well for 1 cycle. Stall is updated -- Latch wb responses as well for 1 cycle. Stall is updated
-- below -- below
@ -344,12 +348,16 @@ begin
auto_sync: process(clk) auto_sync: process(clk)
begin begin
if rising_edge(clk) then if rising_edge(clk) then
auto_state <= auto_next; if rst = '1' then
auto_cnt <= auto_cnt_next; auto_last_addr <= (others => '0');
auto_data <= auto_data_next; else
if auto_latch_adr = '1' then auto_state <= auto_next;
auto_last_addr <= auto_lad_next; auto_cnt <= auto_cnt_next;
end if; auto_data <= auto_data_next;
if auto_latch_adr = '1' then
auto_last_addr <= auto_lad_next;
end if;
end if;
end if; end if;
end process; end process;



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