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@ -1,11 +1,13 @@
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--
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-- This is a simple XICS compliant interrupt controller. This is a
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-- Presenter (ICP) and Source (ICS) in a single unit with no routing
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-- layer.
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-- Presenter (ICP) and Source (ICS) in two small units directly
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-- connected to each other with no routing layer.
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--
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-- The sources have a fixed IRQ priority set by HW_PRIORITY. The
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-- source id starts at 16 for int_level_in(0) and go up from
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-- there (ie int_level_in(1) is source id 17).
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-- The sources have a configurable IRQ priority set a set of ICS
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-- registers in the source units.
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--
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-- The source ids start at 16 for int_level_in(0) and go up from
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-- there (ie int_level_in(1) is source id 17). XXX Make a generic
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--
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-- The presentation layer will pick an interupt that is more
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-- favourable than the current CPPR and present it via the XISR and
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@ -22,38 +24,31 @@ library work;
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use work.common.all;
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use work.wishbone_types.all;
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entity xics is
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generic (
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LEVEL_NUM : positive := 16
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);
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entity xics_icp is
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port (
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clk : in std_logic;
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rst : in std_logic;
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wb_in : in wb_io_master_out;
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wb_out : out wb_io_slave_out;
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int_level_in : in std_ulogic_vector(LEVEL_NUM - 1 downto 0);
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wb_in : in wb_io_master_out;
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wb_out : out wb_io_slave_out;
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ics_in : in ics_to_icp_t;
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core_irq_out : out std_ulogic
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);
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end xics;
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end xics_icp;
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architecture behaviour of xics is
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architecture behaviour of xics_icp is
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type reg_internal_t is record
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xisr : std_ulogic_vector(23 downto 0);
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cppr : std_ulogic_vector(7 downto 0);
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pending_priority : std_ulogic_vector(7 downto 0);
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mfrr : std_ulogic_vector(7 downto 0);
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mfrr_pending : std_ulogic;
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irq : std_ulogic;
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wb_rd_data : std_ulogic_vector(31 downto 0);
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wb_ack : std_ulogic;
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end record;
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constant reg_internal_init : reg_internal_t :=
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(wb_ack => '0',
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mfrr_pending => '0',
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mfrr => x"00", -- mask everything on reset
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mfrr => x"ff", -- mask everything on reset
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irq => '0',
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others => (others => '0'));
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@ -74,25 +69,43 @@ begin
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begin
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if rising_edge(clk) then
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r <= r_next;
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-- We delay core_irq_out by a cycle to help with timing
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core_irq_out <= r.irq;
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end if;
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end process;
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wb_out.dat <= r.wb_rd_data;
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wb_out.ack <= r.wb_ack;
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wb_out.stall <= '0'; -- never stall wishbone
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core_irq_out <= r.irq;
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comb : process(all)
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variable v : reg_internal_t;
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variable xirr_accept_rd : std_ulogic;
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variable irq_eoi : std_ulogic;
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function bswap(v : in std_ulogic_vector(31 downto 0)) return std_ulogic_vector is
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variable r : std_ulogic_vector(31 downto 0);
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begin
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r( 7 downto 0) := v(31 downto 24);
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r(15 downto 8) := v(23 downto 16);
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r(23 downto 16) := v(15 downto 8);
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r(31 downto 24) := v( 7 downto 0);
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return r;
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end function;
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variable be_in : std_ulogic_vector(31 downto 0);
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variable be_out : std_ulogic_vector(31 downto 0);
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variable pending_priority : std_ulogic_vector(7 downto 0);
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begin
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v := r;
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v.wb_ack := '0';
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xirr_accept_rd := '0';
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irq_eoi := '0';
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be_in := bswap(wb_in.dat);
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be_out := (others => '0');
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if wb_in.cyc = '1' and wb_in.stb = '1' then
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v.wb_ack := '1'; -- always ack
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@ -100,112 +113,83 @@ begin
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-- writes to both XIRR are the same
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case wb_in.adr(7 downto 0) is
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when XIRR_POLL =>
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report "XICS XIRR_POLL write";
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if wb_in.sel = x"f" then -- 4 bytes
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v.cppr := wb_in.dat(31 downto 24);
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elsif wb_in.sel = x"1" then -- 1 byte
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v.cppr := wb_in.dat(7 downto 0);
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end if;
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report "ICP XIRR_POLL write";
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v.cppr := be_in(31 downto 24);
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when XIRR =>
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v.cppr := be_in(31 downto 24);
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if wb_in.sel = x"f" then -- 4 byte
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report "XICS XIRR write word:" & to_hstring(wb_in.dat);
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v.cppr := wb_in.dat(31 downto 24);
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irq_eoi := '1';
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report "ICP XIRR write word (EOI) :" & to_hstring(be_in);
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elsif wb_in.sel = x"1" then -- 1 byte
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report "XICS XIRR write byte:" & to_hstring(wb_in.dat(7 downto 0));
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v.cppr := wb_in.dat(7 downto 0);
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report "ICP XIRR write byte (CPPR):" & to_hstring(be_in(31 downto 24));
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else
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report "XICS XIRR UNSUPPORTED write ! sel=" & to_hstring(wb_in.sel);
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report "ICP XIRR UNSUPPORTED write ! sel=" & to_hstring(wb_in.sel);
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end if;
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when MFRR =>
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v.mfrr := be_in(31 downto 24);
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if wb_in.sel = x"f" then -- 4 bytes
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report "XICS MFRR write word:" & to_hstring(wb_in.dat);
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v.mfrr_pending := '1';
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v.mfrr := wb_in.dat(31 downto 24);
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report "ICP MFRR write word:" & to_hstring(be_in);
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elsif wb_in.sel = x"1" then -- 1 byte
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report "XICS MFRR write byte:" & to_hstring(wb_in.dat(7 downto 0));
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v.mfrr_pending := '1';
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v.mfrr := wb_in.dat(7 downto 0);
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report "ICP MFRR write byte:" & to_hstring(be_in(31 downto 24));
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else
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report "XICS MFRR UNSUPPORTED write ! sel=" & to_hstring(wb_in.sel);
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report "ICP MFRR UNSUPPORTED write ! sel=" & to_hstring(wb_in.sel);
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end if;
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when others =>
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end case;
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else -- read
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v.wb_rd_data := (others => '0');
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case wb_in.adr(7 downto 0) is
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when XIRR_POLL =>
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report "XICS XIRR_POLL read";
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if wb_in.sel = x"f" then
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v.wb_rd_data(23 downto 0) := r.xisr;
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v.wb_rd_data(31 downto 24) := r.cppr;
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elsif wb_in.sel = x"1" then
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v.wb_rd_data(7 downto 0) := r.cppr;
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end if;
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report "ICP XIRR_POLL read";
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be_out := r.cppr & r.xisr;
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when XIRR =>
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report "XICS XIRR read";
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report "ICP XIRR read";
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be_out := r.cppr & r.xisr;
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if wb_in.sel = x"f" then
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v.wb_rd_data(23 downto 0) := r.xisr;
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v.wb_rd_data(31 downto 24) := r.cppr;
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xirr_accept_rd := '1';
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elsif wb_in.sel = x"1" then
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v.wb_rd_data(7 downto 0) := r.cppr;
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end if;
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when MFRR =>
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report "XICS MFRR read";
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if wb_in.sel = x"f" then -- 4 bytes
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v.wb_rd_data(31 downto 24) := r.mfrr;
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elsif wb_in.sel = x"1" then -- 1 byte
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v.wb_rd_data( 7 downto 0) := r.mfrr;
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end if;
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report "ICP MFRR read";
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be_out(31 downto 24) := r.mfrr;
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when others =>
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end case;
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end if;
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end if;
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-- generate interrupt
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if r.irq = '0' then
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-- Here we just present any interrupt that's valid and
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-- below cppr. For ordering, we ignore hardware
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-- priorities.
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if unsigned(HW_PRIORITY) < unsigned(r.cppr) then --
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-- lower HW sources are higher priority
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for i in LEVEL_NUM - 1 downto 0 loop
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if int_level_in(i) = '1' then
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v.irq := '1';
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v.xisr := std_ulogic_vector(to_unsigned(16 + i, 24));
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v.pending_priority := HW_PRIORITY; -- hardware HW IRQs
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end if;
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end loop;
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end if;
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pending_priority := x"ff";
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v.xisr := x"000000";
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v.irq := '0';
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-- Do mfrr as a higher priority so mfrr_pending is cleared
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if unsigned(r.mfrr) < unsigned(r.cppr) then --
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report "XICS: MFRR INTERRUPT";
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-- IPI
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if r.mfrr_pending = '1' then
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v.irq := '1';
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v.xisr := x"000002"; -- special XICS MFRR IRQ source number
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v.pending_priority := r.mfrr;
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v.mfrr_pending := '0';
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end if;
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end if;
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end if;
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if ics_in.pri /= x"ff" then
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v.xisr := x"00001" & ics_in.src;
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pending_priority := ics_in.pri;
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end if;
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-- Check MFRR
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if unsigned(r.mfrr) < unsigned(pending_priority) then --
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v.xisr := x"000002"; -- special XICS MFRR IRQ source number
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pending_priority := r.mfrr;
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end if;
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-- Accept the interrupt
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if xirr_accept_rd = '1' then
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report "XICS: ACCEPT" &
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" cppr:" & to_hstring(r.cppr) &
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" xisr:" & to_hstring(r.xisr) &
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" mfrr:" & to_hstring(r.mfrr);
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v.cppr := r.pending_priority;
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report "XICS: ICP ACCEPT" &
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" cppr:" & to_hstring(r.cppr) &
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" xisr:" & to_hstring(r.xisr) &
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" mfrr:" & to_hstring(r.mfrr);
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v.cppr := pending_priority;
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end if;
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if irq_eoi = '1' then
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v.irq := '0';
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end if;
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v.wb_rd_data := bswap(be_out);
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if unsigned(pending_priority) < unsigned(v.cppr) then
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if r.irq = '0' then
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report "IRQ set";
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end if;
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v.irq := '1';
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elsif r.irq = '1' then
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report "IRQ clr";
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end if;
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if rst = '1' then
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v := reg_internal_init;
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@ -216,3 +200,227 @@ begin
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end process;
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end architecture behaviour;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.common.all;
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use work.wishbone_types.all;
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entity xics_ics is
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generic (
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SRC_NUM : integer range 1 to 256 := 16;
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PRIO_BITS : integer range 1 to 8 := 8
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);
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port (
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clk : in std_logic;
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rst : in std_logic;
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wb_in : in wb_io_master_out;
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wb_out : out wb_io_slave_out;
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int_level_in : in std_ulogic_vector(SRC_NUM - 1 downto 0);
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icp_out : out ics_to_icp_t
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);
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end xics_ics;
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architecture rtl of xics_ics is
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subtype pri_t is std_ulogic_vector(PRIO_BITS-1 downto 0);
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type xive_t is record
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pri : pri_t;
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end record;
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constant pri_masked : pri_t := (others => '1');
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type xive_array_t is array(0 to SRC_NUM-1) of xive_t;
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signal xives : xive_array_t;
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signal wb_valid : std_ulogic;
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signal reg_idx : integer range 0 to SRC_NUM - 1;
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signal icp_out_next : ics_to_icp_t;
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signal int_level_l : std_ulogic_vector(SRC_NUM - 1 downto 0);
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function bswap(v : in std_ulogic_vector(31 downto 0)) return std_ulogic_vector is
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variable r : std_ulogic_vector(31 downto 0);
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begin
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r( 7 downto 0) := v(31 downto 24);
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r(15 downto 8) := v(23 downto 16);
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r(23 downto 16) := v(15 downto 8);
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r(31 downto 24) := v( 7 downto 0);
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return r;
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end function;
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function get_config return std_ulogic_vector is
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variable r: std_ulogic_vector(31 downto 0);
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begin
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r := (others => '0');
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r(23 downto 0) := std_ulogic_vector(to_unsigned(SRC_NUM, 24));
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r(27 downto 24) := std_ulogic_vector(to_unsigned(PRIO_BITS, 4));
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return r;
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end function;
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function prio_pack(pri8: std_ulogic_vector(7 downto 0)) return pri_t is
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begin
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return pri8(PRIO_BITS-1 downto 0);
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end function;
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function prio_unpack(pri: pri_t) return std_ulogic_vector is
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variable r : std_ulogic_vector(7 downto 0);
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begin
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if pri = pri_masked then
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r := x"ff";
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else
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r := (others => '0');
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r(PRIO_BITS-1 downto 0) := pri;
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end if;
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return r;
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end function;
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-- Register map
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-- 0 : Config
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-- 4 : Debug/diagnostics
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-- 800 : XIVE0
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-- 804 : XIVE1 ...
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--
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-- Config register format:
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--
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-- 23.. 0 : Interrupt base (hard wired to 16)
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-- 27.. 24 : #prio bits (1..8)
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--
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-- XIVE register format:
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--
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-- 31 : input bit (reflects interrupt input)
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-- 30 : reserved
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-- 29 : P (mirrors input for now)
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-- 28 : Q (not implemented in this version)
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-- 30 .. : reserved
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-- 19 .. 8 : target (not implemented in this version)
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-- 7 .. 0 : prio/mask
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signal reg_is_xive : std_ulogic;
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signal reg_is_config : std_ulogic;
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signal reg_is_debug : std_ulogic;
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begin
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assert SRC_NUM = 16 report "Fixup address decode with log2";
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reg_is_xive <= wb_in.adr(11);
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reg_is_config <= '1' when wb_in.adr(11 downto 0) = x"000" else '0';
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reg_is_debug <= '1' when wb_in.adr(11 downto 0) = x"004" else '0';
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-- Register index XX FIXME: figure out bits from SRC_NUM
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reg_idx <= to_integer(unsigned(wb_in.adr(5 downto 2)));
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-- Latch interrupt inputs for timing
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int_latch: process(clk)
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begin
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if rising_edge(clk) then
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int_level_l <= int_level_in;
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end if;
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end process;
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-- We don't stall. Acks are sent by the read machine one cycle
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-- after a request, but we can handle one access per cycle.
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wb_out.stall <= '0';
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wb_valid <= wb_in.cyc and wb_in.stb;
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-- Big read mux. This could be replaced by a slower state
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-- machine iterating registers instead if timing gets tight.
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reg_read: process(clk)
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variable be_out : std_ulogic_vector(31 downto 0);
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begin
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if rising_edge(clk) then
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be_out := (others => '0');
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if reg_is_xive = '1' then
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be_out := int_level_l(reg_idx) &
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'0' &
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int_level_l(reg_idx) &
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'0' &
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x"00000" &
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prio_unpack(xives(reg_idx).pri);
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elsif reg_is_config = '1' then
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be_out := get_config;
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elsif reg_is_debug = '1' then
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be_out := x"00000" & icp_out_next.src & icp_out_next.pri;
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end if;
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wb_out.dat <= bswap(be_out);
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wb_out.ack <= wb_valid;
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end if;
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end process;
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-- Register write machine
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reg_write: process(clk)
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variable be_in : std_ulogic_vector(31 downto 0);
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begin
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-- Byteswapped input
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be_in := bswap(wb_in.dat);
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if rising_edge(clk) then
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if rst = '1' then
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for i in 0 to SRC_NUM - 1 loop
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xives(i) <= (pri => pri_masked);
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end loop;
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elsif wb_valid = '1' and wb_in.we = '1' then
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if reg_is_xive then
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-- TODO: When adding support for other bits, make sure to
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|
-- properly implement wb_in.sel to allow partial writes.
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xives(reg_idx).pri <= prio_pack(be_in(7 downto 0));
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|
report "ICS irq " & integer'image(reg_idx) &
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" set to:" & to_hstring(be_in(7 downto 0));
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end if;
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end if;
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end if;
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end process;
|
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|
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-- generate interrupt. This is a simple combinational process,
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|
-- potentially wasteful in HW for large number of interrupts.
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--
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-- could be replaced with iterative state machines and a message
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-- system between ICSs' (plural) and ICP incl. reject etc...
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|
|
--
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irq_gen_sync: process(clk)
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begin
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|
|
if rising_edge(clk) then
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|
icp_out <= icp_out_next;
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|
end if;
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|
|
end process;
|
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|
|
irq_gen: process(all)
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|
|
variable max_idx : integer range 0 to SRC_NUM-1;
|
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|
|
variable max_pri : pri_t;
|
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|
|
-- A more favored than b ?
|
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|
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function a_mf_b(a: pri_t; b: pri_t) return boolean is
|
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|
|
variable a_i : unsigned(PRIO_BITS-1 downto 0);
|
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|
|
variable b_i : unsigned(PRIO_BITS-1 downto 0);
|
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|
|
|
begin
|
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|
|
a_i := unsigned(a);
|
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|
|
b_i := unsigned(b);
|
|
|
|
|
report "a_mf_b a=" & to_hstring(a) &
|
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|
|
" b=" & to_hstring(b) &
|
|
|
|
|
" r=" & boolean'image(a < b);
|
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|
|
return a_i < b_i;
|
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|
|
|
end function;
|
|
|
|
|
begin
|
|
|
|
|
-- XXX FIXME: Use a tree
|
|
|
|
|
max_pri := pri_masked;
|
|
|
|
|
max_idx := 0;
|
|
|
|
|
for i in 0 to SRC_NUM - 1 loop
|
|
|
|
|
if int_level_l(i) = '1' and a_mf_b(xives(i).pri, max_pri) then
|
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|
|
|
max_pri := xives(i).pri;
|
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|
|
max_idx := i;
|
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|
|
end if;
|
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|
|
end loop;
|
|
|
|
|
if max_pri /= pri_masked then
|
|
|
|
|
report "MFI: " & integer'image(max_idx) & " pri=" & to_hstring(prio_unpack(max_pri));
|
|
|
|
|
end if;
|
|
|
|
|
icp_out_next.src <= std_ulogic_vector(to_unsigned(max_idx, 4));
|
|
|
|
|
icp_out_next.pri <= prio_unpack(max_pri);
|
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|
|
end process;
|
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|
|
end architecture rtl;
|
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