cores
/
microwatt
mirror of https://github.com/antonblanchard/microwatt
3
1
Fork 1
Code Issues Projects Releases Wiki Activity

litedram: Fix DRAM init mem using too many address bits

Browse Source 
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
pull/194/head
Benjamin Herrenschmidt 5 years ago
parent a93d9e77c9
commit 63f10450a6
4 changed files with 4 additions and 4 deletions
Show Stats Download Patch File Download Diff File

2
litedram/gen-src/dram-init-mem.vhdl
Unescape Escape View File

@ -24,7 +24,7 @@ architecture rtl of dram_init_mem is
constant INIT_RAM_SIZE : integer := 16384; constant INIT_RAM_SIZE : integer := 16384;
constant RND_PAYLOAD_SIZE : integer := round_up(EXTRA_PAYLOAD_SIZE, 8); constant RND_PAYLOAD_SIZE : integer := round_up(EXTRA_PAYLOAD_SIZE, 8);
constant TOTAL_RAM_SIZE : integer := INIT_RAM_SIZE + RND_PAYLOAD_SIZE; constant TOTAL_RAM_SIZE : integer := INIT_RAM_SIZE + RND_PAYLOAD_SIZE;
constant INIT_RAM_ABITS : integer := log2ceil(TOTAL_RAM_SIZE); constant INIT_RAM_ABITS : integer := log2ceil(TOTAL_RAM_SIZE-1);
constant INIT_RAM_FILE : string := "litedram_core.init"; constant INIT_RAM_FILE : string := "litedram_core.init";


type ram_t is array(0 to (TOTAL_RAM_SIZE / 4) - 1) of std_logic_vector(31 downto 0); type ram_t is array(0 to (TOTAL_RAM_SIZE / 4) - 1) of std_logic_vector(31 downto 0);

2
litedram/generated/arty/litedram-initmem.vhdl
Unescape Escape View File

@ -24,7 +24,7 @@ architecture rtl of dram_init_mem is
constant INIT_RAM_SIZE : integer := 16384; constant INIT_RAM_SIZE : integer := 16384;
constant RND_PAYLOAD_SIZE : integer := round_up(EXTRA_PAYLOAD_SIZE, 8); constant RND_PAYLOAD_SIZE : integer := round_up(EXTRA_PAYLOAD_SIZE, 8);
constant TOTAL_RAM_SIZE : integer := INIT_RAM_SIZE + RND_PAYLOAD_SIZE; constant TOTAL_RAM_SIZE : integer := INIT_RAM_SIZE + RND_PAYLOAD_SIZE;
constant INIT_RAM_ABITS : integer := log2ceil(TOTAL_RAM_SIZE); constant INIT_RAM_ABITS : integer := log2ceil(TOTAL_RAM_SIZE-1);
constant INIT_RAM_FILE : string := "litedram_core.init"; constant INIT_RAM_FILE : string := "litedram_core.init";


type ram_t is array(0 to (TOTAL_RAM_SIZE / 4) - 1) of std_logic_vector(31 downto 0); type ram_t is array(0 to (TOTAL_RAM_SIZE / 4) - 1) of std_logic_vector(31 downto 0);

2
litedram/generated/nexys-video/litedram-initmem.vhdl
Unescape Escape View File

@ -24,7 +24,7 @@ architecture rtl of dram_init_mem is
constant INIT_RAM_SIZE : integer := 16384; constant INIT_RAM_SIZE : integer := 16384;
constant RND_PAYLOAD_SIZE : integer := round_up(EXTRA_PAYLOAD_SIZE, 8); constant RND_PAYLOAD_SIZE : integer := round_up(EXTRA_PAYLOAD_SIZE, 8);
constant TOTAL_RAM_SIZE : integer := INIT_RAM_SIZE + RND_PAYLOAD_SIZE; constant TOTAL_RAM_SIZE : integer := INIT_RAM_SIZE + RND_PAYLOAD_SIZE;
constant INIT_RAM_ABITS : integer := log2ceil(TOTAL_RAM_SIZE); constant INIT_RAM_ABITS : integer := log2ceil(TOTAL_RAM_SIZE-1);
constant INIT_RAM_FILE : string := "litedram_core.init"; constant INIT_RAM_FILE : string := "litedram_core.init";


type ram_t is array(0 to (TOTAL_RAM_SIZE / 4) - 1) of std_logic_vector(31 downto 0); type ram_t is array(0 to (TOTAL_RAM_SIZE / 4) - 1) of std_logic_vector(31 downto 0);

2
litedram/generated/sim/litedram-initmem.vhdl
Unescape Escape View File

@ -24,7 +24,7 @@ architecture rtl of dram_init_mem is
constant INIT_RAM_SIZE : integer := 16384; constant INIT_RAM_SIZE : integer := 16384;
constant RND_PAYLOAD_SIZE : integer := round_up(EXTRA_PAYLOAD_SIZE, 8); constant RND_PAYLOAD_SIZE : integer := round_up(EXTRA_PAYLOAD_SIZE, 8);
constant TOTAL_RAM_SIZE : integer := INIT_RAM_SIZE + RND_PAYLOAD_SIZE; constant TOTAL_RAM_SIZE : integer := INIT_RAM_SIZE + RND_PAYLOAD_SIZE;
constant INIT_RAM_ABITS : integer := log2ceil(TOTAL_RAM_SIZE); constant INIT_RAM_ABITS : integer := log2ceil(TOTAL_RAM_SIZE-1);
constant INIT_RAM_FILE : string := "litedram/generated/sim/litedram_core.init"; constant INIT_RAM_FILE : string := "litedram/generated/sim/litedram_core.init";


type ram_t is array(0 to (TOTAL_RAM_SIZE / 4) - 1) of std_logic_vector(31 downto 0); type ram_t is array(0 to (TOTAL_RAM_SIZE / 4) - 1) of std_logic_vector(31 downto 0);

Write Preview
Loading…
Cancel
Save