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@ -118,7 +118,7 @@ architecture behaviour of execute1 is
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constant actions_type_init : actions_type :=
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constant actions_type_init : actions_type :=
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(e => Execute1ToWritebackInit, new_msr => (others => '0'), others => '0');
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(e => Execute1ToWritebackInit, new_msr => (others => '0'), others => '0');
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signal r, rin : reg_type;
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signal ex1, ex1in : reg_type;
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signal actions : actions_type;
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signal actions : actions_type;
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signal a_in, b_in, c_in : std_ulogic_vector(63 downto 0);
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signal a_in, b_in, c_in : std_ulogic_vector(63 downto 0);
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@ -372,7 +372,7 @@ begin
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end generate;
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end generate;
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dbg_ctrl_out <= ctrl;
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dbg_ctrl_out <= ctrl;
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log_rd_addr <= r.log_addr_spr;
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log_rd_addr <= ex1.log_addr_spr;
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a_in <= e_in.read_data1;
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a_in <= e_in.read_data1;
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b_in <= e_in.read_data2;
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b_in <= e_in.read_data2;
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@ -391,11 +391,11 @@ begin
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dtlb_miss_resolved => dc_events.dtlb_miss_resolved,
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dtlb_miss_resolved => dc_events.dtlb_miss_resolved,
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icache_miss => ic_events.icache_miss,
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icache_miss => ic_events.icache_miss,
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itlb_miss_resolved => ic_events.itlb_miss_resolved,
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itlb_miss_resolved => ic_events.itlb_miss_resolved,
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no_instr_avail => r.no_instr_avail,
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no_instr_avail => ex1.no_instr_avail,
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dispatch => r.instr_dispatch,
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dispatch => ex1.instr_dispatch,
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ext_interrupt => r.ext_interrupt,
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ext_interrupt => ex1.ext_interrupt,
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br_taken_complete => r.taken_branch_event,
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br_taken_complete => ex1.taken_branch_event,
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br_mispredict => r.br_mispredict,
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br_mispredict => ex1.br_mispredict,
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others => '0');
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others => '0');
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x_to_pmu.nia <= e_in.nia;
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x_to_pmu.nia <= e_in.nia;
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x_to_pmu.addr <= (others => '0');
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x_to_pmu.addr <= (others => '0');
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@ -409,15 +409,15 @@ begin
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-- (SO, OV[32] and CA[32]) are only modified by instructions that are
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-- (SO, OV[32] and CA[32]) are only modified by instructions that are
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-- handled here, we can just forward the result being sent to
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-- handled here, we can just forward the result being sent to
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-- writeback.
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-- writeback.
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xerc_in <= r.e.xerc when (r.e.write_xerc_enable and r.e.valid) = '1' else e_in.xerc;
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xerc_in <= ex1.e.xerc when (ex1.e.write_xerc_enable and ex1.e.valid) = '1' else e_in.xerc;
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with e_in.unit select busy_out <=
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with e_in.unit select busy_out <=
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l_in.busy or r.busy or fp_in.busy when LDST,
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l_in.busy or ex1.busy or fp_in.busy when LDST,
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l_in.busy or l_in.in_progress or r.busy or fp_in.busy when others;
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l_in.busy or l_in.in_progress or ex1.busy or fp_in.busy when others;
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valid_in <= e_in.valid and not busy_out and not flush_in;
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valid_in <= e_in.valid and not busy_out and not flush_in;
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terminate_out <= r.terminate;
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terminate_out <= ex1.terminate;
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-- Slow SPR read mux
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-- Slow SPR read mux
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with e_in.spr_select.sel select spr_result <=
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with e_in.spr_select.sel select spr_result <=
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@ -425,7 +425,7 @@ begin
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32x"0" & ctrl.tb(63 downto 32) when SPRSEL_TBU,
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32x"0" & ctrl.tb(63 downto 32) when SPRSEL_TBU,
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ctrl.dec when SPRSEL_DEC,
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ctrl.dec when SPRSEL_DEC,
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32x"0" & PVR_MICROWATT when SPRSEL_PVR,
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32x"0" & PVR_MICROWATT when SPRSEL_PVR,
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log_wr_addr & r.log_addr_spr when SPRSEL_LOGA,
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log_wr_addr & ex1.log_addr_spr when SPRSEL_LOGA,
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log_rd_data when SPRSEL_LOGD,
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log_rd_data when SPRSEL_LOGD,
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ctrl.cfar when SPRSEL_CFAR,
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ctrl.cfar when SPRSEL_CFAR,
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assemble_xer(xerc_in, ctrl.xer_low) when others;
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assemble_xer(xerc_in, ctrl.xer_low) when others;
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@ -445,16 +445,16 @@ begin
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begin
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begin
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if rising_edge(clk) then
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if rising_edge(clk) then
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if rst = '1' then
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if rst = '1' then
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r <= reg_type_init;
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ex1 <= reg_type_init;
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ctrl <= ctrl_t_init;
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ctrl <= ctrl_t_init;
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ctrl.msr <= (MSR_SF => '1', MSR_LE => '1', others => '0');
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ctrl.msr <= (MSR_SF => '1', MSR_LE => '1', others => '0');
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else
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else
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r <= rin;
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ex1 <= ex1in;
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ctrl <= ctrl_tmp;
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ctrl <= ctrl_tmp;
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if valid_in = '1' then
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if valid_in = '1' then
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report "execute " & to_hstring(e_in.nia) & " op=" & insn_type_t'image(e_in.insn_type) &
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report "execute " & to_hstring(e_in.nia) & " op=" & insn_type_t'image(e_in.insn_type) &
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" wr=" & to_hstring(rin.e.write_reg) & " we=" & std_ulogic'image(rin.e.write_enable) &
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" wr=" & to_hstring(ex1in.e.write_reg) & " we=" & std_ulogic'image(ex1in.e.write_enable) &
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" tag=" & integer'image(rin.e.instr_tag.tag) & std_ulogic'image(rin.e.instr_tag.valid);
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" tag=" & integer'image(ex1in.e.instr_tag.tag) & std_ulogic'image(ex1in.e.instr_tag.valid);
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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@ -583,7 +583,7 @@ begin
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end if;
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end if;
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shortmul_result <= std_ulogic_vector(resize(signed(mshort_p), 64));
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shortmul_result <= std_ulogic_vector(resize(signed(mshort_p), 64));
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case r.mul_select is
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case ex1.mul_select is
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when "00" =>
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when "00" =>
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muldiv_result <= multiply_to_x.result(63 downto 0);
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muldiv_result <= multiply_to_x.result(63 downto 0);
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when "01" =>
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when "01" =>
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@ -820,7 +820,7 @@ begin
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-- v.trap also means we want to generate an interrupt, but doesn't
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-- v.trap also means we want to generate an interrupt, but doesn't
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-- cancel instruction execution (hence we need to avoid setting any
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-- cancel instruction execution (hence we need to avoid setting any
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-- side-effect flags or write enables when generating a trap).
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-- side-effect flags or write enables when generating a trap).
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-- With v.trap = 1 we will assert both r.e.valid and r.e.interrupt
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-- With v.trap = 1 we will assert both ex1.e.valid and ex1.e.interrupt
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-- to writeback, and it will complete the instruction and take
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-- to writeback, and it will complete the instruction and take
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-- and interrupt. It is OK for v.trap to depend on operand data.
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-- and interrupt. It is OK for v.trap to depend on operand data.
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@ -924,7 +924,7 @@ begin
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if e_in.second = '0' then
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if e_in.second = '0' then
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v.take_branch := ppc_bc_taken(bo, bi, cr_in, a_in);
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v.take_branch := ppc_bc_taken(bo, bi, cr_in, a_in);
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else
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else
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v.take_branch := r.br_taken;
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v.take_branch := ex1.br_taken;
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end if;
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end if;
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if v.take_branch = '1' then
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if v.take_branch = '1' then
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v.e.br_offset := b_in;
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v.e.br_offset := b_in;
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@ -954,7 +954,7 @@ begin
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if e_in.second = '0' then
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if e_in.second = '0' then
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v.take_branch := ppc_bc_taken(bo, bi, cr_in, a_in);
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v.take_branch := ppc_bc_taken(bo, bi, cr_in, a_in);
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else
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else
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v.take_branch := r.br_taken;
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v.take_branch := ex1.br_taken;
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end if;
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end if;
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if v.take_branch = '1' then
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if v.take_branch = '1' then
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v.e.br_offset := b_in;
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v.e.br_offset := b_in;
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@ -1172,8 +1172,8 @@ begin
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variable fv : Execute1ToFPUType;
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variable fv : Execute1ToFPUType;
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variable go : std_ulogic;
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variable go : std_ulogic;
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begin
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begin
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v := r;
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v := ex1;
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if r.busy = '0' then
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if ex1.busy = '0' then
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v.e := actions.e;
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v.e := actions.e;
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v.oe := e_in.oe;
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v.oe := e_in.oe;
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v.mul_select := e_in.sub_select(1 downto 0);
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v.mul_select := e_in.sub_select(1 downto 0);
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@ -1223,9 +1223,9 @@ begin
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do_popcnt <= '1' when e_in.insn_type = OP_POPCNT else '0';
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do_popcnt <= '1' when e_in.insn_type = OP_POPCNT else '0';
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if r.intr_pending = '1' then
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if ex1.intr_pending = '1' then
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v.e.srr1 := r.e.srr1;
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v.e.srr1 := ex1.e.srr1;
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v.e.intr_vec := r.e.intr_vec;
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v.e.intr_vec := ex1.e.intr_vec;
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end if;
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end if;
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if valid_in = '1' then
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if valid_in = '1' then
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@ -1234,9 +1234,9 @@ begin
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-- Determine if there is any interrupt to be taken
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-- Determine if there is any interrupt to be taken
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-- before/instead of executing this instruction
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-- before/instead of executing this instruction
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exception := r.intr_pending or (valid_in and actions.exception);
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exception := ex1.intr_pending or (valid_in and actions.exception);
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if valid_in = '1' and e_in.second = '0' and r.intr_pending = '0' then
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if valid_in = '1' and e_in.second = '0' and ex1.intr_pending = '0' then
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if HAS_FPU and r.fp_exception_next = '1' then
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if HAS_FPU and ex1.fp_exception_next = '1' then
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-- This is used for FP-type program interrupts that
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-- This is used for FP-type program interrupts that
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-- become pending due to MSR[FE0,FE1] changing from 00 to non-zero.
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-- become pending due to MSR[FE0,FE1] changing from 00 to non-zero.
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exception := '1';
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exception := '1';
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@ -1244,17 +1244,18 @@ begin
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v.e.srr1 := (others => '0');
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v.e.srr1 := (others => '0');
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v.e.srr1(47 - 43) := '1';
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v.e.srr1(47 - 43) := '1';
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v.e.srr1(47 - 47) := '1';
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v.e.srr1(47 - 47) := '1';
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elsif r.trace_next = '1' then
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elsif ex1.trace_next = '1' then
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-- Generate a trace interrupt rather than executing the next instruction
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-- Generate a trace interrupt rather than executing the next instruction
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-- or taking any asynchronous interrupt
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-- or taking any asynchronous interrupt
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exception := '1';
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exception := '1';
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v.e.intr_vec := 16#d00#;
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v.e.intr_vec := 16#d00#;
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v.e.srr1 := (others => '0');
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v.e.srr1 := (others => '0');
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v.e.srr1(47 - 33) := '1';
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v.e.srr1(47 - 33) := '1';
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if r.prev_op = OP_LOAD or r.prev_op = OP_ICBI or r.prev_op = OP_ICBT or
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if ex1.prev_op = OP_LOAD or ex1.prev_op = OP_ICBI or ex1.prev_op = OP_ICBT or
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r.prev_op = OP_DCBT or r.prev_op = OP_DCBST or r.prev_op = OP_DCBF then
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ex1.prev_op = OP_DCBT or ex1.prev_op = OP_DCBST or ex1.prev_op = OP_DCBF then
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v.e.srr1(47 - 35) := '1';
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v.e.srr1(47 - 35) := '1';
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elsif r.prev_op = OP_STORE or r.prev_op = OP_DCBZ or r.prev_op = OP_DCBTST then
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elsif ex1.prev_op = OP_STORE or ex1.prev_op = OP_DCBZ or
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ex1.prev_op = OP_DCBTST then
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v.e.srr1(47 - 36) := '1';
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v.e.srr1(47 - 36) := '1';
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end if;
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end if;
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@ -1284,7 +1285,7 @@ begin
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v.busy := '1';
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v.busy := '1';
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end if;
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end if;
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v.no_instr_avail := not (e_in.valid or l_in.busy or l_in.in_progress or r.busy or fp_in.busy);
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v.no_instr_avail := not (e_in.valid or l_in.busy or l_in.in_progress or ex1.busy or fp_in.busy);
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go := valid_in and not exception;
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go := valid_in and not exception;
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v.instr_dispatch := go;
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v.instr_dispatch := go;
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@ -1312,7 +1313,7 @@ begin
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if actions.write_loga = '1' then
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if actions.write_loga = '1' then
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v.log_addr_spr := c_in(31 downto 0);
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v.log_addr_spr := c_in(31 downto 0);
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elsif actions.inc_loga = '1' then
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elsif actions.inc_loga = '1' then
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v.log_addr_spr := std_ulogic_vector(unsigned(r.log_addr_spr) + 1);
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v.log_addr_spr := std_ulogic_vector(unsigned(ex1.log_addr_spr) + 1);
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end if;
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end if;
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x_to_pmu.mtspr <= actions.write_pmuspr;
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x_to_pmu.mtspr <= actions.write_pmuspr;
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icache_inval <= actions.icache_inval;
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icache_inval <= actions.icache_inval;
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@ -1334,22 +1335,22 @@ begin
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end if;
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end if;
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end if;
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end if;
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-- The following cases all occur when r.busy = 1 and therefore
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-- The following cases all occur when ex1.busy = 1 and therefore
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-- valid_in = 0. Hence they don't happen in the same cycle as any of
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-- valid_in = 0. Hence they don't happen in the same cycle as any of
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-- the cases above which depend on valid_in = 1.
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-- the cases above which depend on valid_in = 1.
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if r.cntz_in_progress = '1' then
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if ex1.cntz_in_progress = '1' then
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-- cnt[lt]z and popcnt* always take two cycles
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-- cnt[lt]z and popcnt* always take two cycles
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v.e.valid := '1';
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v.e.valid := '1';
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v.e.write_data := countbits_result;
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v.e.write_data := countbits_result;
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end if;
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end if;
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if r.div_in_progress = '1' then
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if ex1.div_in_progress = '1' then
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if divider_to_x.valid = '1' then
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if divider_to_x.valid = '1' then
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v.e.write_data := muldiv_result;
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v.e.write_data := muldiv_result;
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overflow := divider_to_x.overflow;
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overflow := divider_to_x.overflow;
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-- We must test oe because the RC update code in writeback
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-- We must test oe because the RC update code in writeback
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-- will use the xerc value to set CR0:SO so we must not clobber
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-- will use the xerc value to set CR0:SO so we must not clobber
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-- xerc if OE wasn't set.
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-- xerc if OE wasn't set.
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if r.oe = '1' then
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if ex1.oe = '1' then
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v.e.xerc.ov := overflow;
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v.e.xerc.ov := overflow;
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v.e.xerc.ov32 := overflow;
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v.e.xerc.ov32 := overflow;
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if overflow = '1' then
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if overflow = '1' then
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@ -1362,10 +1363,10 @@ begin
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v.div_in_progress := '1';
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v.div_in_progress := '1';
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end if;
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end if;
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end if;
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end if;
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if r.mul_in_progress = '1' then
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if ex1.mul_in_progress = '1' then
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if multiply_to_x.valid = '1' then
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if multiply_to_x.valid = '1' then
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v.e.write_data := muldiv_result;
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v.e.write_data := muldiv_result;
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if r.oe = '1' then
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if ex1.oe = '1' then
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-- have to wait until next cycle for overflow indication
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-- have to wait until next cycle for overflow indication
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v.mul_finish := '1';
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v.mul_finish := '1';
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v.busy := '1';
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v.busy := '1';
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@ -1377,7 +1378,7 @@ begin
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v.mul_in_progress := '1';
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v.mul_in_progress := '1';
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end if;
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end if;
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end if;
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end if;
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if r.mul_finish = '1' then
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if ex1.mul_finish = '1' then
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v.e.xerc.ov := multiply_to_x.overflow;
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v.e.xerc.ov := multiply_to_x.overflow;
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v.e.xerc.ov32 := multiply_to_x.overflow;
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v.e.xerc.ov32 := multiply_to_x.overflow;
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if multiply_to_x.overflow = '1' then
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if multiply_to_x.overflow = '1' then
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@ -1460,12 +1461,12 @@ begin
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fv.out_cr := e_in.output_cr;
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fv.out_cr := e_in.output_cr;
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-- Update registers
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-- Update registers
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rin <= v;
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ex1in <= v;
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-- update outputs
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-- update outputs
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l_out <= lv;
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l_out <= lv;
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e_out <= r.e;
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e_out <= ex1.e;
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if r.e.valid = '0' then
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if ex1.e.valid = '0' then
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e_out.write_enable <= '0';
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e_out.write_enable <= '0';
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e_out.write_cr_enable <= '0';
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e_out.write_cr_enable <= '0';
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e_out.write_xerc_enable <= '0';
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e_out.write_xerc_enable <= '0';
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@ -1491,10 +1492,10 @@ begin
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irq_valid_log &
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irq_valid_log &
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interrupt_in &
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interrupt_in &
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"000" &
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"000" &
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r.e.write_enable &
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ex1.e.write_enable &
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r.e.valid &
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ex1.e.valid &
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((r.e.redirect and r.e.valid) or r.e.interrupt) &
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((ex1.e.redirect and ex1.e.valid) or ex1.e.interrupt) &
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r.busy &
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ex1.busy &
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flush_in;
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flush_in;
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end if;
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end if;
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end process;
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end process;
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