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@ -8,70 +8,70 @@ use work.wishbone_types.all;
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use work.simple_ram_behavioural_helpers.all;
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entity mw_soc_memory is
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generic (
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RAM_INIT_FILE : string;
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MEMORY_SIZE : integer
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);
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generic (
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RAM_INIT_FILE : string;
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MEMORY_SIZE : integer
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);
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port (
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clk : in std_ulogic;
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rst : in std_ulogic;
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port (
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clk : in std_ulogic;
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rst : in std_ulogic;
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wishbone_in : in wishbone_master_out;
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wishbone_out : out wishbone_slave_out
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);
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wishbone_in : in wishbone_master_out;
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wishbone_out : out wishbone_slave_out
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);
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end mw_soc_memory;
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architecture behave of mw_soc_memory is
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type wishbone_state_t is (IDLE, ACK);
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type wishbone_state_t is (IDLE, ACK);
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signal state : wishbone_state_t := IDLE;
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signal ret_ack : std_ulogic := '0';
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signal identifier : integer := behavioural_initialize(filename => RAM_INIT_FILE, size => MEMORY_SIZE);
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signal reload : integer := 0;
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signal state : wishbone_state_t := IDLE;
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signal ret_ack : std_ulogic := '0';
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signal identifier : integer := behavioural_initialize(filename => RAM_INIT_FILE, size => MEMORY_SIZE);
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signal reload : integer := 0;
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begin
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wishbone_process: process(clk)
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variable ret_dat: std_ulogic_vector(63 downto 0) := (others => '0');
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begin
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wishbone_out.ack <= ret_ack and wishbone_in.cyc and wishbone_in.stb;
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wishbone_out.dat <= ret_dat;
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wishbone_process: process(clk)
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variable ret_dat: std_ulogic_vector(63 downto 0) := (others => '0');
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begin
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wishbone_out.ack <= ret_ack and wishbone_in.cyc and wishbone_in.stb;
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wishbone_out.dat <= ret_dat;
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if rising_edge(clk) then
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if rst = '1' then
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state <= IDLE;
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ret_ack <= '0';
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else
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ret_dat := x"FFFFFFFFFFFFFFFF";
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if rising_edge(clk) then
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if rst = '1' then
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state <= IDLE;
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ret_ack <= '0';
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else
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ret_dat := x"FFFFFFFFFFFFFFFF";
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-- Active
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if wishbone_in.cyc = '1' then
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case state is
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when IDLE =>
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if wishbone_in.stb = '1' then
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-- write
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if wishbone_in.we = '1' then
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assert not(is_x(wishbone_in.dat)) and not(is_x(wishbone_in.adr)) severity failure;
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report "RAM writing " & to_hstring(wishbone_in.dat) & " to " & to_hstring(wishbone_in.adr);
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behavioural_write(wishbone_in.dat, wishbone_in.adr, to_integer(unsigned(wishbone_in.sel)), identifier);
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reload <= reload + 1;
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ret_ack <= '1';
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state <= ACK;
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else
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behavioural_read(ret_dat, wishbone_in.adr, to_integer(unsigned(wishbone_in.sel)), identifier, reload);
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report "RAM reading from " & to_hstring(wishbone_in.adr) & " returns " & to_hstring(ret_dat);
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ret_ack <= '1';
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state <= ACK;
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end if;
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end if;
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when ACK =>
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ret_ack <= '0';
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state <= IDLE;
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end case;
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else
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ret_ack <= '0';
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state <= IDLE;
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end if;
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end if;
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end if;
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end process;
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-- Active
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if wishbone_in.cyc = '1' then
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case state is
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when IDLE =>
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if wishbone_in.stb = '1' then
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-- write
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if wishbone_in.we = '1' then
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assert not(is_x(wishbone_in.dat)) and not(is_x(wishbone_in.adr)) severity failure;
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report "RAM writing " & to_hstring(wishbone_in.dat) & " to " & to_hstring(wishbone_in.adr);
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behavioural_write(wishbone_in.dat, wishbone_in.adr, to_integer(unsigned(wishbone_in.sel)), identifier);
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reload <= reload + 1;
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ret_ack <= '1';
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state <= ACK;
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else
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behavioural_read(ret_dat, wishbone_in.adr, to_integer(unsigned(wishbone_in.sel)), identifier, reload);
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report "RAM reading from " & to_hstring(wishbone_in.adr) & " returns " & to_hstring(ret_dat);
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ret_ack <= '1';
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state <= ACK;
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end if;
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end if;
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when ACK =>
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ret_ack <= '0';
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state <= IDLE;
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end case;
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else
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ret_ack <= '0';
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state <= IDLE;
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end if;
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end if;
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end if;
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end process;
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end behave;
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Anton Blanchard
