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@ -119,10 +119,11 @@ architecture behaviour of execute1 is
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signal overflow_32 : std_ulogic;
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signal overflow_32 : std_ulogic;
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signal overflow_64 : std_ulogic;
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signal overflow_64 : std_ulogic;
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signal cmprb_result : std_ulogic_vector(3 downto 0);
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signal cmpeqb_result : std_ulogic_vector(3 downto 0);
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signal trapval : std_ulogic_vector(4 downto 0);
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signal trapval : std_ulogic_vector(4 downto 0);
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signal write_cr_mask : std_ulogic_vector(7 downto 0);
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signal write_cr_data : std_ulogic_vector(31 downto 0);
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-- multiply signals
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-- multiply signals
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signal x_to_multiply: MultiplyInputType;
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signal x_to_multiply: MultiplyInputType;
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signal multiply_to_x: MultiplyOutputType;
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signal multiply_to_x: MultiplyOutputType;
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@ -169,7 +170,6 @@ architecture behaviour of execute1 is
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begin
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begin
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e.xerc.ca32 := carry32;
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e.xerc.ca32 := carry32;
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e.xerc.ca := carry;
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e.xerc.ca := carry;
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e.write_xerc_enable := '1';
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end;
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end;
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procedure set_ov(e: inout Execute1ToWritebackType;
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procedure set_ov(e: inout Execute1ToWritebackType;
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@ -181,7 +181,6 @@ architecture behaviour of execute1 is
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if ov = '1' then
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if ov = '1' then
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e.xerc.so := '1';
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e.xerc.so := '1';
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end if;
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end if;
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e.write_xerc_enable := '1';
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end;
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end;
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function calc_ov(msb_a : std_ulogic; msb_b: std_ulogic;
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function calc_ov(msb_a : std_ulogic; msb_b: std_ulogic;
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@ -360,7 +359,6 @@ begin
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variable darn : std_ulogic_vector(63 downto 0);
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variable darn : std_ulogic_vector(63 downto 0);
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variable setb_result : std_ulogic_vector(63 downto 0);
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variable setb_result : std_ulogic_vector(63 downto 0);
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variable mfcr_result : std_ulogic_vector(63 downto 0);
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variable mfcr_result : std_ulogic_vector(63 downto 0);
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variable crnum : crnum_t;
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variable lo, hi : integer;
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variable lo, hi : integer;
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variable l : std_ulogic;
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variable l : std_ulogic;
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variable zerohi, zerolo : std_ulogic;
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variable zerohi, zerolo : std_ulogic;
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@ -368,7 +366,16 @@ begin
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variable a_lt : std_ulogic;
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variable a_lt : std_ulogic;
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variable a_lt_lo : std_ulogic;
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variable a_lt_lo : std_ulogic;
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variable a_lt_hi : std_ulogic;
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variable a_lt_hi : std_ulogic;
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variable bfa : std_ulogic_vector(2 downto 0);
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variable newcrf : std_ulogic_vector(3 downto 0);
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variable bf, bfa : std_ulogic_vector(2 downto 0);
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variable crnum : crnum_t;
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variable scrnum : crnum_t;
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variable cr_operands : std_ulogic_vector(1 downto 0);
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variable crresult : std_ulogic;
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variable bt, ba, bb : std_ulogic_vector(4 downto 0);
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variable btnum : integer range 0 to 3;
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variable banum, bbnum : integer range 0 to 31;
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variable j : integer;
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begin
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begin
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-- Main adder
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-- Main adder
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if e_in.invert_a = '0' then
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if e_in.invert_a = '0' then
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@ -591,24 +598,77 @@ begin
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end if;
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end if;
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end if;
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end if;
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cmprb_result <= ppc_cmprb(a_in, b_in, insn_l(e_in.insn));
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-- CR result mux
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cmpeqb_result <= ppc_cmpeqb(a_in, b_in);
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bf := insn_bf(e_in.insn);
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crnum := to_integer(unsigned(bf));
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newcrf := (others => '0');
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case current.sub_select is
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when "000" =>
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-- CMP and CMPL instructions
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if e_in.is_signed = '1' then
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newcrf := trapval(4 downto 2) & xerc_in.so;
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else
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newcrf := trapval(1 downto 0) & trapval(2) & xerc_in.so;
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end if;
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when "001" =>
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newcrf := ppc_cmprb(a_in, b_in, insn_l(e_in.insn));
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when "010" =>
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newcrf := ppc_cmpeqb(a_in, b_in);
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when "011" =>
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if current.insn(1) = '1' then
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-- CR logical instructions
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j := (7 - crnum) * 4;
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newcrf := cr_in(j + 3 downto j);
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bt := insn_bt(e_in.insn);
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ba := insn_ba(e_in.insn);
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bb := insn_bb(e_in.insn);
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btnum := 3 - to_integer(unsigned(bt(1 downto 0)));
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banum := 31 - to_integer(unsigned(ba));
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bbnum := 31 - to_integer(unsigned(bb));
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-- Bits 6-9 of the instruction word give the truth table
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-- of the requested logical operation
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cr_operands := cr_in(banum) & cr_in(bbnum);
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crresult := e_in.insn(6 + to_integer(unsigned(cr_operands)));
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for i in 0 to 3 loop
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if i = btnum then
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newcrf(i) := crresult;
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end if;
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end loop;
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else
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-- MCRF
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bfa := insn_bfa(e_in.insn);
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scrnum := to_integer(unsigned(bfa));
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j := (7 - scrnum) * 4;
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newcrf := cr_in(j + 3 downto j);
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end if;
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when "100" =>
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-- MCRXRX
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newcrf := xerc_in.ov & xerc_in.ca & xerc_in.ov32 & xerc_in.ca32;
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when others =>
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end case;
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if current.insn_type = OP_MTCRF then
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if e_in.insn(20) = '0' then
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-- mtcrf
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write_cr_mask <= insn_fxm(e_in.insn);
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else
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-- mtocrf: We require one hot priority encoding here
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crnum := fxm_to_num(insn_fxm(e_in.insn));
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write_cr_mask <= num_to_fxm(crnum);
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end if;
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write_cr_data <= c_in(31 downto 0);
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else
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write_cr_mask <= num_to_fxm(crnum);
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write_cr_data <= newcrf & newcrf & newcrf & newcrf &
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newcrf & newcrf & newcrf & newcrf;
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end if;
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end process;
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end process;
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execute1_1: process(all)
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execute1_1: process(all)
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variable v : reg_type;
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variable v : reg_type;
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variable newcrf : std_ulogic_vector(3 downto 0);
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variable crnum : crnum_t;
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variable scrnum : crnum_t;
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variable lo, hi : integer;
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variable lo, hi : integer;
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variable sh, mb, me : std_ulogic_vector(5 downto 0);
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variable sh, mb, me : std_ulogic_vector(5 downto 0);
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variable bo, bi : std_ulogic_vector(4 downto 0);
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variable bo, bi : std_ulogic_vector(4 downto 0);
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variable bf, bfa : std_ulogic_vector(2 downto 0);
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variable cr_op : std_ulogic_vector(9 downto 0);
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variable cr_operands : std_ulogic_vector(1 downto 0);
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variable bt, ba, bb : std_ulogic_vector(4 downto 0);
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variable btnum, banum, bbnum : integer range 0 to 31;
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variable crresult : std_ulogic;
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variable overflow : std_ulogic;
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variable overflow : std_ulogic;
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variable lv : Execute1ToLoadstore1Type;
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variable lv : Execute1ToLoadstore1Type;
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variable irq_valid : std_ulogic;
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variable irq_valid : std_ulogic;
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@ -625,7 +685,6 @@ begin
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variable f : Execute1ToFetch1Type;
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variable f : Execute1ToFetch1Type;
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variable fv : Execute1ToFPUType;
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variable fv : Execute1ToFPUType;
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begin
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begin
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newcrf := (others => '0');
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is_branch := '0';
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is_branch := '0';
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is_direct_branch := '0';
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is_direct_branch := '0';
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taken_branch := '0';
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taken_branch := '0';
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@ -800,27 +859,12 @@ begin
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else
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else
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v.e.xerc.ov := carry_64;
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v.e.xerc.ov := carry_64;
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v.e.xerc.ov32 := carry_32;
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v.e.xerc.ov32 := carry_32;
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v.e.write_xerc_enable := '1';
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end if;
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end if;
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end if;
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end if;
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if e_in.oe = '1' then
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if e_in.oe = '1' then
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set_ov(v.e, overflow_64, overflow_32);
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set_ov(v.e, overflow_64, overflow_32);
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end if;
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end if;
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when OP_CMP =>
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when OP_CMP =>
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-- CMP and CMPL instructions
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if e_in.is_signed = '1' then
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newcrf := trapval(4 downto 2) & xerc_in.so;
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else
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newcrf := trapval(1 downto 0) & trapval(2) & xerc_in.so;
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end if;
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bf := insn_bf(e_in.insn);
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crnum := to_integer(unsigned(bf));
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v.e.write_cr_mask := num_to_fxm(crnum);
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for i in 0 to 7 loop
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lo := i*4;
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hi := lo + 3;
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v.e.write_cr_data(hi downto lo) := newcrf;
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end loop;
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when OP_TRAP =>
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when OP_TRAP =>
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-- trap instructions (tw, twi, td, tdi)
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-- trap instructions (tw, twi, td, tdi)
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v.vector := 16#700#;
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v.vector := 16#700#;
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@ -833,19 +877,7 @@ begin
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end if;
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end if;
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when OP_ADDG6S =>
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when OP_ADDG6S =>
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when OP_CMPRB =>
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when OP_CMPRB =>
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newcrf := cmprb_result;
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bf := insn_bf(e_in.insn);
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crnum := to_integer(unsigned(bf));
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v.e.write_cr_mask := num_to_fxm(crnum);
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v.e.write_cr_data := newcrf & newcrf & newcrf & newcrf &
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newcrf & newcrf & newcrf & newcrf;
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when OP_CMPEQB =>
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when OP_CMPEQB =>
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newcrf := cmpeqb_result;
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bf := insn_bf(e_in.insn);
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crnum := to_integer(unsigned(bf));
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v.e.write_cr_mask := num_to_fxm(crnum);
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v.e.write_cr_data := newcrf & newcrf & newcrf & newcrf &
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newcrf & newcrf & newcrf & newcrf;
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when OP_AND | OP_OR | OP_XOR | OP_POPCNT | OP_PRTY | OP_CMPB | OP_EXTS |
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when OP_AND | OP_OR | OP_XOR | OP_POPCNT | OP_PRTY | OP_CMPB | OP_EXTS |
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OP_BPERM | OP_BCD =>
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OP_BPERM | OP_BCD =>
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@ -912,52 +944,7 @@ begin
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v.busy := '1';
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v.busy := '1';
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when OP_ISEL =>
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when OP_ISEL =>
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when OP_CROP =>
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when OP_CROP =>
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cr_op := insn_cr(e_in.insn);
|
|
|
|
|
|
|
|
if cr_op(0) = '0' then -- MCRF
|
|
|
|
|
|
|
|
bf := insn_bf(e_in.insn);
|
|
|
|
|
|
|
|
bfa := insn_bfa(e_in.insn);
|
|
|
|
|
|
|
|
crnum := to_integer(unsigned(bf));
|
|
|
|
|
|
|
|
scrnum := to_integer(unsigned(bfa));
|
|
|
|
|
|
|
|
v.e.write_cr_mask := num_to_fxm(crnum);
|
|
|
|
|
|
|
|
for i in 0 to 7 loop
|
|
|
|
|
|
|
|
lo := (7-i)*4;
|
|
|
|
|
|
|
|
hi := lo + 3;
|
|
|
|
|
|
|
|
if i = scrnum then
|
|
|
|
|
|
|
|
newcrf := cr_in(hi downto lo);
|
|
|
|
|
|
|
|
end if;
|
|
|
|
|
|
|
|
end loop;
|
|
|
|
|
|
|
|
for i in 0 to 7 loop
|
|
|
|
|
|
|
|
lo := i*4;
|
|
|
|
|
|
|
|
hi := lo + 3;
|
|
|
|
|
|
|
|
v.e.write_cr_data(hi downto lo) := newcrf;
|
|
|
|
|
|
|
|
end loop;
|
|
|
|
|
|
|
|
else
|
|
|
|
|
|
|
|
bt := insn_bt(e_in.insn);
|
|
|
|
|
|
|
|
ba := insn_ba(e_in.insn);
|
|
|
|
|
|
|
|
bb := insn_bb(e_in.insn);
|
|
|
|
|
|
|
|
btnum := 31 - to_integer(unsigned(bt));
|
|
|
|
|
|
|
|
banum := 31 - to_integer(unsigned(ba));
|
|
|
|
|
|
|
|
bbnum := 31 - to_integer(unsigned(bb));
|
|
|
|
|
|
|
|
-- Bits 5-8 of cr_op give the truth table of the requested
|
|
|
|
|
|
|
|
-- logical operation
|
|
|
|
|
|
|
|
cr_operands := cr_in(banum) & cr_in(bbnum);
|
|
|
|
|
|
|
|
crresult := cr_op(5 + to_integer(unsigned(cr_operands)));
|
|
|
|
|
|
|
|
v.e.write_cr_mask := num_to_fxm((31-btnum) / 4);
|
|
|
|
|
|
|
|
for i in 0 to 31 loop
|
|
|
|
|
|
|
|
if i = btnum then
|
|
|
|
|
|
|
|
v.e.write_cr_data(i) := crresult;
|
|
|
|
|
|
|
|
else
|
|
|
|
|
|
|
|
v.e.write_cr_data(i) := cr_in(i);
|
|
|
|
|
|
|
|
end if;
|
|
|
|
|
|
|
|
end loop;
|
|
|
|
|
|
|
|
end if;
|
|
|
|
|
|
|
|
when OP_MCRXRX =>
|
|
|
|
when OP_MCRXRX =>
|
|
|
|
newcrf := xerc_in.ov & xerc_in.ca & xerc_in.ov32 & xerc_in.ca32;
|
|
|
|
|
|
|
|
bf := insn_bf(e_in.insn);
|
|
|
|
|
|
|
|
crnum := to_integer(unsigned(bf));
|
|
|
|
|
|
|
|
v.e.write_cr_mask := num_to_fxm(crnum);
|
|
|
|
|
|
|
|
v.e.write_cr_data := newcrf & newcrf & newcrf & newcrf &
|
|
|
|
|
|
|
|
newcrf & newcrf & newcrf & newcrf;
|
|
|
|
|
|
|
|
when OP_DARN =>
|
|
|
|
when OP_DARN =>
|
|
|
|
when OP_MFMSR =>
|
|
|
|
when OP_MFMSR =>
|
|
|
|
when OP_MFSPR =>
|
|
|
|
when OP_MFSPR =>
|
|
|
@ -1007,15 +994,6 @@ begin
|
|
|
|
|
|
|
|
|
|
|
|
when OP_MFCR =>
|
|
|
|
when OP_MFCR =>
|
|
|
|
when OP_MTCRF =>
|
|
|
|
when OP_MTCRF =>
|
|
|
|
if e_in.insn(20) = '0' then
|
|
|
|
|
|
|
|
-- mtcrf
|
|
|
|
|
|
|
|
v.e.write_cr_mask := insn_fxm(e_in.insn);
|
|
|
|
|
|
|
|
else
|
|
|
|
|
|
|
|
-- mtocrf: We require one hot priority encoding here
|
|
|
|
|
|
|
|
crnum := fxm_to_num(insn_fxm(e_in.insn));
|
|
|
|
|
|
|
|
v.e.write_cr_mask := num_to_fxm(crnum);
|
|
|
|
|
|
|
|
end if;
|
|
|
|
|
|
|
|
v.e.write_cr_data := c_in(31 downto 0);
|
|
|
|
|
|
|
|
when OP_MTMSRD =>
|
|
|
|
when OP_MTMSRD =>
|
|
|
|
if e_in.insn(16) = '1' then
|
|
|
|
if e_in.insn(16) = '1' then
|
|
|
|
-- just update EE and RI
|
|
|
|
-- just update EE and RI
|
|
|
@ -1050,7 +1028,6 @@ begin
|
|
|
|
v.e.xerc.ca := c_in(63-34);
|
|
|
|
v.e.xerc.ca := c_in(63-34);
|
|
|
|
v.e.xerc.ov32 := c_in(63-44);
|
|
|
|
v.e.xerc.ov32 := c_in(63-44);
|
|
|
|
v.e.xerc.ca32 := c_in(63-45);
|
|
|
|
v.e.xerc.ca32 := c_in(63-45);
|
|
|
|
v.e.write_xerc_enable := '1';
|
|
|
|
|
|
|
|
end if;
|
|
|
|
end if;
|
|
|
|
else
|
|
|
|
else
|
|
|
|
-- slow spr
|
|
|
|
-- slow spr
|
|
|
@ -1170,7 +1147,6 @@ begin
|
|
|
|
v.mul_finish := '1';
|
|
|
|
v.mul_finish := '1';
|
|
|
|
v.busy := '1';
|
|
|
|
v.busy := '1';
|
|
|
|
else
|
|
|
|
else
|
|
|
|
v.e.write_xerc_enable := current.oe;
|
|
|
|
|
|
|
|
-- We must test oe because the RC update code in writeback
|
|
|
|
-- We must test oe because the RC update code in writeback
|
|
|
|
-- will use the xerc value to set CR0:SO so we must not clobber
|
|
|
|
-- will use the xerc value to set CR0:SO so we must not clobber
|
|
|
|
-- xerc if OE wasn't set.
|
|
|
|
-- xerc if OE wasn't set.
|
|
|
@ -1190,7 +1166,6 @@ begin
|
|
|
|
end if;
|
|
|
|
end if;
|
|
|
|
elsif r.mul_finish = '1' then
|
|
|
|
elsif r.mul_finish = '1' then
|
|
|
|
hold_wr_data := '1';
|
|
|
|
hold_wr_data := '1';
|
|
|
|
v.e.write_xerc_enable := current.oe;
|
|
|
|
|
|
|
|
v.e.xerc.ov := multiply_to_x.overflow;
|
|
|
|
v.e.xerc.ov := multiply_to_x.overflow;
|
|
|
|
v.e.xerc.ov32 := multiply_to_x.overflow;
|
|
|
|
v.e.xerc.ov32 := multiply_to_x.overflow;
|
|
|
|
if multiply_to_x.overflow = '1' then
|
|
|
|
if multiply_to_x.overflow = '1' then
|
|
|
@ -1268,8 +1243,11 @@ begin
|
|
|
|
end if;
|
|
|
|
end if;
|
|
|
|
v.e.write_reg := current.write_reg;
|
|
|
|
v.e.write_reg := current.write_reg;
|
|
|
|
v.e.write_enable := current.write_reg_enable and v.e.valid and not exception;
|
|
|
|
v.e.write_enable := current.write_reg_enable and v.e.valid and not exception;
|
|
|
|
v.e.write_cr_enable := current.output_cr and v.e.valid and not exception;
|
|
|
|
|
|
|
|
v.e.rc := current.rc and v.e.valid and not exception;
|
|
|
|
v.e.rc := current.rc and v.e.valid and not exception;
|
|
|
|
|
|
|
|
v.e.write_cr_data := write_cr_data;
|
|
|
|
|
|
|
|
v.e.write_cr_mask := write_cr_mask;
|
|
|
|
|
|
|
|
v.e.write_cr_enable := current.output_cr and v.e.valid and not exception;
|
|
|
|
|
|
|
|
v.e.write_xerc_enable := current.output_xer and v.e.valid and not exception;
|
|
|
|
|
|
|
|
|
|
|
|
bypass_data.tag.valid <= current.instr_tag.valid and current.write_reg_enable and v.e.valid;
|
|
|
|
bypass_data.tag.valid <= current.instr_tag.valid and current.write_reg_enable and v.e.valid;
|
|
|
|
bypass_data.tag.tag <= current.instr_tag.tag;
|
|
|
|
bypass_data.tag.tag <= current.instr_tag.tag;
|
|
|
|