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@ -146,6 +146,7 @@ architecture behaviour of fpu is
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exp_cmp : std_ulogic;
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madd_cmp : std_ulogic;
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add_bsmall : std_ulogic;
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is_arith : std_ulogic;
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is_addition : std_ulogic;
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is_multiply : std_ulogic;
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is_inverse : std_ulogic;
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@ -176,6 +177,7 @@ architecture behaviour of fpu is
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res_sign : std_ulogic;
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res_int : std_ulogic;
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exec_state : state_t;
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cycle_1 : std_ulogic;
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end record;
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type lookup_table is array(0 to 1023) of std_ulogic_vector(17 downto 0);
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@ -880,6 +882,7 @@ begin
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is_nan_inf := '0';
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is_zero_den := '0';
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sign_inv := '0';
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v.cycle_1 := e_in.valid;
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if r.complete = '1' or r.do_intr = '1' then
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v.instr_done := '0';
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@ -925,6 +928,7 @@ begin
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v.negate := '0';
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v.quieten_nan := '1';
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v.int_result := '0';
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v.is_arith := '0';
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case e_in.op is
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when OP_FP_ARITH =>
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fpin_a := e_in.valid_a;
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@ -932,6 +936,7 @@ begin
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fpin_c := e_in.valid_c;
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v.longmask := e_in.single;
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v.fp_rc := e_in.rc;
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v.is_arith := '1';
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exec_state := arith_decode(to_integer(unsigned(e_in.insn(5 downto 1))));
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if e_in.insn(5 downto 1) = "10110" or e_in.insn(5 downto 1) = "11010" then
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v.is_sqrt := '1';
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@ -1193,6 +1198,11 @@ begin
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rsgn_op := RSGN_NOP;
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if r.cycle_1 = '1' and r.is_arith = '1' then
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v.fpscr(FPSCR_FR) := '0';
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v.fpscr(FPSCR_FI) := '0';
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end if;
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case r.state is
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when IDLE =>
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v.invalid := '0';
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@ -1218,8 +1228,6 @@ begin
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when DO_NAN_INF =>
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-- At least one floating-point operand is infinity or NaN
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v.fpscr(FPSCR_FR) := '0';
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v.fpscr(FPSCR_FI) := '0';
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invalid_mul := '0';
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if (r.a.class = NAN and r.a.mantissa(QNAN_BIT) = '0') or
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@ -1285,8 +1293,6 @@ begin
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when DO_ZERO_DEN =>
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-- At least one floating point operand is zero or denormalized
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v.fpscr(FPSCR_FR) := '0';
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v.fpscr(FPSCR_FI) := '0';
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if (r.use_a = '1' and r.a.class = ZERO) or
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(r.use_b = '1' and r.b.class = ZERO and r.is_multiply = '0') or
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(r.use_c = '1' and r.c.class = ZERO) then
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@ -1559,8 +1565,6 @@ begin
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rs_sel1 <= RSH1_B;
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rs_con2 <= RSCON2_52;
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rs_neg2 <= '1';
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v.fpscr(FPSCR_FR) := '0';
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v.fpscr(FPSCR_FI) := '0';
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if r.b.exponent >= to_signed(52, EXP_BITS) then
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-- integer already, no rounding required
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arith_done := '1';
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@ -1577,8 +1581,6 @@ begin
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rs_sel1 <= RSH1_B;
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rs_con2 <= RSCON2_MINEXP;
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rs_neg2 <= '1';
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v.fpscr(FPSCR_FR) := '0';
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v.fpscr(FPSCR_FI) := '0';
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set_x := '1';
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if r.b.exponent < to_signed(-126, EXP_BITS) then
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v.state := ROUND_UFLOW;
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@ -1598,8 +1600,6 @@ begin
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re_set_result <= '1';
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rs_sel1 <= RSH1_B;
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rs_neg2 <= '1';
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v.fpscr(FPSCR_FR) := '0';
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v.fpscr(FPSCR_FI) := '0';
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if r.b.exponent >= to_signed(64, EXP_BITS) or
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(r.insn(9) = '0' and r.b.exponent >= to_signed(32, EXP_BITS)) then
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@ -1630,8 +1630,6 @@ begin
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v.result_class := r.b.class;
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re_con2 <= RECON2_UNIT;
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re_set_result <= '1';
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v.fpscr(FPSCR_FR) := '0';
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v.fpscr(FPSCR_FI) := '0';
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if r.b.class = ZERO then
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arith_done := '1';
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else
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@ -1648,8 +1646,6 @@ begin
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rs_sel1 <= RSH1_B;
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rs_neg1 <= '1';
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rs_sel2 <= RSH2_A;
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v.fpscr(FPSCR_FR) := '0';
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v.fpscr(FPSCR_FI) := '0';
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v.add_bsmall := r.exp_cmp;
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v.opsel_a := AIN_B;
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if r.exp_cmp = '0' then
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@ -1667,8 +1663,6 @@ begin
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-- fmul[s]
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-- r.opsel_a = AIN_A unless C is denorm and A isn't
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v.result_class := r.a.class;
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v.fpscr(FPSCR_FR) := '0';
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v.fpscr(FPSCR_FI) := '0';
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re_sel1 <= REXP1_A;
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re_sel2 <= REXP2_C;
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re_set_result <= '1';
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@ -1685,8 +1679,6 @@ begin
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when DO_FDIV =>
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-- r.opsel_a = AIN_A unless B is denorm and A isn't
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v.result_class := r.a.class;
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v.fpscr(FPSCR_FR) := '0';
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v.fpscr(FPSCR_FI) := '0';
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re_sel1 <= REXP1_A;
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re_sel2 <= REXP2_B;
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re_neg2 <= '1';
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@ -1714,8 +1706,6 @@ begin
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when DO_FSQRT =>
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-- r.opsel_a = AIN_B
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v.result_class := r.b.class;
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v.fpscr(FPSCR_FR) := '0';
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v.fpscr(FPSCR_FI) := '0';
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re_sel2 <= REXP2_B;
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re_set_result <= '1';
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if r.b.negative = '1' then
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@ -1734,8 +1724,6 @@ begin
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when DO_FRE =>
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-- r.opsel_a = AIN_B
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v.result_class := r.b.class;
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v.fpscr(FPSCR_FR) := '0';
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v.fpscr(FPSCR_FI) := '0';
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re_sel2 <= REXP2_B;
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re_set_result <= '1';
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if r.b.mantissa(UNIT_BIT) = '0' then
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@ -1747,8 +1735,6 @@ begin
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when DO_FRSQRTE =>
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-- r.opsel_a = AIN_B
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v.result_class := r.b.class;
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v.fpscr(FPSCR_FR) := '0';
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v.fpscr(FPSCR_FI) := '0';
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re_sel2 <= REXP2_B;
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re_set_result <= '1';
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-- set shift to 1
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@ -1775,8 +1761,6 @@ begin
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re_set_result <= '1';
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-- put b.exp into shift
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rs_sel1 <= RSH1_B;
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v.fpscr(FPSCR_FR) := '0';
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v.fpscr(FPSCR_FI) := '0';
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-- Make sure A and C are normalized
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if r.a.mantissa(UNIT_BIT) = '0' then
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v.state := RENORM_A;
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