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Reformat register file

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Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
pull/64/head
Anton Blanchard 5 years ago committed by Anton Blanchard
parent 550b2b8608
commit 4d9b2a1165
1 changed files with 50 additions and 50 deletions
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100
register_file.vhdl
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@ -6,64 +6,64 @@ library work;
use work.common.all; use work.common.all;


entity register_file is entity register_file is
port( port(
clk : in std_logic; clk : in std_logic;


d_in : in Decode2ToRegisterFileType; d_in : in Decode2ToRegisterFileType;
d_out : out RegisterFileToDecode2Type; d_out : out RegisterFileToDecode2Type;


w_in : in WritebackToRegisterFileType; w_in : in WritebackToRegisterFileType;


-- debug -- debug
registers_out : out regfile registers_out : out regfile
); );
end entity register_file; end entity register_file;


architecture behaviour of register_file is architecture behaviour of register_file is
signal registers : regfile := (others => (others => '0')); signal registers : regfile := (others => (others => '0'));
begin begin
-- synchronous writes -- synchronous writes
register_write_0: process(clk) register_write_0: process(clk)
begin begin
if rising_edge(clk) then if rising_edge(clk) then
if w_in.write_enable = '1' then if w_in.write_enable = '1' then
assert not(is_x(w_in.write_data)) and not(is_x(w_in.write_reg)) severity failure; assert not(is_x(w_in.write_data)) and not(is_x(w_in.write_reg)) severity failure;
report "Writing GPR " & to_hstring(w_in.write_reg) & " " & to_hstring(w_in.write_data); report "Writing GPR " & to_hstring(w_in.write_reg) & " " & to_hstring(w_in.write_data);
registers(to_integer(unsigned(w_in.write_reg))) <= w_in.write_data; registers(to_integer(unsigned(w_in.write_reg))) <= w_in.write_data;
end if; end if;
end if; end if;
end process register_write_0; end process register_write_0;


-- asynchronous reads -- asynchronous reads
register_read_0: process(all) register_read_0: process(all)
begin begin
if d_in.read1_enable = '1' then if d_in.read1_enable = '1' then
report "Reading GPR " & to_hstring(d_in.read1_reg) & " " & to_hstring(registers(to_integer(unsigned(d_in.read1_reg)))); report "Reading GPR " & to_hstring(d_in.read1_reg) & " " & to_hstring(registers(to_integer(unsigned(d_in.read1_reg))));
end if; end if;
if d_in.read2_enable = '1' then if d_in.read2_enable = '1' then
report "Reading GPR " & to_hstring(d_in.read2_reg) & " " & to_hstring(registers(to_integer(unsigned(d_in.read2_reg)))); report "Reading GPR " & to_hstring(d_in.read2_reg) & " " & to_hstring(registers(to_integer(unsigned(d_in.read2_reg))));
end if; end if;
if d_in.read3_enable = '1' then if d_in.read3_enable = '1' then
report "Reading GPR " & to_hstring(d_in.read3_reg) & " " & to_hstring(registers(to_integer(unsigned(d_in.read3_reg)))); report "Reading GPR " & to_hstring(d_in.read3_reg) & " " & to_hstring(registers(to_integer(unsigned(d_in.read3_reg))));
end if; end if;
d_out.read1_data <= registers(to_integer(unsigned(d_in.read1_reg))); d_out.read1_data <= registers(to_integer(unsigned(d_in.read1_reg)));
d_out.read2_data <= registers(to_integer(unsigned(d_in.read2_reg))); d_out.read2_data <= registers(to_integer(unsigned(d_in.read2_reg)));
d_out.read3_data <= registers(to_integer(unsigned(d_in.read3_reg))); d_out.read3_data <= registers(to_integer(unsigned(d_in.read3_reg)));


-- Forward any written data -- Forward any written data
if w_in.write_enable = '1' then if w_in.write_enable = '1' then
if d_in.read1_reg = w_in.write_reg then if d_in.read1_reg = w_in.write_reg then
d_out.read1_data <= w_in.write_data; d_out.read1_data <= w_in.write_data;
end if; end if;
if d_in.read2_reg = w_in.write_reg then if d_in.read2_reg = w_in.write_reg then
d_out.read2_data <= w_in.write_data; d_out.read2_data <= w_in.write_data;
end if; end if;
if d_in.read3_reg = w_in.write_reg then if d_in.read3_reg = w_in.write_reg then
d_out.read3_data <= w_in.write_data; d_out.read3_data <= w_in.write_data;
end if; end if;
end if; end if;
end process register_read_0; end process register_read_0;


-- debug -- debug
registers_out <= registers; registers_out <= registers;
end architecture behaviour; end architecture behaviour;

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