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@ -85,7 +85,7 @@ begin
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m_out.write_reg_data <= d2;
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m_out.write_reg_data <= d2;
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m_out.write_reg_nr <= v.multiply_pipeline(PIPELINE_DEPTH-1).write_reg;
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m_out.write_reg_nr <= v.multiply_pipeline(PIPELINE_DEPTH-1).write_reg;
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if v.multiply_pipeline(PIPELINE_DEPTH-1).valid then
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if v.multiply_pipeline(PIPELINE_DEPTH-1).valid = '1' then
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m_out.valid <= '1';
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m_out.valid <= '1';
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m_out.write_reg_enable <= '1';
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m_out.write_reg_enable <= '1';
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