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@ -22,6 +22,7 @@ architecture behaviour of divider is
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signal quot : std_ulogic_vector(63 downto 0);
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signal quot : std_ulogic_vector(63 downto 0);
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signal result : std_ulogic_vector(63 downto 0);
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signal result : std_ulogic_vector(63 downto 0);
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signal sresult : std_ulogic_vector(63 downto 0);
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signal sresult : std_ulogic_vector(63 downto 0);
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signal oresult : std_ulogic_vector(63 downto 0);
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signal qbit : std_ulogic;
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signal qbit : std_ulogic;
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signal running : std_ulogic;
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signal running : std_ulogic;
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signal signcheck : std_ulogic;
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signal signcheck : std_ulogic;
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@ -34,7 +35,9 @@ architecture behaviour of divider is
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signal rc : std_ulogic;
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signal rc : std_ulogic;
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signal write_reg : std_ulogic_vector(4 downto 0);
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signal write_reg : std_ulogic_vector(4 downto 0);
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signal overflow : std_ulogic;
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signal overflow : std_ulogic;
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signal ovf32 : std_ulogic;
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signal did_ovf : std_ulogic;
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signal did_ovf : std_ulogic;
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signal cr_data : std_ulogic_vector(2 downto 0);
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begin
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begin
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divider_0: process(clk)
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divider_0: process(clk)
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@ -64,6 +67,7 @@ begin
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count <= "1111111";
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count <= "1111111";
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running <= '1';
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running <= '1';
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overflow <= '0';
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overflow <= '0';
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ovf32 <= '0';
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signcheck <= d_in.is_signed and (d_in.dividend(63) or d_in.divisor(63));
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signcheck <= d_in.is_signed and (d_in.dividend(63) or d_in.divisor(63));
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elsif signcheck = '1' then
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elsif signcheck = '1' then
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signcheck <= '0';
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signcheck <= '0';
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@ -84,16 +88,19 @@ begin
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end if;
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end if;
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overflow <= quot(63);
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overflow <= quot(63);
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if dend(128) = '1' or unsigned(dend(127 downto 64)) >= div then
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if dend(128) = '1' or unsigned(dend(127 downto 64)) >= div then
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ovf32 <= ovf32 or quot(31);
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dend <= std_ulogic_vector(unsigned(dend(127 downto 64)) - div) &
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dend <= std_ulogic_vector(unsigned(dend(127 downto 64)) - div) &
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dend(63 downto 0) & '0';
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dend(63 downto 0) & '0';
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quot <= quot(62 downto 0) & '1';
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quot <= quot(62 downto 0) & '1';
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count <= count + 1;
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count <= count + 1;
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elsif dend(128 downto 57) = x"000000000000000000" and count(6 downto 3) /= "0111" then
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elsif dend(128 downto 57) = x"000000000000000000" and count(6 downto 3) /= "0111" then
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-- consume 8 bits of zeroes in one cycle
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-- consume 8 bits of zeroes in one cycle
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ovf32 <= or (ovf32 & quot(31 downto 24));
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dend <= dend(120 downto 0) & x"00";
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dend <= dend(120 downto 0) & x"00";
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quot <= quot(55 downto 0) & x"00";
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quot <= quot(55 downto 0) & x"00";
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count <= count + 8;
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count <= count + 8;
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else
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else
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ovf32 <= ovf32 or quot(31);
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dend <= dend(127 downto 0) & '0';
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dend <= dend(127 downto 0) & '0';
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quot <= quot(62 downto 0) & '0';
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quot <= quot(62 downto 0) & '0';
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count <= count + 1;
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count <= count + 1;
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@ -106,8 +113,8 @@ begin
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divider_1: process(all)
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divider_1: process(all)
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begin
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begin
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d_out <= DividerToWritebackInit;
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d_out.write_reg_nr <= write_reg;
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d_out.write_reg_nr <= write_reg;
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d_out.write_cr_mask <= num_to_fxm(0);
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if is_modulus = '1' then
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if is_modulus = '1' then
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result <= dend(128 downto 65);
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result <= dend(128 downto 65);
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@ -123,36 +130,43 @@ begin
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if is_32bit = '0' then
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if is_32bit = '0' then
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did_ovf <= overflow or (is_signed and (sresult(63) xor neg_result));
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did_ovf <= overflow or (is_signed and (sresult(63) xor neg_result));
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elsif is_signed = '1' then
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elsif is_signed = '1' then
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if overflow = '1' or
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if ovf32 = '1' or sresult(32) /= sresult(31) then
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(sresult(63 downto 31) /= x"00000000" & '0' and
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sresult(63 downto 31) /= x"ffffffff" & '1') then
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did_ovf <= '1';
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did_ovf <= '1';
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end if;
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end if;
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else
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else
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did_ovf <= overflow or (or (sresult(63 downto 32)));
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did_ovf <= ovf32;
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end if;
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end if;
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if did_ovf = '1' then
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if did_ovf = '1' then
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d_out.write_reg_data <= (others => '0');
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oresult <= (others => '0');
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elsif (is_32bit = '1') and (is_modulus = '0') then
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elsif (is_32bit = '1') and (is_modulus = '0') then
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-- 32-bit divisions set the top 32 bits of the result to 0
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-- 32-bit divisions set the top 32 bits of the result to 0
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d_out.write_reg_data <= x"00000000" & sresult(31 downto 0);
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oresult <= x"00000000" & sresult(31 downto 0);
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else
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else
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d_out.write_reg_data <= sresult;
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oresult <= sresult;
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end if;
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end if;
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if count = "1000000" then
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d_out.valid <= '1';
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d_out.write_reg_enable <= '1';
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if rc = '1' then
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d_out.write_cr_enable <= '1';
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d_out.write_cr_mask <= num_to_fxm(0);
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if (did_ovf = '1') or (or (sresult) = '0') then
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if (did_ovf = '1') or (or (sresult) = '0') then
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d_out.write_cr_data <= x"20000000";
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cr_data <= "001";
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elsif (sresult(63) = '1') and not ((is_32bit = '1') and (is_modulus = '0')) then
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elsif (sresult(63) = '1') and not ((is_32bit = '1') and (is_modulus = '0')) then
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d_out.write_cr_data <= x"80000000";
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cr_data <= "100";
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else
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else
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d_out.write_cr_data <= x"40000000";
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cr_data <= "010";
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end if;
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end if;
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end process;
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divider_out: process(clk)
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begin
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if rising_edge(clk) then
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d_out.write_reg_data <= oresult;
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d_out.write_cr_data <= cr_data & '0' & x"0000000";
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if count = "1000000" then
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d_out.valid <= '1';
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d_out.write_reg_enable <= '1';
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d_out.write_cr_enable <= rc;
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else
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d_out.valid <= '0';
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d_out.write_reg_enable <= '0';
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d_out.write_cr_enable <= '0';
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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