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@ -440,6 +440,10 @@ architecture behaviour of fpu is
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variable result: std_ulogic_vector(63 downto 0);
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variable result: std_ulogic_vector(63 downto 0);
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begin
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begin
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result := (others => '0');
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result := (others => '0');
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if is_X(shift) then
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result := (others => 'X');
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return result;
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end if;
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for i in 0 to 63 loop
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for i in 0 to 63 loop
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if i >= shift then
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if i >= shift then
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result(63 - i) := '1';
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result(63 - i) := '1';
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@ -643,7 +647,11 @@ begin
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addrhi := "00";
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addrhi := "00";
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end if;
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end if;
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addr := addrhi & r.b.mantissa(UNIT_BIT - 1 downto UNIT_BIT - 8);
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addr := addrhi & r.b.mantissa(UNIT_BIT - 1 downto UNIT_BIT - 8);
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inverse_est <= '1' & inverse_table(to_integer(unsigned(addr)));
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if is_X(addr) then
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inverse_est <= (others => 'X');
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else
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inverse_est <= '1' & inverse_table(to_integer(unsigned(addr)));
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end if;
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end if;
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end if;
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end process;
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end process;
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@ -841,10 +849,14 @@ begin
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new_exp := r.result_exp - r.shift;
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new_exp := r.result_exp - r.shift;
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exp_tiny := '0';
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exp_tiny := '0';
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exp_huge := '0';
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exp_huge := '0';
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if new_exp < min_exp then
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if is_X(new_exp) or is_X(min_exp) then
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exp_tiny := 'X';
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elsif new_exp < min_exp then
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exp_tiny := '1';
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exp_tiny := '1';
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end if;
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end if;
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if new_exp > max_exp then
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if is_X(new_exp) or is_X(min_exp) then
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exp_huge := 'X';
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elsif new_exp > max_exp then
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exp_huge := '1';
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exp_huge := '1';
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end if;
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end if;
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@ -855,7 +867,9 @@ begin
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pcmpb_eq := '1';
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pcmpb_eq := '1';
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end if;
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end if;
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pcmpb_lt := '0';
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pcmpb_lt := '0';
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if unsigned(r.p(59 downto 4)) < unsigned(r.b.mantissa(UNIT_BIT + 1 downto DP_RBIT)) then
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if is_X(r.p(59 downto 4)) or is_X(r.b.mantissa(55 downto 0)) then
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pcmpb_lt := 'X';
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elsif unsigned(r.p(59 downto 4)) < unsigned(r.b.mantissa(UNIT_BIT + 1 downto DP_RBIT)) then
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pcmpb_lt := '1';
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pcmpb_lt := '1';
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end if;
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end if;
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pcmpc_eq := '0';
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pcmpc_eq := '0';
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@ -863,7 +877,9 @@ begin
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pcmpc_eq := '1';
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pcmpc_eq := '1';
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end if;
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end if;
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pcmpc_lt := '0';
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pcmpc_lt := '0';
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if unsigned(r.p) < unsigned(r.c.mantissa) then
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if is_X(r.p) or is_X(r.c.mantissa) then
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pcmpc_lt := 'X';
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elsif unsigned(r.p) < unsigned(r.c.mantissa) then
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pcmpc_lt := '1';
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pcmpc_lt := '1';
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end if;
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end if;
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@ -3014,7 +3030,9 @@ begin
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else
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else
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mshift := r.shift;
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mshift := r.shift;
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end if;
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end if;
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if mshift < to_signed(-64, EXP_BITS) then
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if is_X(mshift) then
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mask := (others => 'X');
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elsif mshift < to_signed(-64, EXP_BITS) then
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mask := (others => '1');
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mask := (others => '1');
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elsif mshift >= to_signed(0, EXP_BITS) then
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elsif mshift >= to_signed(0, EXP_BITS) then
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mask := (others => '0');
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mask := (others => '0');
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@ -3060,7 +3078,9 @@ begin
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in_b0 := not in_b0;
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in_b0 := not in_b0;
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end if;
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end if;
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in_b <= in_b0;
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in_b <= in_b0;
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if r.shift >= to_signed(-64, EXP_BITS) and r.shift <= to_signed(63, EXP_BITS) then
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if is_X(r.shift) then
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shift_res := (others => 'X');
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elsif r.shift >= to_signed(-64, EXP_BITS) and r.shift <= to_signed(63, EXP_BITS) then
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shift_res := shifter_64(r.r(63 downto 1) & (shiftin0 or r.r(0)) &
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shift_res := shifter_64(r.r(63 downto 1) & (shiftin0 or r.r(0)) &
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(shiftin or r.s(55)) & r.s(54 downto 0),
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(shiftin or r.s(55)) & r.s(54 downto 0),
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std_ulogic_vector(r.shift(6 downto 0)));
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std_ulogic_vector(r.shift(6 downto 0)));
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@ -3224,7 +3244,9 @@ begin
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v.cr_mask := num_to_fxm(0);
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v.cr_mask := num_to_fxm(0);
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elsif r.is_cmp = '0' then
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elsif r.is_cmp = '0' then
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v.cr_mask := num_to_fxm(1);
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v.cr_mask := num_to_fxm(1);
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else
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elsif is_X(insn_bf(r.insn)) then
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v.cr_mask := (others => 'X');
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else
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v.cr_mask := num_to_fxm(to_integer(unsigned(insn_bf(r.insn))));
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v.cr_mask := num_to_fxm(to_integer(unsigned(insn_bf(r.insn))));
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end if;
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end if;
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v.writing_cr := r.is_cmp or r.rc;
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v.writing_cr := r.is_cmp or r.rc;
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