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@ -23,7 +23,7 @@ entity toplevel is
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LOG_LENGTH : natural := 0;
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UART_IS_16550 : boolean := true;
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HAS_UART1 : boolean := false;
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USE_LITESDCARD : boolean := false;
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USE_LITESDCARD : boolean := true;
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ICACHE_NUM_LINES : natural := 64;
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NGPIO : natural := 0
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);
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@ -57,6 +57,16 @@ entity toplevel is
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spi_flash_wp_n : inout std_ulogic;
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spi_flash_hold_n : inout std_ulogic;
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-- SD card wires
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sdcard_data : inout std_ulogic_vector(3 downto 0);
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sdcard_cmd : inout std_ulogic;
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sdcard_clk : out std_ulogic;
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sdcard_cd : in std_ulogic;
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sdcard_cmd_dir : out std_ulogic;
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sdcard_dat0_dir : out std_ulogic;
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sdcard_dat13_dir : out std_ulogic;
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sdcard_vsel : out std_ulogic;
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-- PMOD ports 0 - 7
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pmod0_0 : inout std_ulogic;
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pmod0_1 : inout std_ulogic;
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@ -156,6 +166,7 @@ architecture behaviour of toplevel is
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signal wb_ext_io_out : wb_io_slave_out;
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signal wb_ext_is_dram_csr : std_ulogic;
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signal wb_ext_is_dram_init : std_ulogic;
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signal wb_ext_is_sdcard : std_ulogic;
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-- DRAM main data wishbone connection
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signal wb_dram_in : wishbone_master_out;
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@ -164,6 +175,16 @@ architecture behaviour of toplevel is
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-- DRAM control wishbone connection
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signal wb_dram_ctrl_out : wb_io_slave_out := wb_io_slave_out_init;
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-- LiteSDCard connection
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signal ext_irq_sdcard : std_ulogic := '0';
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signal wb_sdcard_out : wb_io_slave_out := wb_io_slave_out_init;
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signal wb_sddma_out : wb_io_master_out := wb_io_master_out_init;
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signal wb_sddma_in : wb_io_slave_out;
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signal wb_sddma_nr : wb_io_master_out;
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signal wb_sddma_ir : wb_io_slave_out;
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-- for conversion from non-pipelined wishbone to pipelined
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signal wb_sddma_stb_sent : std_ulogic;
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-- SPI flash
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signal spi_sck : std_ulogic;
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signal spi_sck_ts : std_ulogic;
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@ -245,6 +266,9 @@ begin
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spi_flash_sdat_oe => spi_sdat_oe,
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spi_flash_sdat_i => spi_sdat_i,
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-- External interrupts
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ext_irq_sdcard => ext_irq_sdcard,
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-- DRAM wishbone
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wb_dram_in => wb_dram_in,
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wb_dram_out => wb_dram_out,
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@ -253,7 +277,12 @@ begin
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wb_ext_io_in => wb_ext_io_in,
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wb_ext_io_out => wb_ext_io_out,
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wb_ext_is_dram_csr => wb_ext_is_dram_csr,
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wb_ext_is_dram_init => wb_ext_is_dram_init
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wb_ext_is_dram_init => wb_ext_is_dram_init,
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wb_ext_is_sdcard => wb_ext_is_sdcard,
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-- DMA wishbone
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wishbone_dma_in => wb_sddma_in,
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wishbone_dma_out => wb_sddma_out
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);
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-- SPI Flash
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@ -391,8 +420,125 @@ begin
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led8_g_n <= not (dram_init_done and not dram_init_error);
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end generate;
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-- SD card
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-- The ECPIX-5 has a buffer/level translator chip in order to be able to
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-- support 1.8V signalling to the SD card as well as 3V signalling.
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-- Litesdcard doesn't currently support voltage selection, or the higher
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-- data transfer rates that require the lower voltage.
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has_sdcard : if USE_LITESDCARD generate
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component litesdcard_core port (
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clk : in std_ulogic;
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rst : in std_ulogic;
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irq : out std_ulogic;
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-- wishbone for accessing control registers
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wb_ctrl_adr : in std_ulogic_vector(29 downto 0);
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wb_ctrl_dat_w : in std_ulogic_vector(31 downto 0);
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wb_ctrl_dat_r : out std_ulogic_vector(31 downto 0);
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wb_ctrl_sel : in std_ulogic_vector(3 downto 0);
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wb_ctrl_cyc : in std_ulogic;
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wb_ctrl_stb : in std_ulogic;
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wb_ctrl_ack : out std_ulogic;
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wb_ctrl_we : in std_ulogic;
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wb_ctrl_cti : in std_ulogic_vector(2 downto 0);
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wb_ctrl_bte : in std_ulogic_vector(1 downto 0);
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wb_ctrl_err : out std_ulogic;
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-- wishbone for SD card core to use for DMA
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wb_dma_adr : out std_ulogic_vector(29 downto 0);
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wb_dma_dat_w : out std_ulogic_vector(31 downto 0);
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wb_dma_dat_r : in std_ulogic_vector(31 downto 0);
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wb_dma_sel : out std_ulogic_vector(3 downto 0);
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wb_dma_cyc : out std_ulogic;
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wb_dma_stb : out std_ulogic;
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wb_dma_ack : in std_ulogic;
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wb_dma_we : out std_ulogic;
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wb_dma_cti : out std_ulogic_vector(2 downto 0);
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wb_dma_bte : out std_ulogic_vector(1 downto 0);
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wb_dma_err : in std_ulogic;
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-- connections to SD card
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sdcard_data : inout std_ulogic_vector(3 downto 0);
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sdcard_cmd : inout std_ulogic;
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sdcard_clk : out std_ulogic;
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sdcard_cd : in std_ulogic;
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sdcard_cmd_dir : out std_ulogic;
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sdcard_dat0_dir : out std_ulogic;
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sdcard_dat13_dir : out std_ulogic
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);
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end component;
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signal wb_sdcard_cyc : std_ulogic;
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signal wb_sdcard_adr : std_ulogic_vector(29 downto 0);
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begin
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litesdcard : litesdcard_core
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port map (
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clk => system_clk,
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rst => soc_rst,
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irq => ext_irq_sdcard,
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wb_ctrl_adr => wb_sdcard_adr,
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wb_ctrl_dat_w => wb_ext_io_in.dat,
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wb_ctrl_dat_r => wb_sdcard_out.dat,
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wb_ctrl_sel => wb_ext_io_in.sel,
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wb_ctrl_cyc => wb_sdcard_cyc,
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wb_ctrl_stb => wb_ext_io_in.stb,
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wb_ctrl_ack => wb_sdcard_out.ack,
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wb_ctrl_we => wb_ext_io_in.we,
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wb_ctrl_cti => "000",
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wb_ctrl_bte => "00",
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wb_ctrl_err => open,
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wb_dma_adr => wb_sddma_nr.adr,
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wb_dma_dat_w => wb_sddma_nr.dat,
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wb_dma_dat_r => wb_sddma_ir.dat,
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wb_dma_sel => wb_sddma_nr.sel,
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wb_dma_cyc => wb_sddma_nr.cyc,
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wb_dma_stb => wb_sddma_nr.stb,
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wb_dma_ack => wb_sddma_ir.ack,
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wb_dma_we => wb_sddma_nr.we,
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wb_dma_cti => open,
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wb_dma_bte => open,
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wb_dma_err => '0',
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sdcard_data => sdcard_data,
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sdcard_cmd => sdcard_cmd,
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sdcard_clk => sdcard_clk,
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sdcard_cd => sdcard_cd,
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sdcard_cmd_dir => sdcard_cmd_dir,
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sdcard_dat0_dir => sdcard_dat0_dir,
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sdcard_dat13_dir => sdcard_dat13_dir
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);
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-- Select 3V signalling
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sdcard_vsel <= '0';
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-- Gate cyc with chip select from SoC
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wb_sdcard_cyc <= wb_ext_io_in.cyc and wb_ext_is_sdcard;
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wb_sdcard_adr <= x"0000" & wb_ext_io_in.adr(13 downto 0);
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wb_sdcard_out.stall <= not wb_sdcard_out.ack;
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-- Convert non-pipelined DMA wishbone to pipelined by suppressing
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-- non-acknowledged strobes
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process(system_clk)
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begin
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if rising_edge(system_clk) then
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wb_sddma_out <= wb_sddma_nr;
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if wb_sddma_stb_sent = '1' or
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(wb_sddma_out.stb = '1' and wb_sddma_in.stall = '0') then
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wb_sddma_out.stb <= '0';
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end if;
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if wb_sddma_nr.cyc = '0' or wb_sddma_ir.ack = '1' then
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wb_sddma_stb_sent <= '0';
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elsif wb_sddma_in.stall = '0' then
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wb_sddma_stb_sent <= wb_sddma_nr.stb;
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end if;
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wb_sddma_ir <= wb_sddma_in;
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end if;
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end process;
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end generate;
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-- Mux WB response on the IO bus
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wb_ext_io_out <= wb_dram_ctrl_out;
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wb_ext_io_out <= wb_sdcard_out when wb_ext_is_sdcard = '1' else
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wb_dram_ctrl_out;
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led5_r_n <= '1';
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led5_g_n <= '1';
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