diff --git a/Makefile b/Makefile index de56913..aae24f0 100644 --- a/Makefile +++ b/Makefile @@ -227,6 +227,7 @@ OPENOCD_JTAG_CONFIG=openocd/ecpix-5.cfg OPENOCD_DEVICE_CONFIG=openocd/LFE5UM5G-85F.cfg toplevel=fpga/top-ecpix5.vhdl litedram_target=ecpix-5 +soc_extra_v += litesdcard/generated/lattice.50e6/litesdcard_core.v dmi_dtm=dmi_dtm_ecp5.vhdl endif diff --git a/constraints/ecpix-5.lpf b/constraints/ecpix-5.lpf index e215fbe..4681dee 100644 --- a/constraints/ecpix-5.lpf +++ b/constraints/ecpix-5.lpf @@ -58,6 +58,31 @@ IOBUF PORT "spi_flash_wp_n" IO_TYPE=LVCMOS33; LOCATE COMP "spi_flash_hold_n" SITE "AE1"; IOBUF PORT "spi_flash_hold_n" IO_TYPE=LVCMOS33; +// SD card slot and level translator +LOCATE COMP "sdcard_data[0]" SITE "N26"; +LOCATE COMP "sdcard_data[1]" SITE "N25"; +LOCATE COMP "sdcard_data[2]" SITE "N23"; +LOCATE COMP "sdcard_data[3]" SITE "N21"; +LOCATE COMP "sdcard_cmd" SITE "M24"; +LOCATE COMP "sdcard_clk" SITE "P24"; +LOCATE COMP "sdcard_cd" SITE "L22"; +LOCATE COMP "sdcard_cmd_dir" SITE "M23"; +LOCATE COMP "sdcard_dat0_dir" SITE "N24"; +LOCATE COMP "sdcard_dat13_dir" SITE "P26"; +LOCATE COMP "sdcard_vsel" SITE "L24"; + +IOBUF PORT "sdcard_data[0]" IO_TYPE=LVCMOS33 SLEWRATE=FAST PULLMODE=UP; +IOBUF PORT "sdcard_data[1]" IO_TYPE=LVCMOS33 SLEWRATE=FAST PULLMODE=UP; +IOBUF PORT "sdcard_data[2]" IO_TYPE=LVCMOS33 SLEWRATE=FAST PULLMODE=UP; +IOBUF PORT "sdcard_data[3]" IO_TYPE=LVCMOS33 SLEWRATE=FAST PULLMODE=UP; +IOBUF PORT "sdcard_cmd" IO_TYPE=LVCMOS33 SLEWRATE=FAST PULLMODE=UP; +IOBUF PORT "sdcard_clk" IO_TYPE=LVCMOS33 SLEWRATE=FAST; +IOBUF PORT "sdcard_cd" IO_TYPE=LVCMOS33; +IOBUF PORT "sdcard_cmd_dir" IO_TYPE=LVCMOS33 SLEWRATE=FAST PULLMODE=UP; +IOBUF PORT "sdcard_dat0_dir" IO_TYPE=LVCMOS33 SLEWRATE=FAST; +IOBUF PORT "sdcard_dat13_dir" IO_TYPE=LVCMOS33 SLEWRATE=FAST; +IOBUF PORT "sdcard_vsel" IO_TYPE=LVCMOS33 PULLMODE=DOWN; + // DDR3 SDRAM LOCATE COMP "ddram_a[0]" SITE "T5"; LOCATE COMP "ddram_a[1]" SITE "M3"; diff --git a/fpga/top-ecpix5.vhdl b/fpga/top-ecpix5.vhdl index 20a3a0a..7016067 100644 --- a/fpga/top-ecpix5.vhdl +++ b/fpga/top-ecpix5.vhdl @@ -23,7 +23,7 @@ entity toplevel is LOG_LENGTH : natural := 0; UART_IS_16550 : boolean := true; HAS_UART1 : boolean := false; - USE_LITESDCARD : boolean := false; + USE_LITESDCARD : boolean := true; ICACHE_NUM_LINES : natural := 64; NGPIO : natural := 0 ); @@ -57,6 +57,16 @@ entity toplevel is spi_flash_wp_n : inout std_ulogic; spi_flash_hold_n : inout std_ulogic; + -- SD card wires + sdcard_data : inout std_ulogic_vector(3 downto 0); + sdcard_cmd : inout std_ulogic; + sdcard_clk : out std_ulogic; + sdcard_cd : in std_ulogic; + sdcard_cmd_dir : out std_ulogic; + sdcard_dat0_dir : out std_ulogic; + sdcard_dat13_dir : out std_ulogic; + sdcard_vsel : out std_ulogic; + -- PMOD ports 0 - 7 pmod0_0 : inout std_ulogic; pmod0_1 : inout std_ulogic; @@ -156,6 +166,7 @@ architecture behaviour of toplevel is signal wb_ext_io_out : wb_io_slave_out; signal wb_ext_is_dram_csr : std_ulogic; signal wb_ext_is_dram_init : std_ulogic; + signal wb_ext_is_sdcard : std_ulogic; -- DRAM main data wishbone connection signal wb_dram_in : wishbone_master_out; @@ -164,6 +175,16 @@ architecture behaviour of toplevel is -- DRAM control wishbone connection signal wb_dram_ctrl_out : wb_io_slave_out := wb_io_slave_out_init; + -- LiteSDCard connection + signal ext_irq_sdcard : std_ulogic := '0'; + signal wb_sdcard_out : wb_io_slave_out := wb_io_slave_out_init; + signal wb_sddma_out : wb_io_master_out := wb_io_master_out_init; + signal wb_sddma_in : wb_io_slave_out; + signal wb_sddma_nr : wb_io_master_out; + signal wb_sddma_ir : wb_io_slave_out; + -- for conversion from non-pipelined wishbone to pipelined + signal wb_sddma_stb_sent : std_ulogic; + -- SPI flash signal spi_sck : std_ulogic; signal spi_sck_ts : std_ulogic; @@ -245,6 +266,9 @@ begin spi_flash_sdat_oe => spi_sdat_oe, spi_flash_sdat_i => spi_sdat_i, + -- External interrupts + ext_irq_sdcard => ext_irq_sdcard, + -- DRAM wishbone wb_dram_in => wb_dram_in, wb_dram_out => wb_dram_out, @@ -253,7 +277,12 @@ begin wb_ext_io_in => wb_ext_io_in, wb_ext_io_out => wb_ext_io_out, wb_ext_is_dram_csr => wb_ext_is_dram_csr, - wb_ext_is_dram_init => wb_ext_is_dram_init + wb_ext_is_dram_init => wb_ext_is_dram_init, + wb_ext_is_sdcard => wb_ext_is_sdcard, + + -- DMA wishbone + wishbone_dma_in => wb_sddma_in, + wishbone_dma_out => wb_sddma_out ); -- SPI Flash @@ -391,8 +420,125 @@ begin led8_g_n <= not (dram_init_done and not dram_init_error); end generate; + -- SD card + -- The ECPIX-5 has a buffer/level translator chip in order to be able to + -- support 1.8V signalling to the SD card as well as 3V signalling. + -- Litesdcard doesn't currently support voltage selection, or the higher + -- data transfer rates that require the lower voltage. + has_sdcard : if USE_LITESDCARD generate + component litesdcard_core port ( + clk : in std_ulogic; + rst : in std_ulogic; + irq : out std_ulogic; + -- wishbone for accessing control registers + wb_ctrl_adr : in std_ulogic_vector(29 downto 0); + wb_ctrl_dat_w : in std_ulogic_vector(31 downto 0); + wb_ctrl_dat_r : out std_ulogic_vector(31 downto 0); + wb_ctrl_sel : in std_ulogic_vector(3 downto 0); + wb_ctrl_cyc : in std_ulogic; + wb_ctrl_stb : in std_ulogic; + wb_ctrl_ack : out std_ulogic; + wb_ctrl_we : in std_ulogic; + wb_ctrl_cti : in std_ulogic_vector(2 downto 0); + wb_ctrl_bte : in std_ulogic_vector(1 downto 0); + wb_ctrl_err : out std_ulogic; + -- wishbone for SD card core to use for DMA + wb_dma_adr : out std_ulogic_vector(29 downto 0); + wb_dma_dat_w : out std_ulogic_vector(31 downto 0); + wb_dma_dat_r : in std_ulogic_vector(31 downto 0); + wb_dma_sel : out std_ulogic_vector(3 downto 0); + wb_dma_cyc : out std_ulogic; + wb_dma_stb : out std_ulogic; + wb_dma_ack : in std_ulogic; + wb_dma_we : out std_ulogic; + wb_dma_cti : out std_ulogic_vector(2 downto 0); + wb_dma_bte : out std_ulogic_vector(1 downto 0); + wb_dma_err : in std_ulogic; + -- connections to SD card + sdcard_data : inout std_ulogic_vector(3 downto 0); + sdcard_cmd : inout std_ulogic; + sdcard_clk : out std_ulogic; + sdcard_cd : in std_ulogic; + sdcard_cmd_dir : out std_ulogic; + sdcard_dat0_dir : out std_ulogic; + sdcard_dat13_dir : out std_ulogic + ); + end component; + + signal wb_sdcard_cyc : std_ulogic; + signal wb_sdcard_adr : std_ulogic_vector(29 downto 0); + + begin + litesdcard : litesdcard_core + port map ( + clk => system_clk, + rst => soc_rst, + irq => ext_irq_sdcard, + wb_ctrl_adr => wb_sdcard_adr, + wb_ctrl_dat_w => wb_ext_io_in.dat, + wb_ctrl_dat_r => wb_sdcard_out.dat, + wb_ctrl_sel => wb_ext_io_in.sel, + wb_ctrl_cyc => wb_sdcard_cyc, + wb_ctrl_stb => wb_ext_io_in.stb, + wb_ctrl_ack => wb_sdcard_out.ack, + wb_ctrl_we => wb_ext_io_in.we, + wb_ctrl_cti => "000", + wb_ctrl_bte => "00", + wb_ctrl_err => open, + wb_dma_adr => wb_sddma_nr.adr, + wb_dma_dat_w => wb_sddma_nr.dat, + wb_dma_dat_r => wb_sddma_ir.dat, + wb_dma_sel => wb_sddma_nr.sel, + wb_dma_cyc => wb_sddma_nr.cyc, + wb_dma_stb => wb_sddma_nr.stb, + wb_dma_ack => wb_sddma_ir.ack, + wb_dma_we => wb_sddma_nr.we, + wb_dma_cti => open, + wb_dma_bte => open, + wb_dma_err => '0', + sdcard_data => sdcard_data, + sdcard_cmd => sdcard_cmd, + sdcard_clk => sdcard_clk, + sdcard_cd => sdcard_cd, + sdcard_cmd_dir => sdcard_cmd_dir, + sdcard_dat0_dir => sdcard_dat0_dir, + sdcard_dat13_dir => sdcard_dat13_dir + ); + + -- Select 3V signalling + sdcard_vsel <= '0'; + + -- Gate cyc with chip select from SoC + wb_sdcard_cyc <= wb_ext_io_in.cyc and wb_ext_is_sdcard; + + wb_sdcard_adr <= x"0000" & wb_ext_io_in.adr(13 downto 0); + + wb_sdcard_out.stall <= not wb_sdcard_out.ack; + + -- Convert non-pipelined DMA wishbone to pipelined by suppressing + -- non-acknowledged strobes + process(system_clk) + begin + if rising_edge(system_clk) then + wb_sddma_out <= wb_sddma_nr; + if wb_sddma_stb_sent = '1' or + (wb_sddma_out.stb = '1' and wb_sddma_in.stall = '0') then + wb_sddma_out.stb <= '0'; + end if; + if wb_sddma_nr.cyc = '0' or wb_sddma_ir.ack = '1' then + wb_sddma_stb_sent <= '0'; + elsif wb_sddma_in.stall = '0' then + wb_sddma_stb_sent <= wb_sddma_nr.stb; + end if; + wb_sddma_ir <= wb_sddma_in; + end if; + end process; + + end generate; + -- Mux WB response on the IO bus - wb_ext_io_out <= wb_dram_ctrl_out; + wb_ext_io_out <= wb_sdcard_out when wb_ext_is_sdcard = '1' else + wb_dram_ctrl_out; led5_r_n <= '1'; led5_g_n <= '1'; diff --git a/litesdcard/gen-src/generate.sh b/litesdcard/gen-src/generate.sh index 291845e..9c629ff 100755 --- a/litesdcard/gen-src/generate.sh +++ b/litesdcard/gen-src/generate.sh @@ -1,7 +1,7 @@ #!/bin/bash # vendor:sysclk -VENDORS="xilinx:100e6 lattice:48e6" +VENDORS="xilinx:100e6 lattice:48e6 lattice:50e6" ME=$(realpath $0) echo ME=$ME diff --git a/litesdcard/generated/lattice.50e6/litesdcard_core.v b/litesdcard/generated/lattice.50e6/litesdcard_core.v new file mode 100644 index 0000000..7412820 --- /dev/null +++ b/litesdcard/generated/lattice.50e6/litesdcard_core.v @@ -0,0 +1,4679 @@ +// ----------------------------------------------------------------------------- +// Auto-Generated by: __ _ __ _ __ +// / / (_) /____ | |/_/ +// / /__/ / __/ -_)> < +// /____/_/\__/\__/_/|_| +// Build your hardware, easily! +// https://github.com/enjoy-digital/litex +// +// Filename : litesdcard_core.v +// Device : +// LiteX sha1 : 87137c30 +// Date : 2024-04-03 19:58:12 +//------------------------------------------------------------------------------ + +`timescale 1ns / 1ps + +//------------------------------------------------------------------------------ +// Module +//------------------------------------------------------------------------------ + +module litesdcard_core ( + input wire clk, + output wire irq, + input wire rst, + input wire sdcard_cd, + output wire sdcard_clk, + inout wire sdcard_cmd, + output wire sdcard_cmd_dir, + output wire sdcard_dat0_dir, + output wire sdcard_dat13_dir, + inout wire [3:0] sdcard_data, + output wire wb_ctrl_ack, + input wire [29:0] wb_ctrl_adr, + input wire [1:0] wb_ctrl_bte, + input wire [2:0] wb_ctrl_cti, + input wire wb_ctrl_cyc, + output wire [31:0] wb_ctrl_dat_r, + input wire [31:0] wb_ctrl_dat_w, + output wire wb_ctrl_err, + input wire [3:0] wb_ctrl_sel, + input wire wb_ctrl_stb, + input wire wb_ctrl_we, + input wire wb_dma_ack, + output wire [29:0] wb_dma_adr, + output wire [1:0] wb_dma_bte, + output wire [2:0] wb_dma_cti, + output wire wb_dma_cyc, + input wire [31:0] wb_dma_dat_r, + output wire [31:0] wb_dma_dat_w, + input wire wb_dma_err, + output wire [3:0] wb_dma_sel, + output wire wb_dma_stb, + output wire wb_dma_we +); + + +//------------------------------------------------------------------------------ +// Hierarchy +//------------------------------------------------------------------------------ + +/* +LiteSDCardCore +└─── crg (CRG) +└─── bus (SoCBusHandler) +│ └─── _interconnect (InterconnectPointToPoint) +└─── csr (SoCCSRHandler) +└─── irq (SoCIRQHandler) +└─── ctrl (SoCController) +└─── cpu (CPUNone) +└─── dma_bus (SoCBusHandler) +│ └─── _interconnect (InterconnectShared) +│ │ └─── arbiter (Arbiter) +│ │ │ └─── rr (RoundRobin) +│ │ └─── decoder (Decoder) +│ │ └─── timeout (Timeout) +│ │ │ └─── waittimer_0* (WaitTimer) +└─── sdcard_phy (SDPHY) +│ └─── clocker (SDPHYClocker) +│ └─── init (SDPHYInit) +│ │ └─── fsm_0* (FSM) +│ └─── cmdw (SDPHYCMDW) +│ │ └─── fsm_0* (FSM) +│ └─── cmdr (SDPHYCMDR) +│ │ └─── sdphyr_0* (SDPHYR) +│ │ │ └─── converter_0* (Converter) +│ │ │ │ └─── _upconverter_0* (_UpConverter) +│ │ │ └─── buffer_0* (Buffer) +│ │ │ │ └─── pipe_valid (PipeValid) +│ │ │ │ └─── pipeline (Pipeline) +│ │ └─── fsm_0* (FSM) +│ └─── dataw (SDPHYDATAW) +│ │ └─── crc (SDPHYR) +│ │ │ └─── converter_0* (Converter) +│ │ │ │ └─── _upconverter_0* (_UpConverter) +│ │ │ └─── buffer_0* (Buffer) +│ │ │ │ └─── pipe_valid (PipeValid) +│ │ │ │ └─── pipeline (Pipeline) +│ │ └─── fsm (FSM) +│ └─── datar (SDPHYDATAR) +│ │ └─── sdphyr_0* (SDPHYR) +│ │ │ └─── converter_0* (Converter) +│ │ │ │ └─── _upconverter_0* (_UpConverter) +│ │ │ └─── buffer_0* (Buffer) +│ │ │ │ └─── pipe_valid (PipeValid) +│ │ │ │ └─── pipeline (Pipeline) +│ │ └─── fsm_0* (FSM) +│ └─── io (SDPHYIOGen) +└─── sdcard_core (SDCore) +│ └─── crc7_inserter (CRC) +│ └─── crc16_inserter (CRC16Inserter) +│ │ └─── crc_0* (CRC) +│ │ └─── crc_1* (CRC) +│ │ └─── crc_2* (CRC) +│ │ └─── crc_3* (CRC) +│ │ └─── fsm (FSM) +│ └─── crc16_checker (CRC16Checker) +│ │ └─── syncfifo_0* (SyncFIFO) +│ │ │ └─── fifo (SyncFIFO) +│ └─── fsm (FSM) +└─── sdcard_block2mem (SDBlock2MemDMA) +│ └─── syncfifo_0* (SyncFIFO) +│ │ └─── fifo (SyncFIFOBuffered) +│ │ │ └─── fifo (SyncFIFO) +│ └─── converter_0* (Converter) +│ │ └─── _upconverter_0* (_UpConverter) +│ └─── dma (WishboneDMAWriter) +│ │ └─── fsm (FSM) +└─── sdcard_mem2block (SDMem2BlockDMA) +│ └─── dma (WishboneDMAReader) +│ │ └─── fifo (SyncFIFO) +│ │ │ └─── fifo (SyncFIFO) +│ │ └─── fsm (FSM) +│ └─── converter_0* (Converter) +│ │ └─── _downconverter_0* (_DownConverter) +│ └─── syncfifo_0* (SyncFIFO) +│ │ └─── fifo (SyncFIFOBuffered) +│ │ │ └─── fifo (SyncFIFO) +└─── sdcard_irq (EventManager) +│ └─── eventsourcepulse_0* (EventSourcePulse) +│ └─── eventsourcepulse_1* (EventSourcePulse) +│ └─── eventsourcepulse_2* (EventSourcePulse) +│ └─── eventsourcelevel_0* (EventSourceLevel) +└─── csr_bridge (Wishbone2CSR) +│ └─── fsm (FSM) +└─── csr_bankarray (CSRBankArray) +│ └─── csrbank_0* (CSRBank) +│ │ └─── csrstorage_0* (CSRStorage) +│ │ └─── csrstorage_1* (CSRStorage) +│ │ └─── csrstatus_0* (CSRStatus) +│ └─── csrbank_1* (CSRBank) +│ │ └─── csrstorage_0* (CSRStorage) +│ │ └─── csrstorage_1* (CSRStorage) +│ │ └─── csrstorage_2* (CSRStorage) +│ │ └─── csrstatus_0* (CSRStatus) +│ │ └─── csrstorage_3* (CSRStorage) +│ │ └─── csrstatus_1* (CSRStatus) +│ └─── csrbank_2* (CSRBank) +│ │ └─── csrstorage_0* (CSRStorage) +│ │ └─── csrstorage_1* (CSRStorage) +│ │ └─── csrstorage_2* (CSRStorage) +│ │ └─── csrstatus_0* (CSRStatus) +│ │ └─── csrstatus_1* (CSRStatus) +│ │ └─── csrstatus_2* (CSRStatus) +│ │ └─── csrstorage_3* (CSRStorage) +│ │ └─── csrstorage_4* (CSRStorage) +│ └─── csrbank_3* (CSRBank) +│ │ └─── csrstatus_0* (CSRStatus) +│ │ └─── csrstatus_1* (CSRStatus) +│ │ └─── csrstorage_0* (CSRStorage) +│ └─── csrbank_4* (CSRBank) +│ │ └─── csrstorage_0* (CSRStorage) +│ │ └─── csrstorage_1* (CSRStorage) +│ │ └─── csrstorage_2* (CSRStorage) +│ │ └─── csrstatus_0* (CSRStatus) +│ │ └─── csrstorage_3* (CSRStorage) +│ │ └─── csrstatus_1* (CSRStatus) +│ └─── csrbank_5* (CSRBank) +│ │ └─── csrstatus_0* (CSRStatus) +│ │ └─── csrstorage_0* (CSRStorage) +│ │ └─── csrstatus_1* (CSRStatus) +└─── csr_interconnect (InterconnectShared) +└─── [IFS1P3BX] +└─── [OFS1P3BX] +└─── [IFS1P3BX] +└─── [OFS1P3BX] +└─── [IFS1P3BX] +└─── [IFS1P3BX] +└─── [OFS1P3BX] +└─── [IFS1P3BX] +└─── [OFS1P3BX] +└─── [OFS1P3BX] +└─── [OFS1P3BX] +└─── [OFS1P3BX] +└─── [OFS1P3BX] +└─── [OFS1P3BX] +* : Generated name. +[]: BlackBox. +*/ + +//------------------------------------------------------------------------------ +// Signals +//------------------------------------------------------------------------------ + +wire [13:0] adr; +reg block2mem_dma_clear = 1'd0; +reg block2mem_dma_pending = 1'd0; +wire block2mem_dma_status; +wire block2mem_dma_trigger; +reg bus_error = 1'd0; +reg [31:0] bus_errors = 32'd0; +reg bus_errors_re = 1'd0; +wire [31:0] bus_errors_status; +wire bus_errors_we; +reg card_detect_clear = 1'd0; +reg card_detect_d = 1'd0; +reg card_detect_irq = 1'd0; +reg card_detect_pending = 1'd0; +reg card_detect_re = 1'd0; +wire card_detect_status0; +wire card_detect_status1; +wire card_detect_trigger; +wire card_detect_we; +wire clocker_ce; +reg clocker_ce_delayed = 1'd0; +reg clocker_ce_latched = 1'd0; +wire clocker_clk0; +reg clocker_clk1 = 1'd0; +reg clocker_clk_d = 1'd0; +reg [1:0] clocker_clk_delay = 2'd0; +wire clocker_clk_en; +reg [8:0] clocker_clks = 9'd0; +reg clocker_re = 1'd0; +wire clocker_stop; +reg [8:0] clocker_storage = 9'd256; +reg cmd_done_clear = 1'd0; +wire cmd_done_pending; +wire cmd_done_status; +wire cmd_done_trigger; +reg cmdr_busy = 1'd0; +reg cmdr_busy_sdphycmdr_next_value2 = 1'd0; +reg cmdr_busy_sdphycmdr_next_value_ce2 = 1'd0; +wire cmdr_cmdr_buf_pipe_valid_sink_first; +wire cmdr_cmdr_buf_pipe_valid_sink_last; +wire [7:0] cmdr_cmdr_buf_pipe_valid_sink_payload_data; +wire cmdr_cmdr_buf_pipe_valid_sink_ready; +wire cmdr_cmdr_buf_pipe_valid_sink_valid; +reg cmdr_cmdr_buf_pipe_valid_source_first = 1'd0; +reg cmdr_cmdr_buf_pipe_valid_source_last = 1'd0; +reg [7:0] cmdr_cmdr_buf_pipe_valid_source_payload_data = 8'd0; +wire cmdr_cmdr_buf_pipe_valid_source_ready; +reg cmdr_cmdr_buf_pipe_valid_source_valid = 1'd0; +wire cmdr_cmdr_buf_sink_sink_first; +wire cmdr_cmdr_buf_sink_sink_last; +wire [7:0] cmdr_cmdr_buf_sink_sink_payload_data; +wire cmdr_cmdr_buf_sink_sink_ready; +wire cmdr_cmdr_buf_sink_sink_valid; +wire cmdr_cmdr_buf_source_source_first; +wire cmdr_cmdr_buf_source_source_last; +wire [7:0] cmdr_cmdr_buf_source_source_payload_data; +wire cmdr_cmdr_buf_source_source_ready; +wire cmdr_cmdr_buf_source_source_valid; +reg [2:0] cmdr_cmdr_converter_converter_demux = 3'd0; +wire cmdr_cmdr_converter_converter_load_part; +reg cmdr_cmdr_converter_converter_sink_first = 1'd0; +reg cmdr_cmdr_converter_converter_sink_last = 1'd0; +wire cmdr_cmdr_converter_converter_sink_payload_data; +wire cmdr_cmdr_converter_converter_sink_ready; +wire cmdr_cmdr_converter_converter_sink_valid; +reg cmdr_cmdr_converter_converter_source_first = 1'd0; +reg cmdr_cmdr_converter_converter_source_last = 1'd0; +reg [7:0] cmdr_cmdr_converter_converter_source_payload_data = 8'd0; +reg [3:0] cmdr_cmdr_converter_converter_source_payload_valid_token_count = 4'd0; +wire cmdr_cmdr_converter_converter_source_ready; +wire cmdr_cmdr_converter_converter_source_valid; +reg cmdr_cmdr_converter_converter_strobe_all = 1'd0; +wire cmdr_cmdr_converter_source_source_first; +wire cmdr_cmdr_converter_source_source_last; +wire [7:0] cmdr_cmdr_converter_source_source_payload_data; +wire cmdr_cmdr_converter_source_source_ready; +wire cmdr_cmdr_converter_source_source_valid; +wire cmdr_cmdr_pads_in_first; +wire cmdr_cmdr_pads_in_last; +wire cmdr_cmdr_pads_in_payload_clk; +wire cmdr_cmdr_pads_in_payload_cmd_i; +wire cmdr_cmdr_pads_in_payload_cmd_o; +wire cmdr_cmdr_pads_in_payload_cmd_oe; +wire [3:0] cmdr_cmdr_pads_in_payload_data_i; +wire cmdr_cmdr_pads_in_payload_data_i_ce; +wire [3:0] cmdr_cmdr_pads_in_payload_data_o; +wire cmdr_cmdr_pads_in_payload_data_oe; +reg cmdr_cmdr_pads_in_ready = 1'd0; +wire cmdr_cmdr_pads_in_valid; +reg cmdr_cmdr_reset = 1'd0; +reg cmdr_cmdr_reset_sdphycmdr_next_value3 = 1'd0; +reg cmdr_cmdr_reset_sdphycmdr_next_value_ce3 = 1'd0; +reg cmdr_cmdr_run = 1'd0; +wire cmdr_cmdr_source_first; +wire cmdr_cmdr_source_last; +wire [7:0] cmdr_cmdr_source_payload_data; +reg cmdr_cmdr_source_ready = 1'd0; +wire cmdr_cmdr_source_valid; +wire cmdr_cmdr_start; +reg [7:0] cmdr_count = 8'd0; +reg [7:0] cmdr_count_sdphycmdr_next_value1 = 8'd0; +reg cmdr_count_sdphycmdr_next_value_ce1 = 1'd0; +reg cmdr_pads_in_pads_in_first = 1'd0; +reg cmdr_pads_in_pads_in_last = 1'd0; +reg cmdr_pads_in_pads_in_payload_clk = 1'd0; +wire cmdr_pads_in_pads_in_payload_cmd_i; +reg cmdr_pads_in_pads_in_payload_cmd_o = 1'd0; +reg cmdr_pads_in_pads_in_payload_cmd_oe = 1'd0; +wire [3:0] cmdr_pads_in_pads_in_payload_data_i; +reg cmdr_pads_in_pads_in_payload_data_i_ce = 1'd0; +reg [3:0] cmdr_pads_in_pads_in_payload_data_o = 4'd0; +reg cmdr_pads_in_pads_in_payload_data_oe = 1'd0; +wire cmdr_pads_in_pads_in_ready; +wire cmdr_pads_in_pads_in_valid; +reg cmdr_pads_out_payload_clk = 1'd0; +reg cmdr_pads_out_payload_cmd_o = 1'd0; +reg cmdr_pads_out_payload_cmd_oe = 1'd0; +reg [3:0] cmdr_pads_out_payload_data_o = 4'd0; +reg cmdr_pads_out_payload_data_oe = 1'd0; +wire cmdr_pads_out_ready; +reg [1:0] cmdr_sink_payload_cmd_type = 2'd0; +reg [1:0] cmdr_sink_payload_data_type = 2'd0; +reg [7:0] cmdr_sink_payload_length = 8'd0; +reg cmdr_sink_ready = 1'd0; +reg cmdr_sink_valid = 1'd0; +reg cmdr_source_source_last = 1'd0; +reg [7:0] cmdr_source_source_payload_data = 8'd0; +reg [2:0] cmdr_source_source_payload_status = 3'd0; +reg cmdr_source_source_ready = 1'd0; +reg cmdr_source_source_valid = 1'd0; +reg [31:0] cmdr_timeout = 32'd50000000; +reg [31:0] cmdr_timeout_sdphycmdr_next_value0 = 32'd0; +reg cmdr_timeout_sdphycmdr_next_value_ce0 = 1'd0; +reg [7:0] cmdw_count = 8'd0; +reg [7:0] cmdw_count_sdphycmdw_next_value = 8'd0; +reg cmdw_count_sdphycmdw_next_value_ce = 1'd0; +reg cmdw_done = 1'd0; +wire cmdw_pads_in_payload_cmd_i; +wire [3:0] cmdw_pads_in_payload_data_i; +wire cmdw_pads_in_valid; +reg cmdw_pads_out_payload_clk = 1'd0; +reg cmdw_pads_out_payload_cmd_o = 1'd0; +reg cmdw_pads_out_payload_cmd_oe = 1'd0; +reg [3:0] cmdw_pads_out_payload_data_o = 4'd0; +reg cmdw_pads_out_payload_data_oe = 1'd0; +wire cmdw_pads_out_ready; +reg cmdw_sink_last = 1'd0; +reg [1:0] cmdw_sink_payload_cmd_type = 2'd0; +reg [7:0] cmdw_sink_payload_data = 8'd0; +reg cmdw_sink_ready = 1'd0; +reg cmdw_sink_valid = 1'd0; +reg [19:0] count = 20'd1000000; +wire cpu_rst; +reg crc16inserter_next_state = 1'd0; +reg crc16inserter_state = 1'd0; +wire [31:0] csrbank0_bus_errors_r; +reg csrbank0_bus_errors_re = 1'd0; +wire [31:0] csrbank0_bus_errors_w; +reg csrbank0_bus_errors_we = 1'd0; +wire [1:0] csrbank0_reset0_r; +reg csrbank0_reset0_re = 1'd0; +wire [1:0] csrbank0_reset0_w; +reg csrbank0_reset0_we = 1'd0; +wire [31:0] csrbank0_scratch0_r; +reg csrbank0_scratch0_re = 1'd0; +wire [31:0] csrbank0_scratch0_w; +reg csrbank0_scratch0_we = 1'd0; +wire csrbank0_sel; +wire [31:0] csrbank1_dma_base0_r; +reg csrbank1_dma_base0_re = 1'd0; +wire [31:0] csrbank1_dma_base0_w; +reg csrbank1_dma_base0_we = 1'd0; +wire [31:0] csrbank1_dma_base1_r; +reg csrbank1_dma_base1_re = 1'd0; +wire [31:0] csrbank1_dma_base1_w; +reg csrbank1_dma_base1_we = 1'd0; +wire csrbank1_dma_done_r; +reg csrbank1_dma_done_re = 1'd0; +wire csrbank1_dma_done_w; +reg csrbank1_dma_done_we = 1'd0; +wire csrbank1_dma_enable0_r; +reg csrbank1_dma_enable0_re = 1'd0; +wire csrbank1_dma_enable0_w; +reg csrbank1_dma_enable0_we = 1'd0; +wire [31:0] csrbank1_dma_length0_r; +reg csrbank1_dma_length0_re = 1'd0; +wire [31:0] csrbank1_dma_length0_w; +reg csrbank1_dma_length0_we = 1'd0; +wire csrbank1_dma_loop0_r; +reg csrbank1_dma_loop0_re = 1'd0; +wire csrbank1_dma_loop0_w; +reg csrbank1_dma_loop0_we = 1'd0; +wire [31:0] csrbank1_dma_offset_r; +reg csrbank1_dma_offset_re = 1'd0; +wire [31:0] csrbank1_dma_offset_w; +reg csrbank1_dma_offset_we = 1'd0; +wire csrbank1_sel; +wire [31:0] csrbank2_block_count0_r; +reg csrbank2_block_count0_re = 1'd0; +wire [31:0] csrbank2_block_count0_w; +reg csrbank2_block_count0_we = 1'd0; +wire [9:0] csrbank2_block_length0_r; +reg csrbank2_block_length0_re = 1'd0; +wire [9:0] csrbank2_block_length0_w; +reg csrbank2_block_length0_we = 1'd0; +wire [31:0] csrbank2_cmd_argument0_r; +reg csrbank2_cmd_argument0_re = 1'd0; +wire [31:0] csrbank2_cmd_argument0_w; +reg csrbank2_cmd_argument0_we = 1'd0; +wire [13:0] csrbank2_cmd_command0_r; +reg csrbank2_cmd_command0_re = 1'd0; +wire [13:0] csrbank2_cmd_command0_w; +reg csrbank2_cmd_command0_we = 1'd0; +wire [3:0] csrbank2_cmd_event_r; +reg csrbank2_cmd_event_re = 1'd0; +wire [3:0] csrbank2_cmd_event_w; +reg csrbank2_cmd_event_we = 1'd0; +wire [31:0] csrbank2_cmd_response0_r; +reg csrbank2_cmd_response0_re = 1'd0; +wire [31:0] csrbank2_cmd_response0_w; +reg csrbank2_cmd_response0_we = 1'd0; +wire [31:0] csrbank2_cmd_response1_r; +reg csrbank2_cmd_response1_re = 1'd0; +wire [31:0] csrbank2_cmd_response1_w; +reg csrbank2_cmd_response1_we = 1'd0; +wire [31:0] csrbank2_cmd_response2_r; +reg csrbank2_cmd_response2_re = 1'd0; +wire [31:0] csrbank2_cmd_response2_w; +reg csrbank2_cmd_response2_we = 1'd0; +wire [31:0] csrbank2_cmd_response3_r; +reg csrbank2_cmd_response3_re = 1'd0; +wire [31:0] csrbank2_cmd_response3_w; +reg csrbank2_cmd_response3_we = 1'd0; +wire csrbank2_cmd_send0_r; +reg csrbank2_cmd_send0_re = 1'd0; +wire csrbank2_cmd_send0_w; +reg csrbank2_cmd_send0_we = 1'd0; +wire [3:0] csrbank2_data_event_r; +reg csrbank2_data_event_re = 1'd0; +wire [3:0] csrbank2_data_event_w; +reg csrbank2_data_event_we = 1'd0; +wire csrbank2_sel; +wire [3:0] csrbank3_enable0_r; +reg csrbank3_enable0_re = 1'd0; +wire [3:0] csrbank3_enable0_w; +reg csrbank3_enable0_we = 1'd0; +wire [3:0] csrbank3_pending_r; +reg csrbank3_pending_re = 1'd0; +wire [3:0] csrbank3_pending_w; +reg csrbank3_pending_we = 1'd0; +wire csrbank3_sel; +wire [3:0] csrbank3_status_r; +reg csrbank3_status_re = 1'd0; +wire [3:0] csrbank3_status_w; +reg csrbank3_status_we = 1'd0; +wire [31:0] csrbank4_dma_base0_r; +reg csrbank4_dma_base0_re = 1'd0; +wire [31:0] csrbank4_dma_base0_w; +reg csrbank4_dma_base0_we = 1'd0; +wire [31:0] csrbank4_dma_base1_r; +reg csrbank4_dma_base1_re = 1'd0; +wire [31:0] csrbank4_dma_base1_w; +reg csrbank4_dma_base1_we = 1'd0; +wire csrbank4_dma_done_r; +reg csrbank4_dma_done_re = 1'd0; +wire csrbank4_dma_done_w; +reg csrbank4_dma_done_we = 1'd0; +wire csrbank4_dma_enable0_r; +reg csrbank4_dma_enable0_re = 1'd0; +wire csrbank4_dma_enable0_w; +reg csrbank4_dma_enable0_we = 1'd0; +wire [31:0] csrbank4_dma_length0_r; +reg csrbank4_dma_length0_re = 1'd0; +wire [31:0] csrbank4_dma_length0_w; +reg csrbank4_dma_length0_we = 1'd0; +wire csrbank4_dma_loop0_r; +reg csrbank4_dma_loop0_re = 1'd0; +wire csrbank4_dma_loop0_w; +reg csrbank4_dma_loop0_we = 1'd0; +wire [31:0] csrbank4_dma_offset_r; +reg csrbank4_dma_offset_re = 1'd0; +wire [31:0] csrbank4_dma_offset_w; +reg csrbank4_dma_offset_we = 1'd0; +wire csrbank4_sel; +wire csrbank5_card_detect_r; +reg csrbank5_card_detect_re = 1'd0; +wire csrbank5_card_detect_w; +reg csrbank5_card_detect_we = 1'd0; +wire [8:0] csrbank5_clocker_divider0_r; +reg csrbank5_clocker_divider0_re = 1'd0; +wire [8:0] csrbank5_clocker_divider0_w; +reg csrbank5_clocker_divider0_we = 1'd0; +wire [2:0] csrbank5_dataw_status_r; +reg csrbank5_dataw_status_re = 1'd0; +wire [2:0] csrbank5_dataw_status_w; +reg csrbank5_dataw_status_we = 1'd0; +wire csrbank5_sel; +wire [31:0] dat_r; +wire [31:0] dat_w; +reg [9:0] datar_count = 10'd0; +reg [9:0] datar_count_sdphydatar_next_value0 = 10'd0; +reg datar_count_sdphydatar_next_value_ce0 = 1'd0; +wire datar_datar_buf_pipe_valid_sink_first; +wire datar_datar_buf_pipe_valid_sink_last; +wire [7:0] datar_datar_buf_pipe_valid_sink_payload_data; +wire datar_datar_buf_pipe_valid_sink_ready; +wire datar_datar_buf_pipe_valid_sink_valid; +reg datar_datar_buf_pipe_valid_source_first = 1'd0; +reg datar_datar_buf_pipe_valid_source_last = 1'd0; +reg [7:0] datar_datar_buf_pipe_valid_source_payload_data = 8'd0; +wire datar_datar_buf_pipe_valid_source_ready; +reg datar_datar_buf_pipe_valid_source_valid = 1'd0; +wire datar_datar_buf_sink_sink_first; +wire datar_datar_buf_sink_sink_last; +wire [7:0] datar_datar_buf_sink_sink_payload_data; +wire datar_datar_buf_sink_sink_ready; +wire datar_datar_buf_sink_sink_valid; +wire datar_datar_buf_source_source_first; +wire datar_datar_buf_source_source_last; +wire [7:0] datar_datar_buf_source_source_payload_data; +wire datar_datar_buf_source_source_ready; +wire datar_datar_buf_source_source_valid; +reg datar_datar_converter_converter_demux = 1'd0; +wire datar_datar_converter_converter_load_part; +reg datar_datar_converter_converter_sink_first = 1'd0; +reg datar_datar_converter_converter_sink_last = 1'd0; +wire [3:0] datar_datar_converter_converter_sink_payload_data; +wire datar_datar_converter_converter_sink_ready; +wire datar_datar_converter_converter_sink_valid; +reg datar_datar_converter_converter_source_first = 1'd0; +reg datar_datar_converter_converter_source_last = 1'd0; +reg [7:0] datar_datar_converter_converter_source_payload_data = 8'd0; +reg [1:0] datar_datar_converter_converter_source_payload_valid_token_count = 2'd0; +wire datar_datar_converter_converter_source_ready; +wire datar_datar_converter_converter_source_valid; +reg datar_datar_converter_converter_strobe_all = 1'd0; +wire datar_datar_converter_source_source_first; +wire datar_datar_converter_source_source_last; +wire [7:0] datar_datar_converter_source_source_payload_data; +wire datar_datar_converter_source_source_ready; +wire datar_datar_converter_source_source_valid; +wire datar_datar_pads_in_first; +wire datar_datar_pads_in_last; +wire datar_datar_pads_in_payload_clk; +wire datar_datar_pads_in_payload_cmd_i; +wire datar_datar_pads_in_payload_cmd_o; +wire datar_datar_pads_in_payload_cmd_oe; +wire [3:0] datar_datar_pads_in_payload_data_i; +wire datar_datar_pads_in_payload_data_i_ce; +wire [3:0] datar_datar_pads_in_payload_data_o; +wire datar_datar_pads_in_payload_data_oe; +reg datar_datar_pads_in_ready = 1'd0; +wire datar_datar_pads_in_valid; +reg datar_datar_reset = 1'd0; +reg datar_datar_reset_sdphydatar_next_value2 = 1'd0; +reg datar_datar_reset_sdphydatar_next_value_ce2 = 1'd0; +reg datar_datar_run = 1'd0; +wire datar_datar_source_first; +wire datar_datar_source_last; +wire [7:0] datar_datar_source_payload_data; +reg datar_datar_source_ready = 1'd0; +wire datar_datar_source_valid; +wire datar_datar_start; +reg datar_pads_in_pads_in_first = 1'd0; +reg datar_pads_in_pads_in_last = 1'd0; +reg datar_pads_in_pads_in_payload_clk = 1'd0; +wire datar_pads_in_pads_in_payload_cmd_i; +reg datar_pads_in_pads_in_payload_cmd_o = 1'd0; +reg datar_pads_in_pads_in_payload_cmd_oe = 1'd0; +wire [3:0] datar_pads_in_pads_in_payload_data_i; +reg datar_pads_in_pads_in_payload_data_i_ce = 1'd0; +reg [3:0] datar_pads_in_pads_in_payload_data_o = 4'd0; +reg datar_pads_in_pads_in_payload_data_oe = 1'd0; +wire datar_pads_in_pads_in_ready; +wire datar_pads_in_pads_in_valid; +reg datar_pads_out_payload_clk = 1'd0; +reg datar_pads_out_payload_cmd_o = 1'd0; +reg datar_pads_out_payload_cmd_oe = 1'd0; +reg [3:0] datar_pads_out_payload_data_o = 4'd0; +reg datar_pads_out_payload_data_oe = 1'd0; +wire datar_pads_out_ready; +reg datar_sink_last = 1'd0; +reg [9:0] datar_sink_payload_block_length = 10'd0; +reg datar_sink_ready = 1'd0; +reg datar_sink_valid = 1'd0; +reg datar_source_source_first = 1'd0; +reg datar_source_source_last = 1'd0; +reg [7:0] datar_source_source_payload_data = 8'd0; +reg [2:0] datar_source_source_payload_status = 3'd0; +reg datar_source_source_ready = 1'd0; +reg datar_source_source_valid = 1'd0; +reg datar_stop = 1'd0; +reg [31:0] datar_timeout = 32'd50000000; +reg [31:0] datar_timeout_sdphydatar_next_value1 = 32'd0; +reg datar_timeout_sdphydatar_next_value_ce1 = 1'd0; +wire dataw_accepted0; +reg dataw_accepted1 = 1'd0; +reg dataw_accepted1_sdphydataw_next_value0 = 1'd0; +reg dataw_accepted1_sdphydataw_next_value_ce0 = 1'd0; +reg [7:0] dataw_count = 8'd0; +reg [7:0] dataw_count_sdphydataw_next_value3 = 8'd0; +reg dataw_count_sdphydataw_next_value_ce3 = 1'd0; +wire dataw_crc_buf_pipe_valid_sink_first; +wire dataw_crc_buf_pipe_valid_sink_last; +wire [7:0] dataw_crc_buf_pipe_valid_sink_payload_data; +wire dataw_crc_buf_pipe_valid_sink_ready; +wire dataw_crc_buf_pipe_valid_sink_valid; +reg dataw_crc_buf_pipe_valid_source_first = 1'd0; +reg dataw_crc_buf_pipe_valid_source_last = 1'd0; +reg [7:0] dataw_crc_buf_pipe_valid_source_payload_data = 8'd0; +wire dataw_crc_buf_pipe_valid_source_ready; +reg dataw_crc_buf_pipe_valid_source_valid = 1'd0; +wire dataw_crc_buf_sink_sink_first; +wire dataw_crc_buf_sink_sink_last; +wire [7:0] dataw_crc_buf_sink_sink_payload_data; +wire dataw_crc_buf_sink_sink_ready; +wire dataw_crc_buf_sink_sink_valid; +wire dataw_crc_buf_source_source_first; +wire dataw_crc_buf_source_source_last; +wire [7:0] dataw_crc_buf_source_source_payload_data; +wire dataw_crc_buf_source_source_ready; +wire dataw_crc_buf_source_source_valid; +reg [2:0] dataw_crc_converter_converter_demux = 3'd0; +wire dataw_crc_converter_converter_load_part; +reg dataw_crc_converter_converter_sink_first = 1'd0; +reg dataw_crc_converter_converter_sink_last = 1'd0; +wire dataw_crc_converter_converter_sink_payload_data; +wire dataw_crc_converter_converter_sink_ready; +wire dataw_crc_converter_converter_sink_valid; +reg dataw_crc_converter_converter_source_first = 1'd0; +reg dataw_crc_converter_converter_source_last = 1'd0; +reg [7:0] dataw_crc_converter_converter_source_payload_data = 8'd0; +reg [3:0] dataw_crc_converter_converter_source_payload_valid_token_count = 4'd0; +wire dataw_crc_converter_converter_source_ready; +wire dataw_crc_converter_converter_source_valid; +reg dataw_crc_converter_converter_strobe_all = 1'd0; +wire dataw_crc_converter_source_source_first; +wire dataw_crc_converter_source_source_last; +wire [7:0] dataw_crc_converter_source_source_payload_data; +wire dataw_crc_converter_source_source_ready; +wire dataw_crc_converter_source_source_valid; +wire dataw_crc_error0; +reg dataw_crc_error1 = 1'd0; +reg dataw_crc_error1_sdphydataw_next_value1 = 1'd0; +reg dataw_crc_error1_sdphydataw_next_value_ce1 = 1'd0; +wire dataw_crc_pads_in_first; +wire dataw_crc_pads_in_last; +wire dataw_crc_pads_in_payload_clk; +wire dataw_crc_pads_in_payload_cmd_i; +wire dataw_crc_pads_in_payload_cmd_o; +wire dataw_crc_pads_in_payload_cmd_oe; +wire [3:0] dataw_crc_pads_in_payload_data_i; +wire dataw_crc_pads_in_payload_data_i_ce; +wire [3:0] dataw_crc_pads_in_payload_data_o; +wire dataw_crc_pads_in_payload_data_oe; +wire dataw_crc_pads_in_ready; +wire dataw_crc_pads_in_valid; +reg dataw_crc_reset = 1'd0; +reg dataw_crc_run = 1'd0; +wire dataw_crc_source_first; +wire dataw_crc_source_last; +wire [7:0] dataw_crc_source_payload_data; +reg dataw_crc_source_ready = 1'd0; +wire dataw_crc_source_valid; +wire dataw_crc_start; +reg dataw_pads_in_pads_in_first = 1'd0; +reg dataw_pads_in_pads_in_last = 1'd0; +reg dataw_pads_in_pads_in_payload_clk = 1'd0; +wire dataw_pads_in_pads_in_payload_cmd_i; +reg dataw_pads_in_pads_in_payload_cmd_o = 1'd0; +reg dataw_pads_in_pads_in_payload_cmd_oe = 1'd0; +wire [3:0] dataw_pads_in_pads_in_payload_data_i; +reg dataw_pads_in_pads_in_payload_data_i_ce = 1'd0; +reg [3:0] dataw_pads_in_pads_in_payload_data_o = 4'd0; +reg dataw_pads_in_pads_in_payload_data_oe = 1'd0; +reg dataw_pads_in_pads_in_ready = 1'd0; +wire dataw_pads_in_pads_in_valid; +reg dataw_pads_out_payload_clk = 1'd0; +reg dataw_pads_out_payload_cmd_o = 1'd0; +reg dataw_pads_out_payload_cmd_oe = 1'd0; +reg [3:0] dataw_pads_out_payload_data_o = 4'd0; +reg dataw_pads_out_payload_data_oe = 1'd0; +wire dataw_pads_out_ready; +reg dataw_re = 1'd0; +reg dataw_sink_first = 1'd0; +reg dataw_sink_last = 1'd0; +reg [7:0] dataw_sink_payload_data = 8'd0; +reg dataw_sink_ready = 1'd0; +reg dataw_sink_valid = 1'd0; +reg [2:0] dataw_status = 3'd0; +reg dataw_stop = 1'd0; +wire dataw_we; +wire dataw_write_error0; +reg dataw_write_error1 = 1'd0; +reg dataw_write_error1_sdphydataw_next_value2 = 1'd0; +reg dataw_write_error1_sdphydataw_next_value_ce2 = 1'd0; +wire done; +reg error = 1'd0; +wire eventmanager_block2mem_dma0; +wire eventmanager_block2mem_dma1; +wire eventmanager_block2mem_dma2; +wire eventmanager_card_detect0; +wire eventmanager_card_detect1; +wire eventmanager_card_detect2; +wire eventmanager_cmd_done0; +wire eventmanager_cmd_done1; +wire eventmanager_cmd_done2; +reg eventmanager_enable_re = 1'd0; +reg [3:0] eventmanager_enable_storage = 4'd0; +wire eventmanager_mem2block_dma0; +wire eventmanager_mem2block_dma1; +wire eventmanager_mem2block_dma2; +reg [3:0] eventmanager_pending_r = 4'd0; +reg eventmanager_pending_re = 1'd0; +reg [3:0] eventmanager_pending_status = 4'd0; +wire eventmanager_pending_we; +reg eventmanager_status_re = 1'd0; +reg [3:0] eventmanager_status_status = 4'd0; +wire eventmanager_status_we; +reg [2:0] fsm_next_state = 3'd0; +reg [2:0] fsm_state = 3'd0; +reg grant = 1'd0; +wire inferedsdrtristate0__i; +wire inferedsdrtristate0__o; +reg inferedsdrtristate0_oe = 1'd0; +wire inferedsdrtristate1__i; +wire inferedsdrtristate1__o; +reg inferedsdrtristate1_oe = 1'd0; +wire inferedsdrtristate2__i; +wire inferedsdrtristate2__o; +reg inferedsdrtristate2_oe = 1'd0; +wire inferedsdrtristate3__i; +wire inferedsdrtristate3__o; +reg inferedsdrtristate3_oe = 1'd0; +wire inferedsdrtristate4__i; +wire inferedsdrtristate4__o; +reg inferedsdrtristate4_oe = 1'd0; +reg [7:0] init_count = 8'd0; +reg [7:0] init_count_sdphyinit_next_value = 8'd0; +reg init_count_sdphyinit_next_value_ce = 1'd0; +wire init_initialize_r; +reg init_initialize_re = 1'd0; +reg init_initialize_w = 1'd0; +reg init_initialize_we = 1'd0; +wire init_pads_in_payload_cmd_i; +wire [3:0] init_pads_in_payload_data_i; +wire init_pads_in_valid; +reg init_pads_out_payload_clk = 1'd0; +reg init_pads_out_payload_cmd_o = 1'd0; +reg init_pads_out_payload_cmd_oe = 1'd0; +reg [3:0] init_pads_out_payload_data_o = 4'd0; +reg init_pads_out_payload_data_oe = 1'd0; +wire init_pads_out_ready; +reg int_rst = 1'd1; +reg interface0_ack = 1'd0; +wire [29:0] interface0_adr; +wire [13:0] interface0_bank_bus_adr; +reg [31:0] interface0_bank_bus_dat_r = 32'd0; +wire [31:0] interface0_bank_bus_dat_w; +wire interface0_bank_bus_we; +wire [1:0] interface0_bte; +wire interface0_bus_ack; +wire [31:0] interface0_bus_adr; +reg [1:0] interface0_bus_bte = 2'd0; +reg [2:0] interface0_bus_cti = 3'd0; +wire interface0_bus_cyc; +wire [31:0] interface0_bus_dat_r; +wire [31:0] interface0_bus_dat_w; +wire interface0_bus_err; +wire [3:0] interface0_bus_sel; +wire interface0_bus_stb; +wire interface0_bus_we; +wire [2:0] interface0_cti; +wire interface0_cyc; +reg [31:0] interface0_dat_r = 32'd0; +wire [31:0] interface0_dat_w; +reg interface0_err = 1'd0; +wire [3:0] interface0_sel; +wire interface0_stb; +wire interface0_we; +reg [13:0] interface1_adr = 14'd0; +wire [13:0] interface1_bank_bus_adr; +reg [31:0] interface1_bank_bus_dat_r = 32'd0; +wire [31:0] interface1_bank_bus_dat_w; +wire interface1_bank_bus_we; +wire interface1_bus_ack; +wire [31:0] interface1_bus_adr; +reg [1:0] interface1_bus_bte = 2'd0; +reg [2:0] interface1_bus_cti = 3'd0; +wire interface1_bus_cyc; +wire [31:0] interface1_bus_dat_r; +reg [31:0] interface1_bus_dat_w = 32'd0; +wire interface1_bus_err; +wire [3:0] interface1_bus_sel; +wire interface1_bus_stb; +wire interface1_bus_we; +wire [31:0] interface1_dat_r; +reg [31:0] interface1_dat_w = 32'd0; +reg interface1_we = 1'd0; +wire [13:0] interface2_bank_bus_adr; +reg [31:0] interface2_bank_bus_dat_r = 32'd0; +wire [31:0] interface2_bank_bus_dat_w; +wire interface2_bank_bus_we; +wire [13:0] interface3_bank_bus_adr; +reg [31:0] interface3_bank_bus_dat_r = 32'd0; +wire [31:0] interface3_bank_bus_dat_w; +wire interface3_bank_bus_we; +wire [13:0] interface4_bank_bus_adr; +reg [31:0] interface4_bank_bus_dat_r = 32'd0; +wire [31:0] interface4_bank_bus_dat_w; +wire interface4_bank_bus_we; +wire [13:0] interface5_bank_bus_adr; +reg [31:0] interface5_bank_bus_dat_r = 32'd0; +wire [31:0] interface5_bank_bus_dat_w; +wire interface5_bank_bus_we; +reg mem2block_dma_clear = 1'd0; +reg mem2block_dma_pending = 1'd0; +wire mem2block_dma_status; +wire mem2block_dma_trigger; +wire por_clk; +wire [1:0] request; +reg reset_re = 1'd0; +reg [1:0] reset_storage = 2'd0; +reg scratch_re = 1'd0; +reg [31:0] scratch_storage = 32'd305419896; +reg [1:0] sdblock2memdma_next_state = 2'd0; +reg [1:0] sdblock2memdma_state = 2'd0; +reg sdcard_block2mem_connect = 1'd0; +reg [1:0] sdcard_block2mem_converter_demux = 2'd0; +wire sdcard_block2mem_converter_load_part; +wire sdcard_block2mem_converter_sink_first; +wire sdcard_block2mem_converter_sink_last; +wire [7:0] sdcard_block2mem_converter_sink_payload_data; +wire sdcard_block2mem_converter_sink_ready; +wire sdcard_block2mem_converter_sink_valid; +reg sdcard_block2mem_converter_source_first = 1'd0; +reg sdcard_block2mem_converter_source_last = 1'd0; +reg [31:0] sdcard_block2mem_converter_source_payload_data = 32'd0; +reg [2:0] sdcard_block2mem_converter_source_payload_valid_token_count = 3'd0; +wire sdcard_block2mem_converter_source_ready; +wire sdcard_block2mem_converter_source_valid; +reg sdcard_block2mem_converter_strobe_all = 1'd0; +reg sdcard_block2mem_done_d = 1'd0; +reg [8:0] sdcard_block2mem_fifo_consume = 9'd0; +wire sdcard_block2mem_fifo_do_read; +wire sdcard_block2mem_fifo_fifo_in_first; +wire sdcard_block2mem_fifo_fifo_in_last; +wire [7:0] sdcard_block2mem_fifo_fifo_in_payload_data; +wire sdcard_block2mem_fifo_fifo_out_first; +wire sdcard_block2mem_fifo_fifo_out_last; +wire [7:0] sdcard_block2mem_fifo_fifo_out_payload_data; +reg [9:0] sdcard_block2mem_fifo_level0 = 10'd0; +wire [9:0] sdcard_block2mem_fifo_level1; +reg [8:0] sdcard_block2mem_fifo_produce = 9'd0; +wire [8:0] sdcard_block2mem_fifo_rdport_adr; +wire [9:0] sdcard_block2mem_fifo_rdport_dat_r; +wire sdcard_block2mem_fifo_rdport_re; +wire sdcard_block2mem_fifo_re; +reg sdcard_block2mem_fifo_readable = 1'd0; +reg sdcard_block2mem_fifo_replace = 1'd0; +reg sdcard_block2mem_fifo_sink_first = 1'd0; +reg sdcard_block2mem_fifo_sink_last = 1'd0; +reg [7:0] sdcard_block2mem_fifo_sink_payload_data = 8'd0; +wire sdcard_block2mem_fifo_sink_ready; +reg sdcard_block2mem_fifo_sink_valid = 1'd0; +wire sdcard_block2mem_fifo_source_first; +wire sdcard_block2mem_fifo_source_last; +wire [7:0] sdcard_block2mem_fifo_source_payload_data; +wire sdcard_block2mem_fifo_source_ready; +wire sdcard_block2mem_fifo_source_valid; +wire [9:0] sdcard_block2mem_fifo_syncfifo_din; +wire [9:0] sdcard_block2mem_fifo_syncfifo_dout; +wire sdcard_block2mem_fifo_syncfifo_re; +wire sdcard_block2mem_fifo_syncfifo_readable; +wire sdcard_block2mem_fifo_syncfifo_we; +wire sdcard_block2mem_fifo_syncfifo_writable; +reg [8:0] sdcard_block2mem_fifo_wrport_adr = 9'd0; +wire [9:0] sdcard_block2mem_fifo_wrport_dat_r; +wire [9:0] sdcard_block2mem_fifo_wrport_dat_w; +wire sdcard_block2mem_fifo_wrport_we; +reg sdcard_block2mem_irq = 1'd0; +wire sdcard_block2mem_sink_sink_first; +wire sdcard_block2mem_sink_sink_last0; +reg sdcard_block2mem_sink_sink_last1 = 1'd0; +reg [31:0] sdcard_block2mem_sink_sink_payload_address = 32'd0; +wire [7:0] sdcard_block2mem_sink_sink_payload_data0; +reg [31:0] sdcard_block2mem_sink_sink_payload_data1 = 32'd0; +reg sdcard_block2mem_sink_sink_ready0 = 1'd0; +wire sdcard_block2mem_sink_sink_ready1; +wire sdcard_block2mem_sink_sink_valid0; +reg sdcard_block2mem_sink_sink_valid1 = 1'd0; +wire sdcard_block2mem_source_source_first; +wire sdcard_block2mem_source_source_last; +wire [31:0] sdcard_block2mem_source_source_payload_data; +wire sdcard_block2mem_source_source_ready; +wire sdcard_block2mem_source_source_valid; +wire sdcard_block2mem_start; +wire [31:0] sdcard_block2mem_wishbonedmawriter_base; +reg sdcard_block2mem_wishbonedmawriter_base_re = 1'd0; +reg [63:0] sdcard_block2mem_wishbonedmawriter_base_storage = 64'd0; +reg sdcard_block2mem_wishbonedmawriter_done_re = 1'd0; +reg sdcard_block2mem_wishbonedmawriter_done_status = 1'd0; +wire sdcard_block2mem_wishbonedmawriter_done_we; +reg sdcard_block2mem_wishbonedmawriter_enable_re = 1'd0; +reg sdcard_block2mem_wishbonedmawriter_enable_storage = 1'd0; +wire [31:0] sdcard_block2mem_wishbonedmawriter_length; +reg sdcard_block2mem_wishbonedmawriter_length_re = 1'd0; +reg [31:0] sdcard_block2mem_wishbonedmawriter_length_storage = 32'd0; +reg sdcard_block2mem_wishbonedmawriter_loop_re = 1'd0; +reg sdcard_block2mem_wishbonedmawriter_loop_storage = 1'd0; +reg [31:0] sdcard_block2mem_wishbonedmawriter_offset = 32'd0; +reg sdcard_block2mem_wishbonedmawriter_offset_re = 1'd0; +reg [31:0] sdcard_block2mem_wishbonedmawriter_offset_sdblock2memdma_next_value = 32'd0; +reg sdcard_block2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce = 1'd0; +wire [31:0] sdcard_block2mem_wishbonedmawriter_offset_status; +wire sdcard_block2mem_wishbonedmawriter_offset_we; +wire sdcard_block2mem_wishbonedmawriter_reset; +wire sdcard_block2mem_wishbonedmawriter_sink_first; +wire sdcard_block2mem_wishbonedmawriter_sink_last; +wire [31:0] sdcard_block2mem_wishbonedmawriter_sink_payload_data; +reg sdcard_block2mem_wishbonedmawriter_sink_ready = 1'd0; +wire sdcard_block2mem_wishbonedmawriter_sink_valid; +reg sdcard_core_block_count_re = 1'd0; +reg [31:0] sdcard_core_block_count_storage = 32'd0; +reg sdcard_core_block_length_re = 1'd0; +reg [9:0] sdcard_core_block_length_storage = 10'd0; +wire [5:0] sdcard_core_cmd; +reg sdcard_core_cmd_argument_re = 1'd0; +reg [31:0] sdcard_core_cmd_argument_storage = 32'd0; +reg sdcard_core_cmd_command_re = 1'd0; +reg [13:0] sdcard_core_cmd_command_storage = 14'd0; +reg [2:0] sdcard_core_cmd_count = 3'd0; +reg [2:0] sdcard_core_cmd_count_fsm_next_value2 = 3'd0; +reg sdcard_core_cmd_count_fsm_next_value_ce2 = 1'd0; +reg sdcard_core_cmd_done = 1'd0; +reg sdcard_core_cmd_done_fsm_next_value0 = 1'd0; +reg sdcard_core_cmd_done_fsm_next_value_ce0 = 1'd0; +reg sdcard_core_cmd_error = 1'd0; +reg sdcard_core_cmd_error_fsm_next_value4 = 1'd0; +reg sdcard_core_cmd_error_fsm_next_value_ce4 = 1'd0; +reg sdcard_core_cmd_event_re = 1'd0; +reg [3:0] sdcard_core_cmd_event_status = 4'd0; +wire sdcard_core_cmd_event_we; +reg sdcard_core_cmd_response_re = 1'd0; +reg [127:0] sdcard_core_cmd_response_status = 128'd0; +reg [127:0] sdcard_core_cmd_response_status_fsm_next_value8 = 128'd0; +reg sdcard_core_cmd_response_status_fsm_next_value_ce8 = 1'd0; +wire sdcard_core_cmd_response_we; +reg sdcard_core_cmd_send_re = 1'd0; +reg sdcard_core_cmd_send_storage = 1'd0; +reg sdcard_core_cmd_timeout = 1'd0; +reg sdcard_core_cmd_timeout_fsm_next_value5 = 1'd0; +reg sdcard_core_cmd_timeout_fsm_next_value_ce5 = 1'd0; +wire [1:0] sdcard_core_cmd_type; +reg [2:0] sdcard_core_crc16_inserter_count = 3'd0; +reg [2:0] sdcard_core_crc16_inserter_count_crc16inserter_next_value = 3'd0; +reg sdcard_core_crc16_inserter_count_crc16inserter_next_value_ce = 1'd0; +reg [15:0] sdcard_core_crc16_inserter_crc00 = 16'd0; +wire [15:0] sdcard_core_crc16_inserter_crc01; +wire [15:0] sdcard_core_crc16_inserter_crc02; +reg [15:0] sdcard_core_crc16_inserter_crc0_crc = 16'd0; +reg [1:0] sdcard_core_crc16_inserter_crc0_din = 2'd0; +wire sdcard_core_crc16_inserter_crc0_enable; +wire sdcard_core_crc16_inserter_crc0_reset; +reg [15:0] sdcard_core_crc16_inserter_crc10 = 16'd0; +wire [15:0] sdcard_core_crc16_inserter_crc11; +wire [15:0] sdcard_core_crc16_inserter_crc12; +reg [15:0] sdcard_core_crc16_inserter_crc1_crc = 16'd0; +reg [1:0] sdcard_core_crc16_inserter_crc1_din = 2'd0; +wire sdcard_core_crc16_inserter_crc1_enable; +wire sdcard_core_crc16_inserter_crc1_reset; +reg [15:0] sdcard_core_crc16_inserter_crc20 = 16'd0; +wire [15:0] sdcard_core_crc16_inserter_crc21; +wire [15:0] sdcard_core_crc16_inserter_crc22; +reg [15:0] sdcard_core_crc16_inserter_crc2_crc = 16'd0; +reg [1:0] sdcard_core_crc16_inserter_crc2_din = 2'd0; +wire sdcard_core_crc16_inserter_crc2_enable; +wire sdcard_core_crc16_inserter_crc2_reset; +reg [15:0] sdcard_core_crc16_inserter_crc30 = 16'd0; +wire [15:0] sdcard_core_crc16_inserter_crc31; +wire [15:0] sdcard_core_crc16_inserter_crc32; +reg [15:0] sdcard_core_crc16_inserter_crc3_crc = 16'd0; +reg [1:0] sdcard_core_crc16_inserter_crc3_din = 2'd0; +wire sdcard_core_crc16_inserter_crc3_enable; +wire sdcard_core_crc16_inserter_crc3_reset; +wire sdcard_core_crc16_inserter_sink_first; +wire sdcard_core_crc16_inserter_sink_last; +wire [7:0] sdcard_core_crc16_inserter_sink_payload_data; +reg sdcard_core_crc16_inserter_sink_ready = 1'd0; +wire sdcard_core_crc16_inserter_sink_valid; +reg sdcard_core_crc16_inserter_source_first = 1'd0; +reg sdcard_core_crc16_inserter_source_last = 1'd0; +reg [7:0] sdcard_core_crc16_inserter_source_payload_data = 8'd0; +reg sdcard_core_crc16_inserter_source_ready = 1'd0; +reg sdcard_core_crc16_inserter_source_valid = 1'd0; +reg [6:0] sdcard_core_crc7_inserter_crc0 = 7'd0; +wire [6:0] sdcard_core_crc7_inserter_crc1; +wire [6:0] sdcard_core_crc7_inserter_crc10; +wire [6:0] sdcard_core_crc7_inserter_crc11; +wire [6:0] sdcard_core_crc7_inserter_crc12; +wire [6:0] sdcard_core_crc7_inserter_crc13; +wire [6:0] sdcard_core_crc7_inserter_crc14; +wire [6:0] sdcard_core_crc7_inserter_crc15; +wire [6:0] sdcard_core_crc7_inserter_crc16; +wire [6:0] sdcard_core_crc7_inserter_crc17; +wire [6:0] sdcard_core_crc7_inserter_crc18; +wire [6:0] sdcard_core_crc7_inserter_crc19; +wire [6:0] sdcard_core_crc7_inserter_crc2; +wire [6:0] sdcard_core_crc7_inserter_crc20; +wire [6:0] sdcard_core_crc7_inserter_crc21; +wire [6:0] sdcard_core_crc7_inserter_crc22; +wire [6:0] sdcard_core_crc7_inserter_crc23; +wire [6:0] sdcard_core_crc7_inserter_crc24; +wire [6:0] sdcard_core_crc7_inserter_crc25; +wire [6:0] sdcard_core_crc7_inserter_crc26; +wire [6:0] sdcard_core_crc7_inserter_crc27; +wire [6:0] sdcard_core_crc7_inserter_crc28; +wire [6:0] sdcard_core_crc7_inserter_crc29; +wire [6:0] sdcard_core_crc7_inserter_crc3; +wire [6:0] sdcard_core_crc7_inserter_crc30; +wire [6:0] sdcard_core_crc7_inserter_crc31; +wire [6:0] sdcard_core_crc7_inserter_crc32; +wire [6:0] sdcard_core_crc7_inserter_crc33; +wire [6:0] sdcard_core_crc7_inserter_crc34; +wire [6:0] sdcard_core_crc7_inserter_crc35; +wire [6:0] sdcard_core_crc7_inserter_crc36; +wire [6:0] sdcard_core_crc7_inserter_crc37; +wire [6:0] sdcard_core_crc7_inserter_crc38; +wire [6:0] sdcard_core_crc7_inserter_crc39; +wire [6:0] sdcard_core_crc7_inserter_crc4; +wire [6:0] sdcard_core_crc7_inserter_crc40; +wire [6:0] sdcard_core_crc7_inserter_crc5; +wire [6:0] sdcard_core_crc7_inserter_crc6; +wire [6:0] sdcard_core_crc7_inserter_crc7; +wire [6:0] sdcard_core_crc7_inserter_crc8; +wire [6:0] sdcard_core_crc7_inserter_crc9; +reg [6:0] sdcard_core_crc7_inserter_crc_crc = 7'd0; +wire [39:0] sdcard_core_crc7_inserter_crc_din; +wire sdcard_core_crc7_inserter_crc_enable; +wire sdcard_core_crc7_inserter_crc_reset; +wire [5:0] sdcard_core_csrfield_cmd; +wire [1:0] sdcard_core_csrfield_cmd_type; +wire sdcard_core_csrfield_crc0; +wire sdcard_core_csrfield_crc1; +wire [1:0] sdcard_core_csrfield_data_type; +wire sdcard_core_csrfield_done0; +wire sdcard_core_csrfield_done1; +wire sdcard_core_csrfield_error0; +wire sdcard_core_csrfield_error1; +wire sdcard_core_csrfield_timeout0; +wire sdcard_core_csrfield_timeout1; +reg [31:0] sdcard_core_data_count = 32'd0; +reg [31:0] sdcard_core_data_count_fsm_next_value3 = 32'd0; +reg sdcard_core_data_count_fsm_next_value_ce3 = 1'd0; +reg sdcard_core_data_done = 1'd0; +reg sdcard_core_data_done_fsm_next_value1 = 1'd0; +reg sdcard_core_data_done_fsm_next_value_ce1 = 1'd0; +reg sdcard_core_data_error = 1'd0; +reg sdcard_core_data_error_fsm_next_value6 = 1'd0; +reg sdcard_core_data_error_fsm_next_value_ce6 = 1'd0; +reg sdcard_core_data_event_re = 1'd0; +reg [3:0] sdcard_core_data_event_status = 4'd0; +wire sdcard_core_data_event_we; +reg sdcard_core_data_timeout = 1'd0; +reg sdcard_core_data_timeout_fsm_next_value7 = 1'd0; +reg sdcard_core_data_timeout_fsm_next_value_ce7 = 1'd0; +wire [1:0] sdcard_core_data_type; +reg sdcard_core_done_d = 1'd0; +reg [2:0] sdcard_core_fifo_consume = 3'd0; +wire sdcard_core_fifo_do_read; +wire sdcard_core_fifo_fifo_in_first; +wire sdcard_core_fifo_fifo_in_last; +wire [7:0] sdcard_core_fifo_fifo_in_payload_data; +wire sdcard_core_fifo_fifo_out_first; +wire sdcard_core_fifo_fifo_out_last; +wire [7:0] sdcard_core_fifo_fifo_out_payload_data; +reg [3:0] sdcard_core_fifo_level = 4'd0; +reg [2:0] sdcard_core_fifo_produce = 3'd0; +wire [2:0] sdcard_core_fifo_rdport_adr; +wire [9:0] sdcard_core_fifo_rdport_dat_r; +reg sdcard_core_fifo_replace = 1'd0; +wire sdcard_core_fifo_reset; +wire sdcard_core_fifo_sink_first; +wire sdcard_core_fifo_sink_last; +wire [7:0] sdcard_core_fifo_sink_payload_data; +wire sdcard_core_fifo_sink_ready; +wire sdcard_core_fifo_sink_valid; +wire sdcard_core_fifo_source_first; +wire sdcard_core_fifo_source_last; +wire [7:0] sdcard_core_fifo_source_payload_data; +wire sdcard_core_fifo_source_ready; +wire sdcard_core_fifo_source_valid; +wire [9:0] sdcard_core_fifo_syncfifo_din; +wire [9:0] sdcard_core_fifo_syncfifo_dout; +wire sdcard_core_fifo_syncfifo_re; +wire sdcard_core_fifo_syncfifo_readable; +wire sdcard_core_fifo_syncfifo_we; +wire sdcard_core_fifo_syncfifo_writable; +reg [2:0] sdcard_core_fifo_wrport_adr = 3'd0; +wire [9:0] sdcard_core_fifo_wrport_dat_r; +wire [9:0] sdcard_core_fifo_wrport_dat_w; +wire sdcard_core_fifo_wrport_we; +reg sdcard_core_irq = 1'd0; +wire sdcard_core_sink_sink_first0; +reg sdcard_core_sink_sink_first1 = 1'd0; +wire sdcard_core_sink_sink_last0; +reg sdcard_core_sink_sink_last1 = 1'd0; +wire [7:0] sdcard_core_sink_sink_payload_data0; +reg [7:0] sdcard_core_sink_sink_payload_data1 = 8'd0; +wire sdcard_core_sink_sink_ready0; +wire sdcard_core_sink_sink_ready1; +wire sdcard_core_sink_sink_valid0; +reg sdcard_core_sink_sink_valid1 = 1'd0; +wire sdcard_core_source_source_first0; +wire sdcard_core_source_source_first1; +wire sdcard_core_source_source_last0; +wire sdcard_core_source_source_last1; +wire [7:0] sdcard_core_source_source_payload_data0; +wire [7:0] sdcard_core_source_source_payload_data1; +wire sdcard_core_source_source_ready0; +wire sdcard_core_source_source_ready1; +wire sdcard_core_source_source_valid0; +wire sdcard_core_source_source_valid1; +wire sdcard_irq_irq; +wire sdcard_mem2block_converter_converter_first; +wire sdcard_mem2block_converter_converter_last; +reg [1:0] sdcard_mem2block_converter_converter_mux = 2'd0; +wire sdcard_mem2block_converter_converter_sink_first; +wire sdcard_mem2block_converter_converter_sink_last; +wire [31:0] sdcard_mem2block_converter_converter_sink_payload_data; +wire sdcard_mem2block_converter_converter_sink_ready; +wire sdcard_mem2block_converter_converter_sink_valid; +wire sdcard_mem2block_converter_converter_source_first; +wire sdcard_mem2block_converter_converter_source_last; +reg [7:0] sdcard_mem2block_converter_converter_source_payload_data = 8'd0; +wire sdcard_mem2block_converter_converter_source_payload_valid_token_count; +wire sdcard_mem2block_converter_converter_source_ready; +wire sdcard_mem2block_converter_converter_source_valid; +wire sdcard_mem2block_converter_source_source_first; +wire sdcard_mem2block_converter_source_source_last; +wire [7:0] sdcard_mem2block_converter_source_source_payload_data; +wire sdcard_mem2block_converter_source_source_ready; +wire sdcard_mem2block_converter_source_source_valid; +reg [8:0] sdcard_mem2block_count = 9'd0; +wire [31:0] sdcard_mem2block_dma_base; +reg sdcard_mem2block_dma_base_re = 1'd0; +reg [63:0] sdcard_mem2block_dma_base_storage = 64'd0; +reg sdcard_mem2block_dma_done_re = 1'd0; +reg sdcard_mem2block_dma_done_status = 1'd0; +wire sdcard_mem2block_dma_done_we; +reg sdcard_mem2block_dma_enable_re = 1'd0; +reg sdcard_mem2block_dma_enable_storage = 1'd0; +reg [3:0] sdcard_mem2block_dma_fifo_consume = 4'd0; +wire sdcard_mem2block_dma_fifo_do_read; +wire sdcard_mem2block_dma_fifo_fifo_in_first; +wire sdcard_mem2block_dma_fifo_fifo_in_last; +wire [31:0] sdcard_mem2block_dma_fifo_fifo_in_payload_data; +wire sdcard_mem2block_dma_fifo_fifo_out_first; +wire sdcard_mem2block_dma_fifo_fifo_out_last; +wire [31:0] sdcard_mem2block_dma_fifo_fifo_out_payload_data; +reg [4:0] sdcard_mem2block_dma_fifo_level = 5'd0; +reg [3:0] sdcard_mem2block_dma_fifo_produce = 4'd0; +wire [3:0] sdcard_mem2block_dma_fifo_rdport_adr; +wire [33:0] sdcard_mem2block_dma_fifo_rdport_dat_r; +reg sdcard_mem2block_dma_fifo_replace = 1'd0; +reg sdcard_mem2block_dma_fifo_sink_first = 1'd0; +wire sdcard_mem2block_dma_fifo_sink_last; +wire [31:0] sdcard_mem2block_dma_fifo_sink_payload_data; +wire sdcard_mem2block_dma_fifo_sink_ready; +reg sdcard_mem2block_dma_fifo_sink_valid = 1'd0; +wire sdcard_mem2block_dma_fifo_source_first; +wire sdcard_mem2block_dma_fifo_source_last; +wire [31:0] sdcard_mem2block_dma_fifo_source_payload_data; +wire sdcard_mem2block_dma_fifo_source_ready; +wire sdcard_mem2block_dma_fifo_source_valid; +wire [33:0] sdcard_mem2block_dma_fifo_syncfifo_din; +wire [33:0] sdcard_mem2block_dma_fifo_syncfifo_dout; +wire sdcard_mem2block_dma_fifo_syncfifo_re; +wire sdcard_mem2block_dma_fifo_syncfifo_readable; +wire sdcard_mem2block_dma_fifo_syncfifo_we; +wire sdcard_mem2block_dma_fifo_syncfifo_writable; +reg [3:0] sdcard_mem2block_dma_fifo_wrport_adr = 4'd0; +wire [33:0] sdcard_mem2block_dma_fifo_wrport_dat_r; +wire [33:0] sdcard_mem2block_dma_fifo_wrport_dat_w; +wire sdcard_mem2block_dma_fifo_wrport_we; +wire [31:0] sdcard_mem2block_dma_length; +reg sdcard_mem2block_dma_length_re = 1'd0; +reg [31:0] sdcard_mem2block_dma_length_storage = 32'd0; +reg sdcard_mem2block_dma_loop_re = 1'd0; +reg sdcard_mem2block_dma_loop_storage = 1'd0; +reg [31:0] sdcard_mem2block_dma_offset = 32'd0; +reg sdcard_mem2block_dma_offset_re = 1'd0; +reg [31:0] sdcard_mem2block_dma_offset_sdmem2blockdma_next_value = 32'd0; +reg sdcard_mem2block_dma_offset_sdmem2blockdma_next_value_ce = 1'd0; +wire [31:0] sdcard_mem2block_dma_offset_status; +wire sdcard_mem2block_dma_offset_we; +wire sdcard_mem2block_dma_reset; +reg sdcard_mem2block_dma_sink_sink_last = 1'd0; +reg [31:0] sdcard_mem2block_dma_sink_sink_payload_address = 32'd0; +reg sdcard_mem2block_dma_sink_sink_ready = 1'd0; +reg sdcard_mem2block_dma_sink_sink_valid = 1'd0; +wire sdcard_mem2block_dma_source_source_first; +wire sdcard_mem2block_dma_source_source_last; +wire [31:0] sdcard_mem2block_dma_source_source_payload_data; +wire sdcard_mem2block_dma_source_source_ready; +wire sdcard_mem2block_dma_source_source_valid; +reg sdcard_mem2block_done_d = 1'd0; +reg [8:0] sdcard_mem2block_fifo_consume = 9'd0; +wire sdcard_mem2block_fifo_do_read; +wire sdcard_mem2block_fifo_fifo_in_first; +wire sdcard_mem2block_fifo_fifo_in_last; +wire [7:0] sdcard_mem2block_fifo_fifo_in_payload_data; +wire sdcard_mem2block_fifo_fifo_out_first; +wire sdcard_mem2block_fifo_fifo_out_last; +wire [7:0] sdcard_mem2block_fifo_fifo_out_payload_data; +reg [9:0] sdcard_mem2block_fifo_level0 = 10'd0; +wire [9:0] sdcard_mem2block_fifo_level1; +reg [8:0] sdcard_mem2block_fifo_produce = 9'd0; +wire [8:0] sdcard_mem2block_fifo_rdport_adr; +wire [9:0] sdcard_mem2block_fifo_rdport_dat_r; +wire sdcard_mem2block_fifo_rdport_re; +wire sdcard_mem2block_fifo_re; +reg sdcard_mem2block_fifo_readable = 1'd0; +reg sdcard_mem2block_fifo_replace = 1'd0; +wire sdcard_mem2block_fifo_sink_first; +wire sdcard_mem2block_fifo_sink_last; +wire [7:0] sdcard_mem2block_fifo_sink_payload_data; +wire sdcard_mem2block_fifo_sink_ready; +wire sdcard_mem2block_fifo_sink_valid; +wire sdcard_mem2block_fifo_source_first; +wire sdcard_mem2block_fifo_source_last; +wire [7:0] sdcard_mem2block_fifo_source_payload_data; +wire sdcard_mem2block_fifo_source_ready; +wire sdcard_mem2block_fifo_source_valid; +wire [9:0] sdcard_mem2block_fifo_syncfifo_din; +wire [9:0] sdcard_mem2block_fifo_syncfifo_dout; +wire sdcard_mem2block_fifo_syncfifo_re; +wire sdcard_mem2block_fifo_syncfifo_readable; +wire sdcard_mem2block_fifo_syncfifo_we; +wire sdcard_mem2block_fifo_syncfifo_writable; +reg [8:0] sdcard_mem2block_fifo_wrport_adr = 9'd0; +wire [9:0] sdcard_mem2block_fifo_wrport_dat_r; +wire [9:0] sdcard_mem2block_fifo_wrport_dat_w; +wire sdcard_mem2block_fifo_wrport_we; +reg sdcard_mem2block_irq = 1'd0; +wire sdcard_mem2block_source_source_first; +reg sdcard_mem2block_source_source_last = 1'd0; +wire [7:0] sdcard_mem2block_source_source_payload_data; +wire sdcard_mem2block_source_source_ready; +wire sdcard_mem2block_source_source_valid; +reg [1:0] sdmem2blockdma_next_state = 2'd0; +reg [1:0] sdmem2blockdma_state = 2'd0; +wire sdpads_clk; +wire sdpads_cmd_i; +wire sdpads_cmd_o; +wire sdpads_cmd_oe; +wire [3:0] sdpads_data_i; +reg sdpads_data_i_ce = 1'd0; +wire [3:0] sdpads_data_o; +wire sdpads_data_oe; +reg [2:0] sdphycmdr_next_state = 3'd0; +reg [2:0] sdphycmdr_state = 3'd0; +reg [1:0] sdphycmdw_next_state = 2'd0; +reg [1:0] sdphycmdw_state = 2'd0; +reg [2:0] sdphydatar_next_state = 3'd0; +reg [2:0] sdphydatar_state = 3'd0; +reg [2:0] sdphydataw_next_state = 3'd0; +reg [2:0] sdphydataw_state = 3'd0; +reg sdphyinit_next_state = 1'd0; +reg sdphyinit_state = 1'd0; +wire sdrio_clk; +wire sdrio_clk_1; +wire sdrio_clk_2; +wire sdrio_clk_3; +wire sdrio_clk_4; +reg [31:0] self0 = 32'd0; +reg [31:0] self1 = 32'd0; +reg [3:0] self2 = 4'd0; +reg self3 = 1'd0; +reg self4 = 1'd0; +reg self5 = 1'd0; +reg [2:0] self6 = 3'd0; +reg [1:0] self7 = 2'd0; +reg shared_ack = 1'd0; +wire [31:0] shared_adr; +wire [1:0] shared_bte; +wire [2:0] shared_cti; +wire shared_cyc; +reg [31:0] shared_dat_r = 32'd0; +wire [31:0] shared_dat_w; +wire shared_err; +wire [3:0] shared_sel; +wire shared_stb; +wire shared_we; +reg slave_sel = 1'd0; +reg slave_sel_r = 1'd0; +reg soc_rst = 1'd0; +wire sys_clk; +wire sys_rst; +wire wait_1; +wire wb_ctrl_ack_1; +wire [29:0] wb_ctrl_adr_1; +wire [1:0] wb_ctrl_bte_1; +wire [2:0] wb_ctrl_cti_1; +wire wb_ctrl_cyc_1; +wire [31:0] wb_ctrl_dat_r_1; +wire [31:0] wb_ctrl_dat_w_1; +wire wb_ctrl_err_1; +wire [3:0] wb_ctrl_sel_1; +wire wb_ctrl_stb_1; +wire wb_ctrl_we_1; +wire wb_dma_ack_1; +wire [29:0] wb_dma_adr_1; +wire [1:0] wb_dma_bte_1; +wire [2:0] wb_dma_cti_1; +wire wb_dma_cyc_1; +wire [31:0] wb_dma_dat_r_1; +wire [31:0] wb_dma_dat_w_1; +wire wb_dma_err_1; +wire [3:0] wb_dma_sel_1; +wire wb_dma_stb_1; +wire wb_dma_we_1; +wire we; +reg wishbone2csr_next_state = 1'd0; +reg wishbone2csr_state = 1'd0; + +//------------------------------------------------------------------------------ +// Combinatorial Logic +//------------------------------------------------------------------------------ + +assign wb_ctrl_adr_1 = wb_ctrl_adr; +assign wb_ctrl_dat_w_1 = wb_ctrl_dat_w; +assign wb_ctrl_dat_r = wb_ctrl_dat_r_1; +assign wb_ctrl_sel_1 = wb_ctrl_sel; +assign wb_ctrl_cyc_1 = wb_ctrl_cyc; +assign wb_ctrl_stb_1 = wb_ctrl_stb; +assign wb_ctrl_ack = wb_ctrl_ack_1; +assign wb_ctrl_we_1 = wb_ctrl_we; +assign wb_ctrl_cti_1 = wb_ctrl_cti; +assign wb_ctrl_bte_1 = wb_ctrl_bte; +assign wb_ctrl_err = wb_ctrl_err_1; +assign wb_dma_adr = wb_dma_adr_1; +assign wb_dma_dat_w = wb_dma_dat_w_1; +assign wb_dma_dat_r_1 = wb_dma_dat_r; +assign wb_dma_sel = wb_dma_sel_1; +assign wb_dma_cyc = wb_dma_cyc_1; +assign wb_dma_stb = wb_dma_stb_1; +assign wb_dma_ack_1 = wb_dma_ack; +assign wb_dma_we = wb_dma_we_1; +assign wb_dma_cti = wb_dma_cti_1; +assign wb_dma_bte = wb_dma_bte_1; +assign wb_dma_err_1 = wb_dma_err; +assign sdcard_block2mem_sink_sink_valid0 = sdcard_core_source_source_valid0; +assign sdcard_core_source_source_ready0 = sdcard_block2mem_sink_sink_ready0; +assign sdcard_block2mem_sink_sink_first = sdcard_core_source_source_first0; +assign sdcard_block2mem_sink_sink_last0 = sdcard_core_source_source_last0; +assign sdcard_block2mem_sink_sink_payload_data0 = sdcard_core_source_source_payload_data0; +assign sdcard_core_sink_sink_valid0 = sdcard_mem2block_source_source_valid; +assign sdcard_mem2block_source_source_ready = sdcard_core_sink_sink_ready0; +assign sdcard_core_sink_sink_first0 = sdcard_mem2block_source_source_first; +assign sdcard_core_sink_sink_last0 = sdcard_mem2block_source_source_last; +assign sdcard_core_sink_sink_payload_data0 = sdcard_mem2block_source_source_payload_data; +assign block2mem_dma_trigger = sdcard_block2mem_irq; +assign mem2block_dma_trigger = sdcard_mem2block_irq; +assign card_detect_trigger = card_detect_irq; +assign cmd_done_trigger = sdcard_core_csrfield_done0; +assign irq = sdcard_irq_irq; +assign sys_clk = clk; +assign por_clk = clk; +assign sys_rst = int_rst; +assign interface0_adr = wb_ctrl_adr_1; +assign interface0_dat_w = wb_ctrl_dat_w_1; +assign wb_ctrl_dat_r_1 = interface0_dat_r; +assign interface0_sel = wb_ctrl_sel_1; +assign interface0_cyc = wb_ctrl_cyc_1; +assign interface0_stb = wb_ctrl_stb_1; +assign wb_ctrl_ack_1 = interface0_ack; +assign interface0_we = wb_ctrl_we_1; +assign interface0_cti = wb_ctrl_cti_1; +assign interface0_bte = wb_ctrl_bte_1; +assign wb_ctrl_err_1 = interface0_err; +assign bus_errors_status = bus_errors; +assign shared_adr = self0; +assign shared_dat_w = self1; +assign shared_sel = self2; +assign shared_cyc = self3; +assign shared_stb = self4; +assign shared_we = self5; +assign shared_cti = self6; +assign shared_bte = self7; +assign interface0_bus_dat_r = shared_dat_r; +assign interface1_bus_dat_r = shared_dat_r; +assign interface0_bus_ack = (shared_ack & (grant == 1'd0)); +assign interface1_bus_ack = (shared_ack & (grant == 1'd1)); +assign interface0_bus_err = (shared_err & (grant == 1'd0)); +assign interface1_bus_err = (shared_err & (grant == 1'd1)); +assign request = {interface1_bus_cyc, interface0_bus_cyc}; +always @(*) begin + slave_sel <= 1'd0; + slave_sel <= 1'd1; +end +assign wb_dma_adr_1 = shared_adr; +assign wb_dma_dat_w_1 = shared_dat_w; +assign wb_dma_sel_1 = shared_sel; +assign wb_dma_stb_1 = shared_stb; +assign wb_dma_we_1 = shared_we; +assign wb_dma_cti_1 = shared_cti; +assign wb_dma_bte_1 = shared_bte; +assign wb_dma_cyc_1 = (shared_cyc & slave_sel); +assign shared_err = wb_dma_err_1; +assign wait_1 = ((shared_stb & shared_cyc) & (~shared_ack)); +always @(*) begin + error <= 1'd0; + shared_ack <= 1'd0; + shared_dat_r <= 32'd0; + shared_ack <= wb_dma_ack_1; + shared_dat_r <= ({32{slave_sel_r}} & wb_dma_dat_r_1); + if (done) begin + shared_dat_r <= 32'd4294967295; + shared_ack <= 1'd1; + error <= 1'd1; + end +end +assign done = (count == 1'd0); +assign card_detect_status0 = sdcard_cd; +assign sdpads_clk = ((((init_pads_out_payload_clk | cmdw_pads_out_payload_clk) | cmdr_pads_out_payload_clk) | dataw_pads_out_payload_clk) | datar_pads_out_payload_clk); +assign sdpads_cmd_oe = ((((init_pads_out_payload_cmd_oe | cmdw_pads_out_payload_cmd_oe) | cmdr_pads_out_payload_cmd_oe) | dataw_pads_out_payload_cmd_oe) | datar_pads_out_payload_cmd_oe); +assign sdpads_cmd_o = ((((init_pads_out_payload_cmd_o | cmdw_pads_out_payload_cmd_o) | cmdr_pads_out_payload_cmd_o) | dataw_pads_out_payload_cmd_o) | datar_pads_out_payload_cmd_o); +assign sdpads_data_oe = ((((init_pads_out_payload_data_oe | cmdw_pads_out_payload_data_oe) | cmdr_pads_out_payload_data_oe) | dataw_pads_out_payload_data_oe) | datar_pads_out_payload_data_oe); +assign sdpads_data_o = ((((init_pads_out_payload_data_o | cmdw_pads_out_payload_data_o) | cmdr_pads_out_payload_data_o) | dataw_pads_out_payload_data_o) | datar_pads_out_payload_data_o); +assign init_pads_out_ready = clocker_ce; +assign cmdw_pads_out_ready = clocker_ce; +assign cmdr_pads_out_ready = clocker_ce; +assign dataw_pads_out_ready = clocker_ce; +assign datar_pads_out_ready = clocker_ce; +assign clocker_clk_en = sdpads_clk; +assign init_pads_in_valid = sdpads_data_i_ce; +assign init_pads_in_payload_cmd_i = sdpads_cmd_i; +assign init_pads_in_payload_data_i = sdpads_data_i; +assign cmdw_pads_in_valid = sdpads_data_i_ce; +assign cmdw_pads_in_payload_cmd_i = sdpads_cmd_i; +assign cmdw_pads_in_payload_data_i = sdpads_data_i; +assign cmdr_pads_in_pads_in_valid = sdpads_data_i_ce; +assign cmdr_pads_in_pads_in_payload_cmd_i = sdpads_cmd_i; +assign cmdr_pads_in_pads_in_payload_data_i = sdpads_data_i; +assign dataw_pads_in_pads_in_valid = sdpads_data_i_ce; +assign dataw_pads_in_pads_in_payload_cmd_i = sdpads_cmd_i; +assign dataw_pads_in_pads_in_payload_data_i = sdpads_data_i; +assign datar_pads_in_pads_in_valid = sdpads_data_i_ce; +assign datar_pads_in_pads_in_payload_cmd_i = sdpads_cmd_i; +assign datar_pads_in_pads_in_payload_data_i = sdpads_data_i; +assign clocker_stop = (dataw_stop | datar_stop); +always @(*) begin + clocker_clk1 <= 1'd0; + case (clocker_storage) + 3'd4: begin + clocker_clk1 <= clocker_clks[1]; + end + 4'd8: begin + clocker_clk1 <= clocker_clks[2]; + end + 5'd16: begin + clocker_clk1 <= clocker_clks[3]; + end + 6'd32: begin + clocker_clk1 <= clocker_clks[4]; + end + 7'd64: begin + clocker_clk1 <= clocker_clks[5]; + end + 8'd128: begin + clocker_clk1 <= clocker_clks[6]; + end + 9'd256: begin + clocker_clk1 <= clocker_clks[7]; + end + default: begin + clocker_clk1 <= clocker_clks[0]; + end + endcase +end +assign clocker_ce = (clocker_clk1 & (~clocker_clk_d)); +always @(*) begin + clocker_ce_latched <= 1'd0; + if (clocker_clk_d) begin + clocker_ce_latched <= clocker_clk_en; + end else begin + clocker_ce_latched <= clocker_ce_delayed; + end +end +assign clocker_clk0 = ((~clocker_clk1) & clocker_ce_latched); +always @(*) begin + init_count_sdphyinit_next_value <= 8'd0; + init_count_sdphyinit_next_value_ce <= 1'd0; + init_pads_out_payload_clk <= 1'd0; + init_pads_out_payload_cmd_o <= 1'd0; + init_pads_out_payload_cmd_oe <= 1'd0; + init_pads_out_payload_data_o <= 4'd0; + init_pads_out_payload_data_oe <= 1'd0; + sdphyinit_next_state <= 1'd0; + sdphyinit_next_state <= sdphyinit_state; + case (sdphyinit_state) + 1'd1: begin + init_pads_out_payload_clk <= 1'd1; + init_pads_out_payload_cmd_oe <= 1'd1; + init_pads_out_payload_cmd_o <= 1'd1; + init_pads_out_payload_data_oe <= 1'd1; + init_pads_out_payload_data_o <= 4'd15; + if (init_pads_out_ready) begin + init_count_sdphyinit_next_value <= (init_count + 1'd1); + init_count_sdphyinit_next_value_ce <= 1'd1; + if ((init_count == 7'd79)) begin + sdphyinit_next_state <= 1'd0; + end + end + end + default: begin + init_count_sdphyinit_next_value <= 1'd0; + init_count_sdphyinit_next_value_ce <= 1'd1; + if (init_initialize_re) begin + sdphyinit_next_state <= 1'd1; + end + end + endcase +end +always @(*) begin + cmdw_count_sdphycmdw_next_value <= 8'd0; + cmdw_count_sdphycmdw_next_value_ce <= 1'd0; + cmdw_done <= 1'd0; + cmdw_pads_out_payload_clk <= 1'd0; + cmdw_pads_out_payload_cmd_o <= 1'd0; + cmdw_pads_out_payload_cmd_oe <= 1'd0; + cmdw_sink_ready <= 1'd0; + sdphycmdw_next_state <= 2'd0; + sdphycmdw_next_state <= sdphycmdw_state; + case (sdphycmdw_state) + 1'd1: begin + cmdw_pads_out_payload_clk <= 1'd1; + cmdw_pads_out_payload_cmd_oe <= 1'd1; + case (cmdw_count) + 1'd0: begin + cmdw_pads_out_payload_cmd_o <= cmdw_sink_payload_data[7]; + end + 1'd1: begin + cmdw_pads_out_payload_cmd_o <= cmdw_sink_payload_data[6]; + end + 2'd2: begin + cmdw_pads_out_payload_cmd_o <= cmdw_sink_payload_data[5]; + end + 2'd3: begin + cmdw_pads_out_payload_cmd_o <= cmdw_sink_payload_data[4]; + end + 3'd4: begin + cmdw_pads_out_payload_cmd_o <= cmdw_sink_payload_data[3]; + end + 3'd5: begin + cmdw_pads_out_payload_cmd_o <= cmdw_sink_payload_data[2]; + end + 3'd6: begin + cmdw_pads_out_payload_cmd_o <= cmdw_sink_payload_data[1]; + end + 3'd7: begin + cmdw_pads_out_payload_cmd_o <= cmdw_sink_payload_data[0]; + end + endcase + if (cmdw_pads_out_ready) begin + cmdw_count_sdphycmdw_next_value <= (cmdw_count + 1'd1); + cmdw_count_sdphycmdw_next_value_ce <= 1'd1; + if ((cmdw_count == 3'd7)) begin + if ((cmdw_sink_last & (cmdw_sink_payload_cmd_type == 1'd0))) begin + sdphycmdw_next_state <= 2'd2; + end else begin + cmdw_sink_ready <= 1'd1; + sdphycmdw_next_state <= 1'd0; + end + end + end + end + 2'd2: begin + cmdw_pads_out_payload_clk <= 1'd1; + cmdw_pads_out_payload_cmd_oe <= 1'd1; + cmdw_pads_out_payload_cmd_o <= 1'd1; + if (cmdw_pads_out_ready) begin + cmdw_count_sdphycmdw_next_value <= (cmdw_count + 1'd1); + cmdw_count_sdphycmdw_next_value_ce <= 1'd1; + if ((cmdw_count == 3'd7)) begin + cmdw_sink_ready <= 1'd1; + sdphycmdw_next_state <= 1'd0; + end + end + end + default: begin + cmdw_count_sdphycmdw_next_value <= 1'd0; + cmdw_count_sdphycmdw_next_value_ce <= 1'd1; + if ((cmdw_sink_valid & cmdw_pads_out_ready)) begin + sdphycmdw_next_state <= 1'd1; + end else begin + cmdw_done <= 1'd1; + end + end + endcase +end +assign cmdr_cmdr_pads_in_valid = cmdr_pads_in_pads_in_valid; +assign cmdr_pads_in_pads_in_ready = cmdr_cmdr_pads_in_ready; +assign cmdr_cmdr_pads_in_first = cmdr_pads_in_pads_in_first; +assign cmdr_cmdr_pads_in_last = cmdr_pads_in_pads_in_last; +assign cmdr_cmdr_pads_in_payload_clk = cmdr_pads_in_pads_in_payload_clk; +assign cmdr_cmdr_pads_in_payload_cmd_i = cmdr_pads_in_pads_in_payload_cmd_i; +assign cmdr_cmdr_pads_in_payload_cmd_o = cmdr_pads_in_pads_in_payload_cmd_o; +assign cmdr_cmdr_pads_in_payload_cmd_oe = cmdr_pads_in_pads_in_payload_cmd_oe; +assign cmdr_cmdr_pads_in_payload_data_i = cmdr_pads_in_pads_in_payload_data_i; +assign cmdr_cmdr_pads_in_payload_data_o = cmdr_pads_in_pads_in_payload_data_o; +assign cmdr_cmdr_pads_in_payload_data_oe = cmdr_pads_in_pads_in_payload_data_oe; +assign cmdr_cmdr_pads_in_payload_data_i_ce = cmdr_pads_in_pads_in_payload_data_i_ce; +assign cmdr_cmdr_start = (cmdr_cmdr_pads_in_payload_cmd_i == 1'd0); +assign cmdr_cmdr_converter_converter_sink_valid = (cmdr_cmdr_pads_in_valid & (cmdr_cmdr_start | cmdr_cmdr_run)); +assign cmdr_cmdr_converter_converter_sink_payload_data = cmdr_cmdr_pads_in_payload_cmd_i; +assign cmdr_cmdr_buf_sink_sink_valid = cmdr_cmdr_converter_source_source_valid; +assign cmdr_cmdr_converter_source_source_ready = cmdr_cmdr_buf_sink_sink_ready; +assign cmdr_cmdr_buf_sink_sink_first = cmdr_cmdr_converter_source_source_first; +assign cmdr_cmdr_buf_sink_sink_last = cmdr_cmdr_converter_source_source_last; +assign cmdr_cmdr_buf_sink_sink_payload_data = cmdr_cmdr_converter_source_source_payload_data; +assign cmdr_cmdr_source_valid = cmdr_cmdr_buf_source_source_valid; +assign cmdr_cmdr_buf_source_source_ready = cmdr_cmdr_source_ready; +assign cmdr_cmdr_source_first = cmdr_cmdr_buf_source_source_first; +assign cmdr_cmdr_source_last = cmdr_cmdr_buf_source_source_last; +assign cmdr_cmdr_source_payload_data = cmdr_cmdr_buf_source_source_payload_data; +assign cmdr_cmdr_converter_source_source_valid = cmdr_cmdr_converter_converter_source_valid; +assign cmdr_cmdr_converter_converter_source_ready = cmdr_cmdr_converter_source_source_ready; +assign cmdr_cmdr_converter_source_source_first = cmdr_cmdr_converter_converter_source_first; +assign cmdr_cmdr_converter_source_source_last = cmdr_cmdr_converter_converter_source_last; +assign cmdr_cmdr_converter_source_source_payload_data = cmdr_cmdr_converter_converter_source_payload_data; +assign cmdr_cmdr_converter_converter_sink_ready = ((~cmdr_cmdr_converter_converter_strobe_all) | cmdr_cmdr_converter_converter_source_ready); +assign cmdr_cmdr_converter_converter_source_valid = cmdr_cmdr_converter_converter_strobe_all; +assign cmdr_cmdr_converter_converter_load_part = (cmdr_cmdr_converter_converter_sink_valid & cmdr_cmdr_converter_converter_sink_ready); +assign cmdr_cmdr_buf_pipe_valid_sink_ready = ((~cmdr_cmdr_buf_pipe_valid_source_valid) | cmdr_cmdr_buf_pipe_valid_source_ready); +assign cmdr_cmdr_buf_pipe_valid_sink_valid = cmdr_cmdr_buf_sink_sink_valid; +assign cmdr_cmdr_buf_sink_sink_ready = cmdr_cmdr_buf_pipe_valid_sink_ready; +assign cmdr_cmdr_buf_pipe_valid_sink_first = cmdr_cmdr_buf_sink_sink_first; +assign cmdr_cmdr_buf_pipe_valid_sink_last = cmdr_cmdr_buf_sink_sink_last; +assign cmdr_cmdr_buf_pipe_valid_sink_payload_data = cmdr_cmdr_buf_sink_sink_payload_data; +assign cmdr_cmdr_buf_source_source_valid = cmdr_cmdr_buf_pipe_valid_source_valid; +assign cmdr_cmdr_buf_pipe_valid_source_ready = cmdr_cmdr_buf_source_source_ready; +assign cmdr_cmdr_buf_source_source_first = cmdr_cmdr_buf_pipe_valid_source_first; +assign cmdr_cmdr_buf_source_source_last = cmdr_cmdr_buf_pipe_valid_source_last; +assign cmdr_cmdr_buf_source_source_payload_data = cmdr_cmdr_buf_pipe_valid_source_payload_data; +always @(*) begin + cmdr_busy_sdphycmdr_next_value2 <= 1'd0; + cmdr_busy_sdphycmdr_next_value_ce2 <= 1'd0; + cmdr_cmdr_reset_sdphycmdr_next_value3 <= 1'd0; + cmdr_cmdr_reset_sdphycmdr_next_value_ce3 <= 1'd0; + cmdr_cmdr_source_ready <= 1'd0; + cmdr_count_sdphycmdr_next_value1 <= 8'd0; + cmdr_count_sdphycmdr_next_value_ce1 <= 1'd0; + cmdr_pads_out_payload_clk <= 1'd0; + cmdr_pads_out_payload_cmd_o <= 1'd0; + cmdr_pads_out_payload_cmd_oe <= 1'd0; + cmdr_sink_ready <= 1'd0; + cmdr_source_source_last <= 1'd0; + cmdr_source_source_payload_data <= 8'd0; + cmdr_source_source_payload_status <= 3'd0; + cmdr_source_source_valid <= 1'd0; + cmdr_timeout_sdphycmdr_next_value0 <= 32'd0; + cmdr_timeout_sdphycmdr_next_value_ce0 <= 1'd0; + sdphycmdr_next_state <= 3'd0; + sdphycmdr_next_state <= sdphycmdr_state; + case (sdphycmdr_state) + 1'd1: begin + cmdr_pads_out_payload_clk <= 1'd1; + cmdr_cmdr_reset_sdphycmdr_next_value3 <= 1'd0; + cmdr_cmdr_reset_sdphycmdr_next_value_ce3 <= 1'd1; + if (cmdr_cmdr_source_valid) begin + sdphycmdr_next_state <= 2'd2; + end + cmdr_timeout_sdphycmdr_next_value0 <= (cmdr_timeout - 1'd1); + cmdr_timeout_sdphycmdr_next_value_ce0 <= 1'd1; + if ((cmdr_timeout == 1'd0)) begin + sdphycmdr_next_state <= 3'd5; + end + end + 2'd2: begin + cmdr_pads_out_payload_clk <= 1'd1; + cmdr_source_source_valid <= cmdr_cmdr_source_valid; + cmdr_source_source_payload_status <= 1'd0; + cmdr_source_source_last <= (cmdr_count == (cmdr_sink_payload_length - 1'd1)); + cmdr_source_source_payload_data <= cmdr_cmdr_source_payload_data; + if ((cmdr_cmdr_source_valid & cmdr_source_source_ready)) begin + cmdr_cmdr_source_ready <= 1'd1; + cmdr_count_sdphycmdr_next_value1 <= (cmdr_count + 1'd1); + cmdr_count_sdphycmdr_next_value_ce1 <= 1'd1; + if (cmdr_source_source_last) begin + cmdr_sink_ready <= 1'd1; + if ((cmdr_sink_payload_cmd_type == 2'd3)) begin + cmdr_source_source_valid <= 1'd0; + cmdr_timeout_sdphycmdr_next_value0 <= 26'd50000000; + cmdr_timeout_sdphycmdr_next_value_ce0 <= 1'd1; + sdphycmdr_next_state <= 2'd3; + end else begin + if ((cmdr_sink_payload_data_type == 1'd0)) begin + cmdr_count_sdphycmdr_next_value1 <= 1'd0; + cmdr_count_sdphycmdr_next_value_ce1 <= 1'd1; + sdphycmdr_next_state <= 3'd4; + end else begin + sdphycmdr_next_state <= 1'd0; + end + end + end + end + cmdr_timeout_sdphycmdr_next_value0 <= (cmdr_timeout - 1'd1); + cmdr_timeout_sdphycmdr_next_value_ce0 <= 1'd1; + if ((cmdr_timeout == 1'd0)) begin + sdphycmdr_next_state <= 3'd5; + end + end + 2'd3: begin + cmdr_pads_out_payload_clk <= 1'd1; + if ((cmdr_pads_in_pads_in_valid & cmdr_pads_in_pads_in_payload_data_i[0])) begin + cmdr_busy_sdphycmdr_next_value2 <= 1'd0; + cmdr_busy_sdphycmdr_next_value_ce2 <= 1'd1; + end + if ((~cmdr_busy)) begin + cmdr_source_source_valid <= 1'd1; + cmdr_source_source_last <= 1'd1; + cmdr_source_source_payload_status <= 1'd0; + if (cmdr_source_source_ready) begin + cmdr_count_sdphycmdr_next_value1 <= 1'd0; + cmdr_count_sdphycmdr_next_value_ce1 <= 1'd1; + sdphycmdr_next_state <= 3'd4; + end + end + cmdr_timeout_sdphycmdr_next_value0 <= (cmdr_timeout - 1'd1); + cmdr_timeout_sdphycmdr_next_value_ce0 <= 1'd1; + if ((cmdr_timeout == 1'd0)) begin + sdphycmdr_next_state <= 3'd5; + end + end + 3'd4: begin + cmdr_pads_out_payload_clk <= 1'd1; + cmdr_pads_out_payload_cmd_oe <= 1'd1; + cmdr_pads_out_payload_cmd_o <= 1'd1; + if (cmdr_pads_out_ready) begin + cmdr_count_sdphycmdr_next_value1 <= (cmdr_count + 1'd1); + cmdr_count_sdphycmdr_next_value_ce1 <= 1'd1; + if ((cmdr_count == 3'd7)) begin + sdphycmdr_next_state <= 1'd0; + end + end + end + 3'd5: begin + cmdr_sink_ready <= 1'd1; + cmdr_source_source_valid <= 1'd1; + cmdr_source_source_last <= 1'd1; + cmdr_source_source_payload_status <= 1'd1; + if (cmdr_source_source_ready) begin + sdphycmdr_next_state <= 1'd0; + end + end + default: begin + cmdr_timeout_sdphycmdr_next_value0 <= 26'd50000000; + cmdr_timeout_sdphycmdr_next_value_ce0 <= 1'd1; + cmdr_count_sdphycmdr_next_value1 <= 1'd0; + cmdr_count_sdphycmdr_next_value_ce1 <= 1'd1; + cmdr_busy_sdphycmdr_next_value2 <= 1'd1; + cmdr_busy_sdphycmdr_next_value_ce2 <= 1'd1; + if (((cmdr_sink_valid & cmdr_pads_out_ready) & cmdw_done)) begin + cmdr_cmdr_reset_sdphycmdr_next_value3 <= 1'd1; + cmdr_cmdr_reset_sdphycmdr_next_value_ce3 <= 1'd1; + sdphycmdr_next_state <= 1'd1; + end + end + endcase +end +assign dataw_accepted0 = dataw_accepted1; +assign dataw_crc_error0 = dataw_crc_error1; +assign dataw_write_error0 = dataw_write_error1; +assign dataw_crc_pads_in_valid = dataw_pads_in_pads_in_valid; +assign dataw_crc_pads_in_ready = dataw_pads_in_pads_in_ready; +assign dataw_crc_pads_in_first = dataw_pads_in_pads_in_first; +assign dataw_crc_pads_in_last = dataw_pads_in_pads_in_last; +assign dataw_crc_pads_in_payload_clk = dataw_pads_in_pads_in_payload_clk; +assign dataw_crc_pads_in_payload_cmd_i = dataw_pads_in_pads_in_payload_cmd_i; +assign dataw_crc_pads_in_payload_cmd_o = dataw_pads_in_pads_in_payload_cmd_o; +assign dataw_crc_pads_in_payload_cmd_oe = dataw_pads_in_pads_in_payload_cmd_oe; +assign dataw_crc_pads_in_payload_data_i = dataw_pads_in_pads_in_payload_data_i; +assign dataw_crc_pads_in_payload_data_o = dataw_pads_in_pads_in_payload_data_o; +assign dataw_crc_pads_in_payload_data_oe = dataw_pads_in_pads_in_payload_data_oe; +assign dataw_crc_pads_in_payload_data_i_ce = dataw_pads_in_pads_in_payload_data_i_ce; +assign dataw_crc_start = (dataw_crc_pads_in_payload_data_i[0] == 1'd0); +assign dataw_crc_converter_converter_sink_valid = (dataw_crc_pads_in_valid & dataw_crc_run); +assign dataw_crc_converter_converter_sink_payload_data = dataw_crc_pads_in_payload_data_i[0]; +assign dataw_crc_buf_sink_sink_valid = dataw_crc_converter_source_source_valid; +assign dataw_crc_converter_source_source_ready = dataw_crc_buf_sink_sink_ready; +assign dataw_crc_buf_sink_sink_first = dataw_crc_converter_source_source_first; +assign dataw_crc_buf_sink_sink_last = dataw_crc_converter_source_source_last; +assign dataw_crc_buf_sink_sink_payload_data = dataw_crc_converter_source_source_payload_data; +assign dataw_crc_source_valid = dataw_crc_buf_source_source_valid; +assign dataw_crc_buf_source_source_ready = dataw_crc_source_ready; +assign dataw_crc_source_first = dataw_crc_buf_source_source_first; +assign dataw_crc_source_last = dataw_crc_buf_source_source_last; +assign dataw_crc_source_payload_data = dataw_crc_buf_source_source_payload_data; +assign dataw_crc_converter_source_source_valid = dataw_crc_converter_converter_source_valid; +assign dataw_crc_converter_converter_source_ready = dataw_crc_converter_source_source_ready; +assign dataw_crc_converter_source_source_first = dataw_crc_converter_converter_source_first; +assign dataw_crc_converter_source_source_last = dataw_crc_converter_converter_source_last; +assign dataw_crc_converter_source_source_payload_data = dataw_crc_converter_converter_source_payload_data; +assign dataw_crc_converter_converter_sink_ready = ((~dataw_crc_converter_converter_strobe_all) | dataw_crc_converter_converter_source_ready); +assign dataw_crc_converter_converter_source_valid = dataw_crc_converter_converter_strobe_all; +assign dataw_crc_converter_converter_load_part = (dataw_crc_converter_converter_sink_valid & dataw_crc_converter_converter_sink_ready); +assign dataw_crc_buf_pipe_valid_sink_ready = ((~dataw_crc_buf_pipe_valid_source_valid) | dataw_crc_buf_pipe_valid_source_ready); +assign dataw_crc_buf_pipe_valid_sink_valid = dataw_crc_buf_sink_sink_valid; +assign dataw_crc_buf_sink_sink_ready = dataw_crc_buf_pipe_valid_sink_ready; +assign dataw_crc_buf_pipe_valid_sink_first = dataw_crc_buf_sink_sink_first; +assign dataw_crc_buf_pipe_valid_sink_last = dataw_crc_buf_sink_sink_last; +assign dataw_crc_buf_pipe_valid_sink_payload_data = dataw_crc_buf_sink_sink_payload_data; +assign dataw_crc_buf_source_source_valid = dataw_crc_buf_pipe_valid_source_valid; +assign dataw_crc_buf_pipe_valid_source_ready = dataw_crc_buf_source_source_ready; +assign dataw_crc_buf_source_source_first = dataw_crc_buf_pipe_valid_source_first; +assign dataw_crc_buf_source_source_last = dataw_crc_buf_pipe_valid_source_last; +assign dataw_crc_buf_source_source_payload_data = dataw_crc_buf_pipe_valid_source_payload_data; +always @(*) begin + dataw_accepted1_sdphydataw_next_value0 <= 1'd0; + dataw_accepted1_sdphydataw_next_value_ce0 <= 1'd0; + dataw_count_sdphydataw_next_value3 <= 8'd0; + dataw_count_sdphydataw_next_value_ce3 <= 1'd0; + dataw_crc_error1_sdphydataw_next_value1 <= 1'd0; + dataw_crc_error1_sdphydataw_next_value_ce1 <= 1'd0; + dataw_crc_reset <= 1'd0; + dataw_pads_out_payload_clk <= 1'd0; + dataw_pads_out_payload_cmd_o <= 1'd0; + dataw_pads_out_payload_cmd_oe <= 1'd0; + dataw_pads_out_payload_data_o <= 4'd0; + dataw_pads_out_payload_data_oe <= 1'd0; + dataw_sink_ready <= 1'd0; + dataw_stop <= 1'd0; + dataw_write_error1_sdphydataw_next_value2 <= 1'd0; + dataw_write_error1_sdphydataw_next_value_ce2 <= 1'd0; + sdphydataw_next_state <= 3'd0; + sdphydataw_next_state <= sdphydataw_state; + case (sdphydataw_state) + 1'd1: begin + dataw_pads_out_payload_clk <= 1'd1; + dataw_pads_out_payload_cmd_oe <= 1'd1; + dataw_pads_out_payload_cmd_o <= 1'd1; + if (dataw_pads_out_ready) begin + dataw_count_sdphydataw_next_value3 <= (dataw_count + 1'd1); + dataw_count_sdphydataw_next_value_ce3 <= 1'd1; + if ((dataw_count == 3'd7)) begin + dataw_count_sdphydataw_next_value3 <= 1'd0; + dataw_count_sdphydataw_next_value_ce3 <= 1'd1; + sdphydataw_next_state <= 2'd2; + end + end + end + 2'd2: begin + dataw_pads_out_payload_clk <= 1'd1; + dataw_pads_out_payload_data_oe <= 1'd1; + dataw_pads_out_payload_data_o <= 1'd0; + if (dataw_pads_out_ready) begin + sdphydataw_next_state <= 2'd3; + end + end + 2'd3: begin + dataw_stop <= (~dataw_sink_valid); + dataw_pads_out_payload_clk <= 1'd1; + dataw_pads_out_payload_data_oe <= 1'd1; + case (dataw_count) + 1'd0: begin + dataw_pads_out_payload_data_o <= dataw_sink_payload_data[7:4]; + end + 1'd1: begin + dataw_pads_out_payload_data_o <= dataw_sink_payload_data[3:0]; + end + endcase + if (dataw_pads_out_ready) begin + dataw_count_sdphydataw_next_value3 <= (dataw_count + 1'd1); + dataw_count_sdphydataw_next_value_ce3 <= 1'd1; + if ((dataw_count == 1'd1)) begin + dataw_count_sdphydataw_next_value3 <= 1'd0; + dataw_count_sdphydataw_next_value_ce3 <= 1'd1; + if (dataw_sink_last) begin + sdphydataw_next_state <= 3'd4; + end else begin + dataw_sink_ready <= 1'd1; + end + end + end + end + 3'd4: begin + dataw_pads_out_payload_clk <= 1'd1; + dataw_pads_out_payload_data_oe <= 1'd1; + dataw_pads_out_payload_data_o <= 4'd15; + if (dataw_pads_out_ready) begin + dataw_crc_reset <= 1'd1; + sdphydataw_next_state <= 3'd5; + end + end + 3'd5: begin + dataw_pads_out_payload_clk <= 1'd1; + if (dataw_crc_source_valid) begin + dataw_accepted1_sdphydataw_next_value0 <= (dataw_crc_source_payload_data[7:5] == 2'd2); + dataw_accepted1_sdphydataw_next_value_ce0 <= 1'd1; + dataw_crc_error1_sdphydataw_next_value1 <= (dataw_crc_source_payload_data[7:5] == 3'd5); + dataw_crc_error1_sdphydataw_next_value_ce1 <= 1'd1; + dataw_write_error1_sdphydataw_next_value2 <= (dataw_crc_source_payload_data[7:5] == 3'd6); + dataw_write_error1_sdphydataw_next_value_ce2 <= 1'd1; + sdphydataw_next_state <= 3'd6; + end + end + 3'd6: begin + dataw_pads_out_payload_clk <= 1'd1; + if ((dataw_pads_in_pads_in_valid & dataw_pads_in_pads_in_payload_data_i[0])) begin + dataw_sink_ready <= 1'd1; + sdphydataw_next_state <= 1'd0; + end + end + default: begin + dataw_accepted1_sdphydataw_next_value0 <= 1'd0; + dataw_accepted1_sdphydataw_next_value_ce0 <= 1'd1; + dataw_crc_error1_sdphydataw_next_value1 <= 1'd0; + dataw_crc_error1_sdphydataw_next_value_ce1 <= 1'd1; + dataw_write_error1_sdphydataw_next_value2 <= 1'd0; + dataw_write_error1_sdphydataw_next_value_ce2 <= 1'd1; + dataw_count_sdphydataw_next_value3 <= 1'd0; + dataw_count_sdphydataw_next_value_ce3 <= 1'd1; + if ((dataw_sink_valid & dataw_pads_out_ready)) begin + sdphydataw_next_state <= 1'd1; + end + end + endcase +end +assign datar_datar_pads_in_valid = datar_pads_in_pads_in_valid; +assign datar_pads_in_pads_in_ready = datar_datar_pads_in_ready; +assign datar_datar_pads_in_first = datar_pads_in_pads_in_first; +assign datar_datar_pads_in_last = datar_pads_in_pads_in_last; +assign datar_datar_pads_in_payload_clk = datar_pads_in_pads_in_payload_clk; +assign datar_datar_pads_in_payload_cmd_i = datar_pads_in_pads_in_payload_cmd_i; +assign datar_datar_pads_in_payload_cmd_o = datar_pads_in_pads_in_payload_cmd_o; +assign datar_datar_pads_in_payload_cmd_oe = datar_pads_in_pads_in_payload_cmd_oe; +assign datar_datar_pads_in_payload_data_i = datar_pads_in_pads_in_payload_data_i; +assign datar_datar_pads_in_payload_data_o = datar_pads_in_pads_in_payload_data_o; +assign datar_datar_pads_in_payload_data_oe = datar_pads_in_pads_in_payload_data_oe; +assign datar_datar_pads_in_payload_data_i_ce = datar_pads_in_pads_in_payload_data_i_ce; +assign datar_datar_start = (datar_datar_pads_in_payload_data_i[3:0] == 1'd0); +assign datar_datar_converter_converter_sink_valid = (datar_datar_pads_in_valid & datar_datar_run); +assign datar_datar_converter_converter_sink_payload_data = datar_datar_pads_in_payload_data_i[3:0]; +assign datar_datar_buf_sink_sink_valid = datar_datar_converter_source_source_valid; +assign datar_datar_converter_source_source_ready = datar_datar_buf_sink_sink_ready; +assign datar_datar_buf_sink_sink_first = datar_datar_converter_source_source_first; +assign datar_datar_buf_sink_sink_last = datar_datar_converter_source_source_last; +assign datar_datar_buf_sink_sink_payload_data = datar_datar_converter_source_source_payload_data; +assign datar_datar_source_valid = datar_datar_buf_source_source_valid; +assign datar_datar_buf_source_source_ready = datar_datar_source_ready; +assign datar_datar_source_first = datar_datar_buf_source_source_first; +assign datar_datar_source_last = datar_datar_buf_source_source_last; +assign datar_datar_source_payload_data = datar_datar_buf_source_source_payload_data; +assign datar_datar_converter_source_source_valid = datar_datar_converter_converter_source_valid; +assign datar_datar_converter_converter_source_ready = datar_datar_converter_source_source_ready; +assign datar_datar_converter_source_source_first = datar_datar_converter_converter_source_first; +assign datar_datar_converter_source_source_last = datar_datar_converter_converter_source_last; +assign datar_datar_converter_source_source_payload_data = datar_datar_converter_converter_source_payload_data; +assign datar_datar_converter_converter_sink_ready = ((~datar_datar_converter_converter_strobe_all) | datar_datar_converter_converter_source_ready); +assign datar_datar_converter_converter_source_valid = datar_datar_converter_converter_strobe_all; +assign datar_datar_converter_converter_load_part = (datar_datar_converter_converter_sink_valid & datar_datar_converter_converter_sink_ready); +assign datar_datar_buf_pipe_valid_sink_ready = ((~datar_datar_buf_pipe_valid_source_valid) | datar_datar_buf_pipe_valid_source_ready); +assign datar_datar_buf_pipe_valid_sink_valid = datar_datar_buf_sink_sink_valid; +assign datar_datar_buf_sink_sink_ready = datar_datar_buf_pipe_valid_sink_ready; +assign datar_datar_buf_pipe_valid_sink_first = datar_datar_buf_sink_sink_first; +assign datar_datar_buf_pipe_valid_sink_last = datar_datar_buf_sink_sink_last; +assign datar_datar_buf_pipe_valid_sink_payload_data = datar_datar_buf_sink_sink_payload_data; +assign datar_datar_buf_source_source_valid = datar_datar_buf_pipe_valid_source_valid; +assign datar_datar_buf_pipe_valid_source_ready = datar_datar_buf_source_source_ready; +assign datar_datar_buf_source_source_first = datar_datar_buf_pipe_valid_source_first; +assign datar_datar_buf_source_source_last = datar_datar_buf_pipe_valid_source_last; +assign datar_datar_buf_source_source_payload_data = datar_datar_buf_pipe_valid_source_payload_data; +always @(*) begin + datar_count_sdphydatar_next_value0 <= 10'd0; + datar_count_sdphydatar_next_value_ce0 <= 1'd0; + datar_datar_reset_sdphydatar_next_value2 <= 1'd0; + datar_datar_reset_sdphydatar_next_value_ce2 <= 1'd0; + datar_datar_source_ready <= 1'd0; + datar_pads_out_payload_clk <= 1'd0; + datar_sink_ready <= 1'd0; + datar_source_source_first <= 1'd0; + datar_source_source_last <= 1'd0; + datar_source_source_payload_data <= 8'd0; + datar_source_source_payload_status <= 3'd0; + datar_source_source_valid <= 1'd0; + datar_stop <= 1'd0; + datar_timeout_sdphydatar_next_value1 <= 32'd0; + datar_timeout_sdphydatar_next_value_ce1 <= 1'd0; + sdphydatar_next_state <= 3'd0; + sdphydatar_next_state <= sdphydatar_state; + case (sdphydatar_state) + 1'd1: begin + datar_pads_out_payload_clk <= 1'd1; + datar_datar_reset_sdphydatar_next_value2 <= 1'd0; + datar_datar_reset_sdphydatar_next_value_ce2 <= 1'd1; + datar_timeout_sdphydatar_next_value1 <= (datar_timeout - 1'd1); + datar_timeout_sdphydatar_next_value_ce1 <= 1'd1; + if (datar_datar_source_valid) begin + sdphydatar_next_state <= 2'd2; + end + datar_timeout_sdphydatar_next_value1 <= (datar_timeout - 1'd1); + datar_timeout_sdphydatar_next_value_ce1 <= 1'd1; + if ((datar_timeout == 1'd0)) begin + datar_sink_ready <= 1'd1; + sdphydatar_next_state <= 3'd4; + end + end + 2'd2: begin + datar_pads_out_payload_clk <= 1'd1; + datar_source_source_valid <= datar_datar_source_valid; + datar_source_source_payload_status <= 1'd0; + datar_source_source_first <= (datar_count == 1'd0); + datar_source_source_last <= (datar_count == ((datar_sink_payload_block_length + 4'd8) - 1'd1)); + datar_source_source_payload_data <= datar_datar_source_payload_data; + if (datar_source_source_valid) begin + if (datar_source_source_ready) begin + datar_datar_source_ready <= 1'd1; + datar_count_sdphydatar_next_value0 <= (datar_count + 1'd1); + datar_count_sdphydatar_next_value_ce0 <= 1'd1; + if (datar_source_source_last) begin + datar_sink_ready <= 1'd1; + if (datar_sink_last) begin + datar_count_sdphydatar_next_value0 <= 1'd0; + datar_count_sdphydatar_next_value_ce0 <= 1'd1; + sdphydatar_next_state <= 2'd3; + end else begin + sdphydatar_next_state <= 1'd0; + end + end + end else begin + datar_stop <= 1'd1; + end + end + datar_timeout_sdphydatar_next_value1 <= (datar_timeout - 1'd1); + datar_timeout_sdphydatar_next_value_ce1 <= 1'd1; + if ((datar_timeout == 1'd0)) begin + datar_sink_ready <= 1'd1; + sdphydatar_next_state <= 3'd4; + end + end + 2'd3: begin + datar_pads_out_payload_clk <= 1'd1; + if (datar_pads_out_ready) begin + datar_count_sdphydatar_next_value0 <= (datar_count + 1'd1); + datar_count_sdphydatar_next_value_ce0 <= 1'd1; + if ((datar_count == 6'd39)) begin + sdphydatar_next_state <= 1'd0; + end + end + end + 3'd4: begin + datar_source_source_valid <= 1'd1; + datar_source_source_payload_status <= 1'd1; + datar_source_source_last <= 1'd1; + if (datar_source_source_ready) begin + sdphydatar_next_state <= 1'd0; + end + end + default: begin + datar_count_sdphydatar_next_value0 <= 1'd0; + datar_count_sdphydatar_next_value_ce0 <= 1'd1; + if ((datar_sink_valid & datar_pads_out_ready)) begin + datar_pads_out_payload_clk <= 1'd1; + datar_timeout_sdphydatar_next_value1 <= 32'd50000000; + datar_timeout_sdphydatar_next_value_ce1 <= 1'd1; + datar_count_sdphydatar_next_value0 <= 1'd0; + datar_count_sdphydatar_next_value_ce0 <= 1'd1; + datar_datar_reset_sdphydatar_next_value2 <= 1'd1; + datar_datar_reset_sdphydatar_next_value_ce2 <= 1'd1; + sdphydatar_next_state <= 1'd1; + end + end + endcase +end +assign sdcard_core_crc16_inserter_sink_valid = sdcard_core_sink_sink_valid0; +assign sdcard_core_sink_sink_ready0 = sdcard_core_crc16_inserter_sink_ready; +assign sdcard_core_crc16_inserter_sink_first = sdcard_core_sink_sink_first0; +assign sdcard_core_crc16_inserter_sink_last = sdcard_core_sink_sink_last0; +assign sdcard_core_crc16_inserter_sink_payload_data = sdcard_core_sink_sink_payload_data0; +assign sdcard_core_source_source_valid0 = sdcard_core_source_source_valid1; +assign sdcard_core_source_source_ready1 = sdcard_core_source_source_ready0; +assign sdcard_core_source_source_first0 = sdcard_core_source_source_first1; +assign sdcard_core_source_source_last0 = sdcard_core_source_source_last1; +assign sdcard_core_source_source_payload_data0 = sdcard_core_source_source_payload_data1; +assign sdcard_core_cmd_type = sdcard_core_csrfield_cmd_type; +assign sdcard_core_data_type = sdcard_core_csrfield_data_type; +assign sdcard_core_cmd = sdcard_core_csrfield_cmd; +assign sdcard_core_csrfield_done0 = sdcard_core_cmd_done; +assign sdcard_core_csrfield_error0 = sdcard_core_cmd_error; +assign sdcard_core_csrfield_timeout0 = sdcard_core_cmd_timeout; +assign sdcard_core_csrfield_crc0 = 1'd0; +assign sdcard_core_csrfield_done1 = sdcard_core_data_done; +assign sdcard_core_csrfield_error1 = sdcard_core_data_error; +assign sdcard_core_csrfield_timeout1 = sdcard_core_data_timeout; +assign sdcard_core_csrfield_crc1 = 1'd0; +assign sdcard_core_crc7_inserter_crc_din = {1'd0, 1'd1, sdcard_core_cmd, sdcard_core_cmd_argument_storage}; +assign sdcard_core_crc7_inserter_crc_reset = 1'd1; +assign sdcard_core_crc7_inserter_crc_enable = 1'd1; +assign sdcard_core_crc7_inserter_crc1 = {sdcard_core_crc7_inserter_crc0[5], sdcard_core_crc7_inserter_crc0[4], sdcard_core_crc7_inserter_crc0[3], (sdcard_core_crc7_inserter_crc0[2] ^ (sdcard_core_crc7_inserter_crc_din[39] ^ sdcard_core_crc7_inserter_crc0[6])), sdcard_core_crc7_inserter_crc0[1], sdcard_core_crc7_inserter_crc0[0], (sdcard_core_crc7_inserter_crc_din[39] ^ sdcard_core_crc7_inserter_crc0[6])}; +assign sdcard_core_crc7_inserter_crc2 = {sdcard_core_crc7_inserter_crc1[5], sdcard_core_crc7_inserter_crc1[4], sdcard_core_crc7_inserter_crc1[3], (sdcard_core_crc7_inserter_crc1[2] ^ (sdcard_core_crc7_inserter_crc_din[38] ^ sdcard_core_crc7_inserter_crc1[6])), sdcard_core_crc7_inserter_crc1[1], sdcard_core_crc7_inserter_crc1[0], (sdcard_core_crc7_inserter_crc_din[38] ^ sdcard_core_crc7_inserter_crc1[6])}; +assign sdcard_core_crc7_inserter_crc3 = {sdcard_core_crc7_inserter_crc2[5], sdcard_core_crc7_inserter_crc2[4], sdcard_core_crc7_inserter_crc2[3], (sdcard_core_crc7_inserter_crc2[2] ^ (sdcard_core_crc7_inserter_crc_din[37] ^ sdcard_core_crc7_inserter_crc2[6])), sdcard_core_crc7_inserter_crc2[1], sdcard_core_crc7_inserter_crc2[0], (sdcard_core_crc7_inserter_crc_din[37] ^ sdcard_core_crc7_inserter_crc2[6])}; +assign sdcard_core_crc7_inserter_crc4 = {sdcard_core_crc7_inserter_crc3[5], sdcard_core_crc7_inserter_crc3[4], sdcard_core_crc7_inserter_crc3[3], (sdcard_core_crc7_inserter_crc3[2] ^ (sdcard_core_crc7_inserter_crc_din[36] ^ sdcard_core_crc7_inserter_crc3[6])), sdcard_core_crc7_inserter_crc3[1], sdcard_core_crc7_inserter_crc3[0], (sdcard_core_crc7_inserter_crc_din[36] ^ sdcard_core_crc7_inserter_crc3[6])}; +assign sdcard_core_crc7_inserter_crc5 = {sdcard_core_crc7_inserter_crc4[5], sdcard_core_crc7_inserter_crc4[4], sdcard_core_crc7_inserter_crc4[3], (sdcard_core_crc7_inserter_crc4[2] ^ (sdcard_core_crc7_inserter_crc_din[35] ^ sdcard_core_crc7_inserter_crc4[6])), sdcard_core_crc7_inserter_crc4[1], sdcard_core_crc7_inserter_crc4[0], (sdcard_core_crc7_inserter_crc_din[35] ^ sdcard_core_crc7_inserter_crc4[6])}; +assign sdcard_core_crc7_inserter_crc6 = {sdcard_core_crc7_inserter_crc5[5], sdcard_core_crc7_inserter_crc5[4], sdcard_core_crc7_inserter_crc5[3], (sdcard_core_crc7_inserter_crc5[2] ^ (sdcard_core_crc7_inserter_crc_din[34] ^ sdcard_core_crc7_inserter_crc5[6])), sdcard_core_crc7_inserter_crc5[1], sdcard_core_crc7_inserter_crc5[0], (sdcard_core_crc7_inserter_crc_din[34] ^ sdcard_core_crc7_inserter_crc5[6])}; +assign sdcard_core_crc7_inserter_crc7 = {sdcard_core_crc7_inserter_crc6[5], sdcard_core_crc7_inserter_crc6[4], sdcard_core_crc7_inserter_crc6[3], (sdcard_core_crc7_inserter_crc6[2] ^ (sdcard_core_crc7_inserter_crc_din[33] ^ sdcard_core_crc7_inserter_crc6[6])), sdcard_core_crc7_inserter_crc6[1], sdcard_core_crc7_inserter_crc6[0], (sdcard_core_crc7_inserter_crc_din[33] ^ sdcard_core_crc7_inserter_crc6[6])}; +assign sdcard_core_crc7_inserter_crc8 = {sdcard_core_crc7_inserter_crc7[5], sdcard_core_crc7_inserter_crc7[4], sdcard_core_crc7_inserter_crc7[3], (sdcard_core_crc7_inserter_crc7[2] ^ (sdcard_core_crc7_inserter_crc_din[32] ^ sdcard_core_crc7_inserter_crc7[6])), sdcard_core_crc7_inserter_crc7[1], sdcard_core_crc7_inserter_crc7[0], (sdcard_core_crc7_inserter_crc_din[32] ^ sdcard_core_crc7_inserter_crc7[6])}; +assign sdcard_core_crc7_inserter_crc9 = {sdcard_core_crc7_inserter_crc8[5], sdcard_core_crc7_inserter_crc8[4], sdcard_core_crc7_inserter_crc8[3], (sdcard_core_crc7_inserter_crc8[2] ^ (sdcard_core_crc7_inserter_crc_din[31] ^ sdcard_core_crc7_inserter_crc8[6])), sdcard_core_crc7_inserter_crc8[1], sdcard_core_crc7_inserter_crc8[0], (sdcard_core_crc7_inserter_crc_din[31] ^ sdcard_core_crc7_inserter_crc8[6])}; +assign sdcard_core_crc7_inserter_crc10 = {sdcard_core_crc7_inserter_crc9[5], sdcard_core_crc7_inserter_crc9[4], sdcard_core_crc7_inserter_crc9[3], (sdcard_core_crc7_inserter_crc9[2] ^ (sdcard_core_crc7_inserter_crc_din[30] ^ sdcard_core_crc7_inserter_crc9[6])), sdcard_core_crc7_inserter_crc9[1], sdcard_core_crc7_inserter_crc9[0], (sdcard_core_crc7_inserter_crc_din[30] ^ sdcard_core_crc7_inserter_crc9[6])}; +assign sdcard_core_crc7_inserter_crc11 = {sdcard_core_crc7_inserter_crc10[5], sdcard_core_crc7_inserter_crc10[4], sdcard_core_crc7_inserter_crc10[3], (sdcard_core_crc7_inserter_crc10[2] ^ (sdcard_core_crc7_inserter_crc_din[29] ^ sdcard_core_crc7_inserter_crc10[6])), sdcard_core_crc7_inserter_crc10[1], sdcard_core_crc7_inserter_crc10[0], (sdcard_core_crc7_inserter_crc_din[29] ^ sdcard_core_crc7_inserter_crc10[6])}; +assign sdcard_core_crc7_inserter_crc12 = {sdcard_core_crc7_inserter_crc11[5], sdcard_core_crc7_inserter_crc11[4], sdcard_core_crc7_inserter_crc11[3], (sdcard_core_crc7_inserter_crc11[2] ^ (sdcard_core_crc7_inserter_crc_din[28] ^ sdcard_core_crc7_inserter_crc11[6])), sdcard_core_crc7_inserter_crc11[1], sdcard_core_crc7_inserter_crc11[0], (sdcard_core_crc7_inserter_crc_din[28] ^ sdcard_core_crc7_inserter_crc11[6])}; +assign sdcard_core_crc7_inserter_crc13 = {sdcard_core_crc7_inserter_crc12[5], sdcard_core_crc7_inserter_crc12[4], sdcard_core_crc7_inserter_crc12[3], (sdcard_core_crc7_inserter_crc12[2] ^ (sdcard_core_crc7_inserter_crc_din[27] ^ sdcard_core_crc7_inserter_crc12[6])), sdcard_core_crc7_inserter_crc12[1], sdcard_core_crc7_inserter_crc12[0], (sdcard_core_crc7_inserter_crc_din[27] ^ sdcard_core_crc7_inserter_crc12[6])}; +assign sdcard_core_crc7_inserter_crc14 = {sdcard_core_crc7_inserter_crc13[5], sdcard_core_crc7_inserter_crc13[4], sdcard_core_crc7_inserter_crc13[3], (sdcard_core_crc7_inserter_crc13[2] ^ (sdcard_core_crc7_inserter_crc_din[26] ^ sdcard_core_crc7_inserter_crc13[6])), sdcard_core_crc7_inserter_crc13[1], sdcard_core_crc7_inserter_crc13[0], (sdcard_core_crc7_inserter_crc_din[26] ^ sdcard_core_crc7_inserter_crc13[6])}; +assign sdcard_core_crc7_inserter_crc15 = {sdcard_core_crc7_inserter_crc14[5], sdcard_core_crc7_inserter_crc14[4], sdcard_core_crc7_inserter_crc14[3], (sdcard_core_crc7_inserter_crc14[2] ^ (sdcard_core_crc7_inserter_crc_din[25] ^ sdcard_core_crc7_inserter_crc14[6])), sdcard_core_crc7_inserter_crc14[1], sdcard_core_crc7_inserter_crc14[0], (sdcard_core_crc7_inserter_crc_din[25] ^ sdcard_core_crc7_inserter_crc14[6])}; +assign sdcard_core_crc7_inserter_crc16 = {sdcard_core_crc7_inserter_crc15[5], sdcard_core_crc7_inserter_crc15[4], sdcard_core_crc7_inserter_crc15[3], (sdcard_core_crc7_inserter_crc15[2] ^ (sdcard_core_crc7_inserter_crc_din[24] ^ sdcard_core_crc7_inserter_crc15[6])), sdcard_core_crc7_inserter_crc15[1], sdcard_core_crc7_inserter_crc15[0], (sdcard_core_crc7_inserter_crc_din[24] ^ sdcard_core_crc7_inserter_crc15[6])}; +assign sdcard_core_crc7_inserter_crc17 = {sdcard_core_crc7_inserter_crc16[5], sdcard_core_crc7_inserter_crc16[4], sdcard_core_crc7_inserter_crc16[3], (sdcard_core_crc7_inserter_crc16[2] ^ (sdcard_core_crc7_inserter_crc_din[23] ^ sdcard_core_crc7_inserter_crc16[6])), sdcard_core_crc7_inserter_crc16[1], sdcard_core_crc7_inserter_crc16[0], (sdcard_core_crc7_inserter_crc_din[23] ^ sdcard_core_crc7_inserter_crc16[6])}; +assign sdcard_core_crc7_inserter_crc18 = {sdcard_core_crc7_inserter_crc17[5], sdcard_core_crc7_inserter_crc17[4], sdcard_core_crc7_inserter_crc17[3], (sdcard_core_crc7_inserter_crc17[2] ^ (sdcard_core_crc7_inserter_crc_din[22] ^ sdcard_core_crc7_inserter_crc17[6])), sdcard_core_crc7_inserter_crc17[1], sdcard_core_crc7_inserter_crc17[0], (sdcard_core_crc7_inserter_crc_din[22] ^ sdcard_core_crc7_inserter_crc17[6])}; +assign sdcard_core_crc7_inserter_crc19 = {sdcard_core_crc7_inserter_crc18[5], sdcard_core_crc7_inserter_crc18[4], sdcard_core_crc7_inserter_crc18[3], (sdcard_core_crc7_inserter_crc18[2] ^ (sdcard_core_crc7_inserter_crc_din[21] ^ sdcard_core_crc7_inserter_crc18[6])), sdcard_core_crc7_inserter_crc18[1], sdcard_core_crc7_inserter_crc18[0], (sdcard_core_crc7_inserter_crc_din[21] ^ sdcard_core_crc7_inserter_crc18[6])}; +assign sdcard_core_crc7_inserter_crc20 = {sdcard_core_crc7_inserter_crc19[5], sdcard_core_crc7_inserter_crc19[4], sdcard_core_crc7_inserter_crc19[3], (sdcard_core_crc7_inserter_crc19[2] ^ (sdcard_core_crc7_inserter_crc_din[20] ^ sdcard_core_crc7_inserter_crc19[6])), sdcard_core_crc7_inserter_crc19[1], sdcard_core_crc7_inserter_crc19[0], (sdcard_core_crc7_inserter_crc_din[20] ^ sdcard_core_crc7_inserter_crc19[6])}; +assign sdcard_core_crc7_inserter_crc21 = {sdcard_core_crc7_inserter_crc20[5], sdcard_core_crc7_inserter_crc20[4], sdcard_core_crc7_inserter_crc20[3], (sdcard_core_crc7_inserter_crc20[2] ^ (sdcard_core_crc7_inserter_crc_din[19] ^ sdcard_core_crc7_inserter_crc20[6])), sdcard_core_crc7_inserter_crc20[1], sdcard_core_crc7_inserter_crc20[0], (sdcard_core_crc7_inserter_crc_din[19] ^ sdcard_core_crc7_inserter_crc20[6])}; +assign sdcard_core_crc7_inserter_crc22 = {sdcard_core_crc7_inserter_crc21[5], sdcard_core_crc7_inserter_crc21[4], sdcard_core_crc7_inserter_crc21[3], (sdcard_core_crc7_inserter_crc21[2] ^ (sdcard_core_crc7_inserter_crc_din[18] ^ sdcard_core_crc7_inserter_crc21[6])), sdcard_core_crc7_inserter_crc21[1], sdcard_core_crc7_inserter_crc21[0], (sdcard_core_crc7_inserter_crc_din[18] ^ sdcard_core_crc7_inserter_crc21[6])}; +assign sdcard_core_crc7_inserter_crc23 = {sdcard_core_crc7_inserter_crc22[5], sdcard_core_crc7_inserter_crc22[4], sdcard_core_crc7_inserter_crc22[3], (sdcard_core_crc7_inserter_crc22[2] ^ (sdcard_core_crc7_inserter_crc_din[17] ^ sdcard_core_crc7_inserter_crc22[6])), sdcard_core_crc7_inserter_crc22[1], sdcard_core_crc7_inserter_crc22[0], (sdcard_core_crc7_inserter_crc_din[17] ^ sdcard_core_crc7_inserter_crc22[6])}; +assign sdcard_core_crc7_inserter_crc24 = {sdcard_core_crc7_inserter_crc23[5], sdcard_core_crc7_inserter_crc23[4], sdcard_core_crc7_inserter_crc23[3], (sdcard_core_crc7_inserter_crc23[2] ^ (sdcard_core_crc7_inserter_crc_din[16] ^ sdcard_core_crc7_inserter_crc23[6])), sdcard_core_crc7_inserter_crc23[1], sdcard_core_crc7_inserter_crc23[0], (sdcard_core_crc7_inserter_crc_din[16] ^ sdcard_core_crc7_inserter_crc23[6])}; +assign sdcard_core_crc7_inserter_crc25 = {sdcard_core_crc7_inserter_crc24[5], sdcard_core_crc7_inserter_crc24[4], sdcard_core_crc7_inserter_crc24[3], (sdcard_core_crc7_inserter_crc24[2] ^ (sdcard_core_crc7_inserter_crc_din[15] ^ sdcard_core_crc7_inserter_crc24[6])), sdcard_core_crc7_inserter_crc24[1], sdcard_core_crc7_inserter_crc24[0], (sdcard_core_crc7_inserter_crc_din[15] ^ sdcard_core_crc7_inserter_crc24[6])}; +assign sdcard_core_crc7_inserter_crc26 = {sdcard_core_crc7_inserter_crc25[5], sdcard_core_crc7_inserter_crc25[4], sdcard_core_crc7_inserter_crc25[3], (sdcard_core_crc7_inserter_crc25[2] ^ (sdcard_core_crc7_inserter_crc_din[14] ^ sdcard_core_crc7_inserter_crc25[6])), sdcard_core_crc7_inserter_crc25[1], sdcard_core_crc7_inserter_crc25[0], (sdcard_core_crc7_inserter_crc_din[14] ^ sdcard_core_crc7_inserter_crc25[6])}; +assign sdcard_core_crc7_inserter_crc27 = {sdcard_core_crc7_inserter_crc26[5], sdcard_core_crc7_inserter_crc26[4], sdcard_core_crc7_inserter_crc26[3], (sdcard_core_crc7_inserter_crc26[2] ^ (sdcard_core_crc7_inserter_crc_din[13] ^ sdcard_core_crc7_inserter_crc26[6])), sdcard_core_crc7_inserter_crc26[1], sdcard_core_crc7_inserter_crc26[0], (sdcard_core_crc7_inserter_crc_din[13] ^ sdcard_core_crc7_inserter_crc26[6])}; +assign sdcard_core_crc7_inserter_crc28 = {sdcard_core_crc7_inserter_crc27[5], sdcard_core_crc7_inserter_crc27[4], sdcard_core_crc7_inserter_crc27[3], (sdcard_core_crc7_inserter_crc27[2] ^ (sdcard_core_crc7_inserter_crc_din[12] ^ sdcard_core_crc7_inserter_crc27[6])), sdcard_core_crc7_inserter_crc27[1], sdcard_core_crc7_inserter_crc27[0], (sdcard_core_crc7_inserter_crc_din[12] ^ sdcard_core_crc7_inserter_crc27[6])}; +assign sdcard_core_crc7_inserter_crc29 = {sdcard_core_crc7_inserter_crc28[5], sdcard_core_crc7_inserter_crc28[4], sdcard_core_crc7_inserter_crc28[3], (sdcard_core_crc7_inserter_crc28[2] ^ (sdcard_core_crc7_inserter_crc_din[11] ^ sdcard_core_crc7_inserter_crc28[6])), sdcard_core_crc7_inserter_crc28[1], sdcard_core_crc7_inserter_crc28[0], (sdcard_core_crc7_inserter_crc_din[11] ^ sdcard_core_crc7_inserter_crc28[6])}; +assign sdcard_core_crc7_inserter_crc30 = {sdcard_core_crc7_inserter_crc29[5], sdcard_core_crc7_inserter_crc29[4], sdcard_core_crc7_inserter_crc29[3], (sdcard_core_crc7_inserter_crc29[2] ^ (sdcard_core_crc7_inserter_crc_din[10] ^ sdcard_core_crc7_inserter_crc29[6])), sdcard_core_crc7_inserter_crc29[1], sdcard_core_crc7_inserter_crc29[0], (sdcard_core_crc7_inserter_crc_din[10] ^ sdcard_core_crc7_inserter_crc29[6])}; +assign sdcard_core_crc7_inserter_crc31 = {sdcard_core_crc7_inserter_crc30[5], sdcard_core_crc7_inserter_crc30[4], sdcard_core_crc7_inserter_crc30[3], (sdcard_core_crc7_inserter_crc30[2] ^ (sdcard_core_crc7_inserter_crc_din[9] ^ sdcard_core_crc7_inserter_crc30[6])), sdcard_core_crc7_inserter_crc30[1], sdcard_core_crc7_inserter_crc30[0], (sdcard_core_crc7_inserter_crc_din[9] ^ sdcard_core_crc7_inserter_crc30[6])}; +assign sdcard_core_crc7_inserter_crc32 = {sdcard_core_crc7_inserter_crc31[5], sdcard_core_crc7_inserter_crc31[4], sdcard_core_crc7_inserter_crc31[3], (sdcard_core_crc7_inserter_crc31[2] ^ (sdcard_core_crc7_inserter_crc_din[8] ^ sdcard_core_crc7_inserter_crc31[6])), sdcard_core_crc7_inserter_crc31[1], sdcard_core_crc7_inserter_crc31[0], (sdcard_core_crc7_inserter_crc_din[8] ^ sdcard_core_crc7_inserter_crc31[6])}; +assign sdcard_core_crc7_inserter_crc33 = {sdcard_core_crc7_inserter_crc32[5], sdcard_core_crc7_inserter_crc32[4], sdcard_core_crc7_inserter_crc32[3], (sdcard_core_crc7_inserter_crc32[2] ^ (sdcard_core_crc7_inserter_crc_din[7] ^ sdcard_core_crc7_inserter_crc32[6])), sdcard_core_crc7_inserter_crc32[1], sdcard_core_crc7_inserter_crc32[0], (sdcard_core_crc7_inserter_crc_din[7] ^ sdcard_core_crc7_inserter_crc32[6])}; +assign sdcard_core_crc7_inserter_crc34 = {sdcard_core_crc7_inserter_crc33[5], sdcard_core_crc7_inserter_crc33[4], sdcard_core_crc7_inserter_crc33[3], (sdcard_core_crc7_inserter_crc33[2] ^ (sdcard_core_crc7_inserter_crc_din[6] ^ sdcard_core_crc7_inserter_crc33[6])), sdcard_core_crc7_inserter_crc33[1], sdcard_core_crc7_inserter_crc33[0], (sdcard_core_crc7_inserter_crc_din[6] ^ sdcard_core_crc7_inserter_crc33[6])}; +assign sdcard_core_crc7_inserter_crc35 = {sdcard_core_crc7_inserter_crc34[5], sdcard_core_crc7_inserter_crc34[4], sdcard_core_crc7_inserter_crc34[3], (sdcard_core_crc7_inserter_crc34[2] ^ (sdcard_core_crc7_inserter_crc_din[5] ^ sdcard_core_crc7_inserter_crc34[6])), sdcard_core_crc7_inserter_crc34[1], sdcard_core_crc7_inserter_crc34[0], (sdcard_core_crc7_inserter_crc_din[5] ^ sdcard_core_crc7_inserter_crc34[6])}; +assign sdcard_core_crc7_inserter_crc36 = {sdcard_core_crc7_inserter_crc35[5], sdcard_core_crc7_inserter_crc35[4], sdcard_core_crc7_inserter_crc35[3], (sdcard_core_crc7_inserter_crc35[2] ^ (sdcard_core_crc7_inserter_crc_din[4] ^ sdcard_core_crc7_inserter_crc35[6])), sdcard_core_crc7_inserter_crc35[1], sdcard_core_crc7_inserter_crc35[0], (sdcard_core_crc7_inserter_crc_din[4] ^ sdcard_core_crc7_inserter_crc35[6])}; +assign sdcard_core_crc7_inserter_crc37 = {sdcard_core_crc7_inserter_crc36[5], sdcard_core_crc7_inserter_crc36[4], sdcard_core_crc7_inserter_crc36[3], (sdcard_core_crc7_inserter_crc36[2] ^ (sdcard_core_crc7_inserter_crc_din[3] ^ sdcard_core_crc7_inserter_crc36[6])), sdcard_core_crc7_inserter_crc36[1], sdcard_core_crc7_inserter_crc36[0], (sdcard_core_crc7_inserter_crc_din[3] ^ sdcard_core_crc7_inserter_crc36[6])}; +assign sdcard_core_crc7_inserter_crc38 = {sdcard_core_crc7_inserter_crc37[5], sdcard_core_crc7_inserter_crc37[4], sdcard_core_crc7_inserter_crc37[3], (sdcard_core_crc7_inserter_crc37[2] ^ (sdcard_core_crc7_inserter_crc_din[2] ^ sdcard_core_crc7_inserter_crc37[6])), sdcard_core_crc7_inserter_crc37[1], sdcard_core_crc7_inserter_crc37[0], (sdcard_core_crc7_inserter_crc_din[2] ^ sdcard_core_crc7_inserter_crc37[6])}; +assign sdcard_core_crc7_inserter_crc39 = {sdcard_core_crc7_inserter_crc38[5], sdcard_core_crc7_inserter_crc38[4], sdcard_core_crc7_inserter_crc38[3], (sdcard_core_crc7_inserter_crc38[2] ^ (sdcard_core_crc7_inserter_crc_din[1] ^ sdcard_core_crc7_inserter_crc38[6])), sdcard_core_crc7_inserter_crc38[1], sdcard_core_crc7_inserter_crc38[0], (sdcard_core_crc7_inserter_crc_din[1] ^ sdcard_core_crc7_inserter_crc38[6])}; +assign sdcard_core_crc7_inserter_crc40 = {sdcard_core_crc7_inserter_crc39[5], sdcard_core_crc7_inserter_crc39[4], sdcard_core_crc7_inserter_crc39[3], (sdcard_core_crc7_inserter_crc39[2] ^ (sdcard_core_crc7_inserter_crc_din[0] ^ sdcard_core_crc7_inserter_crc39[6])), sdcard_core_crc7_inserter_crc39[1], sdcard_core_crc7_inserter_crc39[0], (sdcard_core_crc7_inserter_crc_din[0] ^ sdcard_core_crc7_inserter_crc39[6])}; +always @(*) begin + sdcard_core_crc7_inserter_crc_crc <= 7'd0; + if (sdcard_core_crc7_inserter_crc_enable) begin + sdcard_core_crc7_inserter_crc_crc <= sdcard_core_crc7_inserter_crc40; + end else begin + sdcard_core_crc7_inserter_crc_crc <= sdcard_core_crc7_inserter_crc0; + end +end +assign sdcard_core_crc16_inserter_crc0_reset = ((sdcard_core_crc16_inserter_source_valid & sdcard_core_crc16_inserter_source_ready) & sdcard_core_crc16_inserter_source_last); +assign sdcard_core_crc16_inserter_crc0_enable = (sdcard_core_crc16_inserter_sink_valid & sdcard_core_crc16_inserter_sink_ready); +always @(*) begin + sdcard_core_crc16_inserter_crc0_din <= 2'd0; + sdcard_core_crc16_inserter_crc0_din[0] <= sdcard_core_crc16_inserter_sink_payload_data[0]; + sdcard_core_crc16_inserter_crc0_din[1] <= sdcard_core_crc16_inserter_sink_payload_data[4]; +end +assign sdcard_core_crc16_inserter_crc1_reset = ((sdcard_core_crc16_inserter_source_valid & sdcard_core_crc16_inserter_source_ready) & sdcard_core_crc16_inserter_source_last); +assign sdcard_core_crc16_inserter_crc1_enable = (sdcard_core_crc16_inserter_sink_valid & sdcard_core_crc16_inserter_sink_ready); +always @(*) begin + sdcard_core_crc16_inserter_crc1_din <= 2'd0; + sdcard_core_crc16_inserter_crc1_din[0] <= sdcard_core_crc16_inserter_sink_payload_data[1]; + sdcard_core_crc16_inserter_crc1_din[1] <= sdcard_core_crc16_inserter_sink_payload_data[5]; +end +assign sdcard_core_crc16_inserter_crc2_reset = ((sdcard_core_crc16_inserter_source_valid & sdcard_core_crc16_inserter_source_ready) & sdcard_core_crc16_inserter_source_last); +assign sdcard_core_crc16_inserter_crc2_enable = (sdcard_core_crc16_inserter_sink_valid & sdcard_core_crc16_inserter_sink_ready); +always @(*) begin + sdcard_core_crc16_inserter_crc2_din <= 2'd0; + sdcard_core_crc16_inserter_crc2_din[0] <= sdcard_core_crc16_inserter_sink_payload_data[2]; + sdcard_core_crc16_inserter_crc2_din[1] <= sdcard_core_crc16_inserter_sink_payload_data[6]; +end +assign sdcard_core_crc16_inserter_crc3_reset = ((sdcard_core_crc16_inserter_source_valid & sdcard_core_crc16_inserter_source_ready) & sdcard_core_crc16_inserter_source_last); +assign sdcard_core_crc16_inserter_crc3_enable = (sdcard_core_crc16_inserter_sink_valid & sdcard_core_crc16_inserter_sink_ready); +always @(*) begin + sdcard_core_crc16_inserter_crc3_din <= 2'd0; + sdcard_core_crc16_inserter_crc3_din[0] <= sdcard_core_crc16_inserter_sink_payload_data[3]; + sdcard_core_crc16_inserter_crc3_din[1] <= sdcard_core_crc16_inserter_sink_payload_data[7]; +end +assign sdcard_core_crc16_inserter_crc01 = {sdcard_core_crc16_inserter_crc00[14], sdcard_core_crc16_inserter_crc00[13], sdcard_core_crc16_inserter_crc00[12], (sdcard_core_crc16_inserter_crc00[11] ^ (sdcard_core_crc16_inserter_crc0_din[1] ^ sdcard_core_crc16_inserter_crc00[15])), sdcard_core_crc16_inserter_crc00[10], sdcard_core_crc16_inserter_crc00[9], sdcard_core_crc16_inserter_crc00[8], sdcard_core_crc16_inserter_crc00[7], sdcard_core_crc16_inserter_crc00[6], sdcard_core_crc16_inserter_crc00[5], (sdcard_core_crc16_inserter_crc00[4] ^ (sdcard_core_crc16_inserter_crc0_din[1] ^ sdcard_core_crc16_inserter_crc00[15])), sdcard_core_crc16_inserter_crc00[3], sdcard_core_crc16_inserter_crc00[2], sdcard_core_crc16_inserter_crc00[1], sdcard_core_crc16_inserter_crc00[0], (sdcard_core_crc16_inserter_crc0_din[1] ^ sdcard_core_crc16_inserter_crc00[15])}; +assign sdcard_core_crc16_inserter_crc02 = {sdcard_core_crc16_inserter_crc01[14], sdcard_core_crc16_inserter_crc01[13], sdcard_core_crc16_inserter_crc01[12], (sdcard_core_crc16_inserter_crc01[11] ^ (sdcard_core_crc16_inserter_crc0_din[0] ^ sdcard_core_crc16_inserter_crc01[15])), sdcard_core_crc16_inserter_crc01[10], sdcard_core_crc16_inserter_crc01[9], sdcard_core_crc16_inserter_crc01[8], sdcard_core_crc16_inserter_crc01[7], sdcard_core_crc16_inserter_crc01[6], sdcard_core_crc16_inserter_crc01[5], (sdcard_core_crc16_inserter_crc01[4] ^ (sdcard_core_crc16_inserter_crc0_din[0] ^ sdcard_core_crc16_inserter_crc01[15])), sdcard_core_crc16_inserter_crc01[3], sdcard_core_crc16_inserter_crc01[2], sdcard_core_crc16_inserter_crc01[1], sdcard_core_crc16_inserter_crc01[0], (sdcard_core_crc16_inserter_crc0_din[0] ^ sdcard_core_crc16_inserter_crc01[15])}; +always @(*) begin + sdcard_core_crc16_inserter_crc0_crc <= 16'd0; + if (sdcard_core_crc16_inserter_crc0_enable) begin + sdcard_core_crc16_inserter_crc0_crc <= sdcard_core_crc16_inserter_crc02; + end else begin + sdcard_core_crc16_inserter_crc0_crc <= sdcard_core_crc16_inserter_crc00; + end +end +assign sdcard_core_crc16_inserter_crc11 = {sdcard_core_crc16_inserter_crc10[14], sdcard_core_crc16_inserter_crc10[13], sdcard_core_crc16_inserter_crc10[12], (sdcard_core_crc16_inserter_crc10[11] ^ (sdcard_core_crc16_inserter_crc1_din[1] ^ sdcard_core_crc16_inserter_crc10[15])), sdcard_core_crc16_inserter_crc10[10], sdcard_core_crc16_inserter_crc10[9], sdcard_core_crc16_inserter_crc10[8], sdcard_core_crc16_inserter_crc10[7], sdcard_core_crc16_inserter_crc10[6], sdcard_core_crc16_inserter_crc10[5], (sdcard_core_crc16_inserter_crc10[4] ^ (sdcard_core_crc16_inserter_crc1_din[1] ^ sdcard_core_crc16_inserter_crc10[15])), sdcard_core_crc16_inserter_crc10[3], sdcard_core_crc16_inserter_crc10[2], sdcard_core_crc16_inserter_crc10[1], sdcard_core_crc16_inserter_crc10[0], (sdcard_core_crc16_inserter_crc1_din[1] ^ sdcard_core_crc16_inserter_crc10[15])}; +assign sdcard_core_crc16_inserter_crc12 = {sdcard_core_crc16_inserter_crc11[14], sdcard_core_crc16_inserter_crc11[13], sdcard_core_crc16_inserter_crc11[12], (sdcard_core_crc16_inserter_crc11[11] ^ (sdcard_core_crc16_inserter_crc1_din[0] ^ sdcard_core_crc16_inserter_crc11[15])), sdcard_core_crc16_inserter_crc11[10], sdcard_core_crc16_inserter_crc11[9], sdcard_core_crc16_inserter_crc11[8], sdcard_core_crc16_inserter_crc11[7], sdcard_core_crc16_inserter_crc11[6], sdcard_core_crc16_inserter_crc11[5], (sdcard_core_crc16_inserter_crc11[4] ^ (sdcard_core_crc16_inserter_crc1_din[0] ^ sdcard_core_crc16_inserter_crc11[15])), sdcard_core_crc16_inserter_crc11[3], sdcard_core_crc16_inserter_crc11[2], sdcard_core_crc16_inserter_crc11[1], sdcard_core_crc16_inserter_crc11[0], (sdcard_core_crc16_inserter_crc1_din[0] ^ sdcard_core_crc16_inserter_crc11[15])}; +always @(*) begin + sdcard_core_crc16_inserter_crc1_crc <= 16'd0; + if (sdcard_core_crc16_inserter_crc1_enable) begin + sdcard_core_crc16_inserter_crc1_crc <= sdcard_core_crc16_inserter_crc12; + end else begin + sdcard_core_crc16_inserter_crc1_crc <= sdcard_core_crc16_inserter_crc10; + end +end +assign sdcard_core_crc16_inserter_crc21 = {sdcard_core_crc16_inserter_crc20[14], sdcard_core_crc16_inserter_crc20[13], sdcard_core_crc16_inserter_crc20[12], (sdcard_core_crc16_inserter_crc20[11] ^ (sdcard_core_crc16_inserter_crc2_din[1] ^ sdcard_core_crc16_inserter_crc20[15])), sdcard_core_crc16_inserter_crc20[10], sdcard_core_crc16_inserter_crc20[9], sdcard_core_crc16_inserter_crc20[8], sdcard_core_crc16_inserter_crc20[7], sdcard_core_crc16_inserter_crc20[6], sdcard_core_crc16_inserter_crc20[5], (sdcard_core_crc16_inserter_crc20[4] ^ (sdcard_core_crc16_inserter_crc2_din[1] ^ sdcard_core_crc16_inserter_crc20[15])), sdcard_core_crc16_inserter_crc20[3], sdcard_core_crc16_inserter_crc20[2], sdcard_core_crc16_inserter_crc20[1], sdcard_core_crc16_inserter_crc20[0], (sdcard_core_crc16_inserter_crc2_din[1] ^ sdcard_core_crc16_inserter_crc20[15])}; +assign sdcard_core_crc16_inserter_crc22 = {sdcard_core_crc16_inserter_crc21[14], sdcard_core_crc16_inserter_crc21[13], sdcard_core_crc16_inserter_crc21[12], (sdcard_core_crc16_inserter_crc21[11] ^ (sdcard_core_crc16_inserter_crc2_din[0] ^ sdcard_core_crc16_inserter_crc21[15])), sdcard_core_crc16_inserter_crc21[10], sdcard_core_crc16_inserter_crc21[9], sdcard_core_crc16_inserter_crc21[8], sdcard_core_crc16_inserter_crc21[7], sdcard_core_crc16_inserter_crc21[6], sdcard_core_crc16_inserter_crc21[5], (sdcard_core_crc16_inserter_crc21[4] ^ (sdcard_core_crc16_inserter_crc2_din[0] ^ sdcard_core_crc16_inserter_crc21[15])), sdcard_core_crc16_inserter_crc21[3], sdcard_core_crc16_inserter_crc21[2], sdcard_core_crc16_inserter_crc21[1], sdcard_core_crc16_inserter_crc21[0], (sdcard_core_crc16_inserter_crc2_din[0] ^ sdcard_core_crc16_inserter_crc21[15])}; +always @(*) begin + sdcard_core_crc16_inserter_crc2_crc <= 16'd0; + if (sdcard_core_crc16_inserter_crc2_enable) begin + sdcard_core_crc16_inserter_crc2_crc <= sdcard_core_crc16_inserter_crc22; + end else begin + sdcard_core_crc16_inserter_crc2_crc <= sdcard_core_crc16_inserter_crc20; + end +end +assign sdcard_core_crc16_inserter_crc31 = {sdcard_core_crc16_inserter_crc30[14], sdcard_core_crc16_inserter_crc30[13], sdcard_core_crc16_inserter_crc30[12], (sdcard_core_crc16_inserter_crc30[11] ^ (sdcard_core_crc16_inserter_crc3_din[1] ^ sdcard_core_crc16_inserter_crc30[15])), sdcard_core_crc16_inserter_crc30[10], sdcard_core_crc16_inserter_crc30[9], sdcard_core_crc16_inserter_crc30[8], sdcard_core_crc16_inserter_crc30[7], sdcard_core_crc16_inserter_crc30[6], sdcard_core_crc16_inserter_crc30[5], (sdcard_core_crc16_inserter_crc30[4] ^ (sdcard_core_crc16_inserter_crc3_din[1] ^ sdcard_core_crc16_inserter_crc30[15])), sdcard_core_crc16_inserter_crc30[3], sdcard_core_crc16_inserter_crc30[2], sdcard_core_crc16_inserter_crc30[1], sdcard_core_crc16_inserter_crc30[0], (sdcard_core_crc16_inserter_crc3_din[1] ^ sdcard_core_crc16_inserter_crc30[15])}; +assign sdcard_core_crc16_inserter_crc32 = {sdcard_core_crc16_inserter_crc31[14], sdcard_core_crc16_inserter_crc31[13], sdcard_core_crc16_inserter_crc31[12], (sdcard_core_crc16_inserter_crc31[11] ^ (sdcard_core_crc16_inserter_crc3_din[0] ^ sdcard_core_crc16_inserter_crc31[15])), sdcard_core_crc16_inserter_crc31[10], sdcard_core_crc16_inserter_crc31[9], sdcard_core_crc16_inserter_crc31[8], sdcard_core_crc16_inserter_crc31[7], sdcard_core_crc16_inserter_crc31[6], sdcard_core_crc16_inserter_crc31[5], (sdcard_core_crc16_inserter_crc31[4] ^ (sdcard_core_crc16_inserter_crc3_din[0] ^ sdcard_core_crc16_inserter_crc31[15])), sdcard_core_crc16_inserter_crc31[3], sdcard_core_crc16_inserter_crc31[2], sdcard_core_crc16_inserter_crc31[1], sdcard_core_crc16_inserter_crc31[0], (sdcard_core_crc16_inserter_crc3_din[0] ^ sdcard_core_crc16_inserter_crc31[15])}; +always @(*) begin + sdcard_core_crc16_inserter_crc3_crc <= 16'd0; + if (sdcard_core_crc16_inserter_crc3_enable) begin + sdcard_core_crc16_inserter_crc3_crc <= sdcard_core_crc16_inserter_crc32; + end else begin + sdcard_core_crc16_inserter_crc3_crc <= sdcard_core_crc16_inserter_crc30; + end +end +always @(*) begin + crc16inserter_next_state <= 1'd0; + sdcard_core_crc16_inserter_count_crc16inserter_next_value <= 3'd0; + sdcard_core_crc16_inserter_count_crc16inserter_next_value_ce <= 1'd0; + sdcard_core_crc16_inserter_sink_ready <= 1'd0; + sdcard_core_crc16_inserter_source_first <= 1'd0; + sdcard_core_crc16_inserter_source_last <= 1'd0; + sdcard_core_crc16_inserter_source_payload_data <= 8'd0; + sdcard_core_crc16_inserter_source_valid <= 1'd0; + crc16inserter_next_state <= crc16inserter_state; + case (crc16inserter_state) + 1'd1: begin + sdcard_core_crc16_inserter_source_valid <= 1'd1; + sdcard_core_crc16_inserter_source_last <= (sdcard_core_crc16_inserter_count == 3'd7); + case (sdcard_core_crc16_inserter_count) + 1'd0: begin + sdcard_core_crc16_inserter_source_payload_data[0] <= sdcard_core_crc16_inserter_crc0_crc[14]; + sdcard_core_crc16_inserter_source_payload_data[1] <= sdcard_core_crc16_inserter_crc1_crc[14]; + sdcard_core_crc16_inserter_source_payload_data[2] <= sdcard_core_crc16_inserter_crc2_crc[14]; + sdcard_core_crc16_inserter_source_payload_data[3] <= sdcard_core_crc16_inserter_crc3_crc[14]; + sdcard_core_crc16_inserter_source_payload_data[4] <= sdcard_core_crc16_inserter_crc0_crc[15]; + sdcard_core_crc16_inserter_source_payload_data[5] <= sdcard_core_crc16_inserter_crc1_crc[15]; + sdcard_core_crc16_inserter_source_payload_data[6] <= sdcard_core_crc16_inserter_crc2_crc[15]; + sdcard_core_crc16_inserter_source_payload_data[7] <= sdcard_core_crc16_inserter_crc3_crc[15]; + end + 1'd1: begin + sdcard_core_crc16_inserter_source_payload_data[0] <= sdcard_core_crc16_inserter_crc0_crc[12]; + sdcard_core_crc16_inserter_source_payload_data[1] <= sdcard_core_crc16_inserter_crc1_crc[12]; + sdcard_core_crc16_inserter_source_payload_data[2] <= sdcard_core_crc16_inserter_crc2_crc[12]; + sdcard_core_crc16_inserter_source_payload_data[3] <= sdcard_core_crc16_inserter_crc3_crc[12]; + sdcard_core_crc16_inserter_source_payload_data[4] <= sdcard_core_crc16_inserter_crc0_crc[13]; + sdcard_core_crc16_inserter_source_payload_data[5] <= sdcard_core_crc16_inserter_crc1_crc[13]; + sdcard_core_crc16_inserter_source_payload_data[6] <= sdcard_core_crc16_inserter_crc2_crc[13]; + sdcard_core_crc16_inserter_source_payload_data[7] <= sdcard_core_crc16_inserter_crc3_crc[13]; + end + 2'd2: begin + sdcard_core_crc16_inserter_source_payload_data[0] <= sdcard_core_crc16_inserter_crc0_crc[10]; + sdcard_core_crc16_inserter_source_payload_data[1] <= sdcard_core_crc16_inserter_crc1_crc[10]; + sdcard_core_crc16_inserter_source_payload_data[2] <= sdcard_core_crc16_inserter_crc2_crc[10]; + sdcard_core_crc16_inserter_source_payload_data[3] <= sdcard_core_crc16_inserter_crc3_crc[10]; + sdcard_core_crc16_inserter_source_payload_data[4] <= sdcard_core_crc16_inserter_crc0_crc[11]; + sdcard_core_crc16_inserter_source_payload_data[5] <= sdcard_core_crc16_inserter_crc1_crc[11]; + sdcard_core_crc16_inserter_source_payload_data[6] <= sdcard_core_crc16_inserter_crc2_crc[11]; + sdcard_core_crc16_inserter_source_payload_data[7] <= sdcard_core_crc16_inserter_crc3_crc[11]; + end + 2'd3: begin + sdcard_core_crc16_inserter_source_payload_data[0] <= sdcard_core_crc16_inserter_crc0_crc[8]; + sdcard_core_crc16_inserter_source_payload_data[1] <= sdcard_core_crc16_inserter_crc1_crc[8]; + sdcard_core_crc16_inserter_source_payload_data[2] <= sdcard_core_crc16_inserter_crc2_crc[8]; + sdcard_core_crc16_inserter_source_payload_data[3] <= sdcard_core_crc16_inserter_crc3_crc[8]; + sdcard_core_crc16_inserter_source_payload_data[4] <= sdcard_core_crc16_inserter_crc0_crc[9]; + sdcard_core_crc16_inserter_source_payload_data[5] <= sdcard_core_crc16_inserter_crc1_crc[9]; + sdcard_core_crc16_inserter_source_payload_data[6] <= sdcard_core_crc16_inserter_crc2_crc[9]; + sdcard_core_crc16_inserter_source_payload_data[7] <= sdcard_core_crc16_inserter_crc3_crc[9]; + end + 3'd4: begin + sdcard_core_crc16_inserter_source_payload_data[0] <= sdcard_core_crc16_inserter_crc0_crc[6]; + sdcard_core_crc16_inserter_source_payload_data[1] <= sdcard_core_crc16_inserter_crc1_crc[6]; + sdcard_core_crc16_inserter_source_payload_data[2] <= sdcard_core_crc16_inserter_crc2_crc[6]; + sdcard_core_crc16_inserter_source_payload_data[3] <= sdcard_core_crc16_inserter_crc3_crc[6]; + sdcard_core_crc16_inserter_source_payload_data[4] <= sdcard_core_crc16_inserter_crc0_crc[7]; + sdcard_core_crc16_inserter_source_payload_data[5] <= sdcard_core_crc16_inserter_crc1_crc[7]; + sdcard_core_crc16_inserter_source_payload_data[6] <= sdcard_core_crc16_inserter_crc2_crc[7]; + sdcard_core_crc16_inserter_source_payload_data[7] <= sdcard_core_crc16_inserter_crc3_crc[7]; + end + 3'd5: begin + sdcard_core_crc16_inserter_source_payload_data[0] <= sdcard_core_crc16_inserter_crc0_crc[4]; + sdcard_core_crc16_inserter_source_payload_data[1] <= sdcard_core_crc16_inserter_crc1_crc[4]; + sdcard_core_crc16_inserter_source_payload_data[2] <= sdcard_core_crc16_inserter_crc2_crc[4]; + sdcard_core_crc16_inserter_source_payload_data[3] <= sdcard_core_crc16_inserter_crc3_crc[4]; + sdcard_core_crc16_inserter_source_payload_data[4] <= sdcard_core_crc16_inserter_crc0_crc[5]; + sdcard_core_crc16_inserter_source_payload_data[5] <= sdcard_core_crc16_inserter_crc1_crc[5]; + sdcard_core_crc16_inserter_source_payload_data[6] <= sdcard_core_crc16_inserter_crc2_crc[5]; + sdcard_core_crc16_inserter_source_payload_data[7] <= sdcard_core_crc16_inserter_crc3_crc[5]; + end + 3'd6: begin + sdcard_core_crc16_inserter_source_payload_data[0] <= sdcard_core_crc16_inserter_crc0_crc[2]; + sdcard_core_crc16_inserter_source_payload_data[1] <= sdcard_core_crc16_inserter_crc1_crc[2]; + sdcard_core_crc16_inserter_source_payload_data[2] <= sdcard_core_crc16_inserter_crc2_crc[2]; + sdcard_core_crc16_inserter_source_payload_data[3] <= sdcard_core_crc16_inserter_crc3_crc[2]; + sdcard_core_crc16_inserter_source_payload_data[4] <= sdcard_core_crc16_inserter_crc0_crc[3]; + sdcard_core_crc16_inserter_source_payload_data[5] <= sdcard_core_crc16_inserter_crc1_crc[3]; + sdcard_core_crc16_inserter_source_payload_data[6] <= sdcard_core_crc16_inserter_crc2_crc[3]; + sdcard_core_crc16_inserter_source_payload_data[7] <= sdcard_core_crc16_inserter_crc3_crc[3]; + end + 3'd7: begin + sdcard_core_crc16_inserter_source_payload_data[0] <= sdcard_core_crc16_inserter_crc0_crc[0]; + sdcard_core_crc16_inserter_source_payload_data[1] <= sdcard_core_crc16_inserter_crc1_crc[0]; + sdcard_core_crc16_inserter_source_payload_data[2] <= sdcard_core_crc16_inserter_crc2_crc[0]; + sdcard_core_crc16_inserter_source_payload_data[3] <= sdcard_core_crc16_inserter_crc3_crc[0]; + sdcard_core_crc16_inserter_source_payload_data[4] <= sdcard_core_crc16_inserter_crc0_crc[1]; + sdcard_core_crc16_inserter_source_payload_data[5] <= sdcard_core_crc16_inserter_crc1_crc[1]; + sdcard_core_crc16_inserter_source_payload_data[6] <= sdcard_core_crc16_inserter_crc2_crc[1]; + sdcard_core_crc16_inserter_source_payload_data[7] <= sdcard_core_crc16_inserter_crc3_crc[1]; + end + endcase + if ((sdcard_core_crc16_inserter_source_valid & sdcard_core_crc16_inserter_source_ready)) begin + sdcard_core_crc16_inserter_count_crc16inserter_next_value <= (sdcard_core_crc16_inserter_count + 1'd1); + sdcard_core_crc16_inserter_count_crc16inserter_next_value_ce <= 1'd1; + if (sdcard_core_crc16_inserter_source_last) begin + crc16inserter_next_state <= 1'd0; + end + end + end + default: begin + sdcard_core_crc16_inserter_count_crc16inserter_next_value <= 1'd0; + sdcard_core_crc16_inserter_count_crc16inserter_next_value_ce <= 1'd1; + sdcard_core_crc16_inserter_source_valid <= sdcard_core_crc16_inserter_sink_valid; + sdcard_core_crc16_inserter_sink_ready <= sdcard_core_crc16_inserter_source_ready; + sdcard_core_crc16_inserter_source_first <= sdcard_core_crc16_inserter_sink_first; + sdcard_core_crc16_inserter_source_payload_data <= sdcard_core_crc16_inserter_sink_payload_data; + sdcard_core_crc16_inserter_source_last <= 1'd0; + if ((sdcard_core_crc16_inserter_sink_valid & sdcard_core_crc16_inserter_sink_ready)) begin + if (sdcard_core_crc16_inserter_sink_last) begin + crc16inserter_next_state <= 1'd1; + end + end + end + endcase +end +assign sdcard_core_fifo_sink_valid = sdcard_core_sink_sink_valid1; +assign sdcard_core_sink_sink_ready1 = sdcard_core_fifo_sink_ready; +assign sdcard_core_fifo_sink_first = sdcard_core_sink_sink_first1; +assign sdcard_core_fifo_sink_last = sdcard_core_sink_sink_last1; +assign sdcard_core_fifo_sink_payload_data = sdcard_core_sink_sink_payload_data1; +assign sdcard_core_source_source_first1 = sdcard_core_fifo_source_first; +assign sdcard_core_source_source_last1 = sdcard_core_fifo_source_last; +assign sdcard_core_source_source_payload_data1 = sdcard_core_fifo_source_payload_data; +assign sdcard_core_source_source_valid1 = (sdcard_core_fifo_level >= 4'd8); +assign sdcard_core_fifo_source_ready = (sdcard_core_source_source_valid1 & sdcard_core_source_source_ready1); +assign sdcard_core_fifo_reset = ((sdcard_core_sink_sink_valid1 & sdcard_core_sink_sink_ready1) & sdcard_core_sink_sink_last1); +assign sdcard_core_fifo_syncfifo_din = {sdcard_core_fifo_fifo_in_last, sdcard_core_fifo_fifo_in_first, sdcard_core_fifo_fifo_in_payload_data}; +assign {sdcard_core_fifo_fifo_out_last, sdcard_core_fifo_fifo_out_first, sdcard_core_fifo_fifo_out_payload_data} = sdcard_core_fifo_syncfifo_dout; +assign sdcard_core_fifo_sink_ready = sdcard_core_fifo_syncfifo_writable; +assign sdcard_core_fifo_syncfifo_we = sdcard_core_fifo_sink_valid; +assign sdcard_core_fifo_fifo_in_first = sdcard_core_fifo_sink_first; +assign sdcard_core_fifo_fifo_in_last = sdcard_core_fifo_sink_last; +assign sdcard_core_fifo_fifo_in_payload_data = sdcard_core_fifo_sink_payload_data; +assign sdcard_core_fifo_source_valid = sdcard_core_fifo_syncfifo_readable; +assign sdcard_core_fifo_source_first = sdcard_core_fifo_fifo_out_first; +assign sdcard_core_fifo_source_last = sdcard_core_fifo_fifo_out_last; +assign sdcard_core_fifo_source_payload_data = sdcard_core_fifo_fifo_out_payload_data; +assign sdcard_core_fifo_syncfifo_re = sdcard_core_fifo_source_ready; +always @(*) begin + sdcard_core_fifo_wrport_adr <= 3'd0; + if (sdcard_core_fifo_replace) begin + sdcard_core_fifo_wrport_adr <= (sdcard_core_fifo_produce - 1'd1); + end else begin + sdcard_core_fifo_wrport_adr <= sdcard_core_fifo_produce; + end +end +assign sdcard_core_fifo_wrport_dat_w = sdcard_core_fifo_syncfifo_din; +assign sdcard_core_fifo_wrport_we = (sdcard_core_fifo_syncfifo_we & (sdcard_core_fifo_syncfifo_writable | sdcard_core_fifo_replace)); +assign sdcard_core_fifo_do_read = (sdcard_core_fifo_syncfifo_readable & sdcard_core_fifo_syncfifo_re); +assign sdcard_core_fifo_rdport_adr = sdcard_core_fifo_consume; +assign sdcard_core_fifo_syncfifo_dout = sdcard_core_fifo_rdport_dat_r; +assign sdcard_core_fifo_syncfifo_writable = (sdcard_core_fifo_level != 4'd8); +assign sdcard_core_fifo_syncfifo_readable = (sdcard_core_fifo_level != 1'd0); +always @(*) begin + cmdr_sink_payload_cmd_type <= 2'd0; + cmdr_sink_payload_data_type <= 2'd0; + cmdr_sink_payload_length <= 8'd0; + cmdr_sink_valid <= 1'd0; + cmdr_source_source_ready <= 1'd0; + cmdw_sink_last <= 1'd0; + cmdw_sink_payload_cmd_type <= 2'd0; + cmdw_sink_payload_data <= 8'd0; + cmdw_sink_valid <= 1'd0; + datar_sink_last <= 1'd0; + datar_sink_payload_block_length <= 10'd0; + datar_sink_valid <= 1'd0; + datar_source_source_ready <= 1'd0; + dataw_sink_first <= 1'd0; + dataw_sink_last <= 1'd0; + dataw_sink_payload_data <= 8'd0; + dataw_sink_valid <= 1'd0; + fsm_next_state <= 3'd0; + sdcard_core_cmd_count_fsm_next_value2 <= 3'd0; + sdcard_core_cmd_count_fsm_next_value_ce2 <= 1'd0; + sdcard_core_cmd_done_fsm_next_value0 <= 1'd0; + sdcard_core_cmd_done_fsm_next_value_ce0 <= 1'd0; + sdcard_core_cmd_error_fsm_next_value4 <= 1'd0; + sdcard_core_cmd_error_fsm_next_value_ce4 <= 1'd0; + sdcard_core_cmd_response_status_fsm_next_value8 <= 128'd0; + sdcard_core_cmd_response_status_fsm_next_value_ce8 <= 1'd0; + sdcard_core_cmd_timeout_fsm_next_value5 <= 1'd0; + sdcard_core_cmd_timeout_fsm_next_value_ce5 <= 1'd0; + sdcard_core_crc16_inserter_source_ready <= 1'd0; + sdcard_core_data_count_fsm_next_value3 <= 32'd0; + sdcard_core_data_count_fsm_next_value_ce3 <= 1'd0; + sdcard_core_data_done_fsm_next_value1 <= 1'd0; + sdcard_core_data_done_fsm_next_value_ce1 <= 1'd0; + sdcard_core_data_error_fsm_next_value6 <= 1'd0; + sdcard_core_data_error_fsm_next_value_ce6 <= 1'd0; + sdcard_core_data_timeout_fsm_next_value7 <= 1'd0; + sdcard_core_data_timeout_fsm_next_value_ce7 <= 1'd0; + sdcard_core_sink_sink_first1 <= 1'd0; + sdcard_core_sink_sink_last1 <= 1'd0; + sdcard_core_sink_sink_payload_data1 <= 8'd0; + sdcard_core_sink_sink_valid1 <= 1'd0; + fsm_next_state <= fsm_state; + case (fsm_state) + 1'd1: begin + cmdw_sink_valid <= 1'd1; + cmdw_sink_last <= (sdcard_core_cmd_count == 3'd5); + cmdw_sink_payload_cmd_type <= sdcard_core_cmd_type; + case (sdcard_core_cmd_count) + 1'd0: begin + cmdw_sink_payload_data <= {1'd0, 1'd1, sdcard_core_cmd}; + end + 1'd1: begin + cmdw_sink_payload_data <= sdcard_core_cmd_argument_storage[31:24]; + end + 2'd2: begin + cmdw_sink_payload_data <= sdcard_core_cmd_argument_storage[23:16]; + end + 2'd3: begin + cmdw_sink_payload_data <= sdcard_core_cmd_argument_storage[15:8]; + end + 3'd4: begin + cmdw_sink_payload_data <= sdcard_core_cmd_argument_storage[7:0]; + end + 3'd5: begin + cmdw_sink_payload_data <= {sdcard_core_crc7_inserter_crc_crc, 1'd1}; + end + endcase + if (cmdw_sink_ready) begin + sdcard_core_cmd_count_fsm_next_value2 <= (sdcard_core_cmd_count + 1'd1); + sdcard_core_cmd_count_fsm_next_value_ce2 <= 1'd1; + if (cmdw_sink_last) begin + if ((sdcard_core_cmd_type == 1'd0)) begin + fsm_next_state <= 1'd0; + end else begin + fsm_next_state <= 2'd2; + end + end + end + end + 2'd2: begin + cmdr_sink_valid <= 1'd1; + cmdr_sink_payload_cmd_type <= sdcard_core_cmd_type; + cmdr_sink_payload_data_type <= sdcard_core_data_type; + if ((sdcard_core_cmd_type == 2'd2)) begin + cmdr_sink_payload_length <= 5'd18; + end else begin + cmdr_sink_payload_length <= 3'd6; + end + cmdr_source_source_ready <= 1'd1; + if (cmdr_source_source_valid) begin + if ((cmdr_source_source_payload_status == 1'd1)) begin + sdcard_core_cmd_timeout_fsm_next_value5 <= 1'd1; + sdcard_core_cmd_timeout_fsm_next_value_ce5 <= 1'd1; + fsm_next_state <= 1'd0; + end else begin + if (cmdr_source_source_last) begin + if ((sdcard_core_data_type == 2'd2)) begin + fsm_next_state <= 2'd3; + end else begin + if ((sdcard_core_data_type == 1'd1)) begin + fsm_next_state <= 3'd4; + end else begin + fsm_next_state <= 1'd0; + end + end + end else begin + sdcard_core_cmd_response_status_fsm_next_value8 <= {sdcard_core_cmd_response_status, cmdr_source_source_payload_data}; + sdcard_core_cmd_response_status_fsm_next_value_ce8 <= 1'd1; + end + end + end + end + 2'd3: begin + dataw_sink_valid <= sdcard_core_crc16_inserter_source_valid; + sdcard_core_crc16_inserter_source_ready <= dataw_sink_ready; + dataw_sink_first <= sdcard_core_crc16_inserter_source_first; + dataw_sink_last <= sdcard_core_crc16_inserter_source_last; + dataw_sink_payload_data <= sdcard_core_crc16_inserter_source_payload_data; + if (((dataw_sink_valid & dataw_sink_ready) & dataw_sink_last)) begin + sdcard_core_data_count_fsm_next_value3 <= (sdcard_core_data_count + 1'd1); + sdcard_core_data_count_fsm_next_value_ce3 <= 1'd1; + if ((sdcard_core_data_count == (sdcard_core_block_count_storage - 1'd1))) begin + fsm_next_state <= 1'd0; + end + end + datar_source_source_ready <= 1'd1; + if (datar_source_source_valid) begin + if ((datar_source_source_payload_status != 2'd2)) begin + sdcard_core_data_error_fsm_next_value6 <= 1'd1; + sdcard_core_data_error_fsm_next_value_ce6 <= 1'd1; + end + end + end + 3'd4: begin + datar_sink_valid <= 1'd1; + datar_sink_payload_block_length <= sdcard_core_block_length_storage; + datar_sink_last <= (sdcard_core_data_count == (sdcard_core_block_count_storage - 1'd1)); + if (datar_source_source_valid) begin + if ((datar_source_source_payload_status == 1'd0)) begin + sdcard_core_sink_sink_valid1 <= datar_source_source_valid; + datar_source_source_ready <= sdcard_core_sink_sink_ready1; + sdcard_core_sink_sink_first1 <= datar_source_source_first; + sdcard_core_sink_sink_last1 <= datar_source_source_last; + sdcard_core_sink_sink_payload_data1 <= datar_source_source_payload_data; + if ((datar_source_source_last & datar_source_source_ready)) begin + sdcard_core_data_count_fsm_next_value3 <= (sdcard_core_data_count + 1'd1); + sdcard_core_data_count_fsm_next_value_ce3 <= 1'd1; + if ((sdcard_core_data_count == (sdcard_core_block_count_storage - 1'd1))) begin + fsm_next_state <= 1'd0; + end + end + end else begin + if ((datar_source_source_payload_status == 1'd1)) begin + sdcard_core_data_timeout_fsm_next_value7 <= 1'd1; + sdcard_core_data_timeout_fsm_next_value_ce7 <= 1'd1; + datar_source_source_ready <= 1'd1; + fsm_next_state <= 1'd0; + end + end + end + end + default: begin + sdcard_core_cmd_done_fsm_next_value0 <= 1'd1; + sdcard_core_cmd_done_fsm_next_value_ce0 <= 1'd1; + sdcard_core_data_done_fsm_next_value1 <= 1'd1; + sdcard_core_data_done_fsm_next_value_ce1 <= 1'd1; + sdcard_core_cmd_count_fsm_next_value2 <= 1'd0; + sdcard_core_cmd_count_fsm_next_value_ce2 <= 1'd1; + sdcard_core_data_count_fsm_next_value3 <= 1'd0; + sdcard_core_data_count_fsm_next_value_ce3 <= 1'd1; + if (sdcard_core_cmd_send_re) begin + sdcard_core_cmd_done_fsm_next_value0 <= 1'd0; + sdcard_core_cmd_done_fsm_next_value_ce0 <= 1'd1; + sdcard_core_cmd_error_fsm_next_value4 <= 1'd0; + sdcard_core_cmd_error_fsm_next_value_ce4 <= 1'd1; + sdcard_core_cmd_timeout_fsm_next_value5 <= 1'd0; + sdcard_core_cmd_timeout_fsm_next_value_ce5 <= 1'd1; + sdcard_core_data_done_fsm_next_value1 <= 1'd0; + sdcard_core_data_done_fsm_next_value_ce1 <= 1'd1; + sdcard_core_data_error_fsm_next_value6 <= 1'd0; + sdcard_core_data_error_fsm_next_value_ce6 <= 1'd1; + sdcard_core_data_timeout_fsm_next_value7 <= 1'd0; + sdcard_core_data_timeout_fsm_next_value_ce7 <= 1'd1; + fsm_next_state <= 1'd1; + end + end + endcase +end +assign sdcard_block2mem_start = (sdcard_block2mem_sink_sink_valid0 & sdcard_block2mem_sink_sink_first); +always @(*) begin + sdcard_block2mem_fifo_sink_first <= 1'd0; + sdcard_block2mem_fifo_sink_last <= 1'd0; + sdcard_block2mem_fifo_sink_payload_data <= 8'd0; + sdcard_block2mem_fifo_sink_valid <= 1'd0; + sdcard_block2mem_sink_sink_ready0 <= 1'd0; + if ((sdcard_block2mem_wishbonedmawriter_enable_storage & (sdcard_block2mem_start | sdcard_block2mem_connect))) begin + sdcard_block2mem_fifo_sink_valid <= sdcard_block2mem_sink_sink_valid0; + sdcard_block2mem_sink_sink_ready0 <= sdcard_block2mem_fifo_sink_ready; + sdcard_block2mem_fifo_sink_first <= sdcard_block2mem_sink_sink_first; + sdcard_block2mem_fifo_sink_last <= sdcard_block2mem_sink_sink_last0; + sdcard_block2mem_fifo_sink_payload_data <= sdcard_block2mem_sink_sink_payload_data0; + end else begin + sdcard_block2mem_sink_sink_ready0 <= 1'd1; + end +end +assign sdcard_block2mem_converter_sink_valid = sdcard_block2mem_fifo_source_valid; +assign sdcard_block2mem_fifo_source_ready = sdcard_block2mem_converter_sink_ready; +assign sdcard_block2mem_converter_sink_first = sdcard_block2mem_fifo_source_first; +assign sdcard_block2mem_converter_sink_last = sdcard_block2mem_fifo_source_last; +assign sdcard_block2mem_converter_sink_payload_data = sdcard_block2mem_fifo_source_payload_data; +assign sdcard_block2mem_wishbonedmawriter_sink_valid = sdcard_block2mem_source_source_valid; +assign sdcard_block2mem_source_source_ready = sdcard_block2mem_wishbonedmawriter_sink_ready; +assign sdcard_block2mem_wishbonedmawriter_sink_first = sdcard_block2mem_source_source_first; +assign sdcard_block2mem_wishbonedmawriter_sink_last = sdcard_block2mem_source_source_last; +assign sdcard_block2mem_wishbonedmawriter_sink_payload_data = sdcard_block2mem_source_source_payload_data; +assign sdcard_block2mem_fifo_syncfifo_din = {sdcard_block2mem_fifo_fifo_in_last, sdcard_block2mem_fifo_fifo_in_first, sdcard_block2mem_fifo_fifo_in_payload_data}; +assign {sdcard_block2mem_fifo_fifo_out_last, sdcard_block2mem_fifo_fifo_out_first, sdcard_block2mem_fifo_fifo_out_payload_data} = sdcard_block2mem_fifo_syncfifo_dout; +assign sdcard_block2mem_fifo_sink_ready = sdcard_block2mem_fifo_syncfifo_writable; +assign sdcard_block2mem_fifo_syncfifo_we = sdcard_block2mem_fifo_sink_valid; +assign sdcard_block2mem_fifo_fifo_in_first = sdcard_block2mem_fifo_sink_first; +assign sdcard_block2mem_fifo_fifo_in_last = sdcard_block2mem_fifo_sink_last; +assign sdcard_block2mem_fifo_fifo_in_payload_data = sdcard_block2mem_fifo_sink_payload_data; +assign sdcard_block2mem_fifo_source_valid = sdcard_block2mem_fifo_readable; +assign sdcard_block2mem_fifo_source_first = sdcard_block2mem_fifo_fifo_out_first; +assign sdcard_block2mem_fifo_source_last = sdcard_block2mem_fifo_fifo_out_last; +assign sdcard_block2mem_fifo_source_payload_data = sdcard_block2mem_fifo_fifo_out_payload_data; +assign sdcard_block2mem_fifo_re = sdcard_block2mem_fifo_source_ready; +assign sdcard_block2mem_fifo_syncfifo_re = (sdcard_block2mem_fifo_syncfifo_readable & ((~sdcard_block2mem_fifo_readable) | sdcard_block2mem_fifo_re)); +assign sdcard_block2mem_fifo_level1 = (sdcard_block2mem_fifo_level0 + sdcard_block2mem_fifo_readable); +always @(*) begin + sdcard_block2mem_fifo_wrport_adr <= 9'd0; + if (sdcard_block2mem_fifo_replace) begin + sdcard_block2mem_fifo_wrport_adr <= (sdcard_block2mem_fifo_produce - 1'd1); + end else begin + sdcard_block2mem_fifo_wrport_adr <= sdcard_block2mem_fifo_produce; + end +end +assign sdcard_block2mem_fifo_wrport_dat_w = sdcard_block2mem_fifo_syncfifo_din; +assign sdcard_block2mem_fifo_wrport_we = (sdcard_block2mem_fifo_syncfifo_we & (sdcard_block2mem_fifo_syncfifo_writable | sdcard_block2mem_fifo_replace)); +assign sdcard_block2mem_fifo_do_read = (sdcard_block2mem_fifo_syncfifo_readable & sdcard_block2mem_fifo_syncfifo_re); +assign sdcard_block2mem_fifo_rdport_adr = sdcard_block2mem_fifo_consume; +assign sdcard_block2mem_fifo_syncfifo_dout = sdcard_block2mem_fifo_rdport_dat_r; +assign sdcard_block2mem_fifo_rdport_re = sdcard_block2mem_fifo_do_read; +assign sdcard_block2mem_fifo_syncfifo_writable = (sdcard_block2mem_fifo_level0 != 10'd512); +assign sdcard_block2mem_fifo_syncfifo_readable = (sdcard_block2mem_fifo_level0 != 1'd0); +assign sdcard_block2mem_source_source_valid = sdcard_block2mem_converter_source_valid; +assign sdcard_block2mem_converter_source_ready = sdcard_block2mem_source_source_ready; +assign sdcard_block2mem_source_source_first = sdcard_block2mem_converter_source_first; +assign sdcard_block2mem_source_source_last = sdcard_block2mem_converter_source_last; +assign sdcard_block2mem_source_source_payload_data = sdcard_block2mem_converter_source_payload_data; +assign sdcard_block2mem_converter_sink_ready = ((~sdcard_block2mem_converter_strobe_all) | sdcard_block2mem_converter_source_ready); +assign sdcard_block2mem_converter_source_valid = sdcard_block2mem_converter_strobe_all; +assign sdcard_block2mem_converter_load_part = (sdcard_block2mem_converter_sink_valid & sdcard_block2mem_converter_sink_ready); +assign interface0_bus_stb = sdcard_block2mem_sink_sink_valid1; +assign interface0_bus_cyc = sdcard_block2mem_sink_sink_valid1; +assign interface0_bus_we = 1'd1; +assign interface0_bus_sel = 4'd15; +assign interface0_bus_adr = sdcard_block2mem_sink_sink_payload_address; +assign interface0_bus_dat_w = {sdcard_block2mem_sink_sink_payload_data1[7:0], sdcard_block2mem_sink_sink_payload_data1[15:8], sdcard_block2mem_sink_sink_payload_data1[23:16], sdcard_block2mem_sink_sink_payload_data1[31:24]}; +assign sdcard_block2mem_sink_sink_ready1 = interface0_bus_ack; +assign sdcard_block2mem_wishbonedmawriter_base = sdcard_block2mem_wishbonedmawriter_base_storage[63:2]; +assign sdcard_block2mem_wishbonedmawriter_length = sdcard_block2mem_wishbonedmawriter_length_storage[31:2]; +assign sdcard_block2mem_wishbonedmawriter_offset_status = sdcard_block2mem_wishbonedmawriter_offset; +assign sdcard_block2mem_wishbonedmawriter_reset = (~sdcard_block2mem_wishbonedmawriter_enable_storage); +always @(*) begin + sdblock2memdma_next_state <= 2'd0; + sdcard_block2mem_sink_sink_last1 <= 1'd0; + sdcard_block2mem_sink_sink_payload_address <= 32'd0; + sdcard_block2mem_sink_sink_payload_data1 <= 32'd0; + sdcard_block2mem_sink_sink_valid1 <= 1'd0; + sdcard_block2mem_wishbonedmawriter_done_status <= 1'd0; + sdcard_block2mem_wishbonedmawriter_offset_sdblock2memdma_next_value <= 32'd0; + sdcard_block2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce <= 1'd0; + sdcard_block2mem_wishbonedmawriter_sink_ready <= 1'd0; + sdblock2memdma_next_state <= sdblock2memdma_state; + case (sdblock2memdma_state) + 1'd1: begin + sdcard_block2mem_sink_sink_valid1 <= sdcard_block2mem_wishbonedmawriter_sink_valid; + sdcard_block2mem_sink_sink_last1 <= (sdcard_block2mem_wishbonedmawriter_sink_last | ((sdcard_block2mem_wishbonedmawriter_offset + 1'd1) == sdcard_block2mem_wishbonedmawriter_length)); + sdcard_block2mem_sink_sink_payload_address <= (sdcard_block2mem_wishbonedmawriter_base + sdcard_block2mem_wishbonedmawriter_offset); + sdcard_block2mem_sink_sink_payload_data1 <= sdcard_block2mem_wishbonedmawriter_sink_payload_data; + sdcard_block2mem_wishbonedmawriter_sink_ready <= sdcard_block2mem_sink_sink_ready1; + if ((sdcard_block2mem_wishbonedmawriter_sink_valid & sdcard_block2mem_wishbonedmawriter_sink_ready)) begin + sdcard_block2mem_wishbonedmawriter_offset_sdblock2memdma_next_value <= (sdcard_block2mem_wishbonedmawriter_offset + 1'd1); + sdcard_block2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce <= 1'd1; + if (sdcard_block2mem_sink_sink_last1) begin + if (sdcard_block2mem_wishbonedmawriter_loop_storage) begin + sdcard_block2mem_wishbonedmawriter_offset_sdblock2memdma_next_value <= 1'd0; + sdcard_block2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce <= 1'd1; + end else begin + sdblock2memdma_next_state <= 2'd2; + end + end + end + end + 2'd2: begin + sdcard_block2mem_wishbonedmawriter_done_status <= 1'd1; + end + default: begin + sdcard_block2mem_wishbonedmawriter_sink_ready <= 1'd1; + sdcard_block2mem_wishbonedmawriter_offset_sdblock2memdma_next_value <= 1'd0; + sdcard_block2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce <= 1'd1; + sdblock2memdma_next_state <= 1'd1; + end + endcase +end +assign sdcard_mem2block_converter_converter_sink_valid = sdcard_mem2block_dma_source_source_valid; +assign sdcard_mem2block_dma_source_source_ready = sdcard_mem2block_converter_converter_sink_ready; +assign sdcard_mem2block_converter_converter_sink_first = sdcard_mem2block_dma_source_source_first; +assign sdcard_mem2block_converter_converter_sink_last = sdcard_mem2block_dma_source_source_last; +assign sdcard_mem2block_converter_converter_sink_payload_data = sdcard_mem2block_dma_source_source_payload_data; +assign sdcard_mem2block_fifo_sink_valid = sdcard_mem2block_converter_source_source_valid; +assign sdcard_mem2block_converter_source_source_ready = sdcard_mem2block_fifo_sink_ready; +assign sdcard_mem2block_fifo_sink_first = sdcard_mem2block_converter_source_source_first; +assign sdcard_mem2block_fifo_sink_last = sdcard_mem2block_converter_source_source_last; +assign sdcard_mem2block_fifo_sink_payload_data = sdcard_mem2block_converter_source_source_payload_data; +assign sdcard_mem2block_source_source_valid = sdcard_mem2block_fifo_source_valid; +assign sdcard_mem2block_fifo_source_ready = sdcard_mem2block_source_source_ready; +assign sdcard_mem2block_source_source_first = sdcard_mem2block_fifo_source_first; +assign sdcard_mem2block_source_source_payload_data = sdcard_mem2block_fifo_source_payload_data; +always @(*) begin + sdcard_mem2block_source_source_last <= 1'd0; + sdcard_mem2block_source_source_last <= sdcard_mem2block_fifo_source_last; + if ((sdcard_mem2block_count == 9'd511)) begin + sdcard_mem2block_source_source_last <= 1'd1; + end +end +assign interface1_bus_stb = (sdcard_mem2block_dma_sink_sink_valid & sdcard_mem2block_dma_fifo_sink_ready); +assign interface1_bus_cyc = (sdcard_mem2block_dma_sink_sink_valid & sdcard_mem2block_dma_fifo_sink_ready); +assign interface1_bus_we = 1'd0; +assign interface1_bus_sel = 4'd15; +assign interface1_bus_adr = sdcard_mem2block_dma_sink_sink_payload_address; +assign sdcard_mem2block_dma_fifo_sink_last = sdcard_mem2block_dma_sink_sink_last; +assign sdcard_mem2block_dma_fifo_sink_payload_data = {interface1_bus_dat_r[7:0], interface1_bus_dat_r[15:8], interface1_bus_dat_r[23:16], interface1_bus_dat_r[31:24]}; +always @(*) begin + sdcard_mem2block_dma_fifo_sink_valid <= 1'd0; + sdcard_mem2block_dma_sink_sink_ready <= 1'd0; + if ((interface1_bus_stb & interface1_bus_ack)) begin + sdcard_mem2block_dma_sink_sink_ready <= 1'd1; + sdcard_mem2block_dma_fifo_sink_valid <= 1'd1; + end +end +assign sdcard_mem2block_dma_source_source_valid = sdcard_mem2block_dma_fifo_source_valid; +assign sdcard_mem2block_dma_fifo_source_ready = sdcard_mem2block_dma_source_source_ready; +assign sdcard_mem2block_dma_source_source_first = sdcard_mem2block_dma_fifo_source_first; +assign sdcard_mem2block_dma_source_source_last = sdcard_mem2block_dma_fifo_source_last; +assign sdcard_mem2block_dma_source_source_payload_data = sdcard_mem2block_dma_fifo_source_payload_data; +assign sdcard_mem2block_dma_base = sdcard_mem2block_dma_base_storage[63:2]; +assign sdcard_mem2block_dma_length = sdcard_mem2block_dma_length_storage[31:2]; +assign sdcard_mem2block_dma_offset_status = sdcard_mem2block_dma_offset; +assign sdcard_mem2block_dma_reset = (~sdcard_mem2block_dma_enable_storage); +assign sdcard_mem2block_dma_fifo_syncfifo_din = {sdcard_mem2block_dma_fifo_fifo_in_last, sdcard_mem2block_dma_fifo_fifo_in_first, sdcard_mem2block_dma_fifo_fifo_in_payload_data}; +assign {sdcard_mem2block_dma_fifo_fifo_out_last, sdcard_mem2block_dma_fifo_fifo_out_first, sdcard_mem2block_dma_fifo_fifo_out_payload_data} = sdcard_mem2block_dma_fifo_syncfifo_dout; +assign sdcard_mem2block_dma_fifo_sink_ready = sdcard_mem2block_dma_fifo_syncfifo_writable; +assign sdcard_mem2block_dma_fifo_syncfifo_we = sdcard_mem2block_dma_fifo_sink_valid; +assign sdcard_mem2block_dma_fifo_fifo_in_first = sdcard_mem2block_dma_fifo_sink_first; +assign sdcard_mem2block_dma_fifo_fifo_in_last = sdcard_mem2block_dma_fifo_sink_last; +assign sdcard_mem2block_dma_fifo_fifo_in_payload_data = sdcard_mem2block_dma_fifo_sink_payload_data; +assign sdcard_mem2block_dma_fifo_source_valid = sdcard_mem2block_dma_fifo_syncfifo_readable; +assign sdcard_mem2block_dma_fifo_source_first = sdcard_mem2block_dma_fifo_fifo_out_first; +assign sdcard_mem2block_dma_fifo_source_last = sdcard_mem2block_dma_fifo_fifo_out_last; +assign sdcard_mem2block_dma_fifo_source_payload_data = sdcard_mem2block_dma_fifo_fifo_out_payload_data; +assign sdcard_mem2block_dma_fifo_syncfifo_re = sdcard_mem2block_dma_fifo_source_ready; +always @(*) begin + sdcard_mem2block_dma_fifo_wrport_adr <= 4'd0; + if (sdcard_mem2block_dma_fifo_replace) begin + sdcard_mem2block_dma_fifo_wrport_adr <= (sdcard_mem2block_dma_fifo_produce - 1'd1); + end else begin + sdcard_mem2block_dma_fifo_wrport_adr <= sdcard_mem2block_dma_fifo_produce; + end +end +assign sdcard_mem2block_dma_fifo_wrport_dat_w = sdcard_mem2block_dma_fifo_syncfifo_din; +assign sdcard_mem2block_dma_fifo_wrport_we = (sdcard_mem2block_dma_fifo_syncfifo_we & (sdcard_mem2block_dma_fifo_syncfifo_writable | sdcard_mem2block_dma_fifo_replace)); +assign sdcard_mem2block_dma_fifo_do_read = (sdcard_mem2block_dma_fifo_syncfifo_readable & sdcard_mem2block_dma_fifo_syncfifo_re); +assign sdcard_mem2block_dma_fifo_rdport_adr = sdcard_mem2block_dma_fifo_consume; +assign sdcard_mem2block_dma_fifo_syncfifo_dout = sdcard_mem2block_dma_fifo_rdport_dat_r; +assign sdcard_mem2block_dma_fifo_syncfifo_writable = (sdcard_mem2block_dma_fifo_level != 5'd16); +assign sdcard_mem2block_dma_fifo_syncfifo_readable = (sdcard_mem2block_dma_fifo_level != 1'd0); +always @(*) begin + sdcard_mem2block_dma_done_status <= 1'd0; + sdcard_mem2block_dma_offset_sdmem2blockdma_next_value <= 32'd0; + sdcard_mem2block_dma_offset_sdmem2blockdma_next_value_ce <= 1'd0; + sdcard_mem2block_dma_sink_sink_last <= 1'd0; + sdcard_mem2block_dma_sink_sink_payload_address <= 32'd0; + sdcard_mem2block_dma_sink_sink_valid <= 1'd0; + sdmem2blockdma_next_state <= 2'd0; + sdmem2blockdma_next_state <= sdmem2blockdma_state; + case (sdmem2blockdma_state) + 1'd1: begin + sdcard_mem2block_dma_sink_sink_valid <= 1'd1; + sdcard_mem2block_dma_sink_sink_last <= (sdcard_mem2block_dma_offset == (sdcard_mem2block_dma_length - 1'd1)); + sdcard_mem2block_dma_sink_sink_payload_address <= (sdcard_mem2block_dma_base + sdcard_mem2block_dma_offset); + if (sdcard_mem2block_dma_sink_sink_ready) begin + sdcard_mem2block_dma_offset_sdmem2blockdma_next_value <= (sdcard_mem2block_dma_offset + 1'd1); + sdcard_mem2block_dma_offset_sdmem2blockdma_next_value_ce <= 1'd1; + if (sdcard_mem2block_dma_sink_sink_last) begin + if (sdcard_mem2block_dma_loop_storage) begin + sdcard_mem2block_dma_offset_sdmem2blockdma_next_value <= 1'd0; + sdcard_mem2block_dma_offset_sdmem2blockdma_next_value_ce <= 1'd1; + end else begin + sdmem2blockdma_next_state <= 2'd2; + end + end + end + end + 2'd2: begin + sdcard_mem2block_dma_done_status <= 1'd1; + end + default: begin + sdcard_mem2block_dma_offset_sdmem2blockdma_next_value <= 1'd0; + sdcard_mem2block_dma_offset_sdmem2blockdma_next_value_ce <= 1'd1; + sdmem2blockdma_next_state <= 1'd1; + end + endcase +end +assign sdcard_mem2block_converter_source_source_valid = sdcard_mem2block_converter_converter_source_valid; +assign sdcard_mem2block_converter_converter_source_ready = sdcard_mem2block_converter_source_source_ready; +assign sdcard_mem2block_converter_source_source_first = sdcard_mem2block_converter_converter_source_first; +assign sdcard_mem2block_converter_source_source_last = sdcard_mem2block_converter_converter_source_last; +assign sdcard_mem2block_converter_source_source_payload_data = sdcard_mem2block_converter_converter_source_payload_data; +assign sdcard_mem2block_converter_converter_first = (sdcard_mem2block_converter_converter_mux == 1'd0); +assign sdcard_mem2block_converter_converter_last = (sdcard_mem2block_converter_converter_mux == 2'd3); +assign sdcard_mem2block_converter_converter_source_valid = sdcard_mem2block_converter_converter_sink_valid; +assign sdcard_mem2block_converter_converter_source_first = (sdcard_mem2block_converter_converter_sink_first & sdcard_mem2block_converter_converter_first); +assign sdcard_mem2block_converter_converter_source_last = (sdcard_mem2block_converter_converter_sink_last & sdcard_mem2block_converter_converter_last); +assign sdcard_mem2block_converter_converter_sink_ready = (sdcard_mem2block_converter_converter_last & sdcard_mem2block_converter_converter_source_ready); +always @(*) begin + sdcard_mem2block_converter_converter_source_payload_data <= 8'd0; + case (sdcard_mem2block_converter_converter_mux) + 1'd0: begin + sdcard_mem2block_converter_converter_source_payload_data <= sdcard_mem2block_converter_converter_sink_payload_data[31:24]; + end + 1'd1: begin + sdcard_mem2block_converter_converter_source_payload_data <= sdcard_mem2block_converter_converter_sink_payload_data[23:16]; + end + 2'd2: begin + sdcard_mem2block_converter_converter_source_payload_data <= sdcard_mem2block_converter_converter_sink_payload_data[15:8]; + end + default: begin + sdcard_mem2block_converter_converter_source_payload_data <= sdcard_mem2block_converter_converter_sink_payload_data[7:0]; + end + endcase +end +assign sdcard_mem2block_converter_converter_source_payload_valid_token_count = sdcard_mem2block_converter_converter_last; +assign sdcard_mem2block_fifo_syncfifo_din = {sdcard_mem2block_fifo_fifo_in_last, sdcard_mem2block_fifo_fifo_in_first, sdcard_mem2block_fifo_fifo_in_payload_data}; +assign {sdcard_mem2block_fifo_fifo_out_last, sdcard_mem2block_fifo_fifo_out_first, sdcard_mem2block_fifo_fifo_out_payload_data} = sdcard_mem2block_fifo_syncfifo_dout; +assign sdcard_mem2block_fifo_sink_ready = sdcard_mem2block_fifo_syncfifo_writable; +assign sdcard_mem2block_fifo_syncfifo_we = sdcard_mem2block_fifo_sink_valid; +assign sdcard_mem2block_fifo_fifo_in_first = sdcard_mem2block_fifo_sink_first; +assign sdcard_mem2block_fifo_fifo_in_last = sdcard_mem2block_fifo_sink_last; +assign sdcard_mem2block_fifo_fifo_in_payload_data = sdcard_mem2block_fifo_sink_payload_data; +assign sdcard_mem2block_fifo_source_valid = sdcard_mem2block_fifo_readable; +assign sdcard_mem2block_fifo_source_first = sdcard_mem2block_fifo_fifo_out_first; +assign sdcard_mem2block_fifo_source_last = sdcard_mem2block_fifo_fifo_out_last; +assign sdcard_mem2block_fifo_source_payload_data = sdcard_mem2block_fifo_fifo_out_payload_data; +assign sdcard_mem2block_fifo_re = sdcard_mem2block_fifo_source_ready; +assign sdcard_mem2block_fifo_syncfifo_re = (sdcard_mem2block_fifo_syncfifo_readable & ((~sdcard_mem2block_fifo_readable) | sdcard_mem2block_fifo_re)); +assign sdcard_mem2block_fifo_level1 = (sdcard_mem2block_fifo_level0 + sdcard_mem2block_fifo_readable); +always @(*) begin + sdcard_mem2block_fifo_wrport_adr <= 9'd0; + if (sdcard_mem2block_fifo_replace) begin + sdcard_mem2block_fifo_wrport_adr <= (sdcard_mem2block_fifo_produce - 1'd1); + end else begin + sdcard_mem2block_fifo_wrport_adr <= sdcard_mem2block_fifo_produce; + end +end +assign sdcard_mem2block_fifo_wrport_dat_w = sdcard_mem2block_fifo_syncfifo_din; +assign sdcard_mem2block_fifo_wrport_we = (sdcard_mem2block_fifo_syncfifo_we & (sdcard_mem2block_fifo_syncfifo_writable | sdcard_mem2block_fifo_replace)); +assign sdcard_mem2block_fifo_do_read = (sdcard_mem2block_fifo_syncfifo_readable & sdcard_mem2block_fifo_syncfifo_re); +assign sdcard_mem2block_fifo_rdport_adr = sdcard_mem2block_fifo_consume; +assign sdcard_mem2block_fifo_syncfifo_dout = sdcard_mem2block_fifo_rdport_dat_r; +assign sdcard_mem2block_fifo_rdport_re = sdcard_mem2block_fifo_do_read; +assign sdcard_mem2block_fifo_syncfifo_writable = (sdcard_mem2block_fifo_level0 != 10'd512); +assign sdcard_mem2block_fifo_syncfifo_readable = (sdcard_mem2block_fifo_level0 != 1'd0); +assign eventmanager_card_detect0 = card_detect_status1; +assign eventmanager_card_detect1 = card_detect_pending; +always @(*) begin + card_detect_clear <= 1'd0; + if ((eventmanager_pending_re & eventmanager_pending_r[0])) begin + card_detect_clear <= 1'd1; + end +end +assign eventmanager_block2mem_dma0 = block2mem_dma_status; +assign eventmanager_block2mem_dma1 = block2mem_dma_pending; +always @(*) begin + block2mem_dma_clear <= 1'd0; + if ((eventmanager_pending_re & eventmanager_pending_r[1])) begin + block2mem_dma_clear <= 1'd1; + end +end +assign eventmanager_mem2block_dma0 = mem2block_dma_status; +assign eventmanager_mem2block_dma1 = mem2block_dma_pending; +always @(*) begin + mem2block_dma_clear <= 1'd0; + if ((eventmanager_pending_re & eventmanager_pending_r[2])) begin + mem2block_dma_clear <= 1'd1; + end +end +assign eventmanager_cmd_done0 = cmd_done_status; +assign eventmanager_cmd_done1 = cmd_done_pending; +always @(*) begin + cmd_done_clear <= 1'd0; + if ((eventmanager_pending_re & eventmanager_pending_r[3])) begin + cmd_done_clear <= 1'd1; + end +end +assign sdcard_irq_irq = ((((eventmanager_pending_status[0] & eventmanager_enable_storage[0]) | (eventmanager_pending_status[1] & eventmanager_enable_storage[1])) | (eventmanager_pending_status[2] & eventmanager_enable_storage[2])) | (eventmanager_pending_status[3] & eventmanager_enable_storage[3])); +assign card_detect_status1 = 1'd0; +assign block2mem_dma_status = 1'd0; +assign mem2block_dma_status = 1'd0; +assign cmd_done_status = cmd_done_trigger; +assign cmd_done_pending = cmd_done_trigger; +always @(*) begin + interface0_ack <= 1'd0; + interface0_dat_r <= 32'd0; + interface1_adr <= 14'd0; + interface1_dat_w <= 32'd0; + interface1_we <= 1'd0; + wishbone2csr_next_state <= 1'd0; + wishbone2csr_next_state <= wishbone2csr_state; + case (wishbone2csr_state) + 1'd1: begin + interface0_ack <= 1'd1; + interface0_dat_r <= interface1_dat_r; + wishbone2csr_next_state <= 1'd0; + end + default: begin + interface1_dat_w <= interface0_dat_w; + if ((interface0_cyc & interface0_stb)) begin + interface1_adr <= interface0_adr[29:0]; + interface1_we <= (interface0_we & (interface0_sel != 1'd0)); + wishbone2csr_next_state <= 1'd1; + end + end + endcase +end +assign csrbank0_sel = (interface0_bank_bus_adr[13:9] == 1'd0); +assign csrbank0_reset0_r = interface0_bank_bus_dat_w[1:0]; +always @(*) begin + csrbank0_reset0_re <= 1'd0; + csrbank0_reset0_we <= 1'd0; + if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd0))) begin + csrbank0_reset0_re <= interface0_bank_bus_we; + csrbank0_reset0_we <= (~interface0_bank_bus_we); + end +end +assign csrbank0_scratch0_r = interface0_bank_bus_dat_w[31:0]; +always @(*) begin + csrbank0_scratch0_re <= 1'd0; + csrbank0_scratch0_we <= 1'd0; + if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd1))) begin + csrbank0_scratch0_re <= interface0_bank_bus_we; + csrbank0_scratch0_we <= (~interface0_bank_bus_we); + end +end +assign csrbank0_bus_errors_r = interface0_bank_bus_dat_w[31:0]; +always @(*) begin + csrbank0_bus_errors_re <= 1'd0; + csrbank0_bus_errors_we <= 1'd0; + if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 2'd2))) begin + csrbank0_bus_errors_re <= interface0_bank_bus_we; + csrbank0_bus_errors_we <= (~interface0_bank_bus_we); + end +end +always @(*) begin + soc_rst <= 1'd0; + if (reset_re) begin + soc_rst <= reset_storage[0]; + end +end +assign cpu_rst = reset_storage[1]; +assign csrbank0_reset0_w = reset_storage[1:0]; +assign csrbank0_scratch0_w = scratch_storage[31:0]; +assign csrbank0_bus_errors_w = bus_errors_status[31:0]; +assign bus_errors_we = csrbank0_bus_errors_we; +assign csrbank1_sel = (interface1_bank_bus_adr[13:9] == 1'd1); +assign csrbank1_dma_base1_r = interface1_bank_bus_dat_w[31:0]; +always @(*) begin + csrbank1_dma_base1_re <= 1'd0; + csrbank1_dma_base1_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd0))) begin + csrbank1_dma_base1_re <= interface1_bank_bus_we; + csrbank1_dma_base1_we <= (~interface1_bank_bus_we); + end +end +assign csrbank1_dma_base0_r = interface1_bank_bus_dat_w[31:0]; +always @(*) begin + csrbank1_dma_base0_re <= 1'd0; + csrbank1_dma_base0_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd1))) begin + csrbank1_dma_base0_re <= interface1_bank_bus_we; + csrbank1_dma_base0_we <= (~interface1_bank_bus_we); + end +end +assign csrbank1_dma_length0_r = interface1_bank_bus_dat_w[31:0]; +always @(*) begin + csrbank1_dma_length0_re <= 1'd0; + csrbank1_dma_length0_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd2))) begin + csrbank1_dma_length0_re <= interface1_bank_bus_we; + csrbank1_dma_length0_we <= (~interface1_bank_bus_we); + end +end +assign csrbank1_dma_enable0_r = interface1_bank_bus_dat_w[0]; +always @(*) begin + csrbank1_dma_enable0_re <= 1'd0; + csrbank1_dma_enable0_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd3))) begin + csrbank1_dma_enable0_re <= interface1_bank_bus_we; + csrbank1_dma_enable0_we <= (~interface1_bank_bus_we); + end +end +assign csrbank1_dma_done_r = interface1_bank_bus_dat_w[0]; +always @(*) begin + csrbank1_dma_done_re <= 1'd0; + csrbank1_dma_done_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd4))) begin + csrbank1_dma_done_re <= interface1_bank_bus_we; + csrbank1_dma_done_we <= (~interface1_bank_bus_we); + end +end +assign csrbank1_dma_loop0_r = interface1_bank_bus_dat_w[0]; +always @(*) begin + csrbank1_dma_loop0_re <= 1'd0; + csrbank1_dma_loop0_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd5))) begin + csrbank1_dma_loop0_re <= interface1_bank_bus_we; + csrbank1_dma_loop0_we <= (~interface1_bank_bus_we); + end +end +assign csrbank1_dma_offset_r = interface1_bank_bus_dat_w[31:0]; +always @(*) begin + csrbank1_dma_offset_re <= 1'd0; + csrbank1_dma_offset_we <= 1'd0; + if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd6))) begin + csrbank1_dma_offset_re <= interface1_bank_bus_we; + csrbank1_dma_offset_we <= (~interface1_bank_bus_we); + end +end +assign csrbank1_dma_base1_w = sdcard_block2mem_wishbonedmawriter_base_storage[63:32]; +assign csrbank1_dma_base0_w = sdcard_block2mem_wishbonedmawriter_base_storage[31:0]; +assign csrbank1_dma_length0_w = sdcard_block2mem_wishbonedmawriter_length_storage[31:0]; +assign csrbank1_dma_enable0_w = sdcard_block2mem_wishbonedmawriter_enable_storage; +assign csrbank1_dma_done_w = sdcard_block2mem_wishbonedmawriter_done_status; +assign sdcard_block2mem_wishbonedmawriter_done_we = csrbank1_dma_done_we; +assign csrbank1_dma_loop0_w = sdcard_block2mem_wishbonedmawriter_loop_storage; +assign csrbank1_dma_offset_w = sdcard_block2mem_wishbonedmawriter_offset_status[31:0]; +assign sdcard_block2mem_wishbonedmawriter_offset_we = csrbank1_dma_offset_we; +assign csrbank2_sel = (interface2_bank_bus_adr[13:9] == 2'd2); +assign csrbank2_cmd_argument0_r = interface2_bank_bus_dat_w[31:0]; +always @(*) begin + csrbank2_cmd_argument0_re <= 1'd0; + csrbank2_cmd_argument0_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd0))) begin + csrbank2_cmd_argument0_re <= interface2_bank_bus_we; + csrbank2_cmd_argument0_we <= (~interface2_bank_bus_we); + end +end +assign csrbank2_cmd_command0_r = interface2_bank_bus_dat_w[13:0]; +always @(*) begin + csrbank2_cmd_command0_re <= 1'd0; + csrbank2_cmd_command0_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd1))) begin + csrbank2_cmd_command0_re <= interface2_bank_bus_we; + csrbank2_cmd_command0_we <= (~interface2_bank_bus_we); + end +end +assign csrbank2_cmd_send0_r = interface2_bank_bus_dat_w[0]; +always @(*) begin + csrbank2_cmd_send0_re <= 1'd0; + csrbank2_cmd_send0_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd2))) begin + csrbank2_cmd_send0_re <= interface2_bank_bus_we; + csrbank2_cmd_send0_we <= (~interface2_bank_bus_we); + end +end +assign csrbank2_cmd_response3_r = interface2_bank_bus_dat_w[31:0]; +always @(*) begin + csrbank2_cmd_response3_re <= 1'd0; + csrbank2_cmd_response3_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd3))) begin + csrbank2_cmd_response3_re <= interface2_bank_bus_we; + csrbank2_cmd_response3_we <= (~interface2_bank_bus_we); + end +end +assign csrbank2_cmd_response2_r = interface2_bank_bus_dat_w[31:0]; +always @(*) begin + csrbank2_cmd_response2_re <= 1'd0; + csrbank2_cmd_response2_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd4))) begin + csrbank2_cmd_response2_re <= interface2_bank_bus_we; + csrbank2_cmd_response2_we <= (~interface2_bank_bus_we); + end +end +assign csrbank2_cmd_response1_r = interface2_bank_bus_dat_w[31:0]; +always @(*) begin + csrbank2_cmd_response1_re <= 1'd0; + csrbank2_cmd_response1_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd5))) begin + csrbank2_cmd_response1_re <= interface2_bank_bus_we; + csrbank2_cmd_response1_we <= (~interface2_bank_bus_we); + end +end +assign csrbank2_cmd_response0_r = interface2_bank_bus_dat_w[31:0]; +always @(*) begin + csrbank2_cmd_response0_re <= 1'd0; + csrbank2_cmd_response0_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd6))) begin + csrbank2_cmd_response0_re <= interface2_bank_bus_we; + csrbank2_cmd_response0_we <= (~interface2_bank_bus_we); + end +end +assign csrbank2_cmd_event_r = interface2_bank_bus_dat_w[3:0]; +always @(*) begin + csrbank2_cmd_event_re <= 1'd0; + csrbank2_cmd_event_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd7))) begin + csrbank2_cmd_event_re <= interface2_bank_bus_we; + csrbank2_cmd_event_we <= (~interface2_bank_bus_we); + end +end +assign csrbank2_data_event_r = interface2_bank_bus_dat_w[3:0]; +always @(*) begin + csrbank2_data_event_re <= 1'd0; + csrbank2_data_event_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd8))) begin + csrbank2_data_event_re <= interface2_bank_bus_we; + csrbank2_data_event_we <= (~interface2_bank_bus_we); + end +end +assign csrbank2_block_length0_r = interface2_bank_bus_dat_w[9:0]; +always @(*) begin + csrbank2_block_length0_re <= 1'd0; + csrbank2_block_length0_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd9))) begin + csrbank2_block_length0_re <= interface2_bank_bus_we; + csrbank2_block_length0_we <= (~interface2_bank_bus_we); + end +end +assign csrbank2_block_count0_r = interface2_bank_bus_dat_w[31:0]; +always @(*) begin + csrbank2_block_count0_re <= 1'd0; + csrbank2_block_count0_we <= 1'd0; + if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd10))) begin + csrbank2_block_count0_re <= interface2_bank_bus_we; + csrbank2_block_count0_we <= (~interface2_bank_bus_we); + end +end +assign csrbank2_cmd_argument0_w = sdcard_core_cmd_argument_storage[31:0]; +assign sdcard_core_csrfield_cmd_type = sdcard_core_cmd_command_storage[1:0]; +assign sdcard_core_csrfield_data_type = sdcard_core_cmd_command_storage[6:5]; +assign sdcard_core_csrfield_cmd = sdcard_core_cmd_command_storage[13:8]; +assign csrbank2_cmd_command0_w = sdcard_core_cmd_command_storage[13:0]; +assign csrbank2_cmd_send0_w = sdcard_core_cmd_send_storage; +assign csrbank2_cmd_response3_w = sdcard_core_cmd_response_status[127:96]; +assign csrbank2_cmd_response2_w = sdcard_core_cmd_response_status[95:64]; +assign csrbank2_cmd_response1_w = sdcard_core_cmd_response_status[63:32]; +assign csrbank2_cmd_response0_w = sdcard_core_cmd_response_status[31:0]; +assign sdcard_core_cmd_response_we = csrbank2_cmd_response0_we; +always @(*) begin + sdcard_core_cmd_event_status <= 4'd0; + sdcard_core_cmd_event_status[0] <= sdcard_core_csrfield_done0; + sdcard_core_cmd_event_status[1] <= sdcard_core_csrfield_error0; + sdcard_core_cmd_event_status[2] <= sdcard_core_csrfield_timeout0; + sdcard_core_cmd_event_status[3] <= sdcard_core_csrfield_crc0; +end +assign csrbank2_cmd_event_w = sdcard_core_cmd_event_status[3:0]; +assign sdcard_core_cmd_event_we = csrbank2_cmd_event_we; +always @(*) begin + sdcard_core_data_event_status <= 4'd0; + sdcard_core_data_event_status[0] <= sdcard_core_csrfield_done1; + sdcard_core_data_event_status[1] <= sdcard_core_csrfield_error1; + sdcard_core_data_event_status[2] <= sdcard_core_csrfield_timeout1; + sdcard_core_data_event_status[3] <= sdcard_core_csrfield_crc1; +end +assign csrbank2_data_event_w = sdcard_core_data_event_status[3:0]; +assign sdcard_core_data_event_we = csrbank2_data_event_we; +assign csrbank2_block_length0_w = sdcard_core_block_length_storage[9:0]; +assign csrbank2_block_count0_w = sdcard_core_block_count_storage[31:0]; +assign csrbank3_sel = (interface3_bank_bus_adr[13:9] == 2'd3); +assign csrbank3_status_r = interface3_bank_bus_dat_w[3:0]; +always @(*) begin + csrbank3_status_re <= 1'd0; + csrbank3_status_we <= 1'd0; + if ((csrbank3_sel & (interface3_bank_bus_adr[8:0] == 1'd0))) begin + csrbank3_status_re <= interface3_bank_bus_we; + csrbank3_status_we <= (~interface3_bank_bus_we); + end +end +assign csrbank3_pending_r = interface3_bank_bus_dat_w[3:0]; +always @(*) begin + csrbank3_pending_re <= 1'd0; + csrbank3_pending_we <= 1'd0; + if ((csrbank3_sel & (interface3_bank_bus_adr[8:0] == 1'd1))) begin + csrbank3_pending_re <= interface3_bank_bus_we; + csrbank3_pending_we <= (~interface3_bank_bus_we); + end +end +assign csrbank3_enable0_r = interface3_bank_bus_dat_w[3:0]; +always @(*) begin + csrbank3_enable0_re <= 1'd0; + csrbank3_enable0_we <= 1'd0; + if ((csrbank3_sel & (interface3_bank_bus_adr[8:0] == 2'd2))) begin + csrbank3_enable0_re <= interface3_bank_bus_we; + csrbank3_enable0_we <= (~interface3_bank_bus_we); + end +end +always @(*) begin + eventmanager_status_status <= 4'd0; + eventmanager_status_status[0] <= eventmanager_card_detect0; + eventmanager_status_status[1] <= eventmanager_block2mem_dma0; + eventmanager_status_status[2] <= eventmanager_mem2block_dma0; + eventmanager_status_status[3] <= eventmanager_cmd_done0; +end +assign csrbank3_status_w = eventmanager_status_status[3:0]; +assign eventmanager_status_we = csrbank3_status_we; +always @(*) begin + eventmanager_pending_status <= 4'd0; + eventmanager_pending_status[0] <= eventmanager_card_detect1; + eventmanager_pending_status[1] <= eventmanager_block2mem_dma1; + eventmanager_pending_status[2] <= eventmanager_mem2block_dma1; + eventmanager_pending_status[3] <= eventmanager_cmd_done1; +end +assign csrbank3_pending_w = eventmanager_pending_status[3:0]; +assign eventmanager_pending_we = csrbank3_pending_we; +assign eventmanager_card_detect2 = eventmanager_enable_storage[0]; +assign eventmanager_block2mem_dma2 = eventmanager_enable_storage[1]; +assign eventmanager_mem2block_dma2 = eventmanager_enable_storage[2]; +assign eventmanager_cmd_done2 = eventmanager_enable_storage[3]; +assign csrbank3_enable0_w = eventmanager_enable_storage[3:0]; +assign csrbank4_sel = (interface4_bank_bus_adr[13:9] == 3'd4); +assign csrbank4_dma_base1_r = interface4_bank_bus_dat_w[31:0]; +always @(*) begin + csrbank4_dma_base1_re <= 1'd0; + csrbank4_dma_base1_we <= 1'd0; + if ((csrbank4_sel & (interface4_bank_bus_adr[8:0] == 1'd0))) begin + csrbank4_dma_base1_re <= interface4_bank_bus_we; + csrbank4_dma_base1_we <= (~interface4_bank_bus_we); + end +end +assign csrbank4_dma_base0_r = interface4_bank_bus_dat_w[31:0]; +always @(*) begin + csrbank4_dma_base0_re <= 1'd0; + csrbank4_dma_base0_we <= 1'd0; + if ((csrbank4_sel & (interface4_bank_bus_adr[8:0] == 1'd1))) begin + csrbank4_dma_base0_re <= interface4_bank_bus_we; + csrbank4_dma_base0_we <= (~interface4_bank_bus_we); + end +end +assign csrbank4_dma_length0_r = interface4_bank_bus_dat_w[31:0]; +always @(*) begin + csrbank4_dma_length0_re <= 1'd0; + csrbank4_dma_length0_we <= 1'd0; + if ((csrbank4_sel & (interface4_bank_bus_adr[8:0] == 2'd2))) begin + csrbank4_dma_length0_re <= interface4_bank_bus_we; + csrbank4_dma_length0_we <= (~interface4_bank_bus_we); + end +end +assign csrbank4_dma_enable0_r = interface4_bank_bus_dat_w[0]; +always @(*) begin + csrbank4_dma_enable0_re <= 1'd0; + csrbank4_dma_enable0_we <= 1'd0; + if ((csrbank4_sel & (interface4_bank_bus_adr[8:0] == 2'd3))) begin + csrbank4_dma_enable0_re <= interface4_bank_bus_we; + csrbank4_dma_enable0_we <= (~interface4_bank_bus_we); + end +end +assign csrbank4_dma_done_r = interface4_bank_bus_dat_w[0]; +always @(*) begin + csrbank4_dma_done_re <= 1'd0; + csrbank4_dma_done_we <= 1'd0; + if ((csrbank4_sel & (interface4_bank_bus_adr[8:0] == 3'd4))) begin + csrbank4_dma_done_re <= interface4_bank_bus_we; + csrbank4_dma_done_we <= (~interface4_bank_bus_we); + end +end +assign csrbank4_dma_loop0_r = interface4_bank_bus_dat_w[0]; +always @(*) begin + csrbank4_dma_loop0_re <= 1'd0; + csrbank4_dma_loop0_we <= 1'd0; + if ((csrbank4_sel & (interface4_bank_bus_adr[8:0] == 3'd5))) begin + csrbank4_dma_loop0_re <= interface4_bank_bus_we; + csrbank4_dma_loop0_we <= (~interface4_bank_bus_we); + end +end +assign csrbank4_dma_offset_r = interface4_bank_bus_dat_w[31:0]; +always @(*) begin + csrbank4_dma_offset_re <= 1'd0; + csrbank4_dma_offset_we <= 1'd0; + if ((csrbank4_sel & (interface4_bank_bus_adr[8:0] == 3'd6))) begin + csrbank4_dma_offset_re <= interface4_bank_bus_we; + csrbank4_dma_offset_we <= (~interface4_bank_bus_we); + end +end +assign csrbank4_dma_base1_w = sdcard_mem2block_dma_base_storage[63:32]; +assign csrbank4_dma_base0_w = sdcard_mem2block_dma_base_storage[31:0]; +assign csrbank4_dma_length0_w = sdcard_mem2block_dma_length_storage[31:0]; +assign csrbank4_dma_enable0_w = sdcard_mem2block_dma_enable_storage; +assign csrbank4_dma_done_w = sdcard_mem2block_dma_done_status; +assign sdcard_mem2block_dma_done_we = csrbank4_dma_done_we; +assign csrbank4_dma_loop0_w = sdcard_mem2block_dma_loop_storage; +assign csrbank4_dma_offset_w = sdcard_mem2block_dma_offset_status[31:0]; +assign sdcard_mem2block_dma_offset_we = csrbank4_dma_offset_we; +assign csrbank5_sel = (interface5_bank_bus_adr[13:9] == 3'd5); +assign csrbank5_card_detect_r = interface5_bank_bus_dat_w[0]; +always @(*) begin + csrbank5_card_detect_re <= 1'd0; + csrbank5_card_detect_we <= 1'd0; + if ((csrbank5_sel & (interface5_bank_bus_adr[8:0] == 1'd0))) begin + csrbank5_card_detect_re <= interface5_bank_bus_we; + csrbank5_card_detect_we <= (~interface5_bank_bus_we); + end +end +assign csrbank5_clocker_divider0_r = interface5_bank_bus_dat_w[8:0]; +always @(*) begin + csrbank5_clocker_divider0_re <= 1'd0; + csrbank5_clocker_divider0_we <= 1'd0; + if ((csrbank5_sel & (interface5_bank_bus_adr[8:0] == 1'd1))) begin + csrbank5_clocker_divider0_re <= interface5_bank_bus_we; + csrbank5_clocker_divider0_we <= (~interface5_bank_bus_we); + end +end +assign init_initialize_r = interface5_bank_bus_dat_w[0]; +always @(*) begin + init_initialize_re <= 1'd0; + init_initialize_we <= 1'd0; + if ((csrbank5_sel & (interface5_bank_bus_adr[8:0] == 2'd2))) begin + init_initialize_re <= interface5_bank_bus_we; + init_initialize_we <= (~interface5_bank_bus_we); + end +end +assign csrbank5_dataw_status_r = interface5_bank_bus_dat_w[2:0]; +always @(*) begin + csrbank5_dataw_status_re <= 1'd0; + csrbank5_dataw_status_we <= 1'd0; + if ((csrbank5_sel & (interface5_bank_bus_adr[8:0] == 2'd3))) begin + csrbank5_dataw_status_re <= interface5_bank_bus_we; + csrbank5_dataw_status_we <= (~interface5_bank_bus_we); + end +end +assign csrbank5_card_detect_w = card_detect_status0; +assign card_detect_we = csrbank5_card_detect_we; +assign csrbank5_clocker_divider0_w = clocker_storage[8:0]; +always @(*) begin + dataw_status <= 3'd0; + dataw_status[0] <= dataw_accepted0; + dataw_status[1] <= dataw_crc_error0; + dataw_status[2] <= dataw_write_error0; +end +assign csrbank5_dataw_status_w = dataw_status[2:0]; +assign dataw_we = csrbank5_dataw_status_we; +assign adr = interface1_adr; +assign we = interface1_we; +assign dat_w = interface1_dat_w; +assign interface1_dat_r = dat_r; +assign interface0_bank_bus_adr = adr; +assign interface1_bank_bus_adr = adr; +assign interface2_bank_bus_adr = adr; +assign interface3_bank_bus_adr = adr; +assign interface4_bank_bus_adr = adr; +assign interface5_bank_bus_adr = adr; +assign interface0_bank_bus_we = we; +assign interface1_bank_bus_we = we; +assign interface2_bank_bus_we = we; +assign interface3_bank_bus_we = we; +assign interface4_bank_bus_we = we; +assign interface5_bank_bus_we = we; +assign interface0_bank_bus_dat_w = dat_w; +assign interface1_bank_bus_dat_w = dat_w; +assign interface2_bank_bus_dat_w = dat_w; +assign interface3_bank_bus_dat_w = dat_w; +assign interface4_bank_bus_dat_w = dat_w; +assign interface5_bank_bus_dat_w = dat_w; +assign dat_r = (((((interface0_bank_bus_dat_r | interface1_bank_bus_dat_r) | interface2_bank_bus_dat_r) | interface3_bank_bus_dat_r) | interface4_bank_bus_dat_r) | interface5_bank_bus_dat_r); +always @(*) begin + self0 <= 32'd0; + case (grant) + 1'd0: begin + self0 <= interface0_bus_adr; + end + default: begin + self0 <= interface1_bus_adr; + end + endcase +end +always @(*) begin + self1 <= 32'd0; + case (grant) + 1'd0: begin + self1 <= interface0_bus_dat_w; + end + default: begin + self1 <= interface1_bus_dat_w; + end + endcase +end +always @(*) begin + self2 <= 4'd0; + case (grant) + 1'd0: begin + self2 <= interface0_bus_sel; + end + default: begin + self2 <= interface1_bus_sel; + end + endcase +end +always @(*) begin + self3 <= 1'd0; + case (grant) + 1'd0: begin + self3 <= interface0_bus_cyc; + end + default: begin + self3 <= interface1_bus_cyc; + end + endcase +end +always @(*) begin + self4 <= 1'd0; + case (grant) + 1'd0: begin + self4 <= interface0_bus_stb; + end + default: begin + self4 <= interface1_bus_stb; + end + endcase +end +always @(*) begin + self5 <= 1'd0; + case (grant) + 1'd0: begin + self5 <= interface0_bus_we; + end + default: begin + self5 <= interface1_bus_we; + end + endcase +end +always @(*) begin + self6 <= 3'd0; + case (grant) + 1'd0: begin + self6 <= interface0_bus_cti; + end + default: begin + self6 <= interface1_bus_cti; + end + endcase +end +always @(*) begin + self7 <= 2'd0; + case (grant) + 1'd0: begin + self7 <= interface0_bus_bte; + end + default: begin + self7 <= interface1_bus_bte; + end + endcase +end +assign sdrio_clk = sys_clk; +assign sdrio_clk_1 = sys_clk; +assign sdrio_clk_2 = sys_clk; +assign sdrio_clk_3 = sys_clk; +assign sdrio_clk_4 = sys_clk; + + +//------------------------------------------------------------------------------ +// Synchronous Logic +//------------------------------------------------------------------------------ + +always @(posedge por_clk) begin + int_rst <= rst; +end + +always @(posedge sdrio_clk) begin + inferedsdrtristate0_oe <= sdpads_cmd_oe; + inferedsdrtristate1_oe <= sdpads_data_oe; + inferedsdrtristate2_oe <= sdpads_data_oe; + inferedsdrtristate3_oe <= sdpads_data_oe; + inferedsdrtristate4_oe <= sdpads_data_oe; +end + +always @(posedge sys_clk) begin + if ((bus_errors != 32'd4294967295)) begin + if (bus_error) begin + bus_errors <= (bus_errors + 1'd1); + end + end + case (grant) + 1'd0: begin + if ((~request[0])) begin + if (request[1]) begin + grant <= 1'd1; + end + end + end + 1'd1: begin + if ((~request[1])) begin + if (request[0]) begin + grant <= 1'd0; + end + end + end + endcase + slave_sel_r <= slave_sel; + if (wait_1) begin + if ((~done)) begin + count <= (count - 1'd1); + end + end else begin + count <= 20'd1000000; + end + card_detect_d <= card_detect_status0; + card_detect_irq <= (card_detect_status0 ^ card_detect_d); + if ((~clocker_stop)) begin + clocker_clks <= (clocker_clks + 1'd1); + end + clocker_clk_d <= clocker_clk1; + if (clocker_clk_d) begin + clocker_ce_delayed <= clocker_clk_en; + end + sdphyinit_state <= sdphyinit_next_state; + if (init_count_sdphyinit_next_value_ce) begin + init_count <= init_count_sdphyinit_next_value; + end + sdphycmdw_state <= sdphycmdw_next_state; + if (cmdw_count_sdphycmdw_next_value_ce) begin + cmdw_count <= cmdw_count_sdphycmdw_next_value; + end + if (cmdr_cmdr_pads_in_valid) begin + cmdr_cmdr_run <= (cmdr_cmdr_start | cmdr_cmdr_run); + end + if (cmdr_cmdr_converter_converter_source_ready) begin + cmdr_cmdr_converter_converter_strobe_all <= 1'd0; + end + if (cmdr_cmdr_converter_converter_load_part) begin + if (((cmdr_cmdr_converter_converter_demux == 3'd7) | cmdr_cmdr_converter_converter_sink_last)) begin + cmdr_cmdr_converter_converter_demux <= 1'd0; + cmdr_cmdr_converter_converter_strobe_all <= 1'd1; + end else begin + cmdr_cmdr_converter_converter_demux <= (cmdr_cmdr_converter_converter_demux + 1'd1); + end + end + if ((cmdr_cmdr_converter_converter_source_valid & cmdr_cmdr_converter_converter_source_ready)) begin + if ((cmdr_cmdr_converter_converter_sink_valid & cmdr_cmdr_converter_converter_sink_ready)) begin + cmdr_cmdr_converter_converter_source_first <= cmdr_cmdr_converter_converter_sink_first; + cmdr_cmdr_converter_converter_source_last <= cmdr_cmdr_converter_converter_sink_last; + end else begin + cmdr_cmdr_converter_converter_source_first <= 1'd0; + cmdr_cmdr_converter_converter_source_last <= 1'd0; + end + end else begin + if ((cmdr_cmdr_converter_converter_sink_valid & cmdr_cmdr_converter_converter_sink_ready)) begin + cmdr_cmdr_converter_converter_source_first <= (cmdr_cmdr_converter_converter_sink_first | cmdr_cmdr_converter_converter_source_first); + cmdr_cmdr_converter_converter_source_last <= (cmdr_cmdr_converter_converter_sink_last | cmdr_cmdr_converter_converter_source_last); + end + end + if (cmdr_cmdr_converter_converter_load_part) begin + case (cmdr_cmdr_converter_converter_demux) + 1'd0: begin + cmdr_cmdr_converter_converter_source_payload_data[7] <= cmdr_cmdr_converter_converter_sink_payload_data; + end + 1'd1: begin + cmdr_cmdr_converter_converter_source_payload_data[6] <= cmdr_cmdr_converter_converter_sink_payload_data; + end + 2'd2: begin + cmdr_cmdr_converter_converter_source_payload_data[5] <= cmdr_cmdr_converter_converter_sink_payload_data; + end + 2'd3: begin + cmdr_cmdr_converter_converter_source_payload_data[4] <= cmdr_cmdr_converter_converter_sink_payload_data; + end + 3'd4: begin + cmdr_cmdr_converter_converter_source_payload_data[3] <= cmdr_cmdr_converter_converter_sink_payload_data; + end + 3'd5: begin + cmdr_cmdr_converter_converter_source_payload_data[2] <= cmdr_cmdr_converter_converter_sink_payload_data; + end + 3'd6: begin + cmdr_cmdr_converter_converter_source_payload_data[1] <= cmdr_cmdr_converter_converter_sink_payload_data; + end + 3'd7: begin + cmdr_cmdr_converter_converter_source_payload_data[0] <= cmdr_cmdr_converter_converter_sink_payload_data; + end + endcase + end + if (cmdr_cmdr_converter_converter_load_part) begin + cmdr_cmdr_converter_converter_source_payload_valid_token_count <= (cmdr_cmdr_converter_converter_demux + 1'd1); + end + if (((~cmdr_cmdr_buf_pipe_valid_source_valid) | cmdr_cmdr_buf_pipe_valid_source_ready)) begin + cmdr_cmdr_buf_pipe_valid_source_valid <= cmdr_cmdr_buf_pipe_valid_sink_valid; + cmdr_cmdr_buf_pipe_valid_source_first <= cmdr_cmdr_buf_pipe_valid_sink_first; + cmdr_cmdr_buf_pipe_valid_source_last <= cmdr_cmdr_buf_pipe_valid_sink_last; + cmdr_cmdr_buf_pipe_valid_source_payload_data <= cmdr_cmdr_buf_pipe_valid_sink_payload_data; + end + if (cmdr_cmdr_reset) begin + cmdr_cmdr_run <= 1'd0; + cmdr_cmdr_converter_converter_source_payload_data <= 8'd0; + cmdr_cmdr_converter_converter_source_payload_valid_token_count <= 4'd0; + cmdr_cmdr_converter_converter_demux <= 3'd0; + cmdr_cmdr_converter_converter_strobe_all <= 1'd0; + cmdr_cmdr_buf_pipe_valid_source_valid <= 1'd0; + cmdr_cmdr_buf_pipe_valid_source_payload_data <= 8'd0; + end + sdphycmdr_state <= sdphycmdr_next_state; + if (cmdr_timeout_sdphycmdr_next_value_ce0) begin + cmdr_timeout <= cmdr_timeout_sdphycmdr_next_value0; + end + if (cmdr_count_sdphycmdr_next_value_ce1) begin + cmdr_count <= cmdr_count_sdphycmdr_next_value1; + end + if (cmdr_busy_sdphycmdr_next_value_ce2) begin + cmdr_busy <= cmdr_busy_sdphycmdr_next_value2; + end + if (cmdr_cmdr_reset_sdphycmdr_next_value_ce3) begin + cmdr_cmdr_reset <= cmdr_cmdr_reset_sdphycmdr_next_value3; + end + if (dataw_crc_pads_in_valid) begin + dataw_crc_run <= (dataw_crc_start | dataw_crc_run); + end + if (dataw_crc_converter_converter_source_ready) begin + dataw_crc_converter_converter_strobe_all <= 1'd0; + end + if (dataw_crc_converter_converter_load_part) begin + if (((dataw_crc_converter_converter_demux == 3'd7) | dataw_crc_converter_converter_sink_last)) begin + dataw_crc_converter_converter_demux <= 1'd0; + dataw_crc_converter_converter_strobe_all <= 1'd1; + end else begin + dataw_crc_converter_converter_demux <= (dataw_crc_converter_converter_demux + 1'd1); + end + end + if ((dataw_crc_converter_converter_source_valid & dataw_crc_converter_converter_source_ready)) begin + if ((dataw_crc_converter_converter_sink_valid & dataw_crc_converter_converter_sink_ready)) begin + dataw_crc_converter_converter_source_first <= dataw_crc_converter_converter_sink_first; + dataw_crc_converter_converter_source_last <= dataw_crc_converter_converter_sink_last; + end else begin + dataw_crc_converter_converter_source_first <= 1'd0; + dataw_crc_converter_converter_source_last <= 1'd0; + end + end else begin + if ((dataw_crc_converter_converter_sink_valid & dataw_crc_converter_converter_sink_ready)) begin + dataw_crc_converter_converter_source_first <= (dataw_crc_converter_converter_sink_first | dataw_crc_converter_converter_source_first); + dataw_crc_converter_converter_source_last <= (dataw_crc_converter_converter_sink_last | dataw_crc_converter_converter_source_last); + end + end + if (dataw_crc_converter_converter_load_part) begin + case (dataw_crc_converter_converter_demux) + 1'd0: begin + dataw_crc_converter_converter_source_payload_data[7] <= dataw_crc_converter_converter_sink_payload_data; + end + 1'd1: begin + dataw_crc_converter_converter_source_payload_data[6] <= dataw_crc_converter_converter_sink_payload_data; + end + 2'd2: begin + dataw_crc_converter_converter_source_payload_data[5] <= dataw_crc_converter_converter_sink_payload_data; + end + 2'd3: begin + dataw_crc_converter_converter_source_payload_data[4] <= dataw_crc_converter_converter_sink_payload_data; + end + 3'd4: begin + dataw_crc_converter_converter_source_payload_data[3] <= dataw_crc_converter_converter_sink_payload_data; + end + 3'd5: begin + dataw_crc_converter_converter_source_payload_data[2] <= dataw_crc_converter_converter_sink_payload_data; + end + 3'd6: begin + dataw_crc_converter_converter_source_payload_data[1] <= dataw_crc_converter_converter_sink_payload_data; + end + 3'd7: begin + dataw_crc_converter_converter_source_payload_data[0] <= dataw_crc_converter_converter_sink_payload_data; + end + endcase + end + if (dataw_crc_converter_converter_load_part) begin + dataw_crc_converter_converter_source_payload_valid_token_count <= (dataw_crc_converter_converter_demux + 1'd1); + end + if (((~dataw_crc_buf_pipe_valid_source_valid) | dataw_crc_buf_pipe_valid_source_ready)) begin + dataw_crc_buf_pipe_valid_source_valid <= dataw_crc_buf_pipe_valid_sink_valid; + dataw_crc_buf_pipe_valid_source_first <= dataw_crc_buf_pipe_valid_sink_first; + dataw_crc_buf_pipe_valid_source_last <= dataw_crc_buf_pipe_valid_sink_last; + dataw_crc_buf_pipe_valid_source_payload_data <= dataw_crc_buf_pipe_valid_sink_payload_data; + end + if (dataw_crc_reset) begin + dataw_crc_run <= 1'd0; + dataw_crc_converter_converter_source_payload_data <= 8'd0; + dataw_crc_converter_converter_source_payload_valid_token_count <= 4'd0; + dataw_crc_converter_converter_demux <= 3'd0; + dataw_crc_converter_converter_strobe_all <= 1'd0; + dataw_crc_buf_pipe_valid_source_valid <= 1'd0; + dataw_crc_buf_pipe_valid_source_payload_data <= 8'd0; + end + sdphydataw_state <= sdphydataw_next_state; + if (dataw_accepted1_sdphydataw_next_value_ce0) begin + dataw_accepted1 <= dataw_accepted1_sdphydataw_next_value0; + end + if (dataw_crc_error1_sdphydataw_next_value_ce1) begin + dataw_crc_error1 <= dataw_crc_error1_sdphydataw_next_value1; + end + if (dataw_write_error1_sdphydataw_next_value_ce2) begin + dataw_write_error1 <= dataw_write_error1_sdphydataw_next_value2; + end + if (dataw_count_sdphydataw_next_value_ce3) begin + dataw_count <= dataw_count_sdphydataw_next_value3; + end + if (datar_datar_pads_in_valid) begin + datar_datar_run <= (datar_datar_start | datar_datar_run); + end + if (datar_datar_converter_converter_source_ready) begin + datar_datar_converter_converter_strobe_all <= 1'd0; + end + if (datar_datar_converter_converter_load_part) begin + if (((datar_datar_converter_converter_demux == 1'd1) | datar_datar_converter_converter_sink_last)) begin + datar_datar_converter_converter_demux <= 1'd0; + datar_datar_converter_converter_strobe_all <= 1'd1; + end else begin + datar_datar_converter_converter_demux <= (datar_datar_converter_converter_demux + 1'd1); + end + end + if ((datar_datar_converter_converter_source_valid & datar_datar_converter_converter_source_ready)) begin + if ((datar_datar_converter_converter_sink_valid & datar_datar_converter_converter_sink_ready)) begin + datar_datar_converter_converter_source_first <= datar_datar_converter_converter_sink_first; + datar_datar_converter_converter_source_last <= datar_datar_converter_converter_sink_last; + end else begin + datar_datar_converter_converter_source_first <= 1'd0; + datar_datar_converter_converter_source_last <= 1'd0; + end + end else begin + if ((datar_datar_converter_converter_sink_valid & datar_datar_converter_converter_sink_ready)) begin + datar_datar_converter_converter_source_first <= (datar_datar_converter_converter_sink_first | datar_datar_converter_converter_source_first); + datar_datar_converter_converter_source_last <= (datar_datar_converter_converter_sink_last | datar_datar_converter_converter_source_last); + end + end + if (datar_datar_converter_converter_load_part) begin + case (datar_datar_converter_converter_demux) + 1'd0: begin + datar_datar_converter_converter_source_payload_data[7:4] <= datar_datar_converter_converter_sink_payload_data; + end + 1'd1: begin + datar_datar_converter_converter_source_payload_data[3:0] <= datar_datar_converter_converter_sink_payload_data; + end + endcase + end + if (datar_datar_converter_converter_load_part) begin + datar_datar_converter_converter_source_payload_valid_token_count <= (datar_datar_converter_converter_demux + 1'd1); + end + if (((~datar_datar_buf_pipe_valid_source_valid) | datar_datar_buf_pipe_valid_source_ready)) begin + datar_datar_buf_pipe_valid_source_valid <= datar_datar_buf_pipe_valid_sink_valid; + datar_datar_buf_pipe_valid_source_first <= datar_datar_buf_pipe_valid_sink_first; + datar_datar_buf_pipe_valid_source_last <= datar_datar_buf_pipe_valid_sink_last; + datar_datar_buf_pipe_valid_source_payload_data <= datar_datar_buf_pipe_valid_sink_payload_data; + end + if (datar_datar_reset) begin + datar_datar_run <= 1'd0; + datar_datar_converter_converter_source_payload_data <= 8'd0; + datar_datar_converter_converter_source_payload_valid_token_count <= 2'd0; + datar_datar_converter_converter_demux <= 1'd0; + datar_datar_converter_converter_strobe_all <= 1'd0; + datar_datar_buf_pipe_valid_source_valid <= 1'd0; + datar_datar_buf_pipe_valid_source_payload_data <= 8'd0; + end + sdphydatar_state <= sdphydatar_next_state; + if (datar_count_sdphydatar_next_value_ce0) begin + datar_count <= datar_count_sdphydatar_next_value0; + end + if (datar_timeout_sdphydatar_next_value_ce1) begin + datar_timeout <= datar_timeout_sdphydatar_next_value1; + end + if (datar_datar_reset_sdphydatar_next_value_ce2) begin + datar_datar_reset <= datar_datar_reset_sdphydatar_next_value2; + end + clocker_clk_delay <= {clocker_clk_delay, clocker_clk0}; + sdpads_data_i_ce <= (clocker_clk_delay[1] & (~clocker_clk_delay[0])); + sdcard_core_done_d <= sdcard_core_cmd_done; + sdcard_core_irq <= (sdcard_core_cmd_done & (~sdcard_core_done_d)); + if (sdcard_core_crc7_inserter_crc_reset) begin + sdcard_core_crc7_inserter_crc0 <= 1'd0; + end else begin + if (sdcard_core_crc7_inserter_crc_enable) begin + sdcard_core_crc7_inserter_crc0 <= sdcard_core_crc7_inserter_crc40; + end + end + if (sdcard_core_crc16_inserter_crc0_reset) begin + sdcard_core_crc16_inserter_crc00 <= 1'd0; + end else begin + if (sdcard_core_crc16_inserter_crc0_enable) begin + sdcard_core_crc16_inserter_crc00 <= sdcard_core_crc16_inserter_crc02; + end + end + if (sdcard_core_crc16_inserter_crc1_reset) begin + sdcard_core_crc16_inserter_crc10 <= 1'd0; + end else begin + if (sdcard_core_crc16_inserter_crc1_enable) begin + sdcard_core_crc16_inserter_crc10 <= sdcard_core_crc16_inserter_crc12; + end + end + if (sdcard_core_crc16_inserter_crc2_reset) begin + sdcard_core_crc16_inserter_crc20 <= 1'd0; + end else begin + if (sdcard_core_crc16_inserter_crc2_enable) begin + sdcard_core_crc16_inserter_crc20 <= sdcard_core_crc16_inserter_crc22; + end + end + if (sdcard_core_crc16_inserter_crc3_reset) begin + sdcard_core_crc16_inserter_crc30 <= 1'd0; + end else begin + if (sdcard_core_crc16_inserter_crc3_enable) begin + sdcard_core_crc16_inserter_crc30 <= sdcard_core_crc16_inserter_crc32; + end + end + crc16inserter_state <= crc16inserter_next_state; + if (sdcard_core_crc16_inserter_count_crc16inserter_next_value_ce) begin + sdcard_core_crc16_inserter_count <= sdcard_core_crc16_inserter_count_crc16inserter_next_value; + end + if (((sdcard_core_fifo_syncfifo_we & sdcard_core_fifo_syncfifo_writable) & (~sdcard_core_fifo_replace))) begin + sdcard_core_fifo_produce <= (sdcard_core_fifo_produce + 1'd1); + end + if (sdcard_core_fifo_do_read) begin + sdcard_core_fifo_consume <= (sdcard_core_fifo_consume + 1'd1); + end + if (((sdcard_core_fifo_syncfifo_we & sdcard_core_fifo_syncfifo_writable) & (~sdcard_core_fifo_replace))) begin + if ((~sdcard_core_fifo_do_read)) begin + sdcard_core_fifo_level <= (sdcard_core_fifo_level + 1'd1); + end + end else begin + if (sdcard_core_fifo_do_read) begin + sdcard_core_fifo_level <= (sdcard_core_fifo_level - 1'd1); + end + end + if (sdcard_core_fifo_reset) begin + sdcard_core_fifo_level <= 4'd0; + sdcard_core_fifo_produce <= 3'd0; + sdcard_core_fifo_consume <= 3'd0; + end + fsm_state <= fsm_next_state; + if (sdcard_core_cmd_done_fsm_next_value_ce0) begin + sdcard_core_cmd_done <= sdcard_core_cmd_done_fsm_next_value0; + end + if (sdcard_core_data_done_fsm_next_value_ce1) begin + sdcard_core_data_done <= sdcard_core_data_done_fsm_next_value1; + end + if (sdcard_core_cmd_count_fsm_next_value_ce2) begin + sdcard_core_cmd_count <= sdcard_core_cmd_count_fsm_next_value2; + end + if (sdcard_core_data_count_fsm_next_value_ce3) begin + sdcard_core_data_count <= sdcard_core_data_count_fsm_next_value3; + end + if (sdcard_core_cmd_error_fsm_next_value_ce4) begin + sdcard_core_cmd_error <= sdcard_core_cmd_error_fsm_next_value4; + end + if (sdcard_core_cmd_timeout_fsm_next_value_ce5) begin + sdcard_core_cmd_timeout <= sdcard_core_cmd_timeout_fsm_next_value5; + end + if (sdcard_core_data_error_fsm_next_value_ce6) begin + sdcard_core_data_error <= sdcard_core_data_error_fsm_next_value6; + end + if (sdcard_core_data_timeout_fsm_next_value_ce7) begin + sdcard_core_data_timeout <= sdcard_core_data_timeout_fsm_next_value7; + end + if (sdcard_core_cmd_response_status_fsm_next_value_ce8) begin + sdcard_core_cmd_response_status <= sdcard_core_cmd_response_status_fsm_next_value8; + end + if ((~sdcard_block2mem_wishbonedmawriter_enable_storage)) begin + sdcard_block2mem_connect <= 1'd0; + end else begin + if (sdcard_block2mem_start) begin + sdcard_block2mem_connect <= 1'd1; + end + end + sdcard_block2mem_done_d <= sdcard_block2mem_wishbonedmawriter_done_status; + sdcard_block2mem_irq <= (sdcard_block2mem_wishbonedmawriter_done_status & (~sdcard_block2mem_done_d)); + if (sdcard_block2mem_fifo_syncfifo_re) begin + sdcard_block2mem_fifo_readable <= 1'd1; + end else begin + if (sdcard_block2mem_fifo_re) begin + sdcard_block2mem_fifo_readable <= 1'd0; + end + end + if (((sdcard_block2mem_fifo_syncfifo_we & sdcard_block2mem_fifo_syncfifo_writable) & (~sdcard_block2mem_fifo_replace))) begin + sdcard_block2mem_fifo_produce <= (sdcard_block2mem_fifo_produce + 1'd1); + end + if (sdcard_block2mem_fifo_do_read) begin + sdcard_block2mem_fifo_consume <= (sdcard_block2mem_fifo_consume + 1'd1); + end + if (((sdcard_block2mem_fifo_syncfifo_we & sdcard_block2mem_fifo_syncfifo_writable) & (~sdcard_block2mem_fifo_replace))) begin + if ((~sdcard_block2mem_fifo_do_read)) begin + sdcard_block2mem_fifo_level0 <= (sdcard_block2mem_fifo_level0 + 1'd1); + end + end else begin + if (sdcard_block2mem_fifo_do_read) begin + sdcard_block2mem_fifo_level0 <= (sdcard_block2mem_fifo_level0 - 1'd1); + end + end + if (sdcard_block2mem_converter_source_ready) begin + sdcard_block2mem_converter_strobe_all <= 1'd0; + end + if (sdcard_block2mem_converter_load_part) begin + if (((sdcard_block2mem_converter_demux == 2'd3) | sdcard_block2mem_converter_sink_last)) begin + sdcard_block2mem_converter_demux <= 1'd0; + sdcard_block2mem_converter_strobe_all <= 1'd1; + end else begin + sdcard_block2mem_converter_demux <= (sdcard_block2mem_converter_demux + 1'd1); + end + end + if ((sdcard_block2mem_converter_source_valid & sdcard_block2mem_converter_source_ready)) begin + if ((sdcard_block2mem_converter_sink_valid & sdcard_block2mem_converter_sink_ready)) begin + sdcard_block2mem_converter_source_first <= sdcard_block2mem_converter_sink_first; + sdcard_block2mem_converter_source_last <= sdcard_block2mem_converter_sink_last; + end else begin + sdcard_block2mem_converter_source_first <= 1'd0; + sdcard_block2mem_converter_source_last <= 1'd0; + end + end else begin + if ((sdcard_block2mem_converter_sink_valid & sdcard_block2mem_converter_sink_ready)) begin + sdcard_block2mem_converter_source_first <= (sdcard_block2mem_converter_sink_first | sdcard_block2mem_converter_source_first); + sdcard_block2mem_converter_source_last <= (sdcard_block2mem_converter_sink_last | sdcard_block2mem_converter_source_last); + end + end + if (sdcard_block2mem_converter_load_part) begin + case (sdcard_block2mem_converter_demux) + 1'd0: begin + sdcard_block2mem_converter_source_payload_data[31:24] <= sdcard_block2mem_converter_sink_payload_data; + end + 1'd1: begin + sdcard_block2mem_converter_source_payload_data[23:16] <= sdcard_block2mem_converter_sink_payload_data; + end + 2'd2: begin + sdcard_block2mem_converter_source_payload_data[15:8] <= sdcard_block2mem_converter_sink_payload_data; + end + 2'd3: begin + sdcard_block2mem_converter_source_payload_data[7:0] <= sdcard_block2mem_converter_sink_payload_data; + end + endcase + end + if (sdcard_block2mem_converter_load_part) begin + sdcard_block2mem_converter_source_payload_valid_token_count <= (sdcard_block2mem_converter_demux + 1'd1); + end + sdblock2memdma_state <= sdblock2memdma_next_state; + if (sdcard_block2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce) begin + sdcard_block2mem_wishbonedmawriter_offset <= sdcard_block2mem_wishbonedmawriter_offset_sdblock2memdma_next_value; + end + if (sdcard_block2mem_wishbonedmawriter_reset) begin + sdcard_block2mem_wishbonedmawriter_offset <= 32'd0; + sdblock2memdma_state <= 2'd0; + end + if ((sdcard_mem2block_source_source_valid & sdcard_mem2block_source_source_ready)) begin + sdcard_mem2block_count <= (sdcard_mem2block_count + 1'd1); + if (sdcard_mem2block_source_source_last) begin + sdcard_mem2block_count <= 1'd0; + end + end + sdcard_mem2block_done_d <= sdcard_mem2block_dma_done_status; + sdcard_mem2block_irq <= (sdcard_mem2block_dma_done_status & (~sdcard_mem2block_done_d)); + if (((sdcard_mem2block_dma_fifo_syncfifo_we & sdcard_mem2block_dma_fifo_syncfifo_writable) & (~sdcard_mem2block_dma_fifo_replace))) begin + sdcard_mem2block_dma_fifo_produce <= (sdcard_mem2block_dma_fifo_produce + 1'd1); + end + if (sdcard_mem2block_dma_fifo_do_read) begin + sdcard_mem2block_dma_fifo_consume <= (sdcard_mem2block_dma_fifo_consume + 1'd1); + end + if (((sdcard_mem2block_dma_fifo_syncfifo_we & sdcard_mem2block_dma_fifo_syncfifo_writable) & (~sdcard_mem2block_dma_fifo_replace))) begin + if ((~sdcard_mem2block_dma_fifo_do_read)) begin + sdcard_mem2block_dma_fifo_level <= (sdcard_mem2block_dma_fifo_level + 1'd1); + end + end else begin + if (sdcard_mem2block_dma_fifo_do_read) begin + sdcard_mem2block_dma_fifo_level <= (sdcard_mem2block_dma_fifo_level - 1'd1); + end + end + sdmem2blockdma_state <= sdmem2blockdma_next_state; + if (sdcard_mem2block_dma_offset_sdmem2blockdma_next_value_ce) begin + sdcard_mem2block_dma_offset <= sdcard_mem2block_dma_offset_sdmem2blockdma_next_value; + end + if (sdcard_mem2block_dma_reset) begin + sdcard_mem2block_dma_offset <= 32'd0; + sdmem2blockdma_state <= 2'd0; + end + if ((sdcard_mem2block_converter_converter_source_valid & sdcard_mem2block_converter_converter_source_ready)) begin + if (sdcard_mem2block_converter_converter_last) begin + sdcard_mem2block_converter_converter_mux <= 1'd0; + end else begin + sdcard_mem2block_converter_converter_mux <= (sdcard_mem2block_converter_converter_mux + 1'd1); + end + end + if (sdcard_mem2block_fifo_syncfifo_re) begin + sdcard_mem2block_fifo_readable <= 1'd1; + end else begin + if (sdcard_mem2block_fifo_re) begin + sdcard_mem2block_fifo_readable <= 1'd0; + end + end + if (((sdcard_mem2block_fifo_syncfifo_we & sdcard_mem2block_fifo_syncfifo_writable) & (~sdcard_mem2block_fifo_replace))) begin + sdcard_mem2block_fifo_produce <= (sdcard_mem2block_fifo_produce + 1'd1); + end + if (sdcard_mem2block_fifo_do_read) begin + sdcard_mem2block_fifo_consume <= (sdcard_mem2block_fifo_consume + 1'd1); + end + if (((sdcard_mem2block_fifo_syncfifo_we & sdcard_mem2block_fifo_syncfifo_writable) & (~sdcard_mem2block_fifo_replace))) begin + if ((~sdcard_mem2block_fifo_do_read)) begin + sdcard_mem2block_fifo_level0 <= (sdcard_mem2block_fifo_level0 + 1'd1); + end + end else begin + if (sdcard_mem2block_fifo_do_read) begin + sdcard_mem2block_fifo_level0 <= (sdcard_mem2block_fifo_level0 - 1'd1); + end + end + if (card_detect_clear) begin + card_detect_pending <= 1'd0; + end + if (card_detect_trigger) begin + card_detect_pending <= 1'd1; + end + if (block2mem_dma_clear) begin + block2mem_dma_pending <= 1'd0; + end + if (block2mem_dma_trigger) begin + block2mem_dma_pending <= 1'd1; + end + if (mem2block_dma_clear) begin + mem2block_dma_pending <= 1'd0; + end + if (mem2block_dma_trigger) begin + mem2block_dma_pending <= 1'd1; + end + wishbone2csr_state <= wishbone2csr_next_state; + interface0_bank_bus_dat_r <= 1'd0; + if (csrbank0_sel) begin + case (interface0_bank_bus_adr[8:0]) + 1'd0: begin + interface0_bank_bus_dat_r <= csrbank0_reset0_w; + end + 1'd1: begin + interface0_bank_bus_dat_r <= csrbank0_scratch0_w; + end + 2'd2: begin + interface0_bank_bus_dat_r <= csrbank0_bus_errors_w; + end + endcase + end + if (csrbank0_reset0_re) begin + reset_storage[1:0] <= csrbank0_reset0_r; + end + reset_re <= csrbank0_reset0_re; + if (csrbank0_scratch0_re) begin + scratch_storage[31:0] <= csrbank0_scratch0_r; + end + scratch_re <= csrbank0_scratch0_re; + bus_errors_re <= csrbank0_bus_errors_re; + interface1_bank_bus_dat_r <= 1'd0; + if (csrbank1_sel) begin + case (interface1_bank_bus_adr[8:0]) + 1'd0: begin + interface1_bank_bus_dat_r <= csrbank1_dma_base1_w; + end + 1'd1: begin + interface1_bank_bus_dat_r <= csrbank1_dma_base0_w; + end + 2'd2: begin + interface1_bank_bus_dat_r <= csrbank1_dma_length0_w; + end + 2'd3: begin + interface1_bank_bus_dat_r <= csrbank1_dma_enable0_w; + end + 3'd4: begin + interface1_bank_bus_dat_r <= csrbank1_dma_done_w; + end + 3'd5: begin + interface1_bank_bus_dat_r <= csrbank1_dma_loop0_w; + end + 3'd6: begin + interface1_bank_bus_dat_r <= csrbank1_dma_offset_w; + end + endcase + end + if (csrbank1_dma_base1_re) begin + sdcard_block2mem_wishbonedmawriter_base_storage[63:32] <= csrbank1_dma_base1_r; + end + if (csrbank1_dma_base0_re) begin + sdcard_block2mem_wishbonedmawriter_base_storage[31:0] <= csrbank1_dma_base0_r; + end + sdcard_block2mem_wishbonedmawriter_base_re <= csrbank1_dma_base0_re; + if (csrbank1_dma_length0_re) begin + sdcard_block2mem_wishbonedmawriter_length_storage[31:0] <= csrbank1_dma_length0_r; + end + sdcard_block2mem_wishbonedmawriter_length_re <= csrbank1_dma_length0_re; + if (csrbank1_dma_enable0_re) begin + sdcard_block2mem_wishbonedmawriter_enable_storage <= csrbank1_dma_enable0_r; + end + sdcard_block2mem_wishbonedmawriter_enable_re <= csrbank1_dma_enable0_re; + sdcard_block2mem_wishbonedmawriter_done_re <= csrbank1_dma_done_re; + if (csrbank1_dma_loop0_re) begin + sdcard_block2mem_wishbonedmawriter_loop_storage <= csrbank1_dma_loop0_r; + end + sdcard_block2mem_wishbonedmawriter_loop_re <= csrbank1_dma_loop0_re; + sdcard_block2mem_wishbonedmawriter_offset_re <= csrbank1_dma_offset_re; + interface2_bank_bus_dat_r <= 1'd0; + if (csrbank2_sel) begin + case (interface2_bank_bus_adr[8:0]) + 1'd0: begin + interface2_bank_bus_dat_r <= csrbank2_cmd_argument0_w; + end + 1'd1: begin + interface2_bank_bus_dat_r <= csrbank2_cmd_command0_w; + end + 2'd2: begin + interface2_bank_bus_dat_r <= csrbank2_cmd_send0_w; + end + 2'd3: begin + interface2_bank_bus_dat_r <= csrbank2_cmd_response3_w; + end + 3'd4: begin + interface2_bank_bus_dat_r <= csrbank2_cmd_response2_w; + end + 3'd5: begin + interface2_bank_bus_dat_r <= csrbank2_cmd_response1_w; + end + 3'd6: begin + interface2_bank_bus_dat_r <= csrbank2_cmd_response0_w; + end + 3'd7: begin + interface2_bank_bus_dat_r <= csrbank2_cmd_event_w; + end + 4'd8: begin + interface2_bank_bus_dat_r <= csrbank2_data_event_w; + end + 4'd9: begin + interface2_bank_bus_dat_r <= csrbank2_block_length0_w; + end + 4'd10: begin + interface2_bank_bus_dat_r <= csrbank2_block_count0_w; + end + endcase + end + if (csrbank2_cmd_argument0_re) begin + sdcard_core_cmd_argument_storage[31:0] <= csrbank2_cmd_argument0_r; + end + sdcard_core_cmd_argument_re <= csrbank2_cmd_argument0_re; + if (csrbank2_cmd_command0_re) begin + sdcard_core_cmd_command_storage[13:0] <= csrbank2_cmd_command0_r; + end + sdcard_core_cmd_command_re <= csrbank2_cmd_command0_re; + if (csrbank2_cmd_send0_re) begin + sdcard_core_cmd_send_storage <= csrbank2_cmd_send0_r; + end + sdcard_core_cmd_send_re <= csrbank2_cmd_send0_re; + sdcard_core_cmd_response_re <= csrbank2_cmd_response0_re; + sdcard_core_cmd_event_re <= csrbank2_cmd_event_re; + sdcard_core_data_event_re <= csrbank2_data_event_re; + if (csrbank2_block_length0_re) begin + sdcard_core_block_length_storage[9:0] <= csrbank2_block_length0_r; + end + sdcard_core_block_length_re <= csrbank2_block_length0_re; + if (csrbank2_block_count0_re) begin + sdcard_core_block_count_storage[31:0] <= csrbank2_block_count0_r; + end + sdcard_core_block_count_re <= csrbank2_block_count0_re; + interface3_bank_bus_dat_r <= 1'd0; + if (csrbank3_sel) begin + case (interface3_bank_bus_adr[8:0]) + 1'd0: begin + interface3_bank_bus_dat_r <= csrbank3_status_w; + end + 1'd1: begin + interface3_bank_bus_dat_r <= csrbank3_pending_w; + end + 2'd2: begin + interface3_bank_bus_dat_r <= csrbank3_enable0_w; + end + endcase + end + eventmanager_status_re <= csrbank3_status_re; + if (csrbank3_pending_re) begin + eventmanager_pending_r[3:0] <= csrbank3_pending_r; + end + eventmanager_pending_re <= csrbank3_pending_re; + if (csrbank3_enable0_re) begin + eventmanager_enable_storage[3:0] <= csrbank3_enable0_r; + end + eventmanager_enable_re <= csrbank3_enable0_re; + interface4_bank_bus_dat_r <= 1'd0; + if (csrbank4_sel) begin + case (interface4_bank_bus_adr[8:0]) + 1'd0: begin + interface4_bank_bus_dat_r <= csrbank4_dma_base1_w; + end + 1'd1: begin + interface4_bank_bus_dat_r <= csrbank4_dma_base0_w; + end + 2'd2: begin + interface4_bank_bus_dat_r <= csrbank4_dma_length0_w; + end + 2'd3: begin + interface4_bank_bus_dat_r <= csrbank4_dma_enable0_w; + end + 3'd4: begin + interface4_bank_bus_dat_r <= csrbank4_dma_done_w; + end + 3'd5: begin + interface4_bank_bus_dat_r <= csrbank4_dma_loop0_w; + end + 3'd6: begin + interface4_bank_bus_dat_r <= csrbank4_dma_offset_w; + end + endcase + end + if (csrbank4_dma_base1_re) begin + sdcard_mem2block_dma_base_storage[63:32] <= csrbank4_dma_base1_r; + end + if (csrbank4_dma_base0_re) begin + sdcard_mem2block_dma_base_storage[31:0] <= csrbank4_dma_base0_r; + end + sdcard_mem2block_dma_base_re <= csrbank4_dma_base0_re; + if (csrbank4_dma_length0_re) begin + sdcard_mem2block_dma_length_storage[31:0] <= csrbank4_dma_length0_r; + end + sdcard_mem2block_dma_length_re <= csrbank4_dma_length0_re; + if (csrbank4_dma_enable0_re) begin + sdcard_mem2block_dma_enable_storage <= csrbank4_dma_enable0_r; + end + sdcard_mem2block_dma_enable_re <= csrbank4_dma_enable0_re; + sdcard_mem2block_dma_done_re <= csrbank4_dma_done_re; + if (csrbank4_dma_loop0_re) begin + sdcard_mem2block_dma_loop_storage <= csrbank4_dma_loop0_r; + end + sdcard_mem2block_dma_loop_re <= csrbank4_dma_loop0_re; + sdcard_mem2block_dma_offset_re <= csrbank4_dma_offset_re; + interface5_bank_bus_dat_r <= 1'd0; + if (csrbank5_sel) begin + case (interface5_bank_bus_adr[8:0]) + 1'd0: begin + interface5_bank_bus_dat_r <= csrbank5_card_detect_w; + end + 1'd1: begin + interface5_bank_bus_dat_r <= csrbank5_clocker_divider0_w; + end + 2'd2: begin + interface5_bank_bus_dat_r <= init_initialize_w; + end + 2'd3: begin + interface5_bank_bus_dat_r <= csrbank5_dataw_status_w; + end + endcase + end + card_detect_re <= csrbank5_card_detect_re; + if (csrbank5_clocker_divider0_re) begin + clocker_storage[8:0] <= csrbank5_clocker_divider0_r; + end + clocker_re <= csrbank5_clocker_divider0_re; + dataw_re <= csrbank5_dataw_status_re; + if (sys_rst) begin + reset_storage <= 2'd0; + reset_re <= 1'd0; + scratch_storage <= 32'd305419896; + scratch_re <= 1'd0; + bus_errors_re <= 1'd0; + bus_errors <= 32'd0; + card_detect_re <= 1'd0; + clocker_storage <= 9'd256; + clocker_re <= 1'd0; + clocker_clks <= 9'd0; + clocker_clk_d <= 1'd0; + clocker_ce_delayed <= 1'd0; + init_count <= 8'd0; + cmdw_count <= 8'd0; + cmdr_timeout <= 32'd50000000; + cmdr_count <= 8'd0; + cmdr_busy <= 1'd0; + cmdr_cmdr_run <= 1'd0; + cmdr_cmdr_converter_converter_source_payload_data <= 8'd0; + cmdr_cmdr_converter_converter_source_payload_valid_token_count <= 4'd0; + cmdr_cmdr_converter_converter_demux <= 3'd0; + cmdr_cmdr_converter_converter_strobe_all <= 1'd0; + cmdr_cmdr_buf_pipe_valid_source_valid <= 1'd0; + cmdr_cmdr_buf_pipe_valid_source_payload_data <= 8'd0; + cmdr_cmdr_reset <= 1'd0; + dataw_re <= 1'd0; + dataw_count <= 8'd0; + dataw_accepted1 <= 1'd0; + dataw_crc_error1 <= 1'd0; + dataw_write_error1 <= 1'd0; + dataw_crc_run <= 1'd0; + dataw_crc_converter_converter_source_payload_data <= 8'd0; + dataw_crc_converter_converter_source_payload_valid_token_count <= 4'd0; + dataw_crc_converter_converter_demux <= 3'd0; + dataw_crc_converter_converter_strobe_all <= 1'd0; + dataw_crc_buf_pipe_valid_source_valid <= 1'd0; + dataw_crc_buf_pipe_valid_source_payload_data <= 8'd0; + datar_timeout <= 32'd50000000; + datar_count <= 10'd0; + datar_datar_run <= 1'd0; + datar_datar_converter_converter_source_payload_data <= 8'd0; + datar_datar_converter_converter_source_payload_valid_token_count <= 2'd0; + datar_datar_converter_converter_demux <= 1'd0; + datar_datar_converter_converter_strobe_all <= 1'd0; + datar_datar_buf_pipe_valid_source_valid <= 1'd0; + datar_datar_buf_pipe_valid_source_payload_data <= 8'd0; + datar_datar_reset <= 1'd0; + sdpads_data_i_ce <= 1'd0; + clocker_clk_delay <= 2'd0; + card_detect_irq <= 1'd0; + card_detect_d <= 1'd0; + sdcard_core_irq <= 1'd0; + sdcard_core_cmd_argument_storage <= 32'd0; + sdcard_core_cmd_argument_re <= 1'd0; + sdcard_core_cmd_command_storage <= 14'd0; + sdcard_core_cmd_command_re <= 1'd0; + sdcard_core_cmd_send_storage <= 1'd0; + sdcard_core_cmd_send_re <= 1'd0; + sdcard_core_cmd_response_status <= 128'd0; + sdcard_core_cmd_response_re <= 1'd0; + sdcard_core_cmd_event_re <= 1'd0; + sdcard_core_data_event_re <= 1'd0; + sdcard_core_block_length_storage <= 10'd0; + sdcard_core_block_length_re <= 1'd0; + sdcard_core_block_count_storage <= 32'd0; + sdcard_core_block_count_re <= 1'd0; + sdcard_core_crc7_inserter_crc0 <= 7'd0; + sdcard_core_crc16_inserter_count <= 3'd0; + sdcard_core_crc16_inserter_crc00 <= 16'd0; + sdcard_core_crc16_inserter_crc10 <= 16'd0; + sdcard_core_crc16_inserter_crc20 <= 16'd0; + sdcard_core_crc16_inserter_crc30 <= 16'd0; + sdcard_core_fifo_level <= 4'd0; + sdcard_core_fifo_produce <= 3'd0; + sdcard_core_fifo_consume <= 3'd0; + sdcard_core_cmd_count <= 3'd0; + sdcard_core_cmd_done <= 1'd0; + sdcard_core_cmd_error <= 1'd0; + sdcard_core_cmd_timeout <= 1'd0; + sdcard_core_data_count <= 32'd0; + sdcard_core_data_done <= 1'd0; + sdcard_core_data_error <= 1'd0; + sdcard_core_data_timeout <= 1'd0; + sdcard_core_done_d <= 1'd0; + sdcard_block2mem_irq <= 1'd0; + sdcard_block2mem_fifo_readable <= 1'd0; + sdcard_block2mem_fifo_level0 <= 10'd0; + sdcard_block2mem_fifo_produce <= 9'd0; + sdcard_block2mem_fifo_consume <= 9'd0; + sdcard_block2mem_converter_source_payload_data <= 32'd0; + sdcard_block2mem_converter_source_payload_valid_token_count <= 3'd0; + sdcard_block2mem_converter_demux <= 2'd0; + sdcard_block2mem_converter_strobe_all <= 1'd0; + sdcard_block2mem_wishbonedmawriter_base_storage <= 64'd0; + sdcard_block2mem_wishbonedmawriter_base_re <= 1'd0; + sdcard_block2mem_wishbonedmawriter_length_storage <= 32'd0; + sdcard_block2mem_wishbonedmawriter_length_re <= 1'd0; + sdcard_block2mem_wishbonedmawriter_enable_storage <= 1'd0; + sdcard_block2mem_wishbonedmawriter_enable_re <= 1'd0; + sdcard_block2mem_wishbonedmawriter_done_re <= 1'd0; + sdcard_block2mem_wishbonedmawriter_loop_storage <= 1'd0; + sdcard_block2mem_wishbonedmawriter_loop_re <= 1'd0; + sdcard_block2mem_wishbonedmawriter_offset_re <= 1'd0; + sdcard_block2mem_wishbonedmawriter_offset <= 32'd0; + sdcard_block2mem_connect <= 1'd0; + sdcard_block2mem_done_d <= 1'd0; + sdcard_mem2block_irq <= 1'd0; + sdcard_mem2block_dma_fifo_level <= 5'd0; + sdcard_mem2block_dma_fifo_produce <= 4'd0; + sdcard_mem2block_dma_fifo_consume <= 4'd0; + sdcard_mem2block_dma_base_storage <= 64'd0; + sdcard_mem2block_dma_base_re <= 1'd0; + sdcard_mem2block_dma_length_storage <= 32'd0; + sdcard_mem2block_dma_length_re <= 1'd0; + sdcard_mem2block_dma_enable_storage <= 1'd0; + sdcard_mem2block_dma_enable_re <= 1'd0; + sdcard_mem2block_dma_done_re <= 1'd0; + sdcard_mem2block_dma_loop_storage <= 1'd0; + sdcard_mem2block_dma_loop_re <= 1'd0; + sdcard_mem2block_dma_offset_re <= 1'd0; + sdcard_mem2block_dma_offset <= 32'd0; + sdcard_mem2block_converter_converter_mux <= 2'd0; + sdcard_mem2block_fifo_readable <= 1'd0; + sdcard_mem2block_fifo_level0 <= 10'd0; + sdcard_mem2block_fifo_produce <= 9'd0; + sdcard_mem2block_fifo_consume <= 9'd0; + sdcard_mem2block_count <= 9'd0; + sdcard_mem2block_done_d <= 1'd0; + card_detect_pending <= 1'd0; + block2mem_dma_pending <= 1'd0; + mem2block_dma_pending <= 1'd0; + eventmanager_status_re <= 1'd0; + eventmanager_pending_re <= 1'd0; + eventmanager_pending_r <= 4'd0; + eventmanager_enable_storage <= 4'd0; + eventmanager_enable_re <= 1'd0; + grant <= 1'd0; + slave_sel_r <= 1'd0; + count <= 20'd1000000; + sdphyinit_state <= 1'd0; + sdphycmdw_state <= 2'd0; + sdphycmdr_state <= 3'd0; + sdphydataw_state <= 3'd0; + sdphydatar_state <= 3'd0; + crc16inserter_state <= 1'd0; + fsm_state <= 3'd0; + sdblock2memdma_state <= 2'd0; + sdmem2blockdma_state <= 2'd0; + wishbone2csr_state <= 1'd0; + end +end + + +//------------------------------------------------------------------------------ +// Specialized Logic +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +// Memory storage: 8-words x 10-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 10 +// Port 1 | Read: Async | Write: ---- | +reg [9:0] storage[0:7]; +reg [9:0] storage_dat0; +always @(posedge sys_clk) begin + if (sdcard_core_fifo_wrport_we) + storage[sdcard_core_fifo_wrport_adr] <= sdcard_core_fifo_wrport_dat_w; + storage_dat0 <= storage[sdcard_core_fifo_wrport_adr]; +end +always @(posedge sys_clk) begin +end +assign sdcard_core_fifo_wrport_dat_r = storage_dat0; +assign sdcard_core_fifo_rdport_dat_r = storage[sdcard_core_fifo_rdport_adr]; + + +//------------------------------------------------------------------------------ +// Memory storage_1: 512-words x 10-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 10 +// Port 1 | Read: Sync | Write: ---- | +reg [9:0] storage_1[0:511]; +reg [9:0] storage_1_dat0; +reg [9:0] storage_1_dat1; +always @(posedge sys_clk) begin + if (sdcard_block2mem_fifo_wrport_we) + storage_1[sdcard_block2mem_fifo_wrport_adr] <= sdcard_block2mem_fifo_wrport_dat_w; + storage_1_dat0 <= storage_1[sdcard_block2mem_fifo_wrport_adr]; +end +always @(posedge sys_clk) begin + if (sdcard_block2mem_fifo_rdport_re) + storage_1_dat1 <= storage_1[sdcard_block2mem_fifo_rdport_adr]; +end +assign sdcard_block2mem_fifo_wrport_dat_r = storage_1_dat0; +assign sdcard_block2mem_fifo_rdport_dat_r = storage_1_dat1; + + +//------------------------------------------------------------------------------ +// Memory storage_2: 16-words x 34-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 34 +// Port 1 | Read: Async | Write: ---- | +reg [33:0] storage_2[0:15]; +reg [33:0] storage_2_dat0; +always @(posedge sys_clk) begin + if (sdcard_mem2block_dma_fifo_wrport_we) + storage_2[sdcard_mem2block_dma_fifo_wrport_adr] <= sdcard_mem2block_dma_fifo_wrport_dat_w; + storage_2_dat0 <= storage_2[sdcard_mem2block_dma_fifo_wrport_adr]; +end +always @(posedge sys_clk) begin +end +assign sdcard_mem2block_dma_fifo_wrport_dat_r = storage_2_dat0; +assign sdcard_mem2block_dma_fifo_rdport_dat_r = storage_2[sdcard_mem2block_dma_fifo_rdport_adr]; + + +//------------------------------------------------------------------------------ +// Memory storage_3: 512-words x 10-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 10 +// Port 1 | Read: Sync | Write: ---- | +reg [9:0] storage_3[0:511]; +reg [9:0] storage_3_dat0; +reg [9:0] storage_3_dat1; +always @(posedge sys_clk) begin + if (sdcard_mem2block_fifo_wrport_we) + storage_3[sdcard_mem2block_fifo_wrport_adr] <= sdcard_mem2block_fifo_wrport_dat_w; + storage_3_dat0 <= storage_3[sdcard_mem2block_fifo_wrport_adr]; +end +always @(posedge sys_clk) begin + if (sdcard_mem2block_fifo_rdport_re) + storage_3_dat1 <= storage_3[sdcard_mem2block_fifo_rdport_adr]; +end +assign sdcard_mem2block_fifo_wrport_dat_r = storage_3_dat0; +assign sdcard_mem2block_fifo_rdport_dat_r = storage_3_dat1; + + +//------------------------------------------------------------------------------ +// Instance OFS1P3BX of OFS1P3BX Module. +//------------------------------------------------------------------------------ +OFS1P3BX OFS1P3BX( + // Inputs. + .D ((~clocker_clk0)), + .PD (1'd0), + .SCLK (sys_clk), + .SP (1'd1), + + // Outputs. + .Q (sdcard_clk) +); + +assign sdcard_cmd = inferedsdrtristate0_oe ? inferedsdrtristate0__o : 1'bz; +assign inferedsdrtristate0__i = sdcard_cmd; + +assign sdcard_data[0] = inferedsdrtristate1_oe ? inferedsdrtristate1__o : 1'bz; +assign inferedsdrtristate1__i = sdcard_data[0]; + +assign sdcard_data[1] = inferedsdrtristate2_oe ? inferedsdrtristate2__o : 1'bz; +assign inferedsdrtristate2__i = sdcard_data[1]; + +assign sdcard_data[2] = inferedsdrtristate3_oe ? inferedsdrtristate3__o : 1'bz; +assign inferedsdrtristate3__i = sdcard_data[2]; + +assign sdcard_data[3] = inferedsdrtristate4_oe ? inferedsdrtristate4__o : 1'bz; +assign inferedsdrtristate4__i = sdcard_data[3]; + +//------------------------------------------------------------------------------ +// Instance OFS1P3BX_1 of OFS1P3BX Module. +//------------------------------------------------------------------------------ +OFS1P3BX OFS1P3BX_1( + // Inputs. + .D (sdpads_cmd_oe), + .PD (1'd0), + .SCLK (sys_clk), + .SP (1'd1), + + // Outputs. + .Q (sdcard_cmd_dir) +); + +//------------------------------------------------------------------------------ +// Instance OFS1P3BX_2 of OFS1P3BX Module. +//------------------------------------------------------------------------------ +OFS1P3BX OFS1P3BX_2( + // Inputs. + .D (sdpads_data_oe), + .PD (1'd0), + .SCLK (sys_clk), + .SP (1'd1), + + // Outputs. + .Q (sdcard_dat0_dir) +); + +//------------------------------------------------------------------------------ +// Instance OFS1P3BX_3 of OFS1P3BX Module. +//------------------------------------------------------------------------------ +OFS1P3BX OFS1P3BX_3( + // Inputs. + .D (sdpads_data_oe), + .PD (1'd0), + .SCLK (sys_clk), + .SP (1'd1), + + // Outputs. + .Q (sdcard_dat13_dir) +); + +//------------------------------------------------------------------------------ +// Instance OFS1P3BX_4 of OFS1P3BX Module. +//------------------------------------------------------------------------------ +OFS1P3BX OFS1P3BX_4( + // Inputs. + .D (sdpads_cmd_o), + .PD (1'd0), + .SCLK (sys_clk), + .SP (1'd1), + + // Outputs. + .Q (inferedsdrtristate0__o) +); + +//------------------------------------------------------------------------------ +// Instance IFS1P3BX of IFS1P3BX Module. +//------------------------------------------------------------------------------ +IFS1P3BX IFS1P3BX( + // Inputs. + .D (inferedsdrtristate0__i), + .PD (1'd0), + .SCLK (sys_clk), + .SP (1'd1), + + // Outputs. + .Q (sdpads_cmd_i) +); + +//------------------------------------------------------------------------------ +// Instance OFS1P3BX_5 of OFS1P3BX Module. +//------------------------------------------------------------------------------ +OFS1P3BX OFS1P3BX_5( + // Inputs. + .D (sdpads_data_o[0]), + .PD (1'd0), + .SCLK (sys_clk), + .SP (1'd1), + + // Outputs. + .Q (inferedsdrtristate1__o) +); + +//------------------------------------------------------------------------------ +// Instance IFS1P3BX_1 of IFS1P3BX Module. +//------------------------------------------------------------------------------ +IFS1P3BX IFS1P3BX_1( + // Inputs. + .D (inferedsdrtristate1__i), + .PD (1'd0), + .SCLK (sys_clk), + .SP (1'd1), + + // Outputs. + .Q (sdpads_data_i[0]) +); + +//------------------------------------------------------------------------------ +// Instance OFS1P3BX_6 of OFS1P3BX Module. +//------------------------------------------------------------------------------ +OFS1P3BX OFS1P3BX_6( + // Inputs. + .D (sdpads_data_o[1]), + .PD (1'd0), + .SCLK (sys_clk), + .SP (1'd1), + + // Outputs. + .Q (inferedsdrtristate2__o) +); + +//------------------------------------------------------------------------------ +// Instance IFS1P3BX_2 of IFS1P3BX Module. +//------------------------------------------------------------------------------ +IFS1P3BX IFS1P3BX_2( + // Inputs. + .D (inferedsdrtristate2__i), + .PD (1'd0), + .SCLK (sys_clk), + .SP (1'd1), + + // Outputs. + .Q (sdpads_data_i[1]) +); + +//------------------------------------------------------------------------------ +// Instance OFS1P3BX_7 of OFS1P3BX Module. +//------------------------------------------------------------------------------ +OFS1P3BX OFS1P3BX_7( + // Inputs. + .D (sdpads_data_o[2]), + .PD (1'd0), + .SCLK (sys_clk), + .SP (1'd1), + + // Outputs. + .Q (inferedsdrtristate3__o) +); + +//------------------------------------------------------------------------------ +// Instance IFS1P3BX_3 of IFS1P3BX Module. +//------------------------------------------------------------------------------ +IFS1P3BX IFS1P3BX_3( + // Inputs. + .D (inferedsdrtristate3__i), + .PD (1'd0), + .SCLK (sys_clk), + .SP (1'd1), + + // Outputs. + .Q (sdpads_data_i[2]) +); + +//------------------------------------------------------------------------------ +// Instance OFS1P3BX_8 of OFS1P3BX Module. +//------------------------------------------------------------------------------ +OFS1P3BX OFS1P3BX_8( + // Inputs. + .D (sdpads_data_o[3]), + .PD (1'd0), + .SCLK (sys_clk), + .SP (1'd1), + + // Outputs. + .Q (inferedsdrtristate4__o) +); + +//------------------------------------------------------------------------------ +// Instance IFS1P3BX_4 of IFS1P3BX Module. +//------------------------------------------------------------------------------ +IFS1P3BX IFS1P3BX_4( + // Inputs. + .D (inferedsdrtristate4__i), + .PD (1'd0), + .SCLK (sys_clk), + .SP (1'd1), + + // Outputs. + .Q (sdpads_data_i[3]) +); + +endmodule + +// ----------------------------------------------------------------------------- +// Auto-Generated by LiteX on 2024-04-03 19:58:12. +//------------------------------------------------------------------------------