simple_ram: Turn on pipelining

With a 1 cycle delay Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
5 years ago · 365f60b693
parent c22734d0d9
commit 365f60b693
1 changed files with 1 additions and 1 deletions
--- a/simple_ram_behavioural.vhdl
+++ b/simple_ram_behavioural.vhdl
@ -11,7 +11,7 @@ entity mw_soc_memory is
    generic (
        RAM_INIT_FILE  : string;
        MEMORY_SIZE    : integer;
-	PIPELINE_DEPTH : integer := 0
+	PIPELINE_DEPTH : integer := 1
        );
    port (