Re-indent and reformat soc.vhdl

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
pull/40/head
Benjamin Herrenschmidt 5 years ago
parent a69a93b466
commit 310a56c076

@ -144,7 +144,8 @@ begin
uart0: entity work.pp_soc_uart
generic map(
FIFO_DEPTH => 32
) port map(
)
port map(
clk => system_clk,
reset => rst,
txd => uart0_txd,
@ -167,7 +168,8 @@ begin
generic map(
MEMORY_SIZE => MEMORY_SIZE,
RAM_INIT_FILE => RAM_INIT_FILE
) port map(
)
port map(
clk => system_clk,
reset => rst,
wb_adr_in => main_memory_adr_in,
@ -183,7 +185,9 @@ begin
main_memory_dat_in <= processor_dat_out;
main_memory_we_in <= processor_we_out;
main_memory_sel_in <= processor_sel_out;
main_memory_cyc_in <= processor_cyc_out when intercon_peripheral = PERIPHERAL_MAIN_MEMORY else '0';
main_memory_stb_in <= processor_stb_out when intercon_peripheral = PERIPHERAL_MAIN_MEMORY else '0';
main_memory_cyc_in <= processor_cyc_out when
intercon_peripheral = PERIPHERAL_MAIN_MEMORY else '0';
main_memory_stb_in <= processor_stb_out when
intercon_peripheral = PERIPHERAL_MAIN_MEMORY else '0';

end architecture behaviour;

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