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microwatt
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Reformat testbenches

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Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
pull/283/head
Anton Blanchard 4 years ago committed by Anton Blanchard
parent 0d86580ac7
commit 21f482f967
11 changed files with 604 additions and 604 deletions
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50
core_dram_tb.vhdl
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@ -9,7 +9,7 @@ use work.utils.all;


entity core_dram_tb is entity core_dram_tb is
generic ( generic (
MEMORY_SIZE : natural := (384*1024); MEMORY_SIZE : natural := (384*1024);
MAIN_RAM_FILE : string := "main_ram.bin"; MAIN_RAM_FILE : string := "main_ram.bin";
DRAM_INIT_FILE : string := ""; DRAM_INIT_FILE : string := "";
DRAM_INIT_SIZE : natural := 16#c000# DRAM_INIT_SIZE : natural := 16#c000#
@ -57,25 +57,25 @@ architecture behave of core_dram_tb is
begin begin


soc0: entity work.soc soc0: entity work.soc
generic map( generic map(
SIM => true, SIM => true,
MEMORY_SIZE => MEMORY_SIZE, MEMORY_SIZE => MEMORY_SIZE,
RAM_INIT_FILE => MAIN_RAM_FILE, RAM_INIT_FILE => MAIN_RAM_FILE,
HAS_DRAM => true, HAS_DRAM => true,
DRAM_SIZE => 256 * 1024 * 1024, DRAM_SIZE => 256 * 1024 * 1024,
DRAM_INIT_SIZE => ROM_SIZE, DRAM_INIT_SIZE => ROM_SIZE,
CLK_FREQ => 100000000, CLK_FREQ => 100000000,
HAS_SPI_FLASH => true, HAS_SPI_FLASH => true,
SPI_FLASH_DLINES => 4, SPI_FLASH_DLINES => 4,
SPI_FLASH_OFFSET => 0 SPI_FLASH_OFFSET => 0
) )
port map( port map(
rst => soc_rst, rst => soc_rst,
system_clk => system_clk, system_clk => system_clk,
wb_dram_in => wb_dram_in, wb_dram_in => wb_dram_in,
wb_dram_out => wb_dram_out, wb_dram_out => wb_dram_out,
wb_ext_io_in => wb_ext_io_in, wb_ext_io_in => wb_ext_io_in,
wb_ext_io_out => wb_ext_io_out, wb_ext_io_out => wb_ext_io_out,
wb_ext_is_dram_csr => wb_ext_is_dram_csr, wb_ext_is_dram_csr => wb_ext_is_dram_csr,
wb_ext_is_dram_init => wb_ext_is_dram_init, wb_ext_is_dram_init => wb_ext_is_dram_init,
spi_flash_sck => spi_sck, spi_flash_sck => spi_sck,
@ -83,8 +83,8 @@ begin
spi_flash_sdat_o => spi_sdat_o, spi_flash_sdat_o => spi_sdat_o,
spi_flash_sdat_oe => spi_sdat_oe, spi_flash_sdat_oe => spi_sdat_oe,
spi_flash_sdat_i => spi_sdat_i, spi_flash_sdat_i => spi_sdat_i,
alt_reset => core_alt_reset alt_reset => core_alt_reset
); );


flash: entity work.s25fl128s flash: entity work.s25fl128s
generic map ( generic map (
@ -142,18 +142,18 @@ begin


clk_process: process clk_process: process
begin begin
clk <= '0'; clk <= '0';
wait for clk_period/2; wait for clk_period/2;
clk <= '1'; clk <= '1';
wait for clk_period/2; wait for clk_period/2;
end process; end process;


rst_process: process rst_process: process
begin begin
rst <= '1'; rst <= '1';
wait for 10*clk_period; wait for 10*clk_period;
rst <= '0'; rst <= '0';
wait; wait;
end process; end process;


jtag: entity work.sim_jtag; jtag: entity work.sim_jtag;

42
core_flash_tb.vhdl
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@ -10,10 +10,10 @@ entity core_flash_tb is
end core_flash_tb; end core_flash_tb;


architecture behave of core_flash_tb is architecture behave of core_flash_tb is
signal clk, rst: std_logic; signal clk, rst: std_logic;


-- testbench signals -- testbench signals
constant clk_period : time := 10 ns; constant clk_period : time := 10 ns;


-- SPI -- SPI
signal spi_sck : std_ulogic; signal spi_sck : std_ulogic;
@ -28,24 +28,24 @@ architecture behave of core_flash_tb is
begin begin


soc0: entity work.soc soc0: entity work.soc
generic map( generic map(
SIM => true, SIM => true,
MEMORY_SIZE => (384*1024), MEMORY_SIZE => (384*1024),
RAM_INIT_FILE => "main_ram.bin", RAM_INIT_FILE => "main_ram.bin",
CLK_FREQ => 100000000, CLK_FREQ => 100000000,
HAS_SPI_FLASH => true, HAS_SPI_FLASH => true,
SPI_FLASH_DLINES => 4, SPI_FLASH_DLINES => 4,
SPI_FLASH_OFFSET => 0 SPI_FLASH_OFFSET => 0
) )
port map( port map(
rst => rst, rst => rst,
system_clk => clk, system_clk => clk,
spi_flash_sck => spi_sck, spi_flash_sck => spi_sck,
spi_flash_cs_n => spi_cs_n, spi_flash_cs_n => spi_cs_n,
spi_flash_sdat_o => spi_sdat_o, spi_flash_sdat_o => spi_sdat_o,
spi_flash_sdat_oe => spi_sdat_oe, spi_flash_sdat_oe => spi_sdat_oe,
spi_flash_sdat_i => spi_sdat_i spi_flash_sdat_i => spi_sdat_i
); );


flash: entity work.s25fl128s flash: entity work.s25fl128s
generic map ( generic map (
@ -78,18 +78,18 @@ begin
clk_process: process clk_process: process
begin begin
clk <= '0'; clk <= '0';
wait for clk_period/2; wait for clk_period/2;
clk <= '1'; clk <= '1';
wait for clk_period/2; wait for clk_period/2;
end process; end process;


rst_process: process rst_process: process
begin begin
rst <= '1'; rst <= '1';
wait for 10*clk_period; wait for 10*clk_period;
rst <= '0'; rst <= '0';
wait; wait;
end process; end process;


jtag: entity work.sim_jtag; jtag: entity work.sim_jtag;

42
core_tb.vhdl
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@ -10,38 +10,38 @@ entity core_tb is
end core_tb; end core_tb;


architecture behave of core_tb is architecture behave of core_tb is
signal clk, rst: std_logic; signal clk, rst: std_logic;


-- testbench signals -- testbench signals
constant clk_period : time := 10 ns; constant clk_period : time := 10 ns;
begin begin


soc0: entity work.soc soc0: entity work.soc
generic map( generic map(
SIM => true, SIM => true,
MEMORY_SIZE => (384*1024), MEMORY_SIZE => (384*1024),
RAM_INIT_FILE => "main_ram.bin", RAM_INIT_FILE => "main_ram.bin",
CLK_FREQ => 100000000 CLK_FREQ => 100000000
) )
port map( port map(
rst => rst, rst => rst,
system_clk => clk system_clk => clk
); );


clk_process: process clk_process: process
begin begin
clk <= '0'; clk <= '0';
wait for clk_period/2; wait for clk_period/2;
clk <= '1'; clk <= '1';
wait for clk_period/2; wait for clk_period/2;
end process; end process;


rst_process: process rst_process: process
begin begin
rst <= '1'; rst <= '1';
wait for 10*clk_period; wait for 10*clk_period;
rst <= '0'; rst <= '0';
wait; wait;
end process; end process;


jtag: entity work.sim_jtag; jtag: entity work.sim_jtag;

14
countzero_tb.vhdl
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@ -19,13 +19,13 @@ architecture behave of countzero_tb is


begin begin
zerocounter_0: entity work.zero_counter zerocounter_0: entity work.zero_counter
port map ( port map (
clk => clk, clk => clk,
rs => rs, rs => rs,
result => result, result => result,
count_right => count_right, count_right => count_right,
is_32bit => is_32bit is_32bit => is_32bit
); );


clk_process: process clk_process: process
begin begin
@ -109,6 +109,6 @@ begin
end loop; end loop;
end loop; end loop;


std.env.finish; std.env.finish;
end process; end process;
end behave; end behave;

82
dcache_tb.vhdl
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@ -70,69 +70,69 @@ begin


stim: process stim: process
begin begin
-- Clear stuff -- Clear stuff
d_in.valid <= '0'; d_in.valid <= '0';
d_in.load <= '0'; d_in.load <= '0';
d_in.nc <= '0'; d_in.nc <= '0';
d_in.addr <= (others => '0'); d_in.addr <= (others => '0');
d_in.data <= (others => '0'); d_in.data <= (others => '0');
m_in.valid <= '0'; m_in.valid <= '0';
m_in.addr <= (others => '0'); m_in.addr <= (others => '0');
m_in.pte <= (others => '0'); m_in.pte <= (others => '0');


wait for 4*clk_period; wait for 4*clk_period;
wait until rising_edge(clk); wait until rising_edge(clk);


-- Cacheable read of address 4 -- Cacheable read of address 4
d_in.load <= '1'; d_in.load <= '1';
d_in.nc <= '0'; d_in.nc <= '0';
d_in.addr <= x"0000000000000004"; d_in.addr <= x"0000000000000004";
d_in.valid <= '1'; d_in.valid <= '1';
wait until rising_edge(clk); wait until rising_edge(clk);
d_in.valid <= '0'; d_in.valid <= '0';


wait until rising_edge(clk) and d_out.valid = '1'; wait until rising_edge(clk) and d_out.valid = '1';
assert d_out.data = x"0000000100000000" assert d_out.data = x"0000000100000000"
report "data @" & to_hstring(d_in.addr) & report "data @" & to_hstring(d_in.addr) &
"=" & to_hstring(d_out.data) & "=" & to_hstring(d_out.data) &
" expected 0000000100000000" " expected 0000000100000000"
severity failure; severity failure;
-- wait for clk_period; -- wait for clk_period;


-- Cacheable read of address 30 -- Cacheable read of address 30
d_in.load <= '1'; d_in.load <= '1';
d_in.nc <= '0'; d_in.nc <= '0';
d_in.addr <= x"0000000000000030"; d_in.addr <= x"0000000000000030";
d_in.valid <= '1'; d_in.valid <= '1';
wait until rising_edge(clk); wait until rising_edge(clk);
d_in.valid <= '0'; d_in.valid <= '0';


wait until rising_edge(clk) and d_out.valid = '1'; wait until rising_edge(clk) and d_out.valid = '1';
assert d_out.data = x"0000000D0000000C" assert d_out.data = x"0000000D0000000C"
report "data @" & to_hstring(d_in.addr) & report "data @" & to_hstring(d_in.addr) &
"=" & to_hstring(d_out.data) & "=" & to_hstring(d_out.data) &
" expected 0000000D0000000C" " expected 0000000D0000000C"
severity failure; severity failure;


-- Non-cacheable read of address 100 -- Non-cacheable read of address 100
d_in.load <= '1'; d_in.load <= '1';
d_in.nc <= '1'; d_in.nc <= '1';
d_in.addr <= x"0000000000000100"; d_in.addr <= x"0000000000000100";
d_in.valid <= '1'; d_in.valid <= '1';
wait until rising_edge(clk); wait until rising_edge(clk);
d_in.valid <= '0'; d_in.valid <= '0';
wait until rising_edge(clk) and d_out.valid = '1'; wait until rising_edge(clk) and d_out.valid = '1';
assert d_out.data = x"0000004100000040" assert d_out.data = x"0000004100000040"
report "data @" & to_hstring(d_in.addr) & report "data @" & to_hstring(d_in.addr) &
"=" & to_hstring(d_out.data) & "=" & to_hstring(d_out.data) &
" expected 0000004100000040" " expected 0000004100000040"
severity failure; severity failure;


wait until rising_edge(clk); wait until rising_edge(clk);
wait until rising_edge(clk); wait until rising_edge(clk);
wait until rising_edge(clk); wait until rising_edge(clk);
wait until rising_edge(clk); wait until rising_edge(clk);


std.env.finish; std.env.finish;
end process; end process;
end; end;

398
dmi_dtm_tb.vhdl
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@ -19,12 +19,12 @@ architecture behave of dmi_dtm_tb is
constant jclk_period : time := 30 ns; constant jclk_period : time := 30 ns;


-- DMI debug bus signals -- DMI debug bus signals
signal dmi_addr : std_ulogic_vector(7 downto 0); signal dmi_addr : std_ulogic_vector(7 downto 0);
signal dmi_din : std_ulogic_vector(63 downto 0); signal dmi_din : std_ulogic_vector(63 downto 0);
signal dmi_dout : std_ulogic_vector(63 downto 0); signal dmi_dout : std_ulogic_vector(63 downto 0);
signal dmi_req : std_ulogic; signal dmi_req : std_ulogic;
signal dmi_wr : std_ulogic; signal dmi_wr : std_ulogic;
signal dmi_ack : std_ulogic; signal dmi_ack : std_ulogic;


-- Global JTAG signals (used by BSCANE2 inside dmi_dtm -- Global JTAG signals (used by BSCANE2 inside dmi_dtm
alias j : glob_jtag_t is glob_jtag; alias j : glob_jtag_t is glob_jtag;
@ -35,216 +35,216 @@ architecture behave of dmi_dtm_tb is


begin begin
dtm: entity work.dmi_dtm dtm: entity work.dmi_dtm
generic map( generic map(
ABITS => 8, ABITS => 8,
DBITS => 64 DBITS => 64
) )
port map( port map(
sys_clk => clk, sys_clk => clk,
sys_reset => rst, sys_reset => rst,
dmi_addr => dmi_addr, dmi_addr => dmi_addr,
dmi_din => dmi_din, dmi_din => dmi_din,
dmi_dout => dmi_dout, dmi_dout => dmi_dout,
dmi_req => dmi_req, dmi_req => dmi_req,
dmi_wr => dmi_wr, dmi_wr => dmi_wr,
dmi_ack => dmi_ack dmi_ack => dmi_ack
); );


simple_ram_0: entity work.wishbone_bram_wrapper simple_ram_0: entity work.wishbone_bram_wrapper
generic map(RAM_INIT_FILE => "main_ram.bin", generic map(RAM_INIT_FILE => "main_ram.bin",
MEMORY_SIZE => 524288) MEMORY_SIZE => 524288)
port map(clk => clk, rst => rst, port map(clk => clk, rst => rst,
wishbone_in => wishbone_ram_out, wishbone_in => wishbone_ram_out,
wishbone_out => wishbone_ram_in); wishbone_out => wishbone_ram_in);


wishbone_debug_0: entity work.wishbone_debug_master wishbone_debug_0: entity work.wishbone_debug_master
port map(clk => clk, rst => rst, port map(clk => clk, rst => rst,
dmi_addr => dmi_addr(1 downto 0), dmi_addr => dmi_addr(1 downto 0),
dmi_dout => dmi_din, dmi_dout => dmi_din,
dmi_din => dmi_dout, dmi_din => dmi_dout,
dmi_wr => dmi_wr, dmi_wr => dmi_wr,
dmi_ack => dmi_ack, dmi_ack => dmi_ack,
dmi_req => dmi_req, dmi_req => dmi_req,
wb_in => wishbone_ram_in, wb_in => wishbone_ram_in,
wb_out => wishbone_ram_out); wb_out => wishbone_ram_out);


-- system clock -- system clock
sys_clk: process sys_clk: process
begin begin
clk <= '1'; clk <= '1';
wait for clk_period / 2; wait for clk_period / 2;
clk <= '0'; clk <= '0';
wait for clk_period / 2; wait for clk_period / 2;
end process sys_clk; end process sys_clk;


-- system sim: just reset and wait -- system sim: just reset and wait
sys_sim: process sys_sim: process
begin begin
rst <= '1'; rst <= '1';
wait for clk_period; wait for clk_period;
rst <= '0'; rst <= '0';
wait; wait;
end process; end process;


-- jtag sim process -- jtag sim process
sim_jtag: process sim_jtag: process
procedure clock(count: in INTEGER) is procedure clock(count: in INTEGER) is
begin begin
for i in 1 to count loop for i in 1 to count loop
j.tck <= '0'; j.tck <= '0';
wait for jclk_period/2; wait for jclk_period/2;
j.tck <= '1'; j.tck <= '1';
wait for jclk_period/2; wait for jclk_period/2;
end loop; end loop;
end procedure clock; end procedure clock;


procedure shift_out(val: in std_ulogic_vector) is procedure shift_out(val: in std_ulogic_vector) is
begin begin
for i in 0 to val'length-1 loop for i in 0 to val'length-1 loop
j.tdi <= val(i); j.tdi <= val(i);
clock(1); clock(1);
end loop; end loop;
end procedure shift_out; end procedure shift_out;


procedure shift_in(val: out std_ulogic_vector) is procedure shift_in(val: out std_ulogic_vector) is
begin begin
for i in val'length-1 downto 0 loop for i in val'length-1 downto 0 loop
val := j.tdo & val(val'length-1 downto 1); val := j.tdo & val(val'length-1 downto 1);
clock(1); clock(1);
end loop; end loop;
end procedure shift_in; end procedure shift_in;


procedure send_command( procedure send_command(
addr : in std_ulogic_vector(7 downto 0); addr : in std_ulogic_vector(7 downto 0);
data : in std_ulogic_vector(63 downto 0); data : in std_ulogic_vector(63 downto 0);
op : in std_ulogic_vector(1 downto 0)) is op : in std_ulogic_vector(1 downto 0)) is
begin begin
j.capture <= '1'; j.capture <= '1';
clock(1); clock(1);
j.capture <= '0'; j.capture <= '0';
clock(1); clock(1);
j.shift <= '1'; j.shift <= '1';
shift_out(op); shift_out(op);
shift_out(data); shift_out(data);
shift_out(addr); shift_out(addr);
j.shift <= '0'; j.shift <= '0';
j.update <= '1'; j.update <= '1';
clock(1); clock(1);
j.update <= '0'; j.update <= '0';
clock(1); clock(1);
end procedure send_command; end procedure send_command;


procedure read_resp( procedure read_resp(
op : out std_ulogic_vector(1 downto 0); op : out std_ulogic_vector(1 downto 0);
data : out std_ulogic_vector(63 downto 0)) is data : out std_ulogic_vector(63 downto 0)) is


variable addr : std_ulogic_vector(7 downto 0); variable addr : std_ulogic_vector(7 downto 0);
begin begin
j.capture <= '1'; j.capture <= '1';
clock(1); clock(1);
j.capture <= '0'; j.capture <= '0';
clock(1); clock(1);
j.shift <= '1'; j.shift <= '1';
shift_in(op); shift_in(op);
shift_in(data); shift_in(data);
shift_in(addr); shift_in(addr);
j.shift <= '0'; j.shift <= '0';
j.update <= '1'; j.update <= '1';
clock(1); clock(1);
j.update <= '0'; j.update <= '0';
clock(1); clock(1);
end procedure read_resp; end procedure read_resp;


procedure dmi_write(addr : in std_ulogic_vector(7 downto 0); procedure dmi_write(addr : in std_ulogic_vector(7 downto 0);
data : in std_ulogic_vector(63 downto 0)) is data : in std_ulogic_vector(63 downto 0)) is
variable resp_op : std_ulogic_vector(1 downto 0); variable resp_op : std_ulogic_vector(1 downto 0);
variable resp_data : std_ulogic_vector(63 downto 0); variable resp_data : std_ulogic_vector(63 downto 0);
variable timeout : integer; variable timeout : integer;
begin begin
send_command(addr, data, "10"); send_command(addr, data, "10");
loop loop
read_resp(resp_op, resp_data); read_resp(resp_op, resp_data);
case resp_op is case resp_op is
when "00" => when "00" =>
return; return;
when "11" => when "11" =>
timeout := timeout + 1; timeout := timeout + 1;
assert timeout < 0 assert timeout < 0
report "dmi_write timed out !" severity error; report "dmi_write timed out !" severity error;
when others => when others =>
assert 0 > 1 report "dmi_write got odd status: " & assert 0 > 1 report "dmi_write got odd status: " &
to_hstring(resp_op) severity error; to_hstring(resp_op) severity error;
end case; end case;
end loop; end loop;
end procedure dmi_write; end procedure dmi_write;


procedure dmi_read(addr : in std_ulogic_vector(7 downto 0); procedure dmi_read(addr : in std_ulogic_vector(7 downto 0);
data : out std_ulogic_vector(63 downto 0)) is data : out std_ulogic_vector(63 downto 0)) is
variable resp_op : std_ulogic_vector(1 downto 0); variable resp_op : std_ulogic_vector(1 downto 0);
variable timeout : integer; variable timeout : integer;
begin begin
send_command(addr, (others => '0'), "01"); send_command(addr, (others => '0'), "01");
loop loop
read_resp(resp_op, data); read_resp(resp_op, data);
case resp_op is case resp_op is
when "00" => when "00" =>
return; return;
when "11" => when "11" =>
timeout := timeout + 1; timeout := timeout + 1;
assert timeout < 0 assert timeout < 0
report "dmi_read timed out !" severity error; report "dmi_read timed out !" severity error;
when others => when others =>
assert 0 > 1 report "dmi_read got odd status: " & assert 0 > 1 report "dmi_read got odd status: " &
to_hstring(resp_op) severity error; to_hstring(resp_op) severity error;
end case; end case;
end loop; end loop;
end procedure dmi_read; end procedure dmi_read;


variable data : std_ulogic_vector(63 downto 0); variable data : std_ulogic_vector(63 downto 0);
begin begin
-- init & reset -- init & reset
j.reset <= '1'; j.reset <= '1';
j.sel <= "0000"; j.sel <= "0000";
j.capture <= '0'; j.capture <= '0';
j.update <= '0'; j.update <= '0';
j.shift <= '0'; j.shift <= '0';
j.tdi <= '0'; j.tdi <= '0';
j.tms <= '0'; j.tms <= '0';
j.runtest <= '0'; j.runtest <= '0';
clock(5); clock(5);
j.reset <= '0'; j.reset <= '0';
clock(5); clock(5);


-- select chain 2 -- select chain 2
j.sel <= "0010"; j.sel <= "0010";
clock(1); clock(1);


-- send command -- send command
dmi_read(x"00", data); dmi_read(x"00", data);
report "Read addr reg:" & to_hstring(data); report "Read addr reg:" & to_hstring(data);
report "Writing addr reg to all 1's"; report "Writing addr reg to all 1's";
dmi_write(x"00", (others => '1')); dmi_write(x"00", (others => '1'));
dmi_read(x"00", data); dmi_read(x"00", data);
report "Read addr reg:" & to_hstring(data); report "Read addr reg:" & to_hstring(data);


report "Writing ctrl reg to all 1's"; report "Writing ctrl reg to all 1's";
dmi_write(x"02", (others => '1')); dmi_write(x"02", (others => '1'));
dmi_read(x"02", data); dmi_read(x"02", data);
report "Read ctrl reg:" & to_hstring(data); report "Read ctrl reg:" & to_hstring(data);


report "Read memory at 0...\n"; report "Read memory at 0...\n";
dmi_write(x"00", x"0000000000000000"); dmi_write(x"00", x"0000000000000000");
dmi_write(x"02", x"00000000000007ff"); dmi_write(x"02", x"00000000000007ff");
dmi_read(x"01", data); dmi_read(x"01", data);
report "00:" & to_hstring(data); report "00:" & to_hstring(data);
dmi_read(x"01", data); dmi_read(x"01", data);
report "08:" & to_hstring(data); report "08:" & to_hstring(data);
dmi_read(x"01", data); dmi_read(x"01", data);
report "10:" & to_hstring(data); report "10:" & to_hstring(data);
dmi_read(x"01", data); dmi_read(x"01", data);
report "18:" & to_hstring(data); report "18:" & to_hstring(data);
clock(10); clock(10);
std.env.finish; std.env.finish;
end process; end process;
end behave; end behave;

8
dram_tb.vhdl
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@ -104,10 +104,10 @@ begin


-- Read data receive queue -- Read data receive queue
data_queue: entity work.sync_fifo data_queue: entity work.sync_fifo
generic map ( generic map (
DEPTH => 16, DEPTH => 16,
WIDTH => rd_data'length WIDTH => rd_data'length
) )
port map ( port map (
clk => clk, clk => clk,
reset => soc_rst or reset_acks, reset => soc_rst or reset_acks,

36
icache_tb.vhdl
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@ -34,7 +34,7 @@ begin
i_out => i_in, i_out => i_in,
m_in => m_out, m_in => m_out,
stall_in => '0', stall_in => '0',
flush_in => '0', flush_in => '0',
inval_in => '0', inval_in => '0',
wishbone_out => wb_bram_in, wishbone_out => wb_bram_in,
wishbone_in => wb_bram_out wishbone_in => wb_bram_out
@ -73,7 +73,7 @@ begin
begin begin
i_out.req <= '0'; i_out.req <= '0';
i_out.nia <= (others => '0'); i_out.nia <= (others => '0');
i_out.stop_mark <= '0'; i_out.stop_mark <= '0';


m_out.tlbld <= '0'; m_out.tlbld <= '0';
m_out.tlbie <= '0'; m_out.tlbie <= '0';
@ -93,10 +93,10 @@ begin


assert i_in.valid = '1' severity failure; assert i_in.valid = '1' severity failure;
assert i_in.insn = x"00000001" assert i_in.insn = x"00000001"
report "insn @" & to_hstring(i_out.nia) & report "insn @" & to_hstring(i_out.nia) &
"=" & to_hstring(i_in.insn) & "=" & to_hstring(i_in.insn) &
" expected 00000001" " expected 00000001"
severity failure; severity failure;


i_out.req <= '0'; i_out.req <= '0';


@ -109,10 +109,10 @@ begin
wait until rising_edge(clk); wait until rising_edge(clk);
assert i_in.valid = '1' severity failure; assert i_in.valid = '1' severity failure;
assert i_in.insn = x"00000002" assert i_in.insn = x"00000002"
report "insn @" & to_hstring(i_out.nia) & report "insn @" & to_hstring(i_out.nia) &
"=" & to_hstring(i_in.insn) & "=" & to_hstring(i_in.insn) &
" expected 00000002" " expected 00000002"
severity failure; severity failure;
wait until rising_edge(clk); wait until rising_edge(clk);


-- another miss -- another miss
@ -124,10 +124,10 @@ begin


assert i_in.valid = '1' severity failure; assert i_in.valid = '1' severity failure;
assert i_in.insn = x"00000010" assert i_in.insn = x"00000010"
report "insn @" & to_hstring(i_out.nia) & report "insn @" & to_hstring(i_out.nia) &
"=" & to_hstring(i_in.insn) & "=" & to_hstring(i_in.insn) &
" expected 00000010" " expected 00000010"
severity failure; severity failure;


-- test something that aliases -- test something that aliases
i_out.req <= '1'; i_out.req <= '1';
@ -142,10 +142,10 @@ begin


assert i_in.valid = '1' severity failure; assert i_in.valid = '1' severity failure;
assert i_in.insn = x"00000040" assert i_in.insn = x"00000040"
report "insn @" & to_hstring(i_out.nia) & report "insn @" & to_hstring(i_out.nia) &
"=" & to_hstring(i_in.insn) & "=" & to_hstring(i_in.insn) &
" expected 00000040" " expected 00000040"
severity failure; severity failure;


i_out.req <= '0'; i_out.req <= '0';



110
plru_tb.vhdl
Unescape Escape View File

@ -27,9 +27,9 @@ begin
clk => clk, clk => clk,
rst => rst, rst => rst,


acc => acc, acc => acc,
acc_en => acc_en, acc_en => acc_en,
lru => lru lru => lru
); );


clk_process: process clk_process: process
@ -50,58 +50,58 @@ begin


stim: process stim: process
begin begin
wait for 4*clk_period; wait for 4*clk_period;


report "accessing 1:"; report "accessing 1:";
acc <= "001"; acc <= "001";
acc_en <= '1'; acc_en <= '1';
wait for clk_period; wait for clk_period;
report "lru:" & to_hstring(lru); report "lru:" & to_hstring(lru);


report "accessing 2:"; report "accessing 2:";
acc <= "010"; acc <= "010";
wait for clk_period; wait for clk_period;
report "lru:" & to_hstring(lru); report "lru:" & to_hstring(lru);


report "accessing 7:"; report "accessing 7:";
acc <= "111"; acc <= "111";
wait for clk_period; wait for clk_period;
report "lru:" & to_hstring(lru); report "lru:" & to_hstring(lru);


report "accessing 4:"; report "accessing 4:";
acc <= "100"; acc <= "100";
wait for clk_period; wait for clk_period;
report "lru:" & to_hstring(lru); report "lru:" & to_hstring(lru);


report "accessing 3:"; report "accessing 3:";
acc <= "011"; acc <= "011";
wait for clk_period; wait for clk_period;
report "lru:" & to_hstring(lru); report "lru:" & to_hstring(lru);


report "accessing 5:"; report "accessing 5:";
acc <= "101"; acc <= "101";
wait for clk_period; wait for clk_period;
report "lru:" & to_hstring(lru); report "lru:" & to_hstring(lru);


report "accessing 3:"; report "accessing 3:";
acc <= "011"; acc <= "011";
wait for clk_period; wait for clk_period;
report "lru:" & to_hstring(lru); report "lru:" & to_hstring(lru);


report "accessing 5:"; report "accessing 5:";
acc <= "101"; acc <= "101";
wait for clk_period; wait for clk_period;
report "lru:" & to_hstring(lru); report "lru:" & to_hstring(lru);


report "accessing 6:"; report "accessing 6:";
acc <= "110"; acc <= "110";
wait for clk_period; wait for clk_period;
report "lru:" & to_hstring(lru); report "lru:" & to_hstring(lru);


report "accessing 0:"; report "accessing 0:";
acc <= "000"; acc <= "000";
wait for clk_period; wait for clk_period;
report "lru:" & to_hstring(lru); report "lru:" & to_hstring(lru);


std.env.finish; std.env.finish;
end process; end process;

408
rotator_tb.vhdl
Unescape Escape View File

@ -23,272 +23,272 @@ architecture behave of rotator_tb is


begin begin
rotator_0: entity work.rotator rotator_0: entity work.rotator
port map ( port map (
rs => rs, rs => rs,
ra => ra, ra => ra,
shift => shift, shift => shift,
insn => insn, insn => insn,
is_32bit => is_32bit, is_32bit => is_32bit,
right_shift => right_shift, right_shift => right_shift,
arith => arith, arith => arith,
clear_left => clear_left, clear_left => clear_left,
clear_right => clear_right, clear_right => clear_right,
sign_ext_rs => extsw, sign_ext_rs => extsw,
result => result, result => result,
carry_out => carry_out carry_out => carry_out
); );


stim_process: process stim_process: process
variable behave_ra: std_ulogic_vector(63 downto 0); variable behave_ra: std_ulogic_vector(63 downto 0);
variable behave_ca_ra: std_ulogic_vector(64 downto 0); variable behave_ca_ra: std_ulogic_vector(64 downto 0);
begin begin
-- rlwinm, rlwnm -- rlwinm, rlwnm
report "test rlw[i]nm"; report "test rlw[i]nm";
ra <= (others => '0'); ra <= (others => '0');
is_32bit <= '1'; is_32bit <= '1';
right_shift <= '0'; right_shift <= '0';
arith <= '0'; arith <= '0';
clear_left <= '1'; clear_left <= '1';
clear_right <= '1'; clear_right <= '1';
extsw <= '0'; extsw <= '0';
rlwnm_loop : for i in 0 to 1000 loop rlwnm_loop : for i in 0 to 1000 loop
rs <= pseudorand(64); rs <= pseudorand(64);
shift <= pseudorand(7); shift <= pseudorand(7);
insn <= x"00000" & '0' & pseudorand(10) & '0'; insn <= x"00000" & '0' & pseudorand(10) & '0';
wait for clk_period; wait for clk_period;
behave_ra := ppc_rlwinm(rs, shift(4 downto 0), insn_mb32(insn), insn_me32(insn)); behave_ra := ppc_rlwinm(rs, shift(4 downto 0), insn_mb32(insn), insn_me32(insn));
assert behave_ra = result assert behave_ra = result
report "bad rlwnm expected " & to_hstring(behave_ra) & " got " & to_hstring(result); report "bad rlwnm expected " & to_hstring(behave_ra) & " got " & to_hstring(result);
end loop; end loop;


-- rlwimi -- rlwimi
report "test rlwimi"; report "test rlwimi";
is_32bit <= '1'; is_32bit <= '1';
right_shift <= '0'; right_shift <= '0';
arith <= '0'; arith <= '0';
clear_left <= '1'; clear_left <= '1';
clear_right <= '1'; clear_right <= '1';
rlwimi_loop : for i in 0 to 1000 loop rlwimi_loop : for i in 0 to 1000 loop
rs <= pseudorand(64); rs <= pseudorand(64);
ra <= pseudorand(64); ra <= pseudorand(64);
shift <= "00" & pseudorand(5); shift <= "00" & pseudorand(5);
insn <= x"00000" & '0' & pseudorand(10) & '0'; insn <= x"00000" & '0' & pseudorand(10) & '0';
wait for clk_period; wait for clk_period;
behave_ra := ppc_rlwimi(ra, rs, shift(4 downto 0), insn_mb32(insn), insn_me32(insn)); behave_ra := ppc_rlwimi(ra, rs, shift(4 downto 0), insn_mb32(insn), insn_me32(insn));
assert behave_ra = result assert behave_ra = result
report "bad rlwimi expected " & to_hstring(behave_ra) & " got " & to_hstring(result); report "bad rlwimi expected " & to_hstring(behave_ra) & " got " & to_hstring(result);
end loop; end loop;


-- rldicl, rldcl -- rldicl, rldcl
report "test rld[i]cl"; report "test rld[i]cl";
ra <= (others => '0'); ra <= (others => '0');
is_32bit <= '0'; is_32bit <= '0';
right_shift <= '0'; right_shift <= '0';
arith <= '0'; arith <= '0';
clear_left <= '1'; clear_left <= '1';
clear_right <= '0'; clear_right <= '0';
rldicl_loop : for i in 0 to 1000 loop rldicl_loop : for i in 0 to 1000 loop
rs <= pseudorand(64); rs <= pseudorand(64);
shift <= pseudorand(7); shift <= pseudorand(7);
insn <= x"00000" & '0' & pseudorand(10) & '0'; insn <= x"00000" & '0' & pseudorand(10) & '0';
wait for clk_period; wait for clk_period;
behave_ra := ppc_rldicl(rs, shift(5 downto 0), insn_mb(insn)); behave_ra := ppc_rldicl(rs, shift(5 downto 0), insn_mb(insn));
assert behave_ra = result assert behave_ra = result
report "bad rldicl expected " & to_hstring(behave_ra) & " got " & to_hstring(result); report "bad rldicl expected " & to_hstring(behave_ra) & " got " & to_hstring(result);
end loop; end loop;


-- rldicr, rldcr -- rldicr, rldcr
report "test rld[i]cr"; report "test rld[i]cr";
ra <= (others => '0'); ra <= (others => '0');
is_32bit <= '0'; is_32bit <= '0';
right_shift <= '0'; right_shift <= '0';
arith <= '0'; arith <= '0';
clear_left <= '0'; clear_left <= '0';
clear_right <= '1'; clear_right <= '1';
rldicr_loop : for i in 0 to 1000 loop rldicr_loop : for i in 0 to 1000 loop
rs <= pseudorand(64); rs <= pseudorand(64);
shift <= pseudorand(7); shift <= pseudorand(7);
insn <= x"00000" & '0' & pseudorand(10) & '0'; insn <= x"00000" & '0' & pseudorand(10) & '0';
wait for clk_period; wait for clk_period;
behave_ra := ppc_rldicr(rs, shift(5 downto 0), insn_me(insn)); behave_ra := ppc_rldicr(rs, shift(5 downto 0), insn_me(insn));
--report "rs = " & to_hstring(rs); --report "rs = " & to_hstring(rs);
--report "ra = " & to_hstring(ra); --report "ra = " & to_hstring(ra);
--report "shift = " & to_hstring(shift); --report "shift = " & to_hstring(shift);
--report "insn me = " & to_hstring(insn_me(insn)); --report "insn me = " & to_hstring(insn_me(insn));
--report "result = " & to_hstring(result); --report "result = " & to_hstring(result);
assert behave_ra = result assert behave_ra = result
report "bad rldicr expected " & to_hstring(behave_ra) & " got " & to_hstring(result); report "bad rldicr expected " & to_hstring(behave_ra) & " got " & to_hstring(result);
end loop; end loop;


-- rldic -- rldic
report "test rldic"; report "test rldic";
ra <= (others => '0'); ra <= (others => '0');
is_32bit <= '0'; is_32bit <= '0';
right_shift <= '0'; right_shift <= '0';
arith <= '0'; arith <= '0';
clear_left <= '1'; clear_left <= '1';
clear_right <= '1'; clear_right <= '1';
rldic_loop : for i in 0 to 1000 loop rldic_loop : for i in 0 to 1000 loop
rs <= pseudorand(64); rs <= pseudorand(64);
shift <= '0' & pseudorand(6); shift <= '0' & pseudorand(6);
insn <= x"00000" & '0' & pseudorand(10) & '0'; insn <= x"00000" & '0' & pseudorand(10) & '0';
wait for clk_period; wait for clk_period;
behave_ra := ppc_rldic(rs, shift(5 downto 0), insn_mb(insn)); behave_ra := ppc_rldic(rs, shift(5 downto 0), insn_mb(insn));
assert behave_ra = result assert behave_ra = result
report "bad rldic expected " & to_hstring(behave_ra) & " got " & to_hstring(result); report "bad rldic expected " & to_hstring(behave_ra) & " got " & to_hstring(result);
end loop; end loop;


-- rldimi -- rldimi
report "test rldimi"; report "test rldimi";
is_32bit <= '0'; is_32bit <= '0';
right_shift <= '0'; right_shift <= '0';
arith <= '0'; arith <= '0';
clear_left <= '1'; clear_left <= '1';
clear_right <= '1'; clear_right <= '1';
rldimi_loop : for i in 0 to 1000 loop rldimi_loop : for i in 0 to 1000 loop
rs <= pseudorand(64); rs <= pseudorand(64);
ra <= pseudorand(64); ra <= pseudorand(64);
shift <= '0' & pseudorand(6); shift <= '0' & pseudorand(6);
insn <= x"00000" & '0' & pseudorand(10) & '0'; insn <= x"00000" & '0' & pseudorand(10) & '0';
wait for clk_period; wait for clk_period;
behave_ra := ppc_rldimi(ra, rs, shift(5 downto 0), insn_mb(insn)); behave_ra := ppc_rldimi(ra, rs, shift(5 downto 0), insn_mb(insn));
assert behave_ra = result assert behave_ra = result
report "bad rldimi expected " & to_hstring(behave_ra) & " got " & to_hstring(result); report "bad rldimi expected " & to_hstring(behave_ra) & " got " & to_hstring(result);
end loop; end loop;


-- slw -- slw
report "test slw"; report "test slw";
ra <= (others => '0'); ra <= (others => '0');
is_32bit <= '1'; is_32bit <= '1';
right_shift <= '0'; right_shift <= '0';
arith <= '0'; arith <= '0';
clear_left <= '0'; clear_left <= '0';
clear_right <= '0'; clear_right <= '0';
slw_loop : for i in 0 to 1000 loop slw_loop : for i in 0 to 1000 loop
rs <= pseudorand(64); rs <= pseudorand(64);
shift <= pseudorand(7); shift <= pseudorand(7);
wait for clk_period; wait for clk_period;
behave_ra := ppc_slw(rs, std_ulogic_vector(resize(unsigned(shift), 64))); behave_ra := ppc_slw(rs, std_ulogic_vector(resize(unsigned(shift), 64)));
assert behave_ra = result assert behave_ra = result
report "bad slw expected " & to_hstring(behave_ra) & " got " & to_hstring(result); report "bad slw expected " & to_hstring(behave_ra) & " got " & to_hstring(result);
end loop; end loop;


-- sld -- sld
report "test sld"; report "test sld";
ra <= (others => '0'); ra <= (others => '0');
is_32bit <= '0'; is_32bit <= '0';
right_shift <= '0'; right_shift <= '0';
arith <= '0'; arith <= '0';
clear_left <= '0'; clear_left <= '0';
clear_right <= '0'; clear_right <= '0';
sld_loop : for i in 0 to 1000 loop sld_loop : for i in 0 to 1000 loop
rs <= pseudorand(64); rs <= pseudorand(64);
shift <= pseudorand(7); shift <= pseudorand(7);
wait for clk_period; wait for clk_period;
behave_ra := ppc_sld(rs, std_ulogic_vector(resize(unsigned(shift), 64))); behave_ra := ppc_sld(rs, std_ulogic_vector(resize(unsigned(shift), 64)));
assert behave_ra = result assert behave_ra = result
report "bad sld expected " & to_hstring(behave_ra) & " got " & to_hstring(result); report "bad sld expected " & to_hstring(behave_ra) & " got " & to_hstring(result);
end loop; end loop;


-- srw -- srw
report "test srw"; report "test srw";
ra <= (others => '0'); ra <= (others => '0');
is_32bit <= '1'; is_32bit <= '1';
right_shift <= '1'; right_shift <= '1';
arith <= '0'; arith <= '0';
clear_left <= '0'; clear_left <= '0';
clear_right <= '0'; clear_right <= '0';
srw_loop : for i in 0 to 1000 loop srw_loop : for i in 0 to 1000 loop
rs <= pseudorand(64); rs <= pseudorand(64);
shift <= pseudorand(7); shift <= pseudorand(7);
wait for clk_period; wait for clk_period;
behave_ra := ppc_srw(rs, std_ulogic_vector(resize(unsigned(shift), 64))); behave_ra := ppc_srw(rs, std_ulogic_vector(resize(unsigned(shift), 64)));
assert behave_ra = result assert behave_ra = result
report "bad srw expected " & to_hstring(behave_ra) & " got " & to_hstring(result); report "bad srw expected " & to_hstring(behave_ra) & " got " & to_hstring(result);
end loop; end loop;


-- srd -- srd
report "test srd"; report "test srd";
ra <= (others => '0'); ra <= (others => '0');
is_32bit <= '0'; is_32bit <= '0';
right_shift <= '1'; right_shift <= '1';
arith <= '0'; arith <= '0';
clear_left <= '0'; clear_left <= '0';
clear_right <= '0'; clear_right <= '0';
srd_loop : for i in 0 to 1000 loop srd_loop : for i in 0 to 1000 loop
rs <= pseudorand(64); rs <= pseudorand(64);
shift <= pseudorand(7); shift <= pseudorand(7);
wait for clk_period; wait for clk_period;
behave_ra := ppc_srd(rs, std_ulogic_vector(resize(unsigned(shift), 64))); behave_ra := ppc_srd(rs, std_ulogic_vector(resize(unsigned(shift), 64)));
assert behave_ra = result assert behave_ra = result
report "bad srd expected " & to_hstring(behave_ra) & " got " & to_hstring(result); report "bad srd expected " & to_hstring(behave_ra) & " got " & to_hstring(result);
end loop; end loop;


-- sraw[i] -- sraw[i]
report "test sraw[i]"; report "test sraw[i]";
ra <= (others => '0'); ra <= (others => '0');
is_32bit <= '1'; is_32bit <= '1';
right_shift <= '1'; right_shift <= '1';
arith <= '1'; arith <= '1';
clear_left <= '0'; clear_left <= '0';
clear_right <= '0'; clear_right <= '0';
sraw_loop : for i in 0 to 1000 loop sraw_loop : for i in 0 to 1000 loop
rs <= pseudorand(64); rs <= pseudorand(64);
shift <= '0' & pseudorand(6); shift <= '0' & pseudorand(6);
wait for clk_period; wait for clk_period;
behave_ca_ra := ppc_sraw(rs, std_ulogic_vector(resize(unsigned(shift), 64))); behave_ca_ra := ppc_sraw(rs, std_ulogic_vector(resize(unsigned(shift), 64)));
--report "rs = " & to_hstring(rs); --report "rs = " & to_hstring(rs);
--report "ra = " & to_hstring(ra); --report "ra = " & to_hstring(ra);
--report "shift = " & to_hstring(shift); --report "shift = " & to_hstring(shift);
--report "result = " & to_hstring(carry_out & result); --report "result = " & to_hstring(carry_out & result);
assert behave_ca_ra(63 downto 0) = result and behave_ca_ra(64) = carry_out assert behave_ca_ra(63 downto 0) = result and behave_ca_ra(64) = carry_out
report "bad sraw expected " & to_hstring(behave_ca_ra) & " got " & to_hstring(carry_out & result); report "bad sraw expected " & to_hstring(behave_ca_ra) & " got " & to_hstring(carry_out & result);
end loop; end loop;


-- srad[i] -- srad[i]
report "test srad[i]"; report "test srad[i]";
ra <= (others => '0'); ra <= (others => '0');
is_32bit <= '0'; is_32bit <= '0';
right_shift <= '1'; right_shift <= '1';
arith <= '1'; arith <= '1';
clear_left <= '0'; clear_left <= '0';
clear_right <= '0'; clear_right <= '0';
srad_loop : for i in 0 to 1000 loop srad_loop : for i in 0 to 1000 loop
rs <= pseudorand(64); rs <= pseudorand(64);
shift <= pseudorand(7); shift <= pseudorand(7);
wait for clk_period; wait for clk_period;
behave_ca_ra := ppc_srad(rs, std_ulogic_vector(resize(unsigned(shift), 64))); behave_ca_ra := ppc_srad(rs, std_ulogic_vector(resize(unsigned(shift), 64)));
--report "rs = " & to_hstring(rs); --report "rs = " & to_hstring(rs);
--report "ra = " & to_hstring(ra); --report "ra = " & to_hstring(ra);
--report "shift = " & to_hstring(shift); --report "shift = " & to_hstring(shift);
--report "result = " & to_hstring(carry_out & result); --report "result = " & to_hstring(carry_out & result);
assert behave_ca_ra(63 downto 0) = result and behave_ca_ra(64) = carry_out assert behave_ca_ra(63 downto 0) = result and behave_ca_ra(64) = carry_out
report "bad srad expected " & to_hstring(behave_ca_ra) & " got " & to_hstring(carry_out & result); report "bad srad expected " & to_hstring(behave_ca_ra) & " got " & to_hstring(carry_out & result);
end loop; end loop;


-- extswsli -- extswsli
report "test extswsli"; report "test extswsli";
ra <= (others => '0'); ra <= (others => '0');
is_32bit <= '0'; is_32bit <= '0';
right_shift <= '0'; right_shift <= '0';
arith <= '0'; arith <= '0';
clear_left <= '0'; clear_left <= '0';
clear_right <= '0'; clear_right <= '0';
extsw <= '1'; extsw <= '1';
extswsli_loop : for i in 0 to 1000 loop extswsli_loop : for i in 0 to 1000 loop
rs <= pseudorand(64); rs <= pseudorand(64);
shift <= '0' & pseudorand(6); shift <= '0' & pseudorand(6);
wait for clk_period; wait for clk_period;
behave_ra := rs; behave_ra := rs;
behave_ra(63 downto 32) := (others => rs(31)); behave_ra(63 downto 32) := (others => rs(31));
behave_ra := std_ulogic_vector(shift_left(unsigned(behave_ra), behave_ra := std_ulogic_vector(shift_left(unsigned(behave_ra),
to_integer(unsigned(shift)))); to_integer(unsigned(shift))));
--report "rs = " & to_hstring(rs); --report "rs = " & to_hstring(rs);
--report "ra = " & to_hstring(ra); --report "ra = " & to_hstring(ra);
--report "shift = " & to_hstring(shift); --report "shift = " & to_hstring(shift);
--report "result = " & to_hstring(carry_out & result); --report "result = " & to_hstring(carry_out & result);
assert behave_ra = result assert behave_ra = result
report "bad extswsli expected " & to_hstring(behave_ra) & " got " & to_hstring(result); report "bad extswsli expected " & to_hstring(behave_ra) & " got " & to_hstring(result);
end loop; end loop;


std.env.finish; std.env.finish;

18
wishbone_bram_tb.vhdl
Unescape Escape View File

@ -19,7 +19,7 @@ architecture behave of wishbone_bram_tb is


impure function to_adr(a: integer) return std_ulogic_vector is impure function to_adr(a: integer) return std_ulogic_vector is
begin begin
return std_ulogic_vector(to_unsigned(a, w_out.adr'length)); return std_ulogic_vector(to_unsigned(a, w_out.adr'length));
end; end;
begin begin
simple_ram_0: entity work.wishbone_bram_wrapper simple_ram_0: entity work.wishbone_bram_wrapper
@ -57,7 +57,7 @@ begin


w_out.cyc <= '1'; w_out.cyc <= '1';


-- Test read 0 -- Test read 0
w_out.stb <= '1'; w_out.stb <= '1';
w_out.sel <= "11111111"; w_out.sel <= "11111111";
w_out.adr <= to_adr(0); w_out.adr <= to_adr(0);
@ -71,7 +71,7 @@ begin
wait until rising_edge(clk); wait until rising_edge(clk);
assert w_in.ack = '0'; assert w_in.ack = '0';


-- Test read 8 -- Test read 8
w_out.stb <= '1'; w_out.stb <= '1';
w_out.sel <= "11111111"; w_out.sel <= "11111111";
w_out.adr <= to_adr(8); w_out.adr <= to_adr(8);
@ -85,7 +85,7 @@ begin
wait until rising_edge(clk); wait until rising_edge(clk);
assert w_in.ack = '0'; assert w_in.ack = '0';


-- Test write byte at 0 -- Test write byte at 0
w_out.stb <= '1'; w_out.stb <= '1';
w_out.sel <= "00000001"; w_out.sel <= "00000001";
w_out.adr <= to_adr(0); w_out.adr <= to_adr(0);
@ -98,7 +98,7 @@ begin
wait until rising_edge(clk); wait until rising_edge(clk);
assert w_in.ack = '0'; assert w_in.ack = '0';


-- Test read back -- Test read back
w_out.stb <= '1'; w_out.stb <= '1';
w_out.sel <= "11111111"; w_out.sel <= "11111111";
w_out.adr <= to_adr(0); w_out.adr <= to_adr(0);
@ -113,7 +113,7 @@ begin
wait until rising_edge(clk); wait until rising_edge(clk);
assert w_in.ack = '0'; assert w_in.ack = '0';


-- Test write dword at 4 -- Test write dword at 4
w_out.stb <= '1'; w_out.stb <= '1';
w_out.sel <= "11110000"; w_out.sel <= "11110000";
w_out.adr <= to_adr(0); w_out.adr <= to_adr(0);
@ -126,7 +126,7 @@ begin
wait until rising_edge(clk); wait until rising_edge(clk);
assert w_in.ack = '0'; assert w_in.ack = '0';


-- Test read back -- Test read back
w_out.stb <= '1'; w_out.stb <= '1';
w_out.sel <= "11111111"; w_out.sel <= "11111111";
w_out.adr <= to_adr(0); w_out.adr <= to_adr(0);
@ -141,7 +141,7 @@ begin
wait until rising_edge(clk); wait until rising_edge(clk);
assert w_in.ack = '0'; assert w_in.ack = '0';


-- Test write qword at 8 -- Test write qword at 8
w_out.stb <= '1'; w_out.stb <= '1';
w_out.sel <= "11111111"; w_out.sel <= "11111111";
w_out.adr <= to_adr(8); w_out.adr <= to_adr(8);
@ -154,7 +154,7 @@ begin
wait until rising_edge(clk); wait until rising_edge(clk);
assert w_in.ack = '0'; assert w_in.ack = '0';


-- Test read back -- Test read back
w_out.stb <= '1'; w_out.stb <= '1';
w_out.sel <= "11111111"; w_out.sel <= "11111111";
w_out.adr <= to_adr(8); w_out.adr <= to_adr(8);

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