Anton Blanchard
5 years ago
committed by
GitHub
commit
1b6c246379
@ -0,0 +1,830 @@
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--
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-- Set associative dcache write-through
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--
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-- TODO (in no specific order):
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--
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-- * See list in icache.vhdl
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-- * Complete load misses on the cycle when WB data comes instead of
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-- at the end of line (this requires dealing with requests coming in
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-- while not idle...)
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-- * Load with update could use one less non-pipelined cycle by moving
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-- the register update to the pipeline bubble that exists when going
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-- back to the IDLE state.
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--
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.common.all;
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use work.helpers.all;
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use work.wishbone_types.all;
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entity dcache is
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generic (
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-- Line size in bytes
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LINE_SIZE : positive := 64;
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-- Number of lines in a set
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NUM_LINES : positive := 32;
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-- Number of ways
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NUM_WAYS : positive := 4
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);
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port (
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clk : in std_ulogic;
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rst : in std_ulogic;
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d_in : in Loadstore1ToDcacheType;
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d_out : out DcacheToWritebackType;
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stall_out : out std_ulogic;
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wishbone_out : out wishbone_master_out;
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wishbone_in : in wishbone_slave_out
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);
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end entity dcache;
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architecture rtl of dcache is
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function log2(i : natural) return integer is
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variable tmp : integer := i;
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variable ret : integer := 0;
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begin
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while tmp > 1 loop
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ret := ret + 1;
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tmp := tmp / 2;
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end loop;
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return ret;
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end function;
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function ispow2(i : integer) return boolean is
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begin
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if to_integer(to_unsigned(i, 32) and to_unsigned(i - 1, 32)) = 0 then
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return true;
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else
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return false;
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end if;
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end function;
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-- BRAM organisation: We never access more than wishbone_data_bits at
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-- a time so to save resources we make the array only that wide, and
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-- use consecutive indices for to make a cache "line"
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--
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-- ROW_SIZE is the width in bytes of the BRAM (based on WB, so 64-bits)
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constant ROW_SIZE : natural := wishbone_data_bits / 8;
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-- ROW_PER_LINE is the number of row (wishbone transactions) in a line
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constant ROW_PER_LINE : natural := LINE_SIZE / ROW_SIZE;
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-- BRAM_ROWS is the number of rows in BRAM needed to represent the full
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-- dcache
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constant BRAM_ROWS : natural := NUM_LINES * ROW_PER_LINE;
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-- Bit fields counts in the address
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-- ROW_BITS is the number of bits to select a row
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constant ROW_BITS : natural := log2(BRAM_ROWS);
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-- ROW_LINEBITS is the number of bits to select a row within a line
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constant ROW_LINEBITS : natural := log2(ROW_PER_LINE);
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-- LINE_OFF_BITS is the number of bits for the offset in a cache line
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constant LINE_OFF_BITS : natural := log2(LINE_SIZE);
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-- ROW_OFF_BITS is the number of bits for the offset in a row
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constant ROW_OFF_BITS : natural := log2(ROW_SIZE);
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-- INDEX_BITS is the number if bits to select a cache line
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constant INDEX_BITS : natural := log2(NUM_LINES);
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-- TAG_BITS is the number of bits of the tag part of the address
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constant TAG_BITS : natural := 64 - LINE_OFF_BITS - INDEX_BITS;
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-- WAY_BITS is the number of bits to select a way
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constant WAY_BITS : natural := log2(NUM_WAYS);
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-- Example of layout for 32 lines of 64 bytes:
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--
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-- .. tag |index| line |
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-- .. | row | |
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-- .. | |---| | ROW_LINEBITS (3)
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-- .. | |--- - --| LINE_OFF_BITS (6)
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-- .. | |- --| ROW_OFF_BITS (3)
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-- .. |----- ---| | ROW_BITS (8)
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-- .. |-----| | INDEX_BITS (5)
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-- .. --------| | TAG_BITS (53)
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subtype row_t is integer range 0 to BRAM_ROWS-1;
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subtype index_t is integer range 0 to NUM_LINES-1;
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subtype way_t is integer range 0 to NUM_WAYS-1;
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-- The cache data BRAM organized as described above for each way
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subtype cache_row_t is std_ulogic_vector(wishbone_data_bits-1 downto 0);
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-- The cache tags LUTRAM has a row per set. Vivado is a pain and will
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-- not handle a clean (commented) definition of the cache tags as a 3d
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-- memory. For now, work around it by putting all the tags
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subtype cache_tag_t is std_logic_vector(TAG_BITS-1 downto 0);
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-- type cache_tags_set_t is array(way_t) of cache_tag_t;
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-- type cache_tags_array_t is array(index_t) of cache_tags_set_t;
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constant TAG_RAM_WIDTH : natural := TAG_BITS * NUM_WAYS;
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subtype cache_tags_set_t is std_logic_vector(TAG_RAM_WIDTH-1 downto 0);
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type cache_tags_array_t is array(index_t) of cache_tags_set_t;
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-- The cache valid bits
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subtype cache_way_valids_t is std_ulogic_vector(NUM_WAYS-1 downto 0);
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type cache_valids_t is array(index_t) of cache_way_valids_t;
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-- Storage. Hopefully "cache_rows" is a BRAM, the rest is LUTs
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signal cache_tags : cache_tags_array_t;
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signal cache_valids : cache_valids_t;
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attribute ram_style : string;
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attribute ram_style of cache_tags : signal is "distributed";
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-- Type of operation on a "valid" input
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type op_t is (OP_NONE,
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OP_LOAD_HIT, -- Cache hit on load
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OP_LOAD_MISS, -- Load missing cache
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OP_LOAD_NC, -- Non-cachable load
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OP_BAD, -- BAD: Cache hit on NC load/store
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OP_STORE_HIT, -- Store hitting cache
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OP_STORE_MISS); -- Store missing cache
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-- Cache state machine
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type state_t is (IDLE, -- Normal load hit processing
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LOAD_UPDATE, -- Load with update extra cycle
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LOAD_UPDATE2, -- Load with update extra cycle
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RELOAD_WAIT_ACK, -- Cache reload wait ack
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STORE_WAIT_ACK, -- Store wait ack
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NC_LOAD_WAIT_ACK);-- Non-cachable load wait ack
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--
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-- Dcache operations:
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--
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-- In order to make timing, we use the BRAMs with an output buffer,
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-- which means that the BRAM output is delayed by an extra cycle.
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--
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-- Thus, the dcache has a 2-stage internal pipeline for cache hits
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-- with no stalls.
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--
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-- All other operations are handled via stalling in the first stage.
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--
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-- The second stage can thus complete a hit at the same time as the
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-- first stage emits a stall for a complex op.
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--
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-- First stage register, contains state for stage 1 of load hits
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-- and for the state machine used by all other operations
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--
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type reg_stage_1_t is record
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-- Latch the complete request from ls1
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req : Loadstore1ToDcacheType;
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-- Cache hit state
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hit_way : way_t;
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hit_load_valid : std_ulogic;
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-- Register update (load/store with update)
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update_valid : std_ulogic;
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-- Data buffer for "slow" read ops (load miss and NC loads).
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slow_data : std_ulogic_vector(63 downto 0);
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slow_valid : std_ulogic;
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-- Cache miss state (reload state machine)
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state : state_t;
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wb : wishbone_master_out;
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store_way : way_t;
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store_index : index_t;
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end record;
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signal r1 : reg_stage_1_t;
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-- Second stage register, only used for load hits
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--
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type reg_stage_2_t is record
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hit_way : way_t;
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hit_load_valid : std_ulogic;
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load_is_update : std_ulogic;
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load_reg : std_ulogic_vector(4 downto 0);
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data_shift : std_ulogic_vector(2 downto 0);
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length : std_ulogic_vector(3 downto 0);
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sign_extend : std_ulogic;
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byte_reverse : std_ulogic;
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end record;
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signal r2 : reg_stage_2_t;
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-- Async signals on incoming request
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signal req_index : index_t;
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signal req_row : row_t;
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signal req_hit_way : way_t;
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signal req_tag : cache_tag_t;
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signal req_op : op_t;
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-- Cache RAM interface
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type cache_ram_out_t is array(way_t) of cache_row_t;
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signal cache_out : cache_ram_out_t;
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-- PLRU output interface
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type plru_out_t is array(index_t) of std_ulogic_vector(WAY_BITS-1 downto 0);
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signal plru_victim : plru_out_t;
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signal replace_way : way_t;
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-- Wishbone read/write/cache write formatting signals
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signal bus_sel : wishbone_sel_type;
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signal store_data : wishbone_data_type;
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--
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-- Helper functions to decode incoming requests
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--
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-- Return the cache line index (tag index) for an address
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function get_index(addr: std_ulogic_vector(63 downto 0)) return index_t is
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begin
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return to_integer(unsigned(addr(63-TAG_BITS downto LINE_OFF_BITS)));
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end;
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-- Return the cache row index (data memory) for an address
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function get_row(addr: std_ulogic_vector(63 downto 0)) return row_t is
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begin
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return to_integer(unsigned(addr(63-TAG_BITS downto ROW_OFF_BITS)));
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end;
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-- Returns whether this is the last row of a line
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function is_last_row(addr: std_ulogic_vector(63 downto 0)) return boolean is
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constant ones : std_ulogic_vector(ROW_LINEBITS-1 downto 0) := (others => '1');
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begin
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return addr(LINE_OFF_BITS-1 downto ROW_OFF_BITS) = ones;
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end;
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-- Return the address of the next row in the current cache line
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function next_row_addr(addr: std_ulogic_vector(63 downto 0)) return std_ulogic_vector is
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variable row_idx : std_ulogic_vector(ROW_LINEBITS-1 downto 0);
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variable result : std_ulogic_vector(63 downto 0);
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begin
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-- Is there no simpler way in VHDL to generate that 3 bits adder ?
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row_idx := addr(LINE_OFF_BITS-1 downto ROW_OFF_BITS);
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row_idx := std_ulogic_vector(unsigned(row_idx) + 1);
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result := addr;
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result(LINE_OFF_BITS-1 downto ROW_OFF_BITS) := row_idx;
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return result;
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end;
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-- Get the tag value from the address
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function get_tag(addr: std_ulogic_vector(63 downto 0)) return cache_tag_t is
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begin
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return addr(63 downto 64-TAG_BITS);
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end;
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-- Read a tag from a tag memory row
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function read_tag(way: way_t; tagset: cache_tags_set_t) return cache_tag_t is
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begin
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return tagset((way+1) * TAG_BITS - 1 downto way * TAG_BITS);
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end;
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-- Write a tag to tag memory row
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procedure write_tag(way: in way_t; tagset: inout cache_tags_set_t;
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tag: cache_tag_t) is
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begin
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tagset((way+1) * TAG_BITS - 1 downto way * TAG_BITS) := tag;
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end;
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-- Generate byte enables from sizes
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function length_to_sel(length : in std_logic_vector(3 downto 0)) return std_ulogic_vector is
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begin
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case length is
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when "0001" =>
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return "00000001";
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when "0010" =>
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return "00000011";
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when "0100" =>
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return "00001111";
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when "1000" =>
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return "11111111";
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when others =>
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return "00000000";
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end case;
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end function length_to_sel;
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-- Calculate shift and byte enables for wishbone
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function wishbone_data_shift(address : in std_ulogic_vector(63 downto 0)) return natural is
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begin
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return to_integer(unsigned(address(2 downto 0))) * 8;
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end function wishbone_data_shift;
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function wishbone_data_sel(size : in std_logic_vector(3 downto 0);
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address : in std_logic_vector(63 downto 0))
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return std_ulogic_vector is
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begin
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return std_ulogic_vector(shift_left(unsigned(length_to_sel(size)),
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to_integer(unsigned(address(2 downto 0)))));
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end function wishbone_data_sel;
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begin
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assert LINE_SIZE mod ROW_SIZE = 0 report "LINE_SIZE not multiple of ROW_SIZE" severity FAILURE;
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assert ispow2(LINE_SIZE) report "LINE_SIZE not power of 2" severity FAILURE;
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assert ispow2(NUM_LINES) report "NUM_LINES not power of 2" severity FAILURE;
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assert ispow2(ROW_PER_LINE) report "ROW_PER_LINE not power of 2" severity FAILURE;
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assert (ROW_BITS = INDEX_BITS + ROW_LINEBITS)
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report "geometry bits don't add up" severity FAILURE;
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assert (LINE_OFF_BITS = ROW_OFF_BITS + ROW_LINEBITS)
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report "geometry bits don't add up" severity FAILURE;
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assert (64 = TAG_BITS + INDEX_BITS + LINE_OFF_BITS)
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report "geometry bits don't add up" severity FAILURE;
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assert (64 = TAG_BITS + ROW_BITS + ROW_OFF_BITS)
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report "geometry bits don't add up" severity FAILURE;
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assert (64 = wishbone_data_bits)
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report "Can't yet handle a wishbone width that isn't 64-bits" severity FAILURE;
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-- Generate PLRUs
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maybe_plrus: if NUM_WAYS > 1 generate
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begin
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plrus: for i in 0 to NUM_LINES-1 generate
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-- PLRU interface
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signal plru_acc : std_ulogic_vector(WAY_BITS-1 downto 0);
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signal plru_acc_en : std_ulogic;
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signal plru_out : std_ulogic_vector(WAY_BITS-1 downto 0);
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begin
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plru : entity work.plru
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generic map (
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BITS => WAY_BITS
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)
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port map (
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clk => clk,
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rst => rst,
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acc => plru_acc,
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acc_en => plru_acc_en,
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lru => plru_out
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);
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process(req_index, req_op, req_hit_way, plru_out)
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begin
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-- PLRU interface
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if (req_op = OP_LOAD_HIT or
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req_op = OP_STORE_HIT) and req_index = i then
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plru_acc_en <= '1';
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else
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plru_acc_en <= '0';
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end if;
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plru_acc <= std_ulogic_vector(to_unsigned(req_hit_way, WAY_BITS));
|
||||||
|
plru_victim(i) <= plru_out;
|
||||||
|
end process;
|
||||||
|
end generate;
|
||||||
|
end generate;
|
||||||
|
|
||||||
|
-- Cache request parsing and hit detection
|
||||||
|
dcache_request : process(all)
|
||||||
|
variable is_hit : std_ulogic;
|
||||||
|
variable hit_way : way_t;
|
||||||
|
variable op : op_t;
|
||||||
|
variable tmp : std_ulogic_vector(63 downto 0);
|
||||||
|
variable data : std_ulogic_vector(63 downto 0);
|
||||||
|
variable opsel : std_ulogic_vector(3 downto 0);
|
||||||
|
begin
|
||||||
|
-- Extract line, row and tag from request
|
||||||
|
req_index <= get_index(d_in.addr);
|
||||||
|
req_row <= get_row(d_in.addr);
|
||||||
|
req_tag <= get_tag(d_in.addr);
|
||||||
|
|
||||||
|
-- Test if pending request is a hit on any way
|
||||||
|
hit_way := 0;
|
||||||
|
is_hit := '0';
|
||||||
|
for i in way_t loop
|
||||||
|
if d_in.valid = '1' and cache_valids(req_index)(i) = '1' then
|
||||||
|
if read_tag(i, cache_tags(req_index)) = req_tag then
|
||||||
|
hit_way := i;
|
||||||
|
is_hit := '1';
|
||||||
|
end if;
|
||||||
|
end if;
|
||||||
|
end loop;
|
||||||
|
|
||||||
|
-- The way that matched on a hit
|
||||||
|
req_hit_way <= hit_way;
|
||||||
|
|
||||||
|
-- The way to replace on a miss
|
||||||
|
replace_way <= to_integer(unsigned(plru_victim(req_index)));
|
||||||
|
|
||||||
|
-- Combine the request and cache his status to decide what
|
||||||
|
-- operation needs to be done
|
||||||
|
--
|
||||||
|
opsel := d_in.valid & d_in.load & d_in.nc & is_hit;
|
||||||
|
case opsel is
|
||||||
|
when "1101" => op := OP_LOAD_HIT;
|
||||||
|
when "1100" => op := OP_LOAD_MISS;
|
||||||
|
when "1110" => op := OP_LOAD_NC;
|
||||||
|
when "1001" => op := OP_STORE_HIT;
|
||||||
|
when "1000" => op := OP_STORE_MISS;
|
||||||
|
when "1010" => op := OP_STORE_MISS;
|
||||||
|
when "1011" => op := OP_BAD;
|
||||||
|
when "1111" => op := OP_BAD;
|
||||||
|
when others => op := OP_NONE;
|
||||||
|
end case;
|
||||||
|
|
||||||
|
req_op <= op;
|
||||||
|
|
||||||
|
end process;
|
||||||
|
|
||||||
|
--
|
||||||
|
-- Misc signal assignments
|
||||||
|
--
|
||||||
|
|
||||||
|
-- Wire up wishbone request latch out of stage 1
|
||||||
|
wishbone_out <= r1.wb;
|
||||||
|
|
||||||
|
-- Wishbone & BRAM write data formatting for stores (most of it already
|
||||||
|
-- happens in loadstore1, this is the remaining data shifting)
|
||||||
|
--
|
||||||
|
store_data <= std_logic_vector(shift_left(unsigned(d_in.data),
|
||||||
|
wishbone_data_shift(d_in.addr)));
|
||||||
|
|
||||||
|
-- Wishbone read and write and BRAM write sel bits generation
|
||||||
|
bus_sel <= wishbone_data_sel(d_in.length, d_in.addr);
|
||||||
|
|
||||||
|
-- TODO: Generate errors
|
||||||
|
-- err_nc_collision <= '1' when req_op = OP_BAD else '0';
|
||||||
|
|
||||||
|
-- Generate stalls from stage 1 state machine
|
||||||
|
stall_out <= '1' when r1.state /= IDLE else '0';
|
||||||
|
|
||||||
|
-- Writeback (loads and reg updates) & completion control logic
|
||||||
|
--
|
||||||
|
writeback_control: process(all)
|
||||||
|
begin
|
||||||
|
|
||||||
|
-- The mux on d_out.write reg defaults to the normal load hit case.
|
||||||
|
d_out.write_enable <= '0';
|
||||||
|
d_out.valid <= '0';
|
||||||
|
d_out.write_reg <= r2.load_reg;
|
||||||
|
d_out.write_data <= cache_out(r2.hit_way);
|
||||||
|
d_out.write_len <= r2.length;
|
||||||
|
d_out.write_shift <= r2.data_shift;
|
||||||
|
d_out.sign_extend <= r2.sign_extend;
|
||||||
|
d_out.byte_reverse <= r2.byte_reverse;
|
||||||
|
d_out.second_word <= '0';
|
||||||
|
|
||||||
|
-- We have a valid load or store hit or we just completed a slow
|
||||||
|
-- op such as a load miss, a NC load or a store
|
||||||
|
--
|
||||||
|
-- Note: the load hit is delayed by one cycle. However it can still
|
||||||
|
-- not collide with r.slow_valid (well unless I miscalculated) because
|
||||||
|
-- slow_valid can only be set on a subsequent request and not on its
|
||||||
|
-- first cycle (the state machine must have advanced), which makes
|
||||||
|
-- slow_valid at least 2 cycles from the previous hit_load_valid.
|
||||||
|
--
|
||||||
|
|
||||||
|
-- Sanity: Only one of these must be set in any given cycle
|
||||||
|
assert (r1.update_valid and r2.hit_load_valid) /= '1' report
|
||||||
|
"unexpected hit_load_delayed collision with update_valid"
|
||||||
|
severity FAILURE;
|
||||||
|
assert (r1.slow_valid and r2.hit_load_valid) /= '1' report
|
||||||
|
"unexpected hit_load_delayed collision with slow_valid"
|
||||||
|
severity FAILURE;
|
||||||
|
assert (r1.slow_valid and r1.update_valid) /= '1' report
|
||||||
|
"unexpected update_valid collision with slow_valid"
|
||||||
|
severity FAILURE;
|
||||||
|
|
||||||
|
-- Delayed load hit case is the standard path
|
||||||
|
if r2.hit_load_valid = '1' then
|
||||||
|
d_out.write_enable <= '1';
|
||||||
|
|
||||||
|
-- If it's not a load with update, complete it now
|
||||||
|
if r2.load_is_update = '0' then
|
||||||
|
d_out.valid <= '1';
|
||||||
|
end if;
|
||||||
|
end if;
|
||||||
|
|
||||||
|
-- Slow ops (load miss, NC, stores)
|
||||||
|
if r1.slow_valid = '1' then
|
||||||
|
-- If it's a load, enable register writeback and switch
|
||||||
|
-- mux accordingly
|
||||||
|
--
|
||||||
|
if r1.req.load then
|
||||||
|
d_out.write_reg <= r1.req.write_reg;
|
||||||
|
d_out.write_enable <= '1';
|
||||||
|
|
||||||
|
-- Read data comes from the slow data latch, formatter
|
||||||
|
-- from the latched request.
|
||||||
|
--
|
||||||
|
d_out.write_data <= r1.slow_data;
|
||||||
|
d_out.write_shift <= r1.req.addr(2 downto 0);
|
||||||
|
d_out.sign_extend <= r1.req.sign_extend;
|
||||||
|
d_out.byte_reverse <= r1.req.byte_reverse;
|
||||||
|
d_out.write_len <= r1.req.length;
|
||||||
|
end if;
|
||||||
|
|
||||||
|
-- If it's a store or a non-update load form, complete now
|
||||||
|
if r1.req.load = '0' or r1.req.update = '0' then
|
||||||
|
d_out.valid <= '1';
|
||||||
|
end if;
|
||||||
|
end if;
|
||||||
|
|
||||||
|
-- We have a register update to do.
|
||||||
|
if r1.update_valid = '1' then
|
||||||
|
d_out.write_enable <= '1';
|
||||||
|
d_out.write_reg <= r1.req.update_reg;
|
||||||
|
|
||||||
|
-- Change the read data mux to the address that's going into
|
||||||
|
-- the register and the formatter does nothing.
|
||||||
|
--
|
||||||
|
d_out.write_data <= r1.req.addr;
|
||||||
|
d_out.write_shift <= "000";
|
||||||
|
d_out.write_len <= "1000";
|
||||||
|
d_out.sign_extend <= '0';
|
||||||
|
d_out.byte_reverse <= '0';
|
||||||
|
|
||||||
|
-- If it was a load, this completes the operation (load with
|
||||||
|
-- update case).
|
||||||
|
--
|
||||||
|
if r1.req.load = '1' then
|
||||||
|
d_out.valid <= '1';
|
||||||
|
end if;
|
||||||
|
end if;
|
||||||
|
|
||||||
|
end process;
|
||||||
|
|
||||||
|
--
|
||||||
|
-- Generate a cache RAM for each way. This handles the normal
|
||||||
|
-- reads, writes from reloads and the special store-hit update
|
||||||
|
-- path as well.
|
||||||
|
--
|
||||||
|
-- Note: the BRAMs have an extra read buffer, meaning the output
|
||||||
|
-- is pipelined an extra cycle. This differs from the
|
||||||
|
-- icache. The writeback logic needs to take that into
|
||||||
|
-- account by using 1-cycle delayed signals for load hits.
|
||||||
|
--
|
||||||
|
rams: for i in 0 to NUM_WAYS-1 generate
|
||||||
|
signal do_read : std_ulogic;
|
||||||
|
signal rd_addr : std_ulogic_vector(ROW_BITS-1 downto 0);
|
||||||
|
signal do_write : std_ulogic;
|
||||||
|
signal wr_addr : std_ulogic_vector(ROW_BITS-1 downto 0);
|
||||||
|
signal wr_data : std_ulogic_vector(wishbone_data_bits-1 downto 0);
|
||||||
|
signal wr_sel : std_ulogic_vector(ROW_SIZE-1 downto 0);
|
||||||
|
signal dout : cache_row_t;
|
||||||
|
begin
|
||||||
|
way: entity work.cache_ram
|
||||||
|
generic map (
|
||||||
|
ROW_BITS => ROW_BITS,
|
||||||
|
WIDTH => wishbone_data_bits,
|
||||||
|
ADD_BUF => true
|
||||||
|
)
|
||||||
|
port map (
|
||||||
|
clk => clk,
|
||||||
|
rd_en => do_read,
|
||||||
|
rd_addr => rd_addr,
|
||||||
|
rd_data => dout,
|
||||||
|
wr_en => do_write,
|
||||||
|
wr_sel => wr_sel,
|
||||||
|
wr_addr => wr_addr,
|
||||||
|
wr_data => wr_data
|
||||||
|
);
|
||||||
|
process(all)
|
||||||
|
begin
|
||||||
|
-- Cache hit reads
|
||||||
|
do_read <= '1';
|
||||||
|
rd_addr <= std_ulogic_vector(to_unsigned(req_row, ROW_BITS));
|
||||||
|
cache_out(i) <= dout;
|
||||||
|
|
||||||
|
-- Write mux:
|
||||||
|
--
|
||||||
|
-- Defaults to wishbone read responses (cache refill),
|
||||||
|
--
|
||||||
|
-- For timing, the mux on wr_data/sel/addr is not dependent on anything
|
||||||
|
-- other than the current state. Only the do_write signal is.
|
||||||
|
--
|
||||||
|
if r1.state = IDLE then
|
||||||
|
-- When IDLE, the only write path is the store-hit update case
|
||||||
|
wr_addr <= std_ulogic_vector(to_unsigned(req_row, ROW_BITS));
|
||||||
|
wr_data <= store_data;
|
||||||
|
wr_sel <= bus_sel;
|
||||||
|
else
|
||||||
|
-- Otherwise, we might be doing a reload
|
||||||
|
wr_data <= wishbone_in.dat;
|
||||||
|
wr_sel <= (others => '1');
|
||||||
|
wr_addr <= std_ulogic_vector(to_unsigned(get_row(r1.wb.adr), ROW_BITS));
|
||||||
|
end if;
|
||||||
|
|
||||||
|
-- The two actual write cases here
|
||||||
|
do_write <= '0';
|
||||||
|
if r1.state = RELOAD_WAIT_ACK and wishbone_in.ack = '1' and r1.store_way = i then
|
||||||
|
do_write <= '1';
|
||||||
|
end if;
|
||||||
|
if req_op = OP_STORE_HIT and req_hit_way = i then
|
||||||
|
assert r1.state /= RELOAD_WAIT_ACK report "Store hit while in state:" &
|
||||||
|
state_t'image(r1.state)
|
||||||
|
severity FAILURE;
|
||||||
|
do_write <= '1';
|
||||||
|
end if;
|
||||||
|
end process;
|
||||||
|
end generate;
|
||||||
|
|
||||||
|
--
|
||||||
|
-- Cache hit synchronous machine for the easy case. This handles
|
||||||
|
-- non-update form load hits and stage 1 to stage 2 transfers
|
||||||
|
--
|
||||||
|
dcache_fast_hit : process(clk)
|
||||||
|
begin
|
||||||
|
if rising_edge(clk) then
|
||||||
|
-- stage 1 -> stage 2
|
||||||
|
r2.hit_load_valid <= r1.hit_load_valid;
|
||||||
|
r2.hit_way <= r1.hit_way;
|
||||||
|
r2.load_is_update <= r1.req.update;
|
||||||
|
r2.load_reg <= r1.req.write_reg;
|
||||||
|
r2.data_shift <= r1.req.addr(2 downto 0);
|
||||||
|
r2.length <= r1.req.length;
|
||||||
|
r2.sign_extend <= r1.req.sign_extend;
|
||||||
|
r2.byte_reverse <= r1.req.byte_reverse;
|
||||||
|
|
||||||
|
-- If we have a request incoming, we have to latch it as d_in.valid
|
||||||
|
-- is only set for a single cycle. It's up to the control logic to
|
||||||
|
-- ensure we don't override an uncompleted request (for now we are
|
||||||
|
-- single issue on load/stores so we are fine, later, we can generate
|
||||||
|
-- a stall output if necessary).
|
||||||
|
|
||||||
|
if d_in.valid = '1' then
|
||||||
|
r1.req <= d_in;
|
||||||
|
|
||||||
|
report "op:" & op_t'image(req_op) &
|
||||||
|
" addr:" & to_hstring(d_in.addr) &
|
||||||
|
" upd:" & std_ulogic'image(d_in.update) &
|
||||||
|
" nc:" & std_ulogic'image(d_in.nc) &
|
||||||
|
" reg:" & to_hstring(d_in.write_reg) &
|
||||||
|
" idx:" & integer'image(req_index) &
|
||||||
|
" tag:" & to_hstring(req_tag) &
|
||||||
|
" way: " & integer'image(req_hit_way);
|
||||||
|
end if;
|
||||||
|
|
||||||
|
-- Fast path for load/store hits. Set signals for the writeback controls.
|
||||||
|
if req_op = OP_LOAD_HIT then
|
||||||
|
r1.hit_way <= req_hit_way;
|
||||||
|
r1.hit_load_valid <= '1';
|
||||||
|
else
|
||||||
|
r1.hit_load_valid <= '0';
|
||||||
|
end if;
|
||||||
|
end if;
|
||||||
|
end process;
|
||||||
|
|
||||||
|
--
|
||||||
|
-- Every other case is handled by this stage machine:
|
||||||
|
--
|
||||||
|
-- * Cache load miss/reload (in conjunction with "rams")
|
||||||
|
-- * Load hits for update forms
|
||||||
|
-- * Load hits for non-cachable forms
|
||||||
|
-- * Stores (the collision case is handled in "rams")
|
||||||
|
--
|
||||||
|
-- All wishbone requests generation is done here. This machine
|
||||||
|
-- operates at stage 1.
|
||||||
|
--
|
||||||
|
dcache_slow : process(clk)
|
||||||
|
variable tagset : cache_tags_set_t;
|
||||||
|
begin
|
||||||
|
if rising_edge(clk) then
|
||||||
|
-- On reset, clear all valid bits to force misses
|
||||||
|
if rst = '1' then
|
||||||
|
for i in index_t loop
|
||||||
|
cache_valids(i) <= (others => '0');
|
||||||
|
end loop;
|
||||||
|
r1.state <= IDLE;
|
||||||
|
r1.slow_valid <= '0';
|
||||||
|
r1.update_valid <= '0';
|
||||||
|
r1.wb.cyc <= '0';
|
||||||
|
r1.wb.stb <= '0';
|
||||||
|
|
||||||
|
-- Not useful normally but helps avoiding tons of sim warnings
|
||||||
|
r1.wb.adr <= (others => '0');
|
||||||
|
else
|
||||||
|
-- One cycle pulses reset
|
||||||
|
r1.slow_valid <= '0';
|
||||||
|
r1.update_valid <= '0';
|
||||||
|
|
||||||
|
-- We cannot currently process a new request when not idle
|
||||||
|
assert req_op = OP_NONE or r1.state = IDLE report "request " &
|
||||||
|
op_t'image(req_op) & " while in state " & state_t'image(r1.state)
|
||||||
|
severity FAILURE;
|
||||||
|
|
||||||
|
-- Main state machine
|
||||||
|
case r1.state is
|
||||||
|
when IDLE =>
|
||||||
|
case req_op is
|
||||||
|
when OP_LOAD_HIT =>
|
||||||
|
-- We have a load with update hit, we need the delayed update cycle
|
||||||
|
if d_in.update = '1' then
|
||||||
|
r1.state <= LOAD_UPDATE;
|
||||||
|
end if;
|
||||||
|
|
||||||
|
when OP_LOAD_MISS =>
|
||||||
|
-- Normal load cache miss, start the reload machine
|
||||||
|
--
|
||||||
|
report "cache miss addr:" & to_hstring(d_in.addr) &
|
||||||
|
" idx:" & integer'image(req_index) &
|
||||||
|
" way:" & integer'image(replace_way) &
|
||||||
|
" tag:" & to_hstring(req_tag);
|
||||||
|
|
||||||
|
-- Force misses on that way while reloading that line
|
||||||
|
cache_valids(req_index)(replace_way) <= '0';
|
||||||
|
|
||||||
|
-- Store new tag in selected way
|
||||||
|
for i in 0 to NUM_WAYS-1 loop
|
||||||
|
if i = replace_way then
|
||||||
|
tagset := cache_tags(req_index);
|
||||||
|
write_tag(i, tagset, req_tag);
|
||||||
|
cache_tags(req_index) <= tagset;
|
||||||
|
end if;
|
||||||
|
end loop;
|
||||||
|
|
||||||
|
-- Keep track of our index and way for subsequent stores.
|
||||||
|
r1.store_index <= req_index;
|
||||||
|
r1.store_way <= replace_way;
|
||||||
|
|
||||||
|
-- Prep for first wishbone read. We calculate the address of
|
||||||
|
-- the start of the cache line
|
||||||
|
--
|
||||||
|
r1.wb.adr <= d_in.addr(63 downto LINE_OFF_BITS) &
|
||||||
|
(LINE_OFF_BITS-1 downto 0 => '0');
|
||||||
|
r1.wb.sel <= (others => '1');
|
||||||
|
r1.wb.we <= '0';
|
||||||
|
r1.wb.cyc <= '1';
|
||||||
|
r1.wb.stb <= '1';
|
||||||
|
r1.state <= RELOAD_WAIT_ACK;
|
||||||
|
|
||||||
|
when OP_LOAD_NC =>
|
||||||
|
r1.wb.sel <= bus_sel;
|
||||||
|
r1.wb.adr <= d_in.addr(63 downto 3) & "000";
|
||||||
|
r1.wb.cyc <= '1';
|
||||||
|
r1.wb.stb <= '1';
|
||||||
|
r1.wb.we <= '0';
|
||||||
|
r1.state <= NC_LOAD_WAIT_ACK;
|
||||||
|
|
||||||
|
when OP_STORE_HIT | OP_STORE_MISS =>
|
||||||
|
-- For store-with-update do the register update
|
||||||
|
if d_in.update = '1' then
|
||||||
|
r1.update_valid <= '1';
|
||||||
|
end if;
|
||||||
|
r1.wb.sel <= bus_sel;
|
||||||
|
r1.wb.adr <= d_in.addr(63 downto 3) & "000";
|
||||||
|
r1.wb.dat <= store_data;
|
||||||
|
r1.wb.cyc <= '1';
|
||||||
|
r1.wb.stb <= '1';
|
||||||
|
r1.wb.we <= '1';
|
||||||
|
r1.state <= STORE_WAIT_ACK;
|
||||||
|
|
||||||
|
-- OP_NONE and OP_BAD do nothing
|
||||||
|
when OP_NONE =>
|
||||||
|
when OP_BAD =>
|
||||||
|
end case;
|
||||||
|
|
||||||
|
when RELOAD_WAIT_ACK =>
|
||||||
|
if wishbone_in.ack = '1' then
|
||||||
|
-- Is this the data we were looking for ? Latch it so
|
||||||
|
-- we can respond later. We don't currently complete the
|
||||||
|
-- pending miss request immediately, we wait for the
|
||||||
|
-- whole line to be loaded. The reason is that if we
|
||||||
|
-- did, we would potentially get new requests in while
|
||||||
|
-- not idle, which we don't currently know how to deal
|
||||||
|
-- with.
|
||||||
|
--
|
||||||
|
if r1.wb.adr(LINE_OFF_BITS-1 downto ROW_OFF_BITS) =
|
||||||
|
r1.req.addr(LINE_OFF_BITS-1 downto ROW_OFF_BITS) then
|
||||||
|
r1.slow_data <= wishbone_in.dat;
|
||||||
|
end if;
|
||||||
|
|
||||||
|
-- That was the last word ? We are done
|
||||||
|
if is_last_row(r1.wb.adr) then
|
||||||
|
cache_valids(r1.store_index)(r1.store_way) <= '1';
|
||||||
|
r1.wb.cyc <= '0';
|
||||||
|
r1.wb.stb <= '0';
|
||||||
|
|
||||||
|
-- Complete the load that missed. For load with update
|
||||||
|
-- we also need to do the deferred update cycle.
|
||||||
|
--
|
||||||
|
r1.slow_valid <= '1';
|
||||||
|
if r1.req.load = '1' and r1.req.update = '1' then
|
||||||
|
r1.state <= LOAD_UPDATE;
|
||||||
|
report "completing miss with load-update !";
|
||||||
|
else
|
||||||
|
r1.state <= IDLE;
|
||||||
|
report "completing miss !";
|
||||||
|
end if;
|
||||||
|
else
|
||||||
|
-- Otherwise, calculate the next row address
|
||||||
|
r1.wb.adr <= next_row_addr(r1.wb.adr);
|
||||||
|
end if;
|
||||||
|
end if;
|
||||||
|
|
||||||
|
when LOAD_UPDATE =>
|
||||||
|
-- We need the extra cycle to complete a load with update
|
||||||
|
r1.state <= LOAD_UPDATE2;
|
||||||
|
when LOAD_UPDATE2 =>
|
||||||
|
-- We need the extra cycle to complete a load with update
|
||||||
|
r1.update_valid <= '1';
|
||||||
|
r1.state <= IDLE;
|
||||||
|
|
||||||
|
when STORE_WAIT_ACK | NC_LOAD_WAIT_ACK =>
|
||||||
|
if wishbone_in.ack = '1' then
|
||||||
|
if r1.state = NC_LOAD_WAIT_ACK then
|
||||||
|
r1.slow_data <= wishbone_in.dat;
|
||||||
|
end if;
|
||||||
|
r1.slow_valid <= '1';
|
||||||
|
r1.wb.cyc <= '0';
|
||||||
|
r1.wb.stb <= '0';
|
||||||
|
r1.state <= IDLE;
|
||||||
|
end if;
|
||||||
|
end case;
|
||||||
|
end if;
|
||||||
|
end if;
|
||||||
|
end process;
|
||||||
|
end;
|
||||||
@ -0,0 +1,139 @@
|
|||||||
|
library ieee;
|
||||||
|
use ieee.std_logic_1164.all;
|
||||||
|
|
||||||
|
library work;
|
||||||
|
use work.common.all;
|
||||||
|
use work.wishbone_types.all;
|
||||||
|
|
||||||
|
entity dcache_tb is
|
||||||
|
end dcache_tb;
|
||||||
|
|
||||||
|
architecture behave of dcache_tb is
|
||||||
|
signal clk : std_ulogic;
|
||||||
|
signal rst : std_ulogic;
|
||||||
|
|
||||||
|
signal d_in : Loadstore1ToDcacheType;
|
||||||
|
signal d_out : DcacheToWritebackType;
|
||||||
|
|
||||||
|
signal wb_bram_in : wishbone_master_out;
|
||||||
|
signal wb_bram_out : wishbone_slave_out;
|
||||||
|
|
||||||
|
constant clk_period : time := 10 ns;
|
||||||
|
begin
|
||||||
|
dcache0: entity work.dcache
|
||||||
|
generic map(
|
||||||
|
LINE_SIZE => 64,
|
||||||
|
NUM_LINES => 4
|
||||||
|
)
|
||||||
|
port map(
|
||||||
|
clk => clk,
|
||||||
|
rst => rst,
|
||||||
|
d_in => d_in,
|
||||||
|
d_out => d_out,
|
||||||
|
wishbone_out => wb_bram_in,
|
||||||
|
wishbone_in => wb_bram_out
|
||||||
|
);
|
||||||
|
|
||||||
|
-- BRAM Memory slave
|
||||||
|
bram0: entity work.mw_soc_memory
|
||||||
|
generic map(
|
||||||
|
MEMORY_SIZE => 128,
|
||||||
|
RAM_INIT_FILE => "icache_test.bin"
|
||||||
|
)
|
||||||
|
port map(
|
||||||
|
clk => clk,
|
||||||
|
rst => rst,
|
||||||
|
wishbone_in => wb_bram_in,
|
||||||
|
wishbone_out => wb_bram_out
|
||||||
|
);
|
||||||
|
|
||||||
|
clk_process: process
|
||||||
|
begin
|
||||||
|
clk <= '0';
|
||||||
|
wait for clk_period/2;
|
||||||
|
clk <= '1';
|
||||||
|
wait for clk_period/2;
|
||||||
|
end process;
|
||||||
|
|
||||||
|
rst_process: process
|
||||||
|
begin
|
||||||
|
rst <= '1';
|
||||||
|
wait for 2*clk_period;
|
||||||
|
rst <= '0';
|
||||||
|
wait;
|
||||||
|
end process;
|
||||||
|
|
||||||
|
stim: process
|
||||||
|
begin
|
||||||
|
-- Clear stuff
|
||||||
|
d_in.valid <= '0';
|
||||||
|
d_in.load <= '0';
|
||||||
|
d_in.nc <= '0';
|
||||||
|
d_in.addr <= (others => '0');
|
||||||
|
d_in.data <= (others => '0');
|
||||||
|
d_in.write_reg <= (others => '0');
|
||||||
|
d_in.length <= (others => '0');
|
||||||
|
d_in.byte_reverse <= '0';
|
||||||
|
d_in.sign_extend <= '0';
|
||||||
|
d_in.update <= '0';
|
||||||
|
d_in.update_reg <= (others => '0');
|
||||||
|
|
||||||
|
wait for 4*clk_period;
|
||||||
|
wait until rising_edge(clk);
|
||||||
|
|
||||||
|
-- Cacheable read of address 4
|
||||||
|
d_in.load <= '1';
|
||||||
|
d_in.nc <= '0';
|
||||||
|
d_in.addr <= x"0000000000000004";
|
||||||
|
d_in.valid <= '1';
|
||||||
|
wait until rising_edge(clk);
|
||||||
|
d_in.valid <= '0';
|
||||||
|
|
||||||
|
wait until rising_edge(clk) and d_out.write_enable = '1';
|
||||||
|
assert d_out.valid = '1';
|
||||||
|
assert d_out.write_data = x"0000000100000000"
|
||||||
|
report "data @" & to_hstring(d_in.addr) &
|
||||||
|
"=" & to_hstring(d_out.write_data) &
|
||||||
|
" expected 0000000100000000"
|
||||||
|
severity failure;
|
||||||
|
-- wait for clk_period;
|
||||||
|
|
||||||
|
-- Cacheable read of address 30
|
||||||
|
d_in.load <= '1';
|
||||||
|
d_in.nc <= '0';
|
||||||
|
d_in.addr <= x"0000000000000030";
|
||||||
|
d_in.valid <= '1';
|
||||||
|
wait until rising_edge(clk);
|
||||||
|
d_in.valid <= '0';
|
||||||
|
|
||||||
|
wait until rising_edge(clk) and d_out.write_enable = '1';
|
||||||
|
assert d_out.valid = '1';
|
||||||
|
assert d_out.write_data = x"0000000D0000000C"
|
||||||
|
report "data @" & to_hstring(d_in.addr) &
|
||||||
|
"=" & to_hstring(d_out.write_data) &
|
||||||
|
" expected 0000000D0000000C"
|
||||||
|
severity failure;
|
||||||
|
|
||||||
|
-- Non-cacheable read of address 100
|
||||||
|
d_in.load <= '1';
|
||||||
|
d_in.nc <= '1';
|
||||||
|
d_in.addr <= x"0000000000000100";
|
||||||
|
d_in.valid <= '1';
|
||||||
|
wait until rising_edge(clk);
|
||||||
|
d_in.valid <= '0';
|
||||||
|
|
||||||
|
wait until rising_edge(clk) and d_out.write_enable = '1';
|
||||||
|
assert d_out.valid = '1';
|
||||||
|
assert d_out.write_data = x"0000004100000040"
|
||||||
|
report "data @" & to_hstring(d_in.addr) &
|
||||||
|
"=" & to_hstring(d_out.write_data) &
|
||||||
|
" expected 0000004100000040"
|
||||||
|
severity failure;
|
||||||
|
|
||||||
|
wait for clk_period*4;
|
||||||
|
|
||||||
|
assert false report "end of test" severity failure;
|
||||||
|
wait;
|
||||||
|
|
||||||
|
end process;
|
||||||
|
end;
|
||||||
@ -1,148 +0,0 @@
|
|||||||
library ieee;
|
|
||||||
use ieee.std_logic_1164.all;
|
|
||||||
use ieee.numeric_std.all;
|
|
||||||
|
|
||||||
library work;
|
|
||||||
use work.common.all;
|
|
||||||
use work.helpers.all;
|
|
||||||
use work.wishbone_types.all;
|
|
||||||
|
|
||||||
-- 2 cycle LSU
|
|
||||||
-- In this cycle we read or write any data and do sign extension and update if required.
|
|
||||||
|
|
||||||
entity loadstore2 is
|
|
||||||
port (
|
|
||||||
clk : in std_ulogic;
|
|
||||||
|
|
||||||
l_in : in Loadstore1ToLoadstore2Type;
|
|
||||||
w_out : out Loadstore2ToWritebackType;
|
|
||||||
|
|
||||||
m_in : in wishbone_slave_out;
|
|
||||||
m_out : out wishbone_master_out
|
|
||||||
);
|
|
||||||
end loadstore2;
|
|
||||||
|
|
||||||
architecture behave of loadstore2 is
|
|
||||||
signal l_saved : Loadstore1ToLoadstore2Type;
|
|
||||||
signal w_tmp : Loadstore2ToWritebackType;
|
|
||||||
signal m_tmp : wishbone_master_out;
|
|
||||||
signal dlength : std_ulogic_vector(3 downto 0);
|
|
||||||
|
|
||||||
type state_t is (IDLE, WAITING_FOR_READ_ACK, WAITING_FOR_WRITE_ACK);
|
|
||||||
signal state : state_t := IDLE;
|
|
||||||
|
|
||||||
function length_to_sel(length : in std_logic_vector(3 downto 0)) return std_ulogic_vector is
|
|
||||||
begin
|
|
||||||
case length is
|
|
||||||
when "0001" =>
|
|
||||||
return "00000001";
|
|
||||||
when "0010" =>
|
|
||||||
return "00000011";
|
|
||||||
when "0100" =>
|
|
||||||
return "00001111";
|
|
||||||
when "1000" =>
|
|
||||||
return "11111111";
|
|
||||||
when others =>
|
|
||||||
return "00000000";
|
|
||||||
end case;
|
|
||||||
end function length_to_sel;
|
|
||||||
|
|
||||||
function wishbone_data_shift(address : in std_ulogic_vector(63 downto 0)) return natural is
|
|
||||||
begin
|
|
||||||
return to_integer(unsigned(address(2 downto 0))) * 8;
|
|
||||||
end function wishbone_data_shift;
|
|
||||||
|
|
||||||
function wishbone_data_sel(size : in std_logic_vector(3 downto 0); address : in std_logic_vector(63 downto 0)) return std_ulogic_vector is
|
|
||||||
begin
|
|
||||||
return std_ulogic_vector(shift_left(unsigned(length_to_sel(size)), to_integer(unsigned(address(2 downto 0)))));
|
|
||||||
end function wishbone_data_sel;
|
|
||||||
begin
|
|
||||||
|
|
||||||
w_out <= w_tmp;
|
|
||||||
m_out <= m_tmp;
|
|
||||||
|
|
||||||
loadstore2_0: process(clk)
|
|
||||||
begin
|
|
||||||
if rising_edge(clk) then
|
|
||||||
|
|
||||||
w_tmp.valid <= '0';
|
|
||||||
w_tmp.write_enable <= '0';
|
|
||||||
w_tmp.write_reg <= (others => '0');
|
|
||||||
w_tmp.write_len <= "1000";
|
|
||||||
w_tmp.write_shift <= "000";
|
|
||||||
w_tmp.sign_extend <= '0';
|
|
||||||
w_tmp.byte_reverse <= '0';
|
|
||||||
w_tmp.second_word <= '0';
|
|
||||||
|
|
||||||
l_saved <= l_saved;
|
|
||||||
|
|
||||||
case_0: case state is
|
|
||||||
when IDLE =>
|
|
||||||
if l_in.valid = '1' then
|
|
||||||
m_tmp <= wishbone_master_out_init;
|
|
||||||
|
|
||||||
m_tmp.sel <= wishbone_data_sel(l_in.length, l_in.addr);
|
|
||||||
m_tmp.adr <= l_in.addr(63 downto 3) & "000";
|
|
||||||
m_tmp.cyc <= '1';
|
|
||||||
m_tmp.stb <= '1';
|
|
||||||
|
|
||||||
l_saved <= l_in;
|
|
||||||
|
|
||||||
if l_in.load = '1' then
|
|
||||||
m_tmp.we <= '0';
|
|
||||||
|
|
||||||
-- Load with update instructions write two GPR destinations.
|
|
||||||
-- We don't want the expense of two write ports, so make it
|
|
||||||
-- single in the pipeline and write back the update GPR now
|
|
||||||
-- and the load once we get the data back. We'll have to
|
|
||||||
-- revisit this when loads can take exceptions.
|
|
||||||
if l_in.update = '1' then
|
|
||||||
w_tmp.write_enable <= '1';
|
|
||||||
w_tmp.write_reg <= l_in.update_reg;
|
|
||||||
w_tmp.write_data <= l_in.addr;
|
|
||||||
end if;
|
|
||||||
|
|
||||||
state <= WAITING_FOR_READ_ACK;
|
|
||||||
else
|
|
||||||
m_tmp.we <= '1';
|
|
||||||
|
|
||||||
m_tmp.dat <= std_logic_vector(shift_left(unsigned(l_in.data), wishbone_data_shift(l_in.addr)));
|
|
||||||
|
|
||||||
assert l_in.sign_extend = '0' report "sign extension doesn't make sense for stores" severity failure;
|
|
||||||
|
|
||||||
state <= WAITING_FOR_WRITE_ACK;
|
|
||||||
end if;
|
|
||||||
end if;
|
|
||||||
|
|
||||||
when WAITING_FOR_READ_ACK =>
|
|
||||||
if m_in.ack = '1' then
|
|
||||||
-- write data to register file
|
|
||||||
w_tmp.valid <= '1';
|
|
||||||
w_tmp.write_enable <= '1';
|
|
||||||
w_tmp.write_data <= m_in.dat;
|
|
||||||
w_tmp.write_reg <= l_saved.write_reg;
|
|
||||||
w_tmp.write_len <= l_saved.length;
|
|
||||||
w_tmp.write_shift <= l_saved.addr(2 downto 0);
|
|
||||||
w_tmp.sign_extend <= l_saved.sign_extend;
|
|
||||||
w_tmp.byte_reverse <= l_saved.byte_reverse;
|
|
||||||
|
|
||||||
m_tmp <= wishbone_master_out_init;
|
|
||||||
state <= IDLE;
|
|
||||||
end if;
|
|
||||||
|
|
||||||
when WAITING_FOR_WRITE_ACK =>
|
|
||||||
if m_in.ack = '1' then
|
|
||||||
w_tmp.valid <= '1';
|
|
||||||
if l_saved.update = '1' then
|
|
||||||
w_tmp.write_enable <= '1';
|
|
||||||
w_tmp.write_reg <= l_saved.update_reg;
|
|
||||||
w_tmp.write_data <= l_saved.addr;
|
|
||||||
end if;
|
|
||||||
|
|
||||||
m_tmp <= wishbone_master_out_init;
|
|
||||||
state <= IDLE;
|
|
||||||
end if;
|
|
||||||
end case;
|
|
||||||
end if;
|
|
||||||
end process;
|
|
||||||
end;
|
|
||||||
Loading…
Reference in New Issue