VUnit: style

Signed-off-by: umarcor <unai.martinezcorral@ehu.eus>
pull/301/head
umarcor 3 years ago
parent 2031c6d2d2
commit 178c2a7da3

@ -1,28 +1,23 @@
from pathlib import Path from pathlib import Path
from vunit import VUnit from vunit import VUnit


prj = VUnit.from_argv() ROOT = Path(__file__).parent
prj.add_osvvm()
root = Path(__file__).parent


lib = prj.add_library("lib") PRJ = VUnit.from_argv()
lib.add_source_files(root / "litedram" / "extras" / "*.vhdl") PRJ.add_osvvm()
lib.add_source_files(root / "litedram" / "generated" / "sim" / "*.vhdl")


# Use multiply.vhd and not xilinx-mult.vhd. Use VHDL-based random. PRJ.add_library("lib").add_source_files([
vhdl_files = root.glob("*.vhdl") ROOT / "litedram" / "extras" / "*.vhdl",
vhdl_files = [ ROOT / "litedram" / "generated" / "sim" / "*.vhdl"
] + [
src_file src_file
for src_file in vhdl_files for src_file in ROOT.glob("*.vhdl")
if ("xilinx-mult" not in src_file) # Use multiply.vhd and not xilinx-mult.vhd. Use VHDL-based random.
and ("foreign_random" not in src_file) if not any(exclude in str(src_file) for exclude in ["xilinx-mult", "foreign_random", "nonrandom"])
and ("nonrandom" not in src_file) ])
]
lib.add_source_files(vhdl_files)


unisim = prj.add_library("unisim") PRJ.add_library("unisim").add_source_files(ROOT / "sim-unisim" / "*.vhdl")
unisim.add_source_files(root / "sim-unisim" / "*.vhdl")


prj.set_sim_option("disable_ieee_warnings", True) PRJ.set_sim_option("disable_ieee_warnings", True)


prj.main() PRJ.main()

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