Branches - microwatt - OpenPOWER Foundation Git System

master

8be7c53ea0 · arty a7: Fix build error with Vivado (#429) · Updated 2 weeks ago

less-fpga-init ebdddcc402 · Remove some FPGA style signal inits · Updated 2 years ago	234 0	Included
caravel-mpw6-20220530 2083bc3ed0 · ASIC: Fix multiplier power · Updated 2 years ago	238 15
caravel-mpw5-20220323 907c833521 · Move register stage back after the RAM · Updated 2 years ago	238 13
caravel-mpw5-20220322 5c40143754 · Add a script to post process the Microwatt verilog for caravel · Updated 2 years ago	238 12
alt-reset-address 948f6f43a7 · Allow ALT_RESET_ADDRESS to be overridden · Updated 2 years ago	237 0	Included
log2ceil-issue b5accb78b2 · wishbone_bram_wrapper ram_addr_bits is 1 bit off · Updated 2 years ago	239 0	Included
fpu-constant 50b4cb9423 · fpu: Make inverse_table a constant · Updated 2 years ago	245 0	Included
asic-3 11c5ac68e8 · Fix caravel script · Updated 2 years ago	268 16
boxarty-20211011 ceb15d3ca8 · Hack to test under verilator · Updated 3 years ago	291 2
icbi-issue 2d142a6c01 · tests/misc: Add a store/dcbz test · Updated 3 years ago	296 0	Included
orange-crab-freq 06266fe84a · Orange Crab is 48MHz not 50MHz, bump PLL frequency · Updated 3 years ago	315 0	Included
dcache-nc-fix b29c58f3d1 · dcache: Loads from non-cacheable PTEs load entire 64 bits · Updated 3 years ago	326 0	Included
remove-potato-uart 1d29cdcfb4 · Remove Potato UART · Updated 3 years ago	352 1
cache-tlb-parameters-2 53ccf89d26 · Use a record for cache parameters · Updated 3 years ago	433 1
caravel-20210114 f3f159c6dc · Check in verilog · Updated 3 years ago	488 24
caravel-20210105 3da9642020 · Check in verilog · Updated 3 years ago	485 21
jtag-port-2 ab2c87a161 · Update JTAG TAP controller for Microwatt · Updated 3 years ago	499 2
jtag-port 6dbc7c0559 · Update JTAG TAP controller for Microwatt · Updated 3 years ago	499 2
nia-debug 986881f258 · Add a patch to route the NIA out to GPIOs · Updated 5 years ago	1209 1

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