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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.common.all;
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library unisim;
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use unisim.vcomponents.all;
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entity multiply is
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port (
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clk : in std_logic;
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m_in : in MultiplyInputType;
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m_out : out MultiplyOutputType
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);
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end entity multiply;
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architecture behaviour of multiply is
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signal d1sign : std_ulogic_vector(13 downto 0);
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signal d2sign : std_ulogic_vector(4 downto 0);
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signal m00_p, m01_p, m02_p, m03_p : std_ulogic_vector(47 downto 0);
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signal m00_pc, m02_pc : std_ulogic_vector(47 downto 0);
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signal m10_p, m11_p, m12_p, m13_p : std_ulogic_vector(47 downto 0);
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signal m10_pc, m12_pc : std_ulogic_vector(47 downto 0);
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signal m20_p, m21_p, m22_p, m23_p : std_ulogic_vector(47 downto 0);
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signal m20_pc, m22_pc : std_ulogic_vector(47 downto 0);
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signal pp0, pp1 : std_ulogic_vector(127 downto 0);
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signal pp23 : std_ulogic_vector(127 downto 0);
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signal sumlo : std_ulogic_vector(8 downto 0);
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signal s0_pc, s1_pc : std_ulogic_vector(47 downto 0);
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signal s0_carry, p0_carry : std_ulogic_vector(3 downto 0);
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signal product : std_ulogic_vector(127 downto 0);
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signal addend : std_ulogic_vector(127 downto 0);
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signal p0_pat, p0_patb : std_ulogic;
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signal p1_pat, p1_patb : std_ulogic;
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signal rnot_1 : std_ulogic;
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signal valid_1 : std_ulogic;
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signal overflow : std_ulogic;
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begin
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addend <= m_in.addend when m_in.subtract = '0' else not m_in.addend;
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d1sign <= (others => m_in.data1(63) and m_in.is_signed);
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d2sign <= (others => m_in.data2(63) and m_in.is_signed);
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m00: DSP48E1
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generic map (
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ACASCREG => 0,
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ALUMODEREG => 0,
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AREG => 0,
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BCASCREG => 0,
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BREG => 0,
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CARRYINREG => 0,
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CARRYINSELREG => 0,
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CREG => 0,
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INMODEREG => 0,
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MREG => 0,
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OPMODEREG => 0,
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PREG => 1
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)
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port map (
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A => 6x"0" & m_in.data1(23 downto 0),
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ACIN => (others => '0'),
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ALUMODE => "0000",
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B => '0' & m_in.data2(16 downto 0),
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BCIN => (others => '0'),
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C => 14x"0" & addend(33 downto 0),
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CARRYCASCIN => '0',
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CARRYIN => '0',
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CARRYINSEL => "000",
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CEA1 => '0',
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CEA2 => '0',
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CEAD => '0',
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CEALUMODE => '0',
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CEB1 => '0',
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CEB2 => '0',
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CEC => '0',
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CECARRYIN => '0',
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CECTRL => '0',
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CED => '0',
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CEINMODE => '0',
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CEM => '0',
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CEP => m_in.valid,
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CLK => clk,
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D => (others => '0'),
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INMODE => "00000",
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MULTSIGNIN => '0',
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OPMODE => "0110101",
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P => m00_p,
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PCIN => (others => '0'),
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PCOUT => m00_pc,
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RSTA => '0',
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RSTALLCARRYIN => '0',
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RSTALUMODE => '0',
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RSTB => '0',
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RSTC => '0',
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RSTCTRL => '0',
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RSTD => '0',
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RSTINMODE => '0',
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RSTM => '0',
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RSTP => '0'
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);
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m01: DSP48E1
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generic map (
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ACASCREG => 0,
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ALUMODEREG => 0,
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AREG => 0,
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BCASCREG => 0,
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BREG => 0,
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CARRYINREG => 0,
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CARRYINSELREG => 0,
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CREG => 0,
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INMODEREG => 0,
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MREG => 1,
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OPMODEREG => 0,
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PREG => 0
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)
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port map (
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A => 6x"0" & m_in.data1(23 downto 0),
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ACIN => (others => '0'),
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ALUMODE => "0000",
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B => '0' & m_in.data2(33 downto 17),
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BCIN => (others => '0'),
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C => (others => '0'),
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CARRYCASCIN => '0',
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CARRYIN => '0',
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CARRYINSEL => "000",
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CEA1 => '0',
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CEA2 => '0',
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CEAD => '0',
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CEALUMODE => '0',
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CEB1 => '0',
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CEB2 => '0',
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CEC => '0',
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CECARRYIN => '0',
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CECTRL => '0',
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CED => '0',
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CEINMODE => '0',
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CEM => m_in.valid,
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CEP => '0',
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CLK => clk,
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D => (others => '0'),
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INMODE => "00000",
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MULTSIGNIN => '0',
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OPMODE => "1010101",
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P => m01_p,
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PCIN => m00_pc,
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RSTA => '0',
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RSTALLCARRYIN => '0',
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RSTALUMODE => '0',
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RSTB => '0',
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RSTC => '0',
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RSTCTRL => '0',
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RSTD => '0',
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RSTINMODE => '0',
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RSTM => '0',
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RSTP => '0'
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);
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m02: DSP48E1
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generic map (
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ACASCREG => 0,
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ALUMODEREG => 0,
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AREG => 0,
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BCASCREG => 0,
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BREG => 0,
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CARRYINREG => 0,
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CARRYINSELREG => 0,
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CREG => 0,
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INMODEREG => 0,
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MREG => 0,
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OPMODEREG => 0,
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PREG => 1
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)
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port map (
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A => 6x"0" & m_in.data1(23 downto 0),
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ACIN => (others => '0'),
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ALUMODE => "0000",
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B => '0' & m_in.data2(50 downto 34),
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BCIN => (others => '0'),
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C => 24x"0" & addend(57 downto 34),
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CARRYCASCIN => '0',
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CARRYIN => '0',
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CARRYINSEL => "000",
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CEA1 => '0',
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CEA2 => '0',
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CEAD => '0',
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CEALUMODE => '0',
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CEB1 => '0',
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CEB2 => '0',
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CEC => '0',
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CECARRYIN => '0',
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CECTRL => '0',
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CED => '0',
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CEINMODE => '0',
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CEM => '0',
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CEP => m_in.valid,
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CLK => clk,
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D => (others => '0'),
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INMODE => "00000",
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MULTSIGNIN => '0',
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OPMODE => "0110101",
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P => m02_p,
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PCIN => (others => '0'),
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PCOUT => m02_pc,
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RSTA => '0',
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RSTALLCARRYIN => '0',
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RSTALUMODE => '0',
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RSTB => '0',
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RSTC => '0',
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RSTCTRL => '0',
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RSTD => '0',
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RSTINMODE => '0',
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RSTM => '0',
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RSTP => '0'
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);
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m03: DSP48E1
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generic map (
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ACASCREG => 0,
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ALUMODEREG => 0,
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AREG => 0,
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BCASCREG => 0,
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BREG => 0,
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CARRYINREG => 0,
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CARRYINSELREG => 0,
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CREG => 0,
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INMODEREG => 0,
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MREG => 1,
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OPMODEREG => 0,
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PREG => 0
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)
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port map (
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A => 6x"0" & m_in.data1(23 downto 0),
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ACIN => (others => '0'),
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ALUMODE => "0000",
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B => d2sign & m_in.data2(63 downto 51),
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BCIN => (others => '0'),
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C => (others => '0'),
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CARRYCASCIN => '0',
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CARRYIN => '0',
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CARRYINSEL => "000",
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CEA1 => '0',
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CEA2 => '0',
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CEAD => '0',
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CEALUMODE => '0',
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CEB1 => '0',
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CEB2 => '0',
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CEC => '0',
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CECARRYIN => '0',
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CECTRL => '0',
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CED => '0',
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CEINMODE => '0',
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CEM => m_in.valid,
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CEP => '0',
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CLK => clk,
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D => (others => '0'),
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INMODE => "00000",
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MULTSIGNIN => '0',
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OPMODE => "1010101",
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P => m03_p,
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PCIN => m02_pc,
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RSTA => '0',
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RSTALLCARRYIN => '0',
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RSTALUMODE => '0',
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RSTB => '0',
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RSTC => '0',
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RSTCTRL => '0',
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RSTD => '0',
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RSTINMODE => '0',
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RSTM => '0',
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RSTP => '0'
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);
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m10: DSP48E1
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generic map (
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ACASCREG => 0,
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ALUMODEREG => 0,
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AREG => 0,
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BCASCREG => 0,
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BREG => 0,
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CARRYINREG => 0,
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CARRYINSELREG => 0,
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CREG => 0,
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INMODEREG => 0,
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MREG => 0,
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OPMODEREG => 0,
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PREG => 1
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)
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port map (
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A => 6x"0" & m_in.data1(47 downto 24),
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ACIN => (others => '0'),
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ALUMODE => "0000",
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B => '0' & m_in.data2(16 downto 0),
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BCIN => (others => '0'),
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C => (others => '0'),
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CARRYCASCIN => '0',
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CARRYIN => '0',
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CARRYINSEL => "000",
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CEA1 => '0',
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CEA2 => '0',
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CEAD => '0',
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CEALUMODE => '0',
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CEB1 => '0',
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CEB2 => '0',
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CEC => '0',
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CECARRYIN => '0',
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CECTRL => '0',
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CED => '0',
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CEINMODE => '0',
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CEM => '0',
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CEP => m_in.valid,
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CLK => clk,
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D => (others => '0'),
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INMODE => "00000",
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MULTSIGNIN => '0',
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OPMODE => "0000101",
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P => m10_p,
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PCIN => (others => '0'),
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PCOUT => m10_pc,
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RSTA => '0',
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RSTALLCARRYIN => '0',
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RSTALUMODE => '0',
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RSTB => '0',
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RSTC => '0',
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RSTCTRL => '0',
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RSTD => '0',
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RSTINMODE => '0',
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RSTM => '0',
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RSTP => '0'
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);
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m11: DSP48E1
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generic map (
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ACASCREG => 0,
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ALUMODEREG => 0,
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AREG => 0,
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BCASCREG => 0,
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BREG => 0,
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CARRYINREG => 0,
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CARRYINSELREG => 0,
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CREG => 0,
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INMODEREG => 0,
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MREG => 1,
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OPMODEREG => 0,
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PREG => 0
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)
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port map (
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A => 6x"0" & m_in.data1(47 downto 24),
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ACIN => (others => '0'),
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ALUMODE => "0000",
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B => '0' & m_in.data2(33 downto 17),
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BCIN => (others => '0'),
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C => (others => '0'),
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CARRYCASCIN => '0',
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CARRYIN => '0',
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CARRYINSEL => "000",
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CEA1 => '0',
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CEA2 => '0',
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CEAD => '0',
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CEALUMODE => '0',
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CEB1 => '0',
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CEB2 => '0',
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CEC => '0',
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CECARRYIN => '0',
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CECTRL => '0',
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CED => '0',
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CEINMODE => '0',
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CEM => m_in.valid,
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CEP => '0',
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CLK => clk,
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D => (others => '0'),
|
|
|
|
INMODE => "00000",
|
|
|
|
MULTSIGNIN => '0',
|
|
|
|
OPMODE => "1010101",
|
|
|
|
P => m11_p,
|
|
|
|
PCIN => m10_pc,
|
|
|
|
RSTA => '0',
|
|
|
|
RSTALLCARRYIN => '0',
|
|
|
|
RSTALUMODE => '0',
|
|
|
|
RSTB => '0',
|
|
|
|
RSTC => '0',
|
|
|
|
RSTCTRL => '0',
|
|
|
|
RSTD => '0',
|
|
|
|
RSTINMODE => '0',
|
|
|
|
RSTM => '0',
|
|
|
|
RSTP => '0'
|
|
|
|
);
|
|
|
|
|
|
|
|
m12: DSP48E1
|
|
|
|
generic map (
|
|
|
|
ACASCREG => 0,
|
|
|
|
ALUMODEREG => 0,
|
|
|
|
AREG => 0,
|
|
|
|
BCASCREG => 0,
|
|
|
|
BREG => 0,
|
|
|
|
CARRYINREG => 0,
|
|
|
|
CARRYINSELREG => 0,
|
|
|
|
CREG => 0,
|
|
|
|
INMODEREG => 0,
|
|
|
|
MREG => 0,
|
|
|
|
OPMODEREG => 0,
|
|
|
|
PREG => 1
|
|
|
|
)
|
|
|
|
port map (
|
|
|
|
A => 6x"0" & m_in.data1(47 downto 24),
|
|
|
|
ACIN => (others => '0'),
|
|
|
|
ALUMODE => "0000",
|
|
|
|
B => '0' & m_in.data2(50 downto 34),
|
|
|
|
BCIN => (others => '0'),
|
|
|
|
C => 24x"0" & addend(81 downto 58),
|
|
|
|
CARRYCASCIN => '0',
|
|
|
|
CARRYIN => '0',
|
|
|
|
CARRYINSEL => "000",
|
|
|
|
CEA1 => '0',
|
|
|
|
CEA2 => '0',
|
|
|
|
CEAD => '0',
|
|
|
|
CEALUMODE => '0',
|
|
|
|
CEB1 => '0',
|
|
|
|
CEB2 => '0',
|
|
|
|
CEC => '0',
|
|
|
|
CECARRYIN => '0',
|
|
|
|
CECTRL => '0',
|
|
|
|
CED => '0',
|
|
|
|
CEINMODE => '0',
|
|
|
|
CEM => '0',
|
|
|
|
CEP => m_in.valid,
|
|
|
|
CLK => clk,
|
|
|
|
D => (others => '0'),
|
|
|
|
INMODE => "00000",
|
|
|
|
MULTSIGNIN => '0',
|
|
|
|
OPMODE => "0110101",
|
|
|
|
P => m12_p,
|
|
|
|
PCIN => (others => '0'),
|
|
|
|
PCOUT => m12_pc,
|
|
|
|
RSTA => '0',
|
|
|
|
RSTALLCARRYIN => '0',
|
|
|
|
RSTALUMODE => '0',
|
|
|
|
RSTB => '0',
|
|
|
|
RSTC => '0',
|
|
|
|
RSTCTRL => '0',
|
|
|
|
RSTD => '0',
|
|
|
|
RSTINMODE => '0',
|
|
|
|
RSTM => '0',
|
|
|
|
RSTP => '0'
|
|
|
|
);
|
|
|
|
|
|
|
|
m13: DSP48E1
|
|
|
|
generic map (
|
|
|
|
ACASCREG => 0,
|
|
|
|
ALUMODEREG => 0,
|
|
|
|
AREG => 0,
|
|
|
|
BCASCREG => 0,
|
|
|
|
BREG => 0,
|
|
|
|
CARRYINREG => 0,
|
|
|
|
CARRYINSELREG => 0,
|
|
|
|
CREG => 0,
|
|
|
|
INMODEREG => 0,
|
|
|
|
MREG => 1,
|
|
|
|
OPMODEREG => 0,
|
|
|
|
PREG => 0
|
|
|
|
)
|
|
|
|
port map (
|
|
|
|
A => 6x"0" & m_in.data1(47 downto 24),
|
|
|
|
ACIN => (others => '0'),
|
|
|
|
ALUMODE => "0000",
|
|
|
|
B => d2sign & m_in.data2(63 downto 51),
|
|
|
|
BCIN => (others => '0'),
|
|
|
|
C => (others => '0'),
|
|
|
|
CARRYCASCIN => '0',
|
|
|
|
CARRYIN => '0',
|
|
|
|
CARRYINSEL => "000",
|
|
|
|
CEA1 => '0',
|
|
|
|
CEA2 => '0',
|
|
|
|
CEAD => '0',
|
|
|
|
CEALUMODE => '0',
|
|
|
|
CEB1 => '0',
|
|
|
|
CEB2 => '0',
|
|
|
|
CEC => '0',
|
|
|
|
CECARRYIN => '0',
|
|
|
|
CECTRL => '0',
|
|
|
|
CED => '0',
|
|
|
|
CEINMODE => '0',
|
|
|
|
CEM => m_in.valid,
|
|
|
|
CEP => '0',
|
|
|
|
CLK => clk,
|
|
|
|
D => (others => '0'),
|
|
|
|
INMODE => "00000",
|
|
|
|
MULTSIGNIN => '0',
|
|
|
|
OPMODE => "1010101",
|
|
|
|
P => m13_p,
|
|
|
|
PCIN => m12_pc,
|
|
|
|
RSTA => '0',
|
|
|
|
RSTALLCARRYIN => '0',
|
|
|
|
RSTALUMODE => '0',
|
|
|
|
RSTB => '0',
|
|
|
|
RSTC => '0',
|
|
|
|
RSTCTRL => '0',
|
|
|
|
RSTD => '0',
|
|
|
|
RSTINMODE => '0',
|
|
|
|
RSTM => '0',
|
|
|
|
RSTP => '0'
|
|
|
|
);
|
|
|
|
|
|
|
|
m20: DSP48E1
|
|
|
|
generic map (
|
|
|
|
ACASCREG => 0,
|
|
|
|
ALUMODEREG => 0,
|
|
|
|
AREG => 0,
|
|
|
|
BCASCREG => 0,
|
|
|
|
BREG => 0,
|
|
|
|
CARRYINREG => 0,
|
|
|
|
CARRYINSELREG => 0,
|
|
|
|
CREG => 0,
|
|
|
|
INMODEREG => 0,
|
|
|
|
MREG => 0,
|
|
|
|
OPMODEREG => 0,
|
|
|
|
PREG => 1
|
|
|
|
)
|
|
|
|
port map (
|
|
|
|
A => d1sign & m_in.data1(63 downto 48),
|
|
|
|
ACIN => (others => '0'),
|
|
|
|
ALUMODE => "0000",
|
|
|
|
B => '0' & m_in.data2(16 downto 0),
|
|
|
|
BCIN => (others => '0'),
|
|
|
|
C => (others => '0'),
|
|
|
|
CARRYCASCIN => '0',
|
|
|
|
CARRYIN => '0',
|
|
|
|
CARRYINSEL => "000",
|
|
|
|
CEA1 => '0',
|
|
|
|
CEA2 => '0',
|
|
|
|
CEAD => '0',
|
|
|
|
CEALUMODE => '0',
|
|
|
|
CEB1 => '0',
|
|
|
|
CEB2 => '0',
|
|
|
|
CEC => '0',
|
|
|
|
CECARRYIN => '0',
|
|
|
|
CECTRL => '0',
|
|
|
|
CED => '0',
|
|
|
|
CEINMODE => '0',
|
|
|
|
CEM => '0',
|
|
|
|
CEP => m_in.valid,
|
|
|
|
CLK => clk,
|
|
|
|
D => (others => '0'),
|
|
|
|
INMODE => "00000",
|
|
|
|
MULTSIGNIN => '0',
|
|
|
|
OPMODE => "0000101",
|
|
|
|
P => m20_p,
|
|
|
|
PCIN => (others => '0'),
|
|
|
|
PCOUT => m20_pc,
|
|
|
|
RSTA => '0',
|
|
|
|
RSTALLCARRYIN => '0',
|
|
|
|
RSTALUMODE => '0',
|
|
|
|
RSTB => '0',
|
|
|
|
RSTC => '0',
|
|
|
|
RSTCTRL => '0',
|
|
|
|
RSTD => '0',
|
|
|
|
RSTINMODE => '0',
|
|
|
|
RSTM => '0',
|
|
|
|
RSTP => '0'
|
|
|
|
);
|
|
|
|
|
|
|
|
m21: DSP48E1
|
|
|
|
generic map (
|
|
|
|
ACASCREG => 0,
|
|
|
|
ALUMODEREG => 0,
|
|
|
|
AREG => 0,
|
|
|
|
BCASCREG => 0,
|
|
|
|
BREG => 0,
|
|
|
|
CARRYINREG => 0,
|
|
|
|
CARRYINSELREG => 0,
|
|
|
|
CREG => 0,
|
|
|
|
INMODEREG => 0,
|
|
|
|
MREG => 1,
|
|
|
|
OPMODEREG => 0,
|
|
|
|
PREG => 0
|
|
|
|
)
|
|
|
|
port map (
|
|
|
|
A => d1sign & m_in.data1(63 downto 48),
|
|
|
|
ACIN => (others => '0'),
|
|
|
|
ALUMODE => "0000",
|
|
|
|
B => '0' & m_in.data2(33 downto 17),
|
|
|
|
BCIN => (others => '0'),
|
|
|
|
C => (others => '0'),
|
|
|
|
CARRYCASCIN => '0',
|
|
|
|
CARRYIN => '0',
|
|
|
|
CARRYINSEL => "000",
|
|
|
|
CEA1 => '0',
|
|
|
|
CEA2 => '0',
|
|
|
|
CEAD => '0',
|
|
|
|
CEALUMODE => '0',
|
|
|
|
CEB1 => '0',
|
|
|
|
CEB2 => '0',
|
|
|
|
CEC => '0',
|
|
|
|
CECARRYIN => '0',
|
|
|
|
CECTRL => '0',
|
|
|
|
CED => '0',
|
|
|
|
CEINMODE => '0',
|
|
|
|
CEM => m_in.valid,
|
|
|
|
CEP => '0',
|
|
|
|
CLK => clk,
|
|
|
|
D => (others => '0'),
|
|
|
|
INMODE => "00000",
|
|
|
|
MULTSIGNIN => '0',
|
|
|
|
OPMODE => "1010101",
|
|
|
|
P => m21_p,
|
|
|
|
PCIN => m20_pc,
|
|
|
|
RSTA => '0',
|
|
|
|
RSTALLCARRYIN => '0',
|
|
|
|
RSTALUMODE => '0',
|
|
|
|
RSTB => '0',
|
|
|
|
RSTC => '0',
|
|
|
|
RSTCTRL => '0',
|
|
|
|
RSTD => '0',
|
|
|
|
RSTINMODE => '0',
|
|
|
|
RSTM => '0',
|
|
|
|
RSTP => '0'
|
|
|
|
);
|
|
|
|
|
|
|
|
m22: DSP48E1
|
|
|
|
generic map (
|
|
|
|
ACASCREG => 0,
|
|
|
|
ALUMODEREG => 0,
|
|
|
|
AREG => 0,
|
|
|
|
BCASCREG => 0,
|
|
|
|
BREG => 0,
|
|
|
|
CARRYINREG => 0,
|
|
|
|
CARRYINSELREG => 0,
|
|
|
|
CREG => 0,
|
|
|
|
INMODEREG => 0,
|
|
|
|
MREG => 0,
|
|
|
|
OPMODEREG => 0,
|
|
|
|
PREG => 1
|
|
|
|
)
|
|
|
|
port map (
|
|
|
|
A => d1sign & m_in.data1(63 downto 48),
|
|
|
|
ACIN => (others => '0'),
|
|
|
|
ALUMODE => "0000",
|
|
|
|
B => '0' & m_in.data2(50 downto 34),
|
|
|
|
BCIN => (others => '0'),
|
|
|
|
C => "00" & addend(127 downto 82),
|
|
|
|
CARRYCASCIN => '0',
|
|
|
|
CARRYIN => '0',
|
|
|
|
CARRYINSEL => "000",
|
|
|
|
CEA1 => '0',
|
|
|
|
CEA2 => '0',
|
|
|
|
CEAD => '0',
|
|
|
|
CEALUMODE => '0',
|
|
|
|
CEB1 => '0',
|
|
|
|
CEB2 => '0',
|
|
|
|
CEC => '0',
|
|
|
|
CECARRYIN => '0',
|
|
|
|
CECTRL => '0',
|
|
|
|
CED => '0',
|
|
|
|
CEINMODE => '0',
|
|
|
|
CEM => '0',
|
|
|
|
CEP => m_in.valid,
|
|
|
|
CLK => clk,
|
|
|
|
D => (others => '0'),
|
|
|
|
INMODE => "00000",
|
|
|
|
MULTSIGNIN => '0',
|
|
|
|
OPMODE => "0110101",
|
|
|
|
P => m22_p,
|
|
|
|
PCIN => (others => '0'),
|
|
|
|
PCOUT => m22_pc,
|
|
|
|
RSTA => '0',
|
|
|
|
RSTALLCARRYIN => '0',
|
|
|
|
RSTALUMODE => '0',
|
|
|
|
RSTB => '0',
|
|
|
|
RSTC => '0',
|
|
|
|
RSTCTRL => '0',
|
|
|
|
RSTD => '0',
|
|
|
|
RSTINMODE => '0',
|
|
|
|
RSTM => '0',
|
|
|
|
RSTP => '0'
|
|
|
|
);
|
|
|
|
|
|
|
|
m23: DSP48E1
|
|
|
|
generic map (
|
|
|
|
ACASCREG => 0,
|
|
|
|
ALUMODEREG => 0,
|
|
|
|
AREG => 0,
|
|
|
|
BCASCREG => 0,
|
|
|
|
BREG => 0,
|
|
|
|
CARRYINREG => 0,
|
|
|
|
CARRYINSELREG => 0,
|
|
|
|
CREG => 0,
|
|
|
|
INMODEREG => 0,
|
|
|
|
MREG => 1,
|
|
|
|
OPMODEREG => 0,
|
|
|
|
PREG => 0
|
|
|
|
)
|
|
|
|
port map (
|
|
|
|
A => d1sign & m_in.data1(63 downto 48),
|
|
|
|
ACIN => (others => '0'),
|
|
|
|
ALUMODE => "0000",
|
|
|
|
B => d2sign & m_in.data2(63 downto 51),
|
|
|
|
BCIN => (others => '0'),
|
|
|
|
C => (others => '0'),
|
|
|
|
CARRYCASCIN => '0',
|
|
|
|
CARRYIN => '0',
|
|
|
|
CARRYINSEL => "000",
|
|
|
|
CEA1 => '0',
|
|
|
|
CEA2 => '0',
|
|
|
|
CEAD => '0',
|
|
|
|
CEALUMODE => '0',
|
|
|
|
CEB1 => '0',
|
|
|
|
CEB2 => '0',
|
|
|
|
CEC => '0',
|
|
|
|
CECARRYIN => '0',
|
|
|
|
CECTRL => '0',
|
|
|
|
CED => '0',
|
|
|
|
CEINMODE => '0',
|
|
|
|
CEM => m_in.valid,
|
|
|
|
CEP => '0',
|
|
|
|
CLK => clk,
|
|
|
|
D => (others => '0'),
|
|
|
|
INMODE => "00000",
|
|
|
|
MULTSIGNIN => '0',
|
|
|
|
OPMODE => "1010101",
|
|
|
|
P => m23_p,
|
|
|
|
PCIN => m22_pc,
|
|
|
|
RSTA => '0',
|
|
|
|
RSTALLCARRYIN => '0',
|
|
|
|
RSTALUMODE => '0',
|
|
|
|
RSTB => '0',
|
|
|
|
RSTC => '0',
|
|
|
|
RSTCTRL => '0',
|
|
|
|
RSTD => '0',
|
|
|
|
RSTINMODE => '0',
|
|
|
|
RSTM => '0',
|
|
|
|
RSTP => '0'
|
|
|
|
);
|
|
|
|
|
|
|
|
pp0 <= std_ulogic_vector(resize(signed(m13_p(37 downto 0) & m12_p(16 downto 0) &
|
|
|
|
m01_p(40 downto 0) & m00_p(16 downto 0)), 128));
|
|
|
|
pp1 <= m23_p(28 downto 0) & m22_p(16 downto 0) & m11_p(40 downto 0) & m10_p(16 downto 0) & 24x"0";
|
|
|
|
-- pp2 <= std_ulogic_vector(resize(signed(m03_p(37 downto 0) & m02_p(16 downto 0) & 34x"0"), 128));
|
|
|
|
-- pp3 <= std_ulogic_vector(resize(signed(m21_p(34 downto 0) & m20_p(16 downto 0) & 48x"0"), 128));
|
|
|
|
|
|
|
|
pp23 <= std_ulogic_vector(resize(resize(signed(m03_p(37 downto 0) & m02_p(16 downto 0) & 34x"0"), 100) +
|
|
|
|
signed(m21_p(34 downto 0) & m20_p(16 downto 0) & 48x"0"), 128));
|
|
|
|
|
|
|
|
sumlo <= std_ulogic_vector(unsigned('0' & pp0(31 downto 24)) + unsigned('0' & pp1(31 downto 24)));
|
|
|
|
|
|
|
|
s0: DSP48E1
|
|
|
|
generic map (
|
|
|
|
ACASCREG => 0,
|
|
|
|
ALUMODEREG => 0,
|
|
|
|
AREG => 0,
|
|
|
|
BCASCREG => 0,
|
|
|
|
BREG => 0,
|
|
|
|
CARRYINREG => 0,
|
|
|
|
CARRYINSELREG => 0,
|
|
|
|
CREG => 0,
|
|
|
|
INMODEREG => 0,
|
|
|
|
MREG => 0,
|
|
|
|
OPMODEREG => 0,
|
|
|
|
PREG => 0,
|
|
|
|
USE_MULT => "none"
|
|
|
|
)
|
|
|
|
port map (
|
|
|
|
A => pp0(79 downto 50),
|
|
|
|
ACIN => (others => '0'),
|
|
|
|
ALUMODE => "0000",
|
|
|
|
B => pp0(49 downto 32),
|
|
|
|
BCIN => (others => '0'),
|
|
|
|
C => pp1(79 downto 32),
|
|
|
|
CARRYCASCIN => '0',
|
|
|
|
CARRYIN => '0',
|
|
|
|
CARRYINSEL => "000",
|
|