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133 lines
2.6 KiB
Markdown
133 lines
2.6 KiB
Markdown
# A2P for OpenLane/Carousel
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* manually replace inferred mem with array macros; eventually make all arrays components (inferred for FPGA, phys for tech)
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## Arrays to convert to DFFRAM
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* IC (4K)
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```
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reg [21:0] ways_0_tags [0:127];
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reg [31:0] ways_0_datas [0:1023];
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```
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* tag: 128x22b
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* data: 1024x32b
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* DC (4K)
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```
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reg [21:0] DC_DIR_tags [0:127];
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reg [7:0] DC_DIR_data_symbol0 [0:1023];
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reg [7:0] DC_DIR_data_symbol1 [0:1023];
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reg [7:0] DC_DIR_data_symbol2 [0:1023];
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reg [7:0] DC_DIR_data_symbol3 [0:1023];
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```
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* tag: 128x22b
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* data(4): 1024x8b
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* GPR
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```
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reg [31:0] RegFilePlugin_regFile [0:31] /* verilator public */ ;
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```
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* 32x32b, 3 read, 1 write
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## Creating DFFRAM arrays
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* ***REQUIRES DOCKER***
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* github.com/efabless/openlane/blob/master/README.md
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```
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# clone OpenLane
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# make full-pdk
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```
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* github.com/Cloud-V/DFFRAM
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```
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# clone DFFRam
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export PDK_ROOT=/home/wtf/projects2/OpenLane/pdks
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# optionally set design name for any builds; **doesn't set the output name**
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# export FORCE_DESIGN_NAME=ram_32_32
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```
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### GPR
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* need 3r1w and DFFRam creates 2r1w reg; so need 2 regs, or 3 32x32 RAM, or custom 3r script
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* -v 1R1W not supported; is this basically the same as ram_32_32??
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* multiple arrays will be instantiated in single gpr module; use parameter to select gen style
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#### RAM
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```
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#export FORCE_DESIGN_NAME=ram_32x32
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dffram.py -s 32x32 -p $PDK_ROOT
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```
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#### REG
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* building block <pdk>:<scl>:<name> corresponds to platforms/<pdk>/<scl>/_building_blocks/<name>/model.v
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```
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#export FORCE_DESIGN_NAME=reg_32x32
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dffram.py -s 32x32 -v 2R1W -p $PDK_ROOT -b sky130A:sky130_fd_sc_hd:rf
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```
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#### Tag Arrays, 4K
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* need to make **decellerator** script to whack the extra 10 bits/word after place and then run rest of stuff
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```
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#export FORCE_DESIGN_NAME=ram_128x32
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dffram.py -s 128x32 -p $PDK_ROOT
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```
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* OR try...
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```
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export FORCE_ACCEPT_SIZE=wtf
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#export FORCE_DESIGN_NAME=ram_128x22
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dffram.py -s 128x22 -p $PDK_ROOT
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unset FORCE_ACCEPT_SIZE
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```
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#### Data Array, IC
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```
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#export FORCE_DESIGN_NAME=ram_1024x32
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dffram.py -s 1024x32 -p $PDK_ROOT
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```
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#### Data Array, DC (4)
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* DFFRam handles byte writes, so this is same as IC
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```
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#export FORCE_DESIGN_NAME=ram_1024x8
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#dffram.py -s 1024x8 -p $PDK_ROOT
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```
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IC/DC arrays could be built using different subunits if better for layout/timing; 4KB = 128 lines x 32B.
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## Updating core manually
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* this is compiling components on non-generated paths...
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```verilator --lint-only -Wno-fatal A2P_WB_RAM.v```
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* add gpr.v and module to top; can use this to test on FPGA with ```EXPAND_TYPE=`INFERRED```
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