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a2p/build/openroad/litex
History
wtf 4d544f92de or stuff 3 years ago
..
a2p or and litex caravel 3 years ago
build/caravel_user or and litex caravel 3 years ago
modules or and litex caravel 3 years ago
output or and litex caravel 3 years ago
platforms or and litex caravel 3 years ago
src or and litex caravel 3 years ago
.gitignore or stuff 3 years ago
a2p_site.py or and litex caravel 3 years ago
caravel_user.v or and litex caravel 3 years ago
config.mk or and litex caravel 3 years ago
constraint.sdc or and litex caravel 3 years ago
csr.csv or and litex caravel 3 years ago
mem.init or and litex caravel 3 years ago
readme.md or and litex caravel 3 years ago

readme.md

Using Litex to build a Caravel User Project Area

Create a module usable for FPGA and tech mapping, containing various Litex structures like CSR, WB, UART, I2C, etc. and custom verilog modules (core, async RAM, GPIO, etc.).

  • create a virtual platform corresponding to the I/O on the Caravel User module

  • create virtual 'soc' design using that platform

    • module can be used for OL synthesis (expand_type set for tech)

    • module can be included in FPGA SOC for testing and development (expand_type set for inferred)

  • create real soc incorporating above, plus clocks, real GPIO connections, etc.

Virtual Platform

  • create user area
a2p_site.py
cp build/caravel_user/gateware/mem.init .
cp build/caravel_user/gateware/caravel_user.v .
  • OL didn't die
make DESIGN_CONFIG=./designs/sky130hd/a2p_litex/config.mk