or and litex caravel

2 years ago · d11a5838c3
parent e9e85815fb
commit d11a5838c3
81 changed files with 847306 additions and 5 deletions
--- a/build/openroad/.gitignore
+++ b/build/openroad/.gitignore
@ -1,2 +1,3 @@
 dffram/
-output/
+output/results
+output/objects
--- a/build/openroad/config.mk
+++ b/build/openroad/config.mk
@ -35,7 +35,6 @@ $(info [WTF] Output Dirs: $(DESIGN_NICKNAME))
 # CTS

 # forget about this for now - occurred when added dffram dir/caches.  anton says hold misses are fake anyway :)
-# (at least at 100mhz)
 # do i need something else from dffram build?
 # Repair hold violations...
 # [INFO RSZ-0046] Found 60472 endpoints with hold violations.
@ -43,4 +42,4 @@ $(info [WTF] Output Dirs: $(DESIGN_NICKNAME))
 # [INFO RSZ-0032] Inserted 213923 hold buffers.
 # [ERROR DPL-0019] detailed placement failed on hold33177
 # continue if cts wants to barf...
-#export WTF_CTS_IGNORE_HOLD_MISSES = 1
+export WTF_CTS_IGNORE_HOLD_MISSES = 1
--- a/build/openroad/litex/.gitignore
+++ b/build/openroad/litex/.gitignore
@ -0,0 +1,3 @@
+dffram/
+output/results
+output/objects
--- a/build/openroad/litex/a2p/init.py
+++ b/build/openroad/litex/a2p/init.py
@ -0,0 +1 @@
+from .core import A2P
--- a/build/openroad/litex/a2p/boot-helper.S
+++ b/build/openroad/litex/a2p/boot-helper.S
@ -0,0 +1,5 @@
+.section .text, "ax", @progbits
+
+.global boot_helper
+boot_helper:
+   blr
--- a/build/openroad/litex/a2p/core.py
+++ b/build/openroad/litex/a2p/core.py
@ -0,0 +1,145 @@
+
+import os
+
+from migen import *
+
+from litex import get_data_mod
+from litex.soc.interconnect import wishbone
+from litex.soc.interconnect.csr import *
+from litex.soc.cores.cpu import CPU
+
+dir = os.path.dirname(os.path.realpath(__file__))
+
+# these select the top RTL file for each variant name
+CPU_VARIANTS = {
+    'AXI': 'A2P_AXI',
+    'WB':  'A2P_WB',
+    'standard': 'A2P_WB'   #wtf litex does this as default
+}
+
+GCC_FLAGS = {
+   'WB' : '-fomit-frame-pointer -Wall -fno-builtin -nostdinc -fno-stack-protector -fexceptions -Wstrict-prototypes -Wold-style-definition -Wmissing-prototypes'
+}
+
+class A2P(CPU, AutoCSR):
+    name                 = 'a2p'
+    human_name           = 'a2p'
+    family               = 'ppc32'
+    variants             = CPU_VARIANTS
+    data_width           = 32
+    endianness           = 'big'
+    gcc_triple           = 'powerpc-linux-gnu'
+    linker_output_format = 'elf32-powerpc'
+    nop                  = 'nop'
+    io_regions           = {0x80000000: 0x80000000} # origin, length
+
+    @property
+    def mem_map(self):
+        return {
+            'rom':          0x00000000,
+            'sram':         0x00004000,
+            'main_ram':     0x40000000,
+            'csr':          0xf0000000,
+        }
+
+    @property
+    def gcc_flags(self):
+        flags = GCC_FLAGS[self.variant]
+        flags += " -D__a2p__"
+        return flags
+
+    def __init__(self, platform, variant='WB'):
+
+         if variant == 'standard':
+            variant = 'WB'
+
+         self.platform         = platform
+         self.variant          = variant
+         self.human_name       = CPU_VARIANTS.get(variant, 'A2P')
+         self.external_variant = None
+         self.reset            = Signal()
+         self.interrupt        = Signal(32)
+         self.interruptS       = Signal()
+         self.ibus             = ibus = wishbone.Interface()
+         self.dbus             = dbus = wishbone.Interface()
+         self.periph_buses     = [ibus, dbus]
+         self.memory_buses     = []
+         self.enableDebug      = False
+         self.enableJTAG       = False
+         self.externalResetVector = 0
+
+        # # #
+
+         self.cpu_params = dict(
+                i_clk                    = ClockSignal(),
+                i_reset                  = ResetSignal() | self.reset,
+
+                i_externalInterrupt  = self.interrupt[0],
+                i_externalInterruptS = self.interruptS,
+                i_timerInterrupt    = 0,
+                i_softwareInterrupt = 0,
+
+                o_iBusWB_ADR      = ibus.adr,
+                o_iBusWB_DAT_MOSI = ibus.dat_w,
+                o_iBusWB_SEL      = ibus.sel,
+                o_iBusWB_CYC      = ibus.cyc,
+                o_iBusWB_STB      = ibus.stb,
+                o_iBusWB_WE       = ibus.we,
+                o_iBusWB_CTI      = ibus.cti,
+                o_iBusWB_BTE      = ibus.bte,
+                i_iBusWB_DAT_MISO = ibus.dat_r,
+                i_iBusWB_ACK      = ibus.ack,
+                i_iBusWB_ERR      = ibus.err,
+
+                o_dBusWB_ADR      = dbus.adr,
+                o_dBusWB_DAT_MOSI = dbus.dat_w,
+                o_dBusWB_SEL      = dbus.sel,
+                o_dBusWB_CYC      = dbus.cyc,
+                o_dBusWB_STB      = dbus.stb,
+                o_dBusWB_WE       = dbus.we,
+                o_dBusWB_CTI      = dbus.cti,
+                o_dBusWB_BTE      = dbus.bte,
+                i_dBusWB_DAT_MISO = dbus.dat_r,
+                i_dBusWB_ACK      = dbus.ack,
+                i_dBusWB_ERR      = dbus.err
+            )
+
+         self.cpu_params['i_externalResetVector'] = self.externalResetVector
+
+         # these need to connect to top nets
+         if self.enableDebug:
+            self.cpu_params['i_debugReset'] = 0
+            self.cpu_params['o_debug_resetOut'] = 0
+            self.cpu_params['i_debug_bus_cmd_valid'] = 0
+            self.cpu_params['i_debug_bus_cmd_ready'] = 0
+            self.cpu_params['i_debug_bus_cmd_payload_wr'] = 0
+            self.cpu_params['i_debug_bus_cmd_payload_address'] = 0
+            self.cpu_params['i_debug_bus_cmd_payload_data'] = 0
+            self.cpu_params['o_debug_bus_rsp_data'] = 0
+
+         if self.enableJTAG:
+            self.cpu_params['i_jtag_tms'] = 0
+            self.cpu_params['i_jtag_tck'] = 0
+            self.cpu_params['i_jtag_tdi'] = 0
+            self.cpu_params['o_jtag_tdo'] = 0
+
+    def set_reset_address(self, reset_address):
+        assert not hasattr(self, "reset_address")
+        self.reset_address = reset_address
+        self.cpu_params.update(i_externalResetVector=Signal(32, reset=reset_address))
+
+    @staticmethod
+    def add_sources(platform, variant="WB"):
+        cpu_filename = CPU_VARIANTS[variant] + ".v"
+        vdir = os.path.join(dir, 'verilog')
+        platform.add_source(os.path.join(vdir, cpu_filename))
+
+    def use_external_variant(self, variant_filename):
+        self.external_variant = True
+        self.platform.add_source(variant_filename)
+
+    def do_finalize(self):
+        assert hasattr(self, "reset_address")
+        if not self.external_variant:
+            self.add_sources(self.platform, self.variant)
+        self.specials += Instance("A2P_WB", **self.cpu_params)
--- a/build/openroad/litex/a2p/csr-defs.h
+++ b/build/openroad/litex/a2p/csr-defs.h
--- a/build/openroad/litex/a2p/irq.h
+++ b/build/openroad/litex/a2p/irq.h
@ -0,0 +1,18 @@
+#ifndef __IRQ_H
+#define __IRQ_H
+
+static inline void irq_setmask(unsigned int mask) {
+}
+
+static inline unsigned int irq_getmask(void) {
+   return 0;
+}
+
+static inline unsigned int irq_pending(void) {
+   return 0;
+}
+
+static inline void irq_setie(unsigned int mask) {
+}
+
+#endif
--- a/build/openroad/litex/a2p/system.h
+++ b/build/openroad/litex/a2p/system.h
@ -0,0 +1,55 @@
+// swizzlin
+
+#ifndef __SYSTEM_H
+#define __SYSTEM_H
+
+#include <stdint.h>
+
+/*
+void flush_l2_cache(void) {
+}
+*/
+static void flush_cpu_icache(void);
+static void flush_cpu_dcache(void);
+
+static void flush_cpu_icache(void) {
+}
+static void flush_cpu_dcache(void) {
+}
+
+#define CSR_ACCESSORS_DEFINED
+
+#ifdef __ASSEMBLER__
+#define MMPTR(x) x
+#else /* ! __ASSEMBLER__ */
+
+#include <generated/soc.h>
+#if !defined(CONFIG_CSR_DATA_WIDTH)
+#error CSR_DATA_WIDTH MUST be set before including this file!
+#endif
+
+#define MMPTR(a) (*((volatile uint32_t *)(a)))
+
+static inline unsigned long swizzle(unsigned long v);
+
+static inline unsigned long swizzle(unsigned long v) {
+   return ((v & 0x000000FF) << 24) | ((v & 0x0000FF00) <<  8) | ((v & 0x00FF0000) >>  8) | ((v & 0xFF000000) >> 24);
+   //return v;
+}
+
+static inline void csr_write_simple(unsigned long v, unsigned long a)
+{
+	//MMPTR(a) = v;
+   MMPTR(a) = swizzle(v);
+}
+
+static inline unsigned long csr_read_simple(unsigned long a)
+{
+	//return MMPTR(a);
+	return swizzle(MMPTR(a));
+}
+
+#endif /* ! __ASSEMBLER__ */
+
+#endif /* __SYSTEM_H */
+
--- a/build/openroad/litex/a2p/verilog/A2P_WB.v
+++ b/build/openroad/litex/a2p/verilog/A2P_WB.v
--- a/build/openroad/litex/a2p/verilog/A2P_WB_no_byps.v
+++ b/build/openroad/litex/a2p/verilog/A2P_WB_no_byps.v
--- a/build/openroad/litex/a2p/verilog/A2P_WB_no_cr_byp.v
+++ b/build/openroad/litex/a2p/verilog/A2P_WB_no_cr_byp.v
--- a/build/openroad/litex/a2p/verilog/A2P_WB_normal.v
+++ b/build/openroad/litex/a2p/verilog/A2P_WB_normal.v
--- a/build/openroad/litex/a2p_site.py
+++ b/build/openroad/litex/a2p_site.py
@ -0,0 +1,274 @@
+#!/usr/bin/python3
+
+# A2P Caravel Site Test
+# python3 a2p_site.py
+#
+# 1 or 2 cores
+# Manager (wb is only slave)
+# Async RAM interface  ** won't work - only half of io can be outputs **
+#  use custom serial interface ~ 8 pins, 4B/32B packets
+# UARTs
+# I2C
+# special-purpose GPIO
+# Mgmt interface
+# Beer on tap
+
+import os
+import argparse
+
+from migen import *
+
+# wtf - use local platform
+from platforms import caravel_user
+
+# wtf - use local core
+# help python find package
+import sys
+binPath = os.path.dirname(os.path.realpath(__file__))
+sys.path.append(os.path.join(binPath, 'a2p'))
+# get core def
+from a2p import A2P
+# add to litex dict
+from litex.soc.cores import cpu
+cpu.CPUS['a2p'] = A2P
+
+# local modules
+sys.path.append(os.path.join(binPath, 'modules'))
+
+from litex.soc.integration.soc import colorer
+from litex.soc.integration.soc import SoCRegion
+from litex.soc.integration.soc_core import *
+from litex.soc.integration.soc_sdram import *
+from litex.soc.integration.builder import *
+
+from litex.soc.cores.led import LedChaser
+from litex.soc.cores.gpio import GPIOIn
+from litex.soc.cores.gpio import GPIOOut
+from litex.soc.cores.bitbang import I2CMaster
+
+from litex.soc.interconnect import wishbone
+from litex.soc.interconnect import csr
+
+from litex.soc.cores.uart import UART
+from litex.soc.cores.uart import RS232PHY
+
+# possibly use octspi with a memory controller to send/rcv 32b/128b data with header and crc?
+#from litespi.common import *
+#from litespi.phy.generic_sdr import LiteSPISDRPHYCore
+#from litespi.phy.generic_ddr import LiteSPIDDRPHYCore
+
+
+# BaseSoC ------------------------------------------------------------------------------------------
+
+from litex.soc.interconnect import wishbone
+
+def _to_signal(obj):
+      return obj.raw_bits() if isinstance(obj, Record) else obj
+
+class BaseSoC(SoCCore):
+
+    def __init__(self, sys_clk_freq=50e6, uart_baudrate=115200,  **kwargs):
+
+        platform = caravel_user.Platform()
+
+        SoCCore.__init__(self, platform, 50e6, sys_clk_freq=50e6, cpu_type='a2p',
+            csr_data_width=32, with_uart=False, integrated_sram_size=0, integrated_rom_size=0,
+            ident='A2P Caravel Site Test', ident_version=True)
+
+        # no irq yet
+        self.add_constant('UART_POLLING')
+
+        self.mem_map = {
+         'csr':      0xFFF00000,
+         'sram':     0x00000000,
+         'mgmt':     0xE0000000
+        }
+
+
+        # I/O connections --------------------------------------------------------------------------
+        # clk is connected by platform
+        # make these exist even if unconnected so i/o are defined
+
+        # --- clk/rst
+        #self.sys_rst = Signal() #this creates sys_rst_1
+        #self.comb += self.int_rst.eq(platform.request('wb_rst_i')) no idea how to connect to top level sigs that are magically gen'd
+        # apprarently they give you a few things useful!
+        self.sys_rst = ResetSignal()
+        self.comb += self.sys_rst.eq(platform.request('wb_rst_i'))
+        # but gens some whack logic
+        # always @(*) begin
+	     #   sys_rst <= 1'd0;
+	     #   sys_rst <= wb_rst_i;
+	     #   sys_rst <= int_rst;
+        # end
+
+        self.user_clock2 = Signal()
+        self.comb += self.user_clock2.eq(platform.request('user_clock2'))
+
+        # --- wb
+        # options:
+        #  * unused
+        #  * user area is slave (config/test only)
+        #  * user area is master/slave - not possible - NO MASTER SIGS!!!
+
+        # slave interface for mgmt macro (core controls, etc.); could hang csr off it and interface through them
+        # i suppose then you could let the csr be read/written by both sides, so you could do some polled mailbox messaging; probs could proxy i/o through pico
+        # they would have to be r/w by 2 different wb's
+        self.wb_mgmt = wishbone.Interface()
+        self.wb_io = Record([('cyc', 1), ('stb', 1), ('we', 1), ('sel', 4), ('adr', 32), ('ack', 1), ('dat_r', 32), ('dat_w', 32),
+                             ('cti', 1), ('bte', 32), ('err', 1)])
+        self.wb_io.cyc = platform.request('wbs_cyc_i')
+        self.wb_io.stb = platform.request('wbs_stb_i')
+        self.wb_io.we = platform.request('wbs_we_i')
+        self.wb_io.sel = platform.request('wbs_sel_i')
+        self.wb_io.adr = platform.request('wbs_adr_i')
+        self.wb_io.ack = platform.request('wbs_ack_o')
+        self.wb_io.dat_r = platform.request('wbs_dat_o')
+        self.wb_io.dat_w = platform.request('wbs_dat_i')
+        self.wb_io.cti = Signal()
+        self.wb_io.bte = Signal()
+        self.wb_io.err = Signal()
+        self.wb_mgmt.connect_to_pads(self.wb_io, mode='slave')
+
+        #somehow get this built and then connected to 2 wb
+        #self.wb_shared = wishbone.InterconnectShared(masters,slaves)
+        self.mailbox = csr.CSRStorage(size=16, name='mailbox')
+        self.add_csr('mailbox')
+
+        # --- gpio
+        self.in_in = Signal(19)
+        self.comb += self.in_in.eq(platform.request('in_in'))
+        self.in_out = Signal(19)
+        self.comb += self.in_out.eq(platform.request('in_out'))
+        self.in_oeb = Signal(19)
+        self.comb += self.in_oeb.eq(platform.request('in_oeb'))
+        # skip analog_in; too curvy
+
+        # allocate
+        uart_0_io = {
+           'rx': self.in_in[0],
+           'tx': self.in_out[0]
+        }
+        uart_1_io = {
+           'rx': self.in_in[1],
+           'tx': self.in_out[1]
+        }
+        i2c_io = {
+           'scl': self.in_out[2],
+           'sda': self.in_out[3]
+        }
+        dshot_io = self.in_out[3:6]
+        # toss
+        ram_io = {
+          'ce': Signal(1),
+           'oe': Signal(),    # self.in_out[7],
+           'we': Signal(),    # self.in_out[8],
+           'adr': Signal(19), # self.in_out[18:0],
+           'dat': Signal(8)   # self.in_out[18:11]
+        }
+
+        # --- misc
+        self.user_irq = Signal(3)
+        self.comb += self.user_irq.eq(platform.request('user_irq'))
+
+        # --- la
+        self.la_data_in = Signal(128)
+        self.comb += self.la_data_in.eq(platform.request('la_data_in'))
+        self.la_data_out = Signal(128)
+        self.comb += self.la_data_out.eq(platform.request('la_data_out'))
+        self.la_oenb = Signal(128)
+        self.comb += self.la_oenb.eq(platform.request('la_oenb'))
+
+        # ON-BOARD MEM ------------------------------------------------------------------------------
+        # None, unless a small 'ROM'-like device
+        #self.add_rom('rom', origin=self.mem_map['rom'], size=rom_size, contents=romdata)
+
+        # MANAGER -----------------------------------------------------------------------------------
+        # service processor stuff controlled by the man
+
+        # External SRAM (512K) -----------------------------------------------------------------------
+        # GPIO-connected SRAM/FPGA
+
+        #  *** doh, won't work - only half the i/o are outputs!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! ***
+        # will have to resurrect custom serial i/o with fpga on other end
+
+        from issiram import ISSIRam
+        platform.add_source('./momv modules/issiram.v')
+
+        sram_bus = wishbone.Interface()
+        sram = ISSIRam(self, ClockSignal(), ResetSignal(), sram_bus, ram_io)
+        self.submodules.sram = sram
+         #     ERROR: Output port top.issiram.mem_adr (issiram) is connected to constants: { \basesoc_in_out [17:0] 1'x }
+         #     Command exited with non-zero status 1
+         #     Elapsed time: 0:12.27[h:]min:sec. CPU time: user 11.77 sys 0.48 (99%). Peak memory: 1468464KB.
+         #     make: *** [Makefile:354: results/sky130hd/a2p_litex/output/20211125085224/base/1_1_yosys.v] Error 1
+        self.bus.add_slave('sram', sram_bus, SoCRegion(origin=self.mem_map['sram'], size=sram.size))
+        #self.logger.info('SRAM {} {} {}.'.format(
+        #    colorer('sram'),
+        #    colorer('added', color='green'),
+        #    self.bus.regions['sram']))
+
+        # Leds n LaserBeams -----------------------------------------------------------------------
+        #self.submodules.leds = LedChaser(
+        #    pads         = platform.request_all('user_led'),
+        #    sys_clk_freq = sys_clk_freq
+        #)
+        #self.add_csr('leds')
+
+        # Buttons n KillSwitches ------------------------------------------------------------------
+        #self.submodules.buttons = GPIOIn(
+        #    pads         = platform.request_all('user_btn')
+        #)
+        #self.add_csr('buttons')
+
+        # GPIO I2C
+        #wtf must be an elegant pythonic way to do this junk
+        pins = Record([('scl', 1), ('sda', 1)])
+        pins.scl = i2c_io['scl']
+        pins.sda = i2c_io['sda']
+        #wtf needs to be 'i2c' for bios for now
+        self.submodules.i2c = I2CMaster(pins)
+        self.add_csr('i2c')
+
+        # GPIO UARTs = 2 pins per -----------------------------------------------------------------
+        pins = Record([('rx', 1), ('tx', 1)])
+        pins.rx = uart_0_io['rx']
+        pins.tx = uart_0_io['tx']
+        self.submodules.uart_0_phy = RS232PHY(pins, sys_clk_freq, with_dynamic_baudrate=True)
+        self.add_csr('uart_0_phy')
+        self.submodules.uart_0 = UART(phy=self.uart_0_phy)
+        self.add_csr('uart_0')
+
+        pins = Record([('rx', 1), ('tx', 1)])
+        pins.rx = uart_1_io['tx']
+        pins.tx = uart_1_io['tx']
+        self.submodules.uart_1_phy = RS232PHY(pins, sys_clk_freq, with_dynamic_baudrate=True)
+        self.add_csr('uart_1_phy')
+        self.submodules.uart_1 = UART(phy=self.uart_1_phy)
+        self.add_csr('uart_1')
+
+        # DShot M0:M3 (no telemetry) = 4 pins -----------------------------------------------------
+        #self.submodules.dshot = DShot(dshot_io)
+        #self.add_csr('dshot')
+
+# Build -------------------------------------------------------------------------------------------
+
+def main():
+
+    parser = argparse.ArgumentParser(description='A2P Caravel Test Site')
+
+    builder_args(parser)
+    soc_sdram_args(parser)
+    args = parser.parse_args()
+
+    soc = BaseSoC(**soc_sdram_argdict(args))
+    builder = Builder(soc, **builder_argdict(args))
+
+    soc.build_name = 'wtf' #wtf dont work!
+    builder.build_name = 'wtf' #wtf dont work!
+    builder.compile_software = False
+    builder.csr_csv = 'csr.csv'
+    builder.build(run=False)
+
+if __name__ == "__main__":
+    main()
--- a/build/openroad/litex/build/caravel_user/gateware/caravel_user.tcl
+++ b/build/openroad/litex/build/caravel_user/gateware/caravel_user.tcl
@ -0,0 +1,79 @@
+
+# Create Project
+
+create_project -force -name caravel_user -part xc7a35t-CPG236-1
+set_msg_config -id {Common 17-55} -new_severity {Warning}
+
+# Add Sources
+
+read_verilog {/home/wtf/projects/a2p-opf/build/openroad/litex/momv modules/issiram.v}
+read_verilog {/home/wtf/projects/a2p-opf/build/openroad/litex/a2p/verilog/A2P_WB.v}
+read_verilog {/home/wtf/projects/a2p-opf/build/openroad/litex/build/caravel_user/gateware/caravel_user.v}
+
+# Add EDIFs
+
+
+# Add IPs
+
+
+# Add constraints
+
+read_xdc caravel_user.xdc
+set_property PROCESSING_ORDER EARLY [get_files caravel_user.xdc]
+
+# Add pre-synthesis commands
+
+
+# Synthesis
+
+synth_design -directive default -top caravel_user -part xc7a35t-CPG236-1
+
+# Synthesis report
+
+report_timing_summary -file caravel_user_timing_synth.rpt
+report_utilization -hierarchical -file caravel_user_utilization_hierarchical_synth.rpt
+report_utilization -file caravel_user_utilization_synth.rpt
+
+# Optimize design
+
+opt_design -directive default
+
+# Add pre-placement commands
+
+
+# Placement
+
+place_design -directive default
+
+# Placement report
+
+report_utilization -hierarchical -file caravel_user_utilization_hierarchical_place.rpt
+report_utilization -file caravel_user_utilization_place.rpt
+report_io -file caravel_user_io.rpt
+report_control_sets -verbose -file caravel_user_control_sets.rpt
+report_clock_utilization -file caravel_user_clock_utilization.rpt
+
+# Add pre-routing commands
+
+
+# Routing
+
+route_design -directive default
+phys_opt_design -directive default
+write_checkpoint -force caravel_user_route.dcp
+
+# Routing report
+
+report_timing_summary -no_header -no_detailed_paths
+report_route_status -file caravel_user_route_status.rpt
+report_drc -file caravel_user_drc.rpt
+report_timing_summary -datasheet -max_paths 10 -file caravel_user_timing.rpt
+report_power -file caravel_user_power.rpt
+
+# Bitstream generation
+
+write_bitstream -force caravel_user.bit 
+
+# End
+
+quit
--- a/build/openroad/litex/build/caravel_user/gateware/caravel_user.v
+++ b/build/openroad/litex/build/caravel_user/gateware/caravel_user.v
--- a/build/openroad/litex/build/caravel_user/gateware/caravel_user.xdc
+++ b/build/openroad/litex/build/caravel_user/gateware/caravel_user.xdc
--- a/build/openroad/litex/build/caravel_user/gateware/mem.init
+++ b/build/openroad/litex/build/caravel_user/gateware/mem.init
@ -0,0 +1,42 @@
+41
+32
+50
+20
+43
+61
+72
+61
+76
+65
+6c
+20
+53
+69
+74
+65
+20
+54
+65
+73
+74
+20
+32
+30
+32
+31
+2d
+31
+31
+2d
+32
+35
+20
+31
+33
+3a
+35
+33
+3a
+33
+32
+00
--- a/build/openroad/litex/build/caravel_user/software/include/generated/csr.h
+++ b/build/openroad/litex/build/caravel_user/software/include/generated/csr.h
@ -0,0 +1,591 @@
+//--------------------------------------------------------------------------------
+// Auto-generated by Migen (9a0be7a) & LiteX (85d6cb4b) on 2021-11-25 13:53:32
+//--------------------------------------------------------------------------------
+#include <generated/soc.h>
+#ifndef __GENERATED_CSR_H
+#define __GENERATED_CSR_H
+#include <stdint.h>
+#include <system.h>
+#ifndef CSR_ACCESSORS_DEFINED
+#include <hw/common.h>
+#endif /* ! CSR_ACCESSORS_DEFINED */
+#ifndef CSR_BASE
+#define CSR_BASE 0xfff00000L
+#endif
+
+/* i2c */
+#define CSR_I2C_BASE (CSR_BASE + 0x800L)
+#define CSR_I2C_W_ADDR (CSR_BASE + 0x800L)
+#define CSR_I2C_W_SIZE 1
+static inline uint32_t i2c_w_read(void) {
+	return csr_read_simple(CSR_BASE + 0x800L);
+}
+static inline void i2c_w_write(uint32_t v) {
+	csr_write_simple(v, CSR_BASE + 0x800L);
+}
+#define CSR_I2C_W_SCL_OFFSET 0
+#define CSR_I2C_W_SCL_SIZE 1
+static inline uint32_t i2c_w_scl_extract(uint32_t oldword) {
+	uint32_t mask = ((1 << 1)-1);
+	return ( (oldword >> 0) & mask );
+}
+static inline uint32_t i2c_w_scl_read(void) {
+	uint32_t word = i2c_w_read();
+	return i2c_w_scl_extract(word);
+}
+static inline uint32_t i2c_w_scl_replace(uint32_t oldword, uint32_t plain_value) {
+	uint32_t mask = ((1 << 1)-1);
+	return (oldword & (~(mask << 0))) | (mask & plain_value)<< 0 ;
+}
+static inline void i2c_w_scl_write(uint32_t plain_value) {
+	uint32_t oldword = i2c_w_read();
+	uint32_t newword = i2c_w_scl_replace(oldword, plain_value);
+	i2c_w_write(newword);
+}
+#define CSR_I2C_W_OE_OFFSET 1
+#define CSR_I2C_W_OE_SIZE 1
+static inline uint32_t i2c_w_oe_extract(uint32_t oldword) {
+	uint32_t mask = ((1 << 1)-1);
+	return ( (oldword >> 1) & mask );
+}
+static inline uint32_t i2c_w_oe_read(void) {
+	uint32_t word = i2c_w_read();
+	return i2c_w_oe_extract(word);
+}
+static inline uint32_t i2c_w_oe_replace(uint32_t oldword, uint32_t plain_value) {
+	uint32_t mask = ((1 << 1)-1);
+	return (oldword & (~(mask << 1))) | (mask & plain_value)<< 1 ;
+}
+static inline void i2c_w_oe_write(uint32_t plain_value) {
+	uint32_t oldword = i2c_w_read();
+	uint32_t newword = i2c_w_oe_replace(oldword, plain_value);
+	i2c_w_write(newword);
+}
+#define CSR_I2C_W_SDA_OFFSET 2
+#define CSR_I2C_W_SDA_SIZE 1
+static inline uint32_t i2c_w_sda_extract(uint32_t oldword) {
+	uint32_t mask = ((1 << 1)-1);
+	return ( (oldword >> 2) & mask );
+}
+static inline uint32_t i2c_w_sda_read(void) {
+	uint32_t word = i2c_w_read();
+	return i2c_w_sda_extract(word);
+}
+static inline uint32_t i2c_w_sda_replace(uint32_t oldword, uint32_t plain_value) {
+	uint32_t mask = ((1 << 1)-1);
+	return (oldword & (~(mask << 2))) | (mask & plain_value)<< 2 ;
+}
+static inline void i2c_w_sda_write(uint32_t plain_value) {
+	uint32_t oldword = i2c_w_read();
+	uint32_t newword = i2c_w_sda_replace(oldword, plain_value);
+	i2c_w_write(newword);
+}
+#define CSR_I2C_R_ADDR (CSR_BASE + 0x804L)
+#define CSR_I2C_R_SIZE 1
+static inline uint32_t i2c_r_read(void) {
+	return csr_read_simple(CSR_BASE + 0x804L);
+}
+#define CSR_I2C_R_SDA_OFFSET 0
+#define CSR_I2C_R_SDA_SIZE 1
+static inline uint32_t i2c_r_sda_extract(uint32_t oldword) {
+	uint32_t mask = ((1 << 1)-1);
+	return ( (oldword >> 0) & mask );
+}
+static inline uint32_t i2c_r_sda_read(void) {
+	uint32_t word = i2c_r_read();
+	return i2c_r_sda_extract(word);
+}
+
+/* uart_0_phy */
+#define CSR_UART_0_PHY_BASE (CSR_BASE + 0x1000L)
+#define CSR_UART_0_PHY_TUNING_WORD_ADDR (CSR_BASE + 0x1000L)
+#define CSR_UART_0_PHY_TUNING_WORD_SIZE 1
+static inline uint32_t uart_0_phy_tuning_word_read(void) {
+	return csr_read_simple(CSR_BASE + 0x1000L);
+}
+static inline void uart_0_phy_tuning_word_write(uint32_t v) {
+	csr_write_simple(v, CSR_BASE + 0x1000L);
+}
+
+/* uart_0 */
+#define CSR_UART_0_BASE (CSR_BASE + 0x1800L)
+#define CSR_UART_0_RXTX_ADDR (CSR_BASE + 0x1800L)
+#define CSR_UART_0_RXTX_SIZE 1
+static inline uint32_t uart_0_rxtx_read(void) {
+	return csr_read_simple(CSR_BASE + 0x1800L);
+}
+static inline void uart_0_rxtx_write(uint32_t v) {
+	csr_write_simple(v, CSR_BASE + 0x1800L);
+}
+#define CSR_UART_0_TXFULL_ADDR (CSR_BASE + 0x1804L)
+#define CSR_UART_0_TXFULL_SIZE 1
+static inline uint32_t uart_0_txfull_read(void) {
+	return csr_read_simple(CSR_BASE + 0x1804L);
+}
+#define CSR_UART_0_RXEMPTY_ADDR (CSR_BASE + 0x1808L)
+#define CSR_UART_0_RXEMPTY_SIZE 1
+static inline uint32_t uart_0_rxempty_read(void) {
+	return csr_read_simple(CSR_BASE + 0x1808L);
+}
+#define CSR_UART_0_EV_STATUS_ADDR (CSR_BASE + 0x180cL)
+#define CSR_UART_0_EV_STATUS_SIZE 1
+static inline uint32_t uart_0_ev_status_read(void) {
+	return csr_read_simple(CSR_BASE + 0x180cL);
+}
+#define CSR_UART_0_EV_STATUS_TX_OFFSET 0
+#define CSR_UART_0_EV_STATUS_TX_SIZE 1
+static inline uint32_t uart_0_ev_status_tx_extract(uint32_t oldword) {
+	uint32_t mask = ((1 << 1)-1);
+	return ( (oldword >> 0) & mask );
+}
+static inline uint32_t uart_0_ev_status_tx_read(void) {
+	uint32_t word = uart_0_ev_status_read();
+	return uart_0_ev_status_tx_extract(word);
+}
+#define CSR_UART_0_EV_STATUS_RX_OFFSET 1
+#define CSR_UART_0_EV_STATUS_RX_SIZE 1
+static inline uint32_t uart_0_ev_status_rx_extract(uint32_t oldword) {
+	uint32_t mask = ((1 << 1)-1);
+	return ( (oldword >> 1) & mask );
+}
+static inline uint32_t uart_0_ev_status_rx_read(void) {
+	uint32_t word = uart_0_ev_status_read();
+	return uart_0_ev_status_rx_extract(word);
+}
+#define CSR_UART_0_EV_PENDING_ADDR (CSR_BASE + 0x1810L)
+#define CSR_UART_0_EV_PENDING_SIZE 1
+static inline uint32_t uart_0_ev_pending_read(void) {
+	return csr_read_simple(CSR_BASE + 0x1810L);
+}
+static inline void uart_0_ev_pending_write(uint32_t v) {
+	csr_write_simple(v, CSR_BASE + 0x1810L);
+}
+#define CSR_UART_0_EV_PENDING_TX_OFFSET 0
+#define CSR_UART_0_EV_PENDING_TX_SIZE 1
+static inline uint32_t uart_0_ev_pending_tx_extract(uint32_t oldword) {
+	uint32_t mask = ((1 << 1)-1);
+	return ( (oldword >> 0) & mask );
+}
+static inline uint32_t uart_0_ev_pending_tx_read(void) {
+	uint32_t word = uart_0_ev_pending_read();
+	return uart_0_ev_pending_tx_extract(word);
+}
+static inline uint32_t uart_0_ev_pending_tx_replace(uint32_t oldword, uint32_t plain_value) {
+	uint32_t mask = ((1 << 1)-1);
+	return (oldword & (~(mask << 0))) | (mask & plain_value)<< 0 ;
+}
+static inline void uart_0_ev_pending_tx_write(uint32_t plain_value) {
+	uint32_t oldword = uart_0_ev_pending_read();
+	uint32_t newword = uart_0_ev_pending_tx_replace(oldword, plain_value);
+	uart_0_ev_pending_write(newword);
+}
+#define CSR_UART_0_EV_PENDING_RX_OFFSET 1
+#define CSR_UART_0_EV_PENDING_RX_SIZE 1
+static inline uint32_t uart_0_ev_pending_rx_extract(uint32_t oldword) {
+	uint32_t mask = ((1 << 1)-1);
+	return ( (oldword >> 1) & mask );
+}
+static inline uint32_t uart_0_ev_pending_rx_read(void) {
+	uint32_t word = uart_0_ev_pending_read();
+	return uart_0_ev_pending_rx_extract(word);
+}
+static inline uint32_t uart_0_ev_pending_rx_replace(uint32_t oldword, uint32_t plain_value) {
+	uint32_t mask = ((1 << 1)-1);
+	return (oldword & (~(mask << 1))) | (mask & plain_value)<< 1 ;
+}
+static inline void uart_0_ev_pending_rx_write(uint32_t plain_value) {
+	uint32_t oldword = uart_0_ev_pending_read();
+	uint32_t newword = uart_0_ev_pending_rx_replace(oldword, plain_value);
+	uart_0_ev_pending_write(newword);
+}
+#define CSR_UART_0_EV_ENABLE_ADDR (CSR_BASE + 0x1814L)
+#define CSR_UART_0_EV_ENABLE_SIZE 1
+static inline uint32_t uart_0_ev_enable_read(void) {
+	return csr_read_simple(CSR_BASE + 0x1814L);
+}
+static inline void uart_0_ev_enable_write(uint32_t v) {
+	csr_write_simple(v, CSR_BASE + 0x1814L);
+}
+#define CSR_UART_0_EV_ENABLE_TX_OFFSET 0
+#define CSR_UART_0_EV_ENABLE_TX_SIZE 1
+static inline uint32_t uart_0_ev_enable_tx_extract(uint32_t oldword) {
+	uint32_t mask = ((1 << 1)-1);
+	return ( (oldword >> 0) & mask );
+}
+static inline uint32_t uart_0_ev_enable_tx_read(void) {
+	uint32_t word = uart_0_ev_enable_read();
+	return uart_0_ev_enable_tx_extract(word);
+}
+static inline uint32_t uart_0_ev_enable_tx_replace(uint32_t oldword, uint32_t plain_value) {
+	uint32_t mask = ((1 << 1)-1);
+	return (oldword & (~(mask << 0))) | (mask & plain_value)<< 0 ;
+}
+static inline void uart_0_ev_enable_tx_write(uint32_t plain_value) {
+	uint32_t oldword = uart_0_ev_enable_read();
+	uint32_t newword = uart_0_ev_enable_tx_replace(oldword, plain_value);
+	uart_0_ev_enable_write(newword);
+}
+#define CSR_UART_0_EV_ENABLE_RX_OFFSET 1
+#define CSR_UART_0_EV_ENABLE_RX_SIZE 1
+static inline uint32_t uart_0_ev_enable_rx_extract(uint32_t oldword) {
+	uint32_t mask = ((1 << 1)-1);
+	return ( (oldword >> 1) & mask );
+}
+static inline uint32_t uart_0_ev_enable_rx_read(void) {
+	uint32_t word = uart_0_ev_enable_read();
+	return uart_0_ev_enable_rx_extract(word);
+}
+static inline uint32_t uart_0_ev_enable_rx_replace(uint32_t oldword, uint32_t plain_value) {
+	uint32_t mask = ((1 << 1)-1);
+	return (oldword & (~(mask << 1))) | (mask & plain_value)<< 1 ;
+}
+static inline void uart_0_ev_enable_rx_write(uint32_t plain_value) {
+	uint32_t oldword = uart_0_ev_enable_read();
+	uint32_t newword = uart_0_ev_enable_rx_replace(oldword, plain_value);
+	uart_0_ev_enable_write(newword);
+}
+#define CSR_UART_0_TXEMPTY_ADDR (CSR_BASE + 0x1818L)
+#define CSR_UART_0_TXEMPTY_SIZE 1
+static inline uint32_t uart_0_txempty_read(void) {
+	return csr_read_simple(CSR_BASE + 0x1818L);
+}
+#define CSR_UART_0_RXFULL_ADDR (CSR_BASE + 0x181cL)
+#define CSR_UART_0_RXFULL_SIZE 1
+static inline uint32_t uart_0_rxfull_read(void) {
+	return csr_read_simple(CSR_BASE + 0x181cL);
+}
+
+/* uart_1_phy */
+#define CSR_UART_1_PHY_BASE (CSR_BASE + 0x2000L)
+#define CSR_UART_1_PHY_TUNING_WORD_ADDR (CSR_BASE + 0x2000L)
+#define CSR_UART_1_PHY_TUNING_WORD_SIZE 1
+static inline uint32_t uart_1_phy_tuning_word_read(void) {
+	return csr_read_simple(CSR_BASE + 0x2000L);
+}
+static inline void uart_1_phy_tuning_word_write(uint32_t v) {
+	csr_write_simple(v, CSR_BASE + 0x2000L);
+}
+
+/* uart_1 */
+#define CSR_UART_1_BASE (CSR_BASE + 0x2800L)
+#define CSR_UART_1_RXTX_ADDR (CSR_BASE + 0x2800L)
+#define CSR_UART_1_RXTX_SIZE 1
+static inline uint32_t uart_1_rxtx_read(void) {
+	return csr_read_simple(CSR_BASE + 0x2800L);
+}
+static inline void uart_1_rxtx_write(uint32_t v) {
+	csr_write_simple(v, CSR_BASE + 0x2800L);
+}
+#define CSR_UART_1_TXFULL_ADDR (CSR_BASE + 0x2804L)
+#define CSR_UART_1_TXFULL_SIZE 1
+static inline uint32_t uart_1_txfull_read(void) {
+	return csr_read_simple(CSR_BASE + 0x2804L);
+}
+#define CSR_UART_1_RXEMPTY_ADDR (CSR_BASE + 0x2808L)
+#define CSR_UART_1_RXEMPTY_SIZE 1
+static inline uint32_t uart_1_rxempty_read(void) {
+	return csr_read_simple(CSR_BASE + 0x2808L);
+}
+#define CSR_UART_1_EV_STATUS_ADDR (CSR_BASE + 0x280cL)
+#define CSR_UART_1_EV_STATUS_SIZE 1
+static inline uint32_t uart_1_ev_status_read(void) {
+	return csr_read_simple(CSR_BASE + 0x280cL);
+}
+#define CSR_UART_1_EV_STATUS_TX_OFFSET 0
+#define CSR_UART_1_EV_STATUS_TX_SIZE 1
+static inline uint32_t uart_1_ev_status_tx_extract(uint32_t oldword) {
+	uint32_t mask = ((1 << 1)-1);
+	return ( (oldword >> 0) & mask );
+}
+static inline uint32_t uart_1_ev_status_tx_read(void) {
+	uint32_t word = uart_1_ev_status_read();
+	return uart_1_ev_status_tx_extract(word);
+}
+#define CSR_UART_1_EV_STATUS_RX_OFFSET 1
+#define CSR_UART_1_EV_STATUS_RX_SIZE 1
+static inline uint32_t uart_1_ev_status_rx_extract(uint32_t oldword) {
+	uint32_t mask = ((1 << 1)-1);
+	return ( (oldword >> 1) & mask );
+}
+static inline uint32_t uart_1_ev_status_rx_read(void) {
+	uint32_t word = uart_1_ev_status_read();
+	return uart_1_ev_status_rx_extract(word);
+}
+#define CSR_UART_1_EV_PENDING_ADDR (CSR_BASE + 0x2810L)
+#define CSR_UART_1_EV_PENDING_SIZE 1
+static inline uint32_t uart_1_ev_pending_read(void) {
+	return csr_read_simple(CSR_BASE + 0x2810L);
+}
+static inline void uart_1_ev_pending_write(uint32_t v) {
+	csr_write_simple(v, CSR_BASE + 0x2810L);
+}
+#define CSR_UART_1_EV_PENDING_TX_OFFSET 0
+#define CSR_UART_1_EV_PENDING_TX_SIZE 1
+static inline uint32_t uart_1_ev_pending_tx_extract(uint32_t oldword) {
+	uint32_t mask = ((1 << 1)-1);
+	return ( (oldword >> 0) & mask );
+}
+static inline uint32_t uart_1_ev_pending_tx_read(void) {
+	uint32_t word = uart_1_ev_pending_read();
+	return uart_1_ev_pending_tx_extract(word);
+}
+static inline uint32_t uart_1_ev_pending_tx_replace(uint32_t oldword, uint32_t plain_value) {
+	uint32_t mask = ((1 << 1)-1);
+	return (oldword & (~(mask << 0))) | (mask & plain_value)<< 0 ;
+}
+static inline void uart_1_ev_pending_tx_write(uint32_t plain_value) {
+	uint32_t oldword = uart_1_ev_pending_read();
+	uint32_t newword = uart_1_ev_pending_tx_replace(oldword, plain_value);
+	uart_1_ev_pending_write(newword);
+}
+#define CSR_UART_1_EV_PENDING_RX_OFFSET 1
+#define CSR_UART_1_EV_PENDING_RX_SIZE 1
+static inline uint32_t uart_1_ev_pending_rx_extract(uint32_t oldword) {
+	uint32_t mask = ((1 << 1)-1);
+	return ( (oldword >> 1) & mask );
+}
+static inline uint32_t uart_1_ev_pending_rx_read(void) {
+	uint32_t word = uart_1_ev_pending_read();
+	return uart_1_ev_pending_rx_extract(word);
+}
+static inline uint32_t uart_1_ev_pending_rx_replace(uint32_t oldword, uint32_t plain_value) {
+	uint32_t mask = ((1 << 1)-1);
+	return (oldword & (~(mask << 1))) | (mask & plain_value)<< 1 ;
+}
+static inline void uart_1_ev_pending_rx_write(uint32_t plain_value) {
+	uint32_t oldword = uart_1_ev_pending_read();
+	uint32_t newword = uart_1_ev_pending_rx_replace(oldword, plain_value);
+	uart_1_ev_pending_write(newword);
+}
+#define CSR_UART_1_EV_ENABLE_ADDR (CSR_BASE + 0x2814L)
+#define CSR_UART_1_EV_ENABLE_SIZE 1
+static inline uint32_t uart_1_ev_enable_read(void) {
+	return csr_read_simple(CSR_BASE + 0x2814L);
+}
+static inline void uart_1_ev_enable_write(uint32_t v) {
+	csr_write_simple(v, CSR_BASE + 0x2814L);
+}
+#define CSR_UART_1_EV_ENABLE_TX_OFFSET 0
+#define CSR_UART_1_EV_ENABLE_TX_SIZE 1
+static inline uint32_t uart_1_ev_enable_tx_extract(uint32_t oldword) {
+	uint32_t mask = ((1 << 1)-1);
+	return ( (oldword >> 0) & mask );
+}
+static inline uint32_t uart_1_ev_enable_tx_read(void) {
+	uint32_t word = uart_1_ev_enable_read();
+	return uart_1_ev_enable_tx_extract(word);
+}
+static inline uint32_t uart_1_ev_enable_tx_replace(uint32_t oldword, uint32_t plain_value) {
+	uint32_t mask = ((1 << 1)-1);
+	return (oldword & (~(mask << 0))) | (mask & plain_value)<< 0 ;
+}
+static inline void uart_1_ev_enable_tx_write(uint32_t plain_value) {
+	uint32_t oldword = uart_1_ev_enable_read();
+	uint32_t newword = uart_1_ev_enable_tx_replace(oldword, plain_value);
+	uart_1_ev_enable_write(newword);
+}
+#define CSR_UART_1_EV_ENABLE_RX_OFFSET 1
+#define CSR_UART_1_EV_ENABLE_RX_SIZE 1
+static inline uint32_t uart_1_ev_enable_rx_extract(uint32_t oldword) {
+	uint32_t mask = ((1 << 1)-1);
+	return ( (oldword >> 1) & mask );
+}
+static inline uint32_t uart_1_ev_enable_rx_read(void) {
+	uint32_t word = uart_1_ev_enable_read();
+	return uart_1_ev_enable_rx_extract(word);
+}
+static inline uint32_t uart_1_ev_enable_rx_replace(uint32_t oldword, uint32_t plain_value) {
+	uint32_t mask = ((1 << 1)-1);
+	return (oldword & (~(mask << 1))) | (mask & plain_value)<< 1 ;
+}
+static inline void uart_1_ev_enable_rx_write(uint32_t plain_value) {
+	uint32_t oldword = uart_1_ev_enable_read();
+	uint32_t newword = uart_1_ev_enable_rx_replace(oldword, plain_value);
+	uart_1_ev_enable_write(newword);
+}
+#define CSR_UART_1_TXEMPTY_ADDR (CSR_BASE + 0x2818L)
+#define CSR_UART_1_TXEMPTY_SIZE 1
+static inline uint32_t uart_1_txempty_read(void) {
+	return csr_read_simple(CSR_BASE + 0x2818L);
+}
+#define CSR_UART_1_RXFULL_ADDR (CSR_BASE + 0x281cL)
+#define CSR_UART_1_RXFULL_SIZE 1
+static inline uint32_t uart_1_rxfull_read(void) {
+	return csr_read_simple(CSR_BASE + 0x281cL);
+}
+
+/* ctrl */
+#define CSR_CTRL_BASE (CSR_BASE + 0x3000L)
+#define CSR_CTRL_RESET_ADDR (CSR_BASE + 0x3000L)
+#define CSR_CTRL_RESET_SIZE 1
+static inline uint32_t ctrl_reset_read(void) {
+	return csr_read_simple(CSR_BASE + 0x3000L);
+}
+static inline void ctrl_reset_write(uint32_t v) {
+	csr_write_simple(v, CSR_BASE + 0x3000L);
+}
+#define CSR_CTRL_RESET_SOC_RST_OFFSET 0
+#define CSR_CTRL_RESET_SOC_RST_SIZE 1
+static inline uint32_t ctrl_reset_soc_rst_extract(uint32_t oldword) {
+	uint32_t mask = ((1 << 1)-1);
+	return ( (oldword >> 0) & mask );
+}
+static inline uint32_t ctrl_reset_soc_rst_read(void) {
+	uint32_t word = ctrl_reset_read();
+	return ctrl_reset_soc_rst_extract(word);
+}
+static inline uint32_t ctrl_reset_soc_rst_replace(uint32_t oldword, uint32_t plain_value) {
+	uint32_t mask = ((1 << 1)-1);
+	return (oldword & (~(mask << 0))) | (mask & plain_value)<< 0 ;
+}
+static inline void ctrl_reset_soc_rst_write(uint32_t plain_value) {
+	uint32_t oldword = ctrl_reset_read();
+	uint32_t newword = ctrl_reset_soc_rst_replace(oldword, plain_value);
+	ctrl_reset_write(newword);
+}
+#define CSR_CTRL_RESET_CPU_RST_OFFSET 1
+#define CSR_CTRL_RESET_CPU_RST_SIZE 1
+static inline uint32_t ctrl_reset_cpu_rst_extract(uint32_t oldword) {
+	uint32_t mask = ((1 << 1)-1);
+	return ( (oldword >> 1) & mask );
+}
+static inline uint32_t ctrl_reset_cpu_rst_read(void) {
+	uint32_t word = ctrl_reset_read();
+	return ctrl_reset_cpu_rst_extract(word);
+}
+static inline uint32_t ctrl_reset_cpu_rst_replace(uint32_t oldword, uint32_t plain_value) {
+	uint32_t mask = ((1 << 1)-1);
+	return (oldword & (~(mask << 1))) | (mask & plain_value)<< 1 ;
+}
+static inline void ctrl_reset_cpu_rst_write(uint32_t plain_value) {
+	uint32_t oldword = ctrl_reset_read();
+	uint32_t newword = ctrl_reset_cpu_rst_replace(oldword, plain_value);
+	ctrl_reset_write(newword);
+}
+#define CSR_CTRL_SCRATCH_ADDR (CSR_BASE + 0x3004L)
+#define CSR_CTRL_SCRATCH_SIZE 1
+static inline uint32_t ctrl_scratch_read(void) {
+	return csr_read_simple(CSR_BASE + 0x3004L);
+}
+static inline void ctrl_scratch_write(uint32_t v) {
+	csr_write_simple(v, CSR_BASE + 0x3004L);
+}
+#define CSR_CTRL_BUS_ERRORS_ADDR (CSR_BASE + 0x3008L)
+#define CSR_CTRL_BUS_ERRORS_SIZE 1
+static inline uint32_t ctrl_bus_errors_read(void) {
+	return csr_read_simple(CSR_BASE + 0x3008L);
+}
+
+/* identifier_mem */
+#define CSR_IDENTIFIER_MEM_BASE (CSR_BASE + 0x3800L)
+
+/* timer0 */
+#define CSR_TIMER0_BASE (CSR_BASE + 0x4000L)
+#define CSR_TIMER0_LOAD_ADDR (CSR_BASE + 0x4000L)
+#define CSR_TIMER0_LOAD_SIZE 1
+static inline uint32_t timer0_load_read(void) {
+	return csr_read_simple(CSR_BASE + 0x4000L);
+}
+static inline void timer0_load_write(uint32_t v) {
+	csr_write_simple(v, CSR_BASE + 0x4000L);
+}
+#define CSR_TIMER0_RELOAD_ADDR (CSR_BASE + 0x4004L)
+#define CSR_TIMER0_RELOAD_SIZE 1
+static inline uint32_t timer0_reload_read(void) {
+	return csr_read_simple(CSR_BASE + 0x4004L);
+}
+static inline void timer0_reload_write(uint32_t v) {
+	csr_write_simple(v, CSR_BASE + 0x4004L);
+}
+#define CSR_TIMER0_EN_ADDR (CSR_BASE + 0x4008L)
+#define CSR_TIMER0_EN_SIZE 1
+static inline uint32_t timer0_en_read(void) {
+	return csr_read_simple(CSR_BASE + 0x4008L);
+}
+static inline void timer0_en_write(uint32_t v) {
+	csr_write_simple(v, CSR_BASE + 0x4008L);
+}
+#define CSR_TIMER0_UPDATE_VALUE_ADDR (CSR_BASE + 0x400cL)
+#define CSR_TIMER0_UPDATE_VALUE_SIZE 1
+static inline uint32_t timer0_update_value_read(void) {
+	return csr_read_simple(CSR_BASE + 0x400cL);
+}
+static inline void timer0_update_value_write(uint32_t v) {
+	csr_write_simple(v, CSR_BASE + 0x400cL);
+}
+#define CSR_TIMER0_VALUE_ADDR (CSR_BASE + 0x4010L)
+#define CSR_TIMER0_VALUE_SIZE 1
+static inline uint32_t timer0_value_read(void) {
+	return csr_read_simple(CSR_BASE + 0x4010L);
+}
+#define CSR_TIMER0_EV_STATUS_ADDR (CSR_BASE + 0x4014L)
+#define CSR_TIMER0_EV_STATUS_SIZE 1
+static inline uint32_t timer0_ev_status_read(void) {
+	return csr_read_simple(CSR_BASE + 0x4014L);
+}
+#define CSR_TIMER0_EV_STATUS_ZERO_OFFSET 0
+#define CSR_TIMER0_EV_STATUS_ZERO_SIZE 1
+static inline uint32_t timer0_ev_status_zero_extract(uint32_t oldword) {
+	uint32_t mask = ((1 << 1)-1);
+	return ( (oldword >> 0) & mask );
+}
+static inline uint32_t timer0_ev_status_zero_read(void) {
+	uint32_t word = timer0_ev_status_read();
+	return timer0_ev_status_zero_extract(word);
+}
+#define CSR_TIMER0_EV_PENDING_ADDR (CSR_BASE + 0x4018L)
+#define CSR_TIMER0_EV_PENDING_SIZE 1
+static inline uint32_t timer0_ev_pending_read(void) {
+	return csr_read_simple(CSR_BASE + 0x4018L);
+}
+static inline void timer0_ev_pending_write(uint32_t v) {
+	csr_write_simple(v, CSR_BASE + 0x4018L);
+}
+#define CSR_TIMER0_EV_PENDING_ZERO_OFFSET 0
+#define CSR_TIMER0_EV_PENDING_ZERO_SIZE 1
+static inline uint32_t timer0_ev_pending_zero_extract(uint32_t oldword) {
+	uint32_t mask = ((1 << 1)-1);
+	return ( (oldword >> 0) & mask );
+}
+static inline uint32_t timer0_ev_pending_zero_read(void) {
+	uint32_t word = timer0_ev_pending_read();
+	return timer0_ev_pending_zero_extract(word);
+}
+static inline uint32_t timer0_ev_pending_zero_replace(uint32_t oldword, uint32_t plain_value) {
+	uint32_t mask = ((1 << 1)-1);
+	return (oldword & (~(mask << 0))) | (mask & plain_value)<< 0 ;
+}
+static inline void timer0_ev_pending_zero_write(uint32_t plain_value) {
+	uint32_t oldword = timer0_ev_pending_read();
+	uint32_t newword = timer0_ev_pending_zero_replace(oldword, plain_value);
+	timer0_ev_pending_write(newword);
+}
+#define CSR_TIMER0_EV_ENABLE_ADDR (CSR_BASE + 0x401cL)
+#define CSR_TIMER0_EV_ENABLE_SIZE 1
+static inline uint32_t timer0_ev_enable_read(void) {
+	return csr_read_simple(CSR_BASE + 0x401cL);
+}
+static inline void timer0_ev_enable_write(uint32_t v) {
+	csr_write_simple(v, CSR_BASE + 0x401cL);
+}
+#define CSR_TIMER0_EV_ENABLE_ZERO_OFFSET 0
+#define CSR_TIMER0_EV_ENABLE_ZERO_SIZE 1
+static inline uint32_t timer0_ev_enable_zero_extract(uint32_t oldword) {
+	uint32_t mask = ((1 << 1)-1);
+	return ( (oldword >> 0) & mask );
+}
+static inline uint32_t timer0_ev_enable_zero_read(void) {
+	uint32_t word = timer0_ev_enable_read();
+	return timer0_ev_enable_zero_extract(word);
+}
+static inline uint32_t timer0_ev_enable_zero_replace(uint32_t oldword, uint32_t plain_value) {
+	uint32_t mask = ((1 << 1)-1);
+	return (oldword & (~(mask << 0))) | (mask & plain_value)<< 0 ;
+}
+static inline void timer0_ev_enable_zero_write(uint32_t plain_value) {
+	uint32_t oldword = timer0_ev_enable_read();
+	uint32_t newword = timer0_ev_enable_zero_replace(oldword, plain_value);
+	timer0_ev_enable_write(newword);
+}
+
+#endif
--- a/build/openroad/litex/build/caravel_user/software/include/generated/git.h
+++ b/build/openroad/litex/build/caravel_user/software/include/generated/git.h
@ -0,0 +1,9 @@
+//--------------------------------------------------------------------------------
+// Auto-generated by Migen (9a0be7a) & LiteX (85d6cb4b) on 2021-11-25 13:53:32
+//--------------------------------------------------------------------------------
+#ifndef __GENERATED_GIT_H
+#define __GENERATED_GIT_H
+
+#define MIGEN_GIT_SHA1 "9a0be7a"
+#define LITEX_GIT_SHA1 "85d6cb4b"
+#endif
--- a/build/openroad/litex/build/caravel_user/software/include/generated/mem.h
+++ b/build/openroad/litex/build/caravel_user/software/include/generated/mem.h
@ -0,0 +1,20 @@
+//--------------------------------------------------------------------------------
+// Auto-generated by Migen (9a0be7a) & LiteX (85d6cb4b) on 2021-11-25 13:53:32
+//--------------------------------------------------------------------------------
+#ifndef __GENERATED_MEM_H
+#define __GENERATED_MEM_H
+
+#ifndef SRAM_BASE
+#define SRAM_BASE 0x00000000L
+#define SRAM_SIZE 0x00080000
+#endif
+
+#ifndef CSR_BASE
+#define CSR_BASE 0xfff00000L
+#define CSR_SIZE 0x00010000
+#endif
+
+#ifndef MEM_REGIONS
+#define MEM_REGIONS "SRAM      0x00000000 0x80000 \nCSR       0xfff00000 0x10000 "
+#endif
+#endif
--- a/build/openroad/litex/build/caravel_user/software/include/generated/output_format.ld
+++ b/build/openroad/litex/build/caravel_user/software/include/generated/output_format.ld
@ -0,0 +1 @@
+OUTPUT_FORMAT("elf32-powerpc")
--- a/build/openroad/litex/build/caravel_user/software/include/generated/regions.ld
+++ b/build/openroad/litex/build/caravel_user/software/include/generated/regions.ld
@ -0,0 +1,4 @@
+MEMORY {
+	sram : ORIGIN = 0x00000000, LENGTH = 0x00080000
+	csr : ORIGIN = 0xfff00000, LENGTH = 0x00010000
+}
--- a/build/openroad/litex/build/caravel_user/software/include/generated/soc.h
+++ b/build/openroad/litex/build/caravel_user/software/include/generated/soc.h
@ -0,0 +1,55 @@
+//--------------------------------------------------------------------------------
+// Auto-generated by Migen (9a0be7a) & LiteX (85d6cb4b) on 2021-11-25 13:53:32
+//--------------------------------------------------------------------------------
+#ifndef __GENERATED_SOC_H
+#define __GENERATED_SOC_H
+#define CONFIG_CLOCK_FREQUENCY 50000000
+#define CONFIG_CPU_HAS_INTERRUPT
+#define CONFIG_CPU_RESET_ADDR 0
+#define CONFIG_CPU_TYPE_A2P
+#define CONFIG_CPU_VARIANT_STANDARD
+#define CONFIG_CPU_HUMAN_NAME "A2P_WB"
+#define CONFIG_CPU_NOP "nop"
+#define CONFIG_WITH_BUILD_TIME
+#define UART_POLLING
+#define CONFIG_CSR_DATA_WIDTH 32
+#define CONFIG_CSR_ALIGNMENT 32
+#define CONFIG_BUS_STANDARD "WISHBONE"
+#define CONFIG_BUS_DATA_WIDTH 32
+#define CONFIG_BUS_ADDRESS_WIDTH 32
+#define TIMER0_INTERRUPT 0
+
+#ifndef __ASSEMBLER__
+static inline int config_clock_frequency_read(void) {
+	return 50000000;
+}
+static inline int config_cpu_reset_addr_read(void) {
+	return 0;
+}
+static inline const char * config_cpu_human_name_read(void) {
+	return "A2P_WB";
+}
+static inline const char * config_cpu_nop_read(void) {
+	return "nop";
+}
+static inline int config_csr_data_width_read(void) {
+	return 32;
+}
+static inline int config_csr_alignment_read(void) {
+	return 32;
+}
+static inline const char * config_bus_standard_read(void) {
+	return "WISHBONE";
+}
+static inline int config_bus_data_width_read(void) {
+	return 32;
+}
+static inline int config_bus_address_width_read(void) {
+	return 32;
+}
+static inline int timer0_interrupt_read(void) {
+	return 0;
+}
+#endif // !__ASSEMBLER__
+
+#endif
--- a/build/openroad/litex/build/caravel_user/software/include/generated/variables.mak
+++ b/build/openroad/litex/build/caravel_user/software/include/generated/variables.mak
@ -0,0 +1,25 @@
+PACKAGES=libc libcompiler_rt libbase libfatfs liblitespi liblitedram libliteeth liblitesdcard liblitesata bios
+PACKAGE_DIRS=/home/wtf/projects/litex/litex/soc/software/libc /home/wtf/projects/litex/litex/soc/software/libcompiler_rt /home/wtf/projects/litex/litex/soc/software/libbase /home/wtf/projects/litex/litex/soc/software/libfatfs /home/wtf/projects/litex/litex/soc/software/liblitespi /home/wtf/projects/litex/litex/soc/software/liblitedram /home/wtf/projects/litex/litex/soc/software/libliteeth /home/wtf/projects/litex/litex/soc/software/liblitesdcard /home/wtf/projects/litex/litex/soc/software/liblitesata /home/wtf/projects/litex/litex/soc/software/bios
+LIBS=libc libcompiler_rt libbase libfatfs liblitespi liblitedram libliteeth liblitesdcard liblitesata
+TRIPLE=--not-found--
+CPU=a2p
+CPUFAMILY=ppc32
+CPUFLAGS=-fomit-frame-pointer -Wall -fno-builtin -nostdinc -fno-stack-protector -fexceptions -Wstrict-prototypes -Wold-style-definition -Wmissing-prototypes -D__a2p__
+CPUENDIANNESS=big
+CLANG=0
+CPU_DIRECTORY=/home/wtf/projects/a2p-opf/build/openroad/litex/a2p
+SOC_DIRECTORY=/home/wtf/projects/litex/litex/soc
+PICOLIBC_DIRECTORY=/home/wtf/projects/pythondata-software-picolibc/pythondata_software_picolibc/data
+COMPILER_RT_DIRECTORY=/home/wtf/projects/pythondata-software-compiler_rt/pythondata_software_compiler_rt/data
+export BUILDINC_DIRECTORY
+BUILDINC_DIRECTORY=/home/wtf/projects/a2p-opf/build/openroad/litex/build/caravel_user/software/include
+LIBC_DIRECTORY=/home/wtf/projects/litex/litex/soc/software/libc
+LIBCOMPILER_RT_DIRECTORY=/home/wtf/projects/litex/litex/soc/software/libcompiler_rt
+LIBBASE_DIRECTORY=/home/wtf/projects/litex/litex/soc/software/libbase
+LIBFATFS_DIRECTORY=/home/wtf/projects/litex/litex/soc/software/libfatfs
+LIBLITESPI_DIRECTORY=/home/wtf/projects/litex/litex/soc/software/liblitespi
+LIBLITEDRAM_DIRECTORY=/home/wtf/projects/litex/litex/soc/software/liblitedram
+LIBLITEETH_DIRECTORY=/home/wtf/projects/litex/litex/soc/software/libliteeth
+LIBLITESDCARD_DIRECTORY=/home/wtf/projects/litex/litex/soc/software/liblitesdcard
+LIBLITESATA_DIRECTORY=/home/wtf/projects/litex/litex/soc/software/liblitesata
+BIOS_DIRECTORY=/home/wtf/projects/litex/litex/soc/software/bios
--- a/build/openroad/litex/caravel_user.v
+++ b/build/openroad/litex/caravel_user.v
--- a/build/openroad/litex/config.mk
+++ b/build/openroad/litex/config.mk
@ -0,0 +1,49 @@
+# design and tech
+export DESIGN_NICKNAME = a2p_litex
+export DESIGN_NAME = top
+export PLATFORM = sky130hd
+
+export VERILOG_FILES := $(sort $(wildcard ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/src/*.v) \
+                               ./designs//$(PLATFORM)/$(DESIGN_NICKNAME)/litex/caravel_user.v \
+                               ./designs//$(PLATFORM)/$(DESIGN_NICKNAME)/litex/modules/issiram.v \
+										 )
+export SDC_FILE := ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc
+
+$(info Source files:)
+$(info $(VERILOG_FILES))
+$(info ..................................................)
+
+# design and tech
+unit = a2p
+
+export DIE_AREA    = 0.0 0.0 5200 4609.14
+export CORE_AREA   = 210 210 4990 4389.14
+
+export ABC_CLOCK_PERIOD_IN_PS = 10000
+export ABC_DRIVER_CELL = sky130_fd_sc_hd__buf_1
+export ABC_LOAD_IN_FF = 3
+
+export SYNTH_MAX_FANOUT ?= 32
+export SYNTH_MAX_TRAN ?= 100
+
+export REPORT_SLACK_MAX_PATHS ?= 100
+
+#HACK! uniquify logs, objects, reports, results
+#wtf need to fix to all be in one timestamped dir
+export DESIGN_NICKNAME := $(DESIGN_NICKNAME)/output/$(shell date "+%Y%m%d%H%M%S")
+$(info [WTF] Output Dirs: $(DESIGN_NICKNAME))
+
+
+# ----------------------------------------------------------------------------------
+# ----------------------------------------------------------------------------------
+# CTS
+
+# forget about this for now - occurred when added dffram dir/caches.  anton says hold misses are fake anyway :)
+# do i need something else from dffram build?
+# Repair hold violations...
+# [INFO RSZ-0046] Found 60472 endpoints with hold violations.
+# [WARNING RSZ-0066] Unable to repair all hold violations.
+# [INFO RSZ-0032] Inserted 213923 hold buffers.
+# [ERROR DPL-0019] detailed placement failed on hold33177
+# continue if cts wants to barf...
+export WTF_CTS_IGNORE_HOLD_MISSES = 1
--- a/build/openroad/litex/constraint.sdc
+++ b/build/openroad/litex/constraint.sdc
@ -0,0 +1,32 @@
+# A2P single-core with DFFRAM gpr, icdir, icdata, dcdir, dcdata gen'd by Litex
+
+# ----------------------------------------------------------------------------------
+# define clock
+
+set clk_name wbs_clk_i
+# set clk_period 50.0            ;# make it easy for or
+#set clk_period 10.0             ;# 100Mhz
+#set clk_period 25.0             ;# 40Mhz
+set clk_period 40.0             ;# 25Mhz
+
+puts "\[WTF\] clk_period=$clk_period"
+
+set clkPort [get_ports $clk_name]
+create_clock $clkPort -name clk -period $clk_period
+
+# ----------------------------------------------------------------------------------
+# apply clock to ins and outs
+
+set input_delay_value   0.0
+set output_delay_value  0.0
+
+set clk_index [lsearch [all_inputs] $clkPort]
+set all_inputs_wo_clk [lreplace [all_inputs] $clk_index $clk_index]
+set_input_delay $input_delay_value -clock [get_clocks clk] $all_inputs_wo_clk
+set_output_delay $output_delay_value -clock [get_clocks clk] [all_outputs]
+
+# ----------------------------------------------------------------------------------
+# false paths
+
+set_false_path -from [get_ports {wbs_rst_i}] -to [get_clocks clk]
+#set_false_path -from [get_ports {externalResetVector}] -to [get_clocks clk]
--- a/build/openroad/litex/csr.csv
+++ b/build/openroad/litex/csr.csv
@ -0,0 +1,59 @@
+#--------------------------------------------------------------------------------
+# Auto-generated by Migen (9a0be7a) & LiteX (85d6cb4b) on 2021-11-25 13:53:32
+#--------------------------------------------------------------------------------
+csr_base,i2c,0xfff00800,,
+csr_base,uart_0_phy,0xfff01000,,
+csr_base,uart_0,0xfff01800,,
+csr_base,uart_1_phy,0xfff02000,,
+csr_base,uart_1,0xfff02800,,
+csr_base,ctrl,0xfff03000,,
+csr_base,identifier_mem,0xfff03800,,
+csr_base,timer0,0xfff04000,,
+csr_register,i2c_w,0xfff00800,1,rw
+csr_register,i2c_r,0xfff00804,1,ro
+csr_register,uart_0_phy_tuning_word,0xfff01000,1,rw
+csr_register,uart_0_rxtx,0xfff01800,1,rw
+csr_register,uart_0_txfull,0xfff01804,1,ro
+csr_register,uart_0_rxempty,0xfff01808,1,ro
+csr_register,uart_0_ev_status,0xfff0180c,1,ro
+csr_register,uart_0_ev_pending,0xfff01810,1,rw
+csr_register,uart_0_ev_enable,0xfff01814,1,rw
+csr_register,uart_0_txempty,0xfff01818,1,ro
+csr_register,uart_0_rxfull,0xfff0181c,1,ro
+csr_register,uart_1_phy_tuning_word,0xfff02000,1,rw
+csr_register,uart_1_rxtx,0xfff02800,1,rw
+csr_register,uart_1_txfull,0xfff02804,1,ro
+csr_register,uart_1_rxempty,0xfff02808,1,ro
+csr_register,uart_1_ev_status,0xfff0280c,1,ro
+csr_register,uart_1_ev_pending,0xfff02810,1,rw
+csr_register,uart_1_ev_enable,0xfff02814,1,rw
+csr_register,uart_1_txempty,0xfff02818,1,ro
+csr_register,uart_1_rxfull,0xfff0281c,1,ro
+csr_register,ctrl_reset,0xfff03000,1,rw
+csr_register,ctrl_scratch,0xfff03004,1,rw
+csr_register,ctrl_bus_errors,0xfff03008,1,ro
+csr_register,timer0_load,0xfff04000,1,rw
+csr_register,timer0_reload,0xfff04004,1,rw
+csr_register,timer0_en,0xfff04008,1,rw
+csr_register,timer0_update_value,0xfff0400c,1,rw
+csr_register,timer0_value,0xfff04010,1,ro
+csr_register,timer0_ev_status,0xfff04014,1,ro
+csr_register,timer0_ev_pending,0xfff04018,1,rw
+csr_register,timer0_ev_enable,0xfff0401c,1,rw
+constant,config_clock_frequency,50000000,,
+constant,config_cpu_has_interrupt,None,,
+constant,config_cpu_reset_addr,0,,
+constant,config_cpu_type_a2p,None,,
+constant,config_cpu_variant_standard,None,,
+constant,config_cpu_human_name,a2p_wb,,
+constant,config_cpu_nop,nop,,
+constant,config_with_build_time,None,,
+constant,uart_polling,None,,
+constant,config_csr_data_width,32,,
+constant,config_csr_alignment,32,,
+constant,config_bus_standard,wishbone,,
+constant,config_bus_data_width,32,,
+constant,config_bus_address_width,32,,
+constant,timer0_interrupt,0,,
+memory_region,sram,0x00000000,524288,cached
+memory_region,csr,0xfff00000,65536,io
--- a/build/openroad/litex/mem.init
+++ b/build/openroad/litex/mem.init
@ -0,0 +1,42 @@
+41
+32
+50
+20
+43
+61
+72
+61
+76
+65
+6c
+20
+53
+69
+74
+65
+20
+54
+65
+73
+74
+20
+32
+30
+32
+31
+2d
+31
+31
+2d
+32
+35
+20
+30
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+3a
+30
+30
+3a
+35
+33
+00
--- a/build/openroad/litex/modules/issiram.py
+++ b/build/openroad/litex/modules/issiram.py
@ -0,0 +1,102 @@
+#!/usr/bin/python3
+
+"""© IBM Corp. 2020
+Licensed under the Apache License, Version 2.0 (the "License"), as modified by the terms below; you may not use the files in this
+repository except in compliance with the License as modified.
+You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+
+Modified Terms:
+
+   1)	For the purpose of the patent license granted to you in Section 3 of the License, the "Work" hereby includes implementations of
+   the work of authorship in physical form.
+
+   2)	Notwithstanding any terms to the contrary in the License, any licenses necessary for implementation of the Work that are available
+   from OpenPOWER via the Power ISA End User License Agreement (EULA) are explicitly excluded hereunder, and may be obtained from OpenPOWER
+   under the terms and conditions of the EULA.
+
+Unless required by applicable law or agreed to in writing, the reference design distributed under the License is distributed on an
+"AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language
+governing permissions and limitations under the License.
+
+Additional rights, including the ability to physically implement a softcore that is compliant with the required sections of the Power
+ISA Specification, are available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be obtained (along with the Power
+ISA) here: https://openpowerfoundation.org.
+
+Brief explanation of modifications:
+
+Modification 1: This modification extends the patent license to an implementation of the Work in physical form – i.e.,
+it unambiguously permits a user to make and use the physical chip.
+
+Modification 2: This modification clarifies that licenses for the Power ISA are provided via the (royalty-free) Power ISA EULA,
+and not under this license.  To prevent fragmentation of the Power ISA, the Power ISA EULA requires that Power ISA Cores be
+licensed consistent with the terms of the Power ISA EULA.  By ensuring that rights available via the Power ISA EULA are received
+under (and subject to) the EULA, this consistency is maintained in accordance with the terms of the EULA. Any necessary additional
+licenses for the specific Power ISA Core are granted under this modified Apache license.
+"""
+
+from migen import *
+# if want AutoCSR
+#from litex.soc.interconnect.csr import *
+#class WB_ExtMem(Module, AutoCSR):
+class ISSIRam(Module):
+
+   def __init__(self, module, clk, rst, wishbone, pins):
+
+      self.bus = wishbone
+      self.data_width = 32
+      self.size = 524288
+
+      module.specials += Instance("issiram",
+         i_clk = clk,
+         i_rst = rst,
+         i_wbs_stb_i = wishbone.stb,
+         i_wbs_cyc_i = wishbone.cyc,
+         i_wbs_adr_i = wishbone.adr,
+         i_wbs_we_i = wishbone.we,
+         i_wbs_sel_i = wishbone.sel,
+         i_wbs_dat_i = wishbone.dat_w,
+         o_wbs_ack_o = wishbone.ack,
+         o_wbs_dat_o = wishbone.dat_r,
+         o_mem_ce_n = pins['ce'],
+         o_mem_oe_n = pins['oe'],
+         o_mem_we_n = pins['we'],
+         o_mem_adr = pins['adr'],
+         io_mem_dat = pins['dat']
+      )
+
+   #def _to_signal(self, obj):
+   #   return obj.raw_bits() if isinstance(obj, Record) else obj
+
+
+if __name__ == '__main__':
+
+   from litex.build.generic_platform import *
+   from litex.soc.interconnect import wishbone
+
+# need to use local; no oen here
+#   from litex_boards.platforms import cmod_a7
+   import sys
+   binPath = os.path.dirname(os.path.realpath(__file__))
+   sys.path.append(os.path.join(binPath, '../../build/litex'))
+   from platforms import cmod7
+
+   platform = cmod7.Platform()
+
+   platform.add_source("issiram.v")
+   clk = ClockSignal()
+   rst = ResetSignal()
+   bus = wishbone.Interface()
+
+   issiram = platform.request('issiram')
+   pins = {
+      'ce': issiram.cen,
+      'oe': issiram.oen,
+      'we': issiram.wen,
+      'adr': issiram.addr,
+      'dat': issiram.data
+   }
+   module = Module()
+   extmem = ISSIRam(module, clk, rst, bus, pins)
+
+   platform.build(module)
+
--- a/build/openroad/litex/modules/issiram.v
+++ b/build/openroad/litex/modules/issiram.v
@ -0,0 +1,362 @@
+/*
+© IBM Corp. 2020
+Licensed under the Apache License, Version 2.0 (the "License"), as modified by the terms below; you may not use the files in this
+repository except in compliance with the License as modified.
+You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+
+Modified Terms:
+
+   1)	For the purpose of the patent license granted to you in Section 3 of the License, the "Work" hereby includes implementations of
+   the work of authorship in physical form.
+
+   2)	Notwithstanding any terms to the contrary in the License, any licenses necessary for implementation of the Work that are available
+   from OpenPOWER via the Power ISA End User License Agreement (EULA) are explicitly excluded hereunder, and may be obtained from OpenPOWER
+   under the terms and conditions of the EULA.
+
+Unless required by applicable law or agreed to in writing, the reference design distributed under the License is distributed on an
+"AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language
+governing permissions and limitations under the License.
+
+Additional rights, including the ability to physically implement a softcore that is compliant with the required sections of the Power
+ISA Specification, are available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be obtained (along with the Power
+ISA) here: https://openpowerfoundation.org.
+
+Brief explanation of modifications:
+
+Modification 1: This modification extends the patent license to an implementation of the Work in physical form – i.e.,
+it unambiguously permits a user to make and use the physical chip.
+
+Modification 2: This modification clarifies that licenses for the Power ISA are provided via the (royalty-free) Power ISA EULA,
+and not under this license.  To prevent fragmentation of the Power ISA, the Power ISA EULA requires that Power ISA Cores be
+licensed consistent with the terms of the Power ISA EULA.  By ensuring that rights available via the Power ISA EULA are received
+under (and subject to) the EULA, this consistency is maintained in accordance with the terms of the EULA. Any necessary additional
+licenses for the specific Power ISA Core are granted under this modified Apache license.
+*/
+
+`timescale 1 ns / 1 ns
+
+// Asynchronous SRAM Wishbone Slave (IS61WV5128)
+// 32b non-pipelined, 3-cycle write, 512Kx8
+
+module issiram  #(
+   parameter WB_BITWIDTH = 32,
+   parameter RAM_BITWIDTH = 8
+)(
+   input                clk,
+   input                rst,
+   input                wbs_stb_i,
+   input                wbs_cyc_i,