or and litex caravel

master
wtf 2 years ago
parent e9e85815fb
commit d11a5838c3

@ -1,2 +1,3 @@
dffram/
output/
output/results
output/objects

@ -35,7 +35,6 @@ $(info [WTF] Output Dirs: $(DESIGN_NICKNAME))
# CTS

# forget about this for now - occurred when added dffram dir/caches. anton says hold misses are fake anyway :)
# (at least at 100mhz)
# do i need something else from dffram build?
# Repair hold violations...
# [INFO RSZ-0046] Found 60472 endpoints with hold violations.
@ -43,4 +42,4 @@ $(info [WTF] Output Dirs: $(DESIGN_NICKNAME))
# [INFO RSZ-0032] Inserted 213923 hold buffers.
# [ERROR DPL-0019] detailed placement failed on hold33177
# continue if cts wants to barf...
#export WTF_CTS_IGNORE_HOLD_MISSES = 1
export WTF_CTS_IGNORE_HOLD_MISSES = 1

@ -0,0 +1,3 @@
dffram/
output/results
output/objects

@ -0,0 +1 @@
from .core import A2P

@ -0,0 +1,5 @@
.section .text, "ax", @progbits

.global boot_helper
boot_helper:
blr

@ -0,0 +1,145 @@

import os

from migen import *

from litex import get_data_mod
from litex.soc.interconnect import wishbone
from litex.soc.interconnect.csr import *
from litex.soc.cores.cpu import CPU

dir = os.path.dirname(os.path.realpath(__file__))

# these select the top RTL file for each variant name
CPU_VARIANTS = {
'AXI': 'A2P_AXI',
'WB': 'A2P_WB',
'standard': 'A2P_WB' #wtf litex does this as default
}

GCC_FLAGS = {
'WB' : '-fomit-frame-pointer -Wall -fno-builtin -nostdinc -fno-stack-protector -fexceptions -Wstrict-prototypes -Wold-style-definition -Wmissing-prototypes'
}

class A2P(CPU, AutoCSR):
name = 'a2p'
human_name = 'a2p'
family = 'ppc32'
variants = CPU_VARIANTS
data_width = 32
endianness = 'big'
gcc_triple = 'powerpc-linux-gnu'
linker_output_format = 'elf32-powerpc'
nop = 'nop'
io_regions = {0x80000000: 0x80000000} # origin, length

@property
def mem_map(self):
return {
'rom': 0x00000000,
'sram': 0x00004000,
'main_ram': 0x40000000,
'csr': 0xf0000000,
}

@property
def gcc_flags(self):
flags = GCC_FLAGS[self.variant]
flags += " -D__a2p__"
return flags

def __init__(self, platform, variant='WB'):

if variant == 'standard':
variant = 'WB'

self.platform = platform
self.variant = variant
self.human_name = CPU_VARIANTS.get(variant, 'A2P')
self.external_variant = None
self.reset = Signal()
self.interrupt = Signal(32)
self.interruptS = Signal()
self.ibus = ibus = wishbone.Interface()
self.dbus = dbus = wishbone.Interface()
self.periph_buses = [ibus, dbus]
self.memory_buses = []
self.enableDebug = False
self.enableJTAG = False
self.externalResetVector = 0

# # #

self.cpu_params = dict(
i_clk = ClockSignal(),
i_reset = ResetSignal() | self.reset,

i_externalInterrupt = self.interrupt[0],
i_externalInterruptS = self.interruptS,
i_timerInterrupt = 0,
i_softwareInterrupt = 0,

o_iBusWB_ADR = ibus.adr,
o_iBusWB_DAT_MOSI = ibus.dat_w,
o_iBusWB_SEL = ibus.sel,
o_iBusWB_CYC = ibus.cyc,
o_iBusWB_STB = ibus.stb,
o_iBusWB_WE = ibus.we,
o_iBusWB_CTI = ibus.cti,
o_iBusWB_BTE = ibus.bte,
i_iBusWB_DAT_MISO = ibus.dat_r,
i_iBusWB_ACK = ibus.ack,
i_iBusWB_ERR = ibus.err,

o_dBusWB_ADR = dbus.adr,
o_dBusWB_DAT_MOSI = dbus.dat_w,
o_dBusWB_SEL = dbus.sel,
o_dBusWB_CYC = dbus.cyc,
o_dBusWB_STB = dbus.stb,
o_dBusWB_WE = dbus.we,
o_dBusWB_CTI = dbus.cti,
o_dBusWB_BTE = dbus.bte,
i_dBusWB_DAT_MISO = dbus.dat_r,
i_dBusWB_ACK = dbus.ack,
i_dBusWB_ERR = dbus.err
)

self.cpu_params['i_externalResetVector'] = self.externalResetVector

# these need to connect to top nets
if self.enableDebug:
self.cpu_params['i_debugReset'] = 0
self.cpu_params['o_debug_resetOut'] = 0
self.cpu_params['i_debug_bus_cmd_valid'] = 0
self.cpu_params['i_debug_bus_cmd_ready'] = 0
self.cpu_params['i_debug_bus_cmd_payload_wr'] = 0
self.cpu_params['i_debug_bus_cmd_payload_address'] = 0
self.cpu_params['i_debug_bus_cmd_payload_data'] = 0
self.cpu_params['o_debug_bus_rsp_data'] = 0

if self.enableJTAG:
self.cpu_params['i_jtag_tms'] = 0
self.cpu_params['i_jtag_tck'] = 0
self.cpu_params['i_jtag_tdi'] = 0
self.cpu_params['o_jtag_tdo'] = 0

def set_reset_address(self, reset_address):
assert not hasattr(self, "reset_address")
self.reset_address = reset_address
self.cpu_params.update(i_externalResetVector=Signal(32, reset=reset_address))

@staticmethod
def add_sources(platform, variant="WB"):
cpu_filename = CPU_VARIANTS[variant] + ".v"
vdir = os.path.join(dir, 'verilog')
platform.add_source(os.path.join(vdir, cpu_filename))

def use_external_variant(self, variant_filename):
self.external_variant = True
self.platform.add_source(variant_filename)

def do_finalize(self):
assert hasattr(self, "reset_address")
if not self.external_variant:
self.add_sources(self.platform, self.variant)
self.specials += Instance("A2P_WB", **self.cpu_params)

@ -0,0 +1,18 @@
#ifndef __IRQ_H
#define __IRQ_H

static inline void irq_setmask(unsigned int mask) {
}

static inline unsigned int irq_getmask(void) {
return 0;
}

static inline unsigned int irq_pending(void) {
return 0;
}

static inline void irq_setie(unsigned int mask) {
}

#endif

@ -0,0 +1,55 @@
// swizzlin

#ifndef __SYSTEM_H
#define __SYSTEM_H

#include <stdint.h>

/*
void flush_l2_cache(void) {
}
*/
static void flush_cpu_icache(void);
static void flush_cpu_dcache(void);

static void flush_cpu_icache(void) {
}
static void flush_cpu_dcache(void) {
}

#define CSR_ACCESSORS_DEFINED

#ifdef __ASSEMBLER__
#define MMPTR(x) x
#else /* ! __ASSEMBLER__ */

#include <generated/soc.h>
#if !defined(CONFIG_CSR_DATA_WIDTH)
#error CSR_DATA_WIDTH MUST be set before including this file!
#endif

#define MMPTR(a) (*((volatile uint32_t *)(a)))

static inline unsigned long swizzle(unsigned long v);

static inline unsigned long swizzle(unsigned long v) {
return ((v & 0x000000FF) << 24) | ((v & 0x0000FF00) << 8) | ((v & 0x00FF0000) >> 8) | ((v & 0xFF000000) >> 24);
//return v;
}

static inline void csr_write_simple(unsigned long v, unsigned long a)
{
//MMPTR(a) = v;
MMPTR(a) = swizzle(v);
}

static inline unsigned long csr_read_simple(unsigned long a)
{
//return MMPTR(a);
return swizzle(MMPTR(a));
}

#endif /* ! __ASSEMBLER__ */

#endif /* __SYSTEM_H */

File diff suppressed because it is too large Load Diff

File diff suppressed because it is too large Load Diff

File diff suppressed because it is too large Load Diff

File diff suppressed because it is too large Load Diff

@ -0,0 +1,274 @@
#!/usr/bin/python3

# A2P Caravel Site Test
# python3 a2p_site.py
#
# 1 or 2 cores
# Manager (wb is only slave)
# Async RAM interface ** won't work - only half of io can be outputs **
# use custom serial interface ~ 8 pins, 4B/32B packets
# UARTs
# I2C
# special-purpose GPIO
# Mgmt interface
# Beer on tap

import os
import argparse

from migen import *

# wtf - use local platform
from platforms import caravel_user

# wtf - use local core
# help python find package
import sys
binPath = os.path.dirname(os.path.realpath(__file__))
sys.path.append(os.path.join(binPath, 'a2p'))
# get core def
from a2p import A2P
# add to litex dict
from litex.soc.cores import cpu
cpu.CPUS['a2p'] = A2P

# local modules
sys.path.append(os.path.join(binPath, 'modules'))

from litex.soc.integration.soc import colorer
from litex.soc.integration.soc import SoCRegion
from litex.soc.integration.soc_core import *
from litex.soc.integration.soc_sdram import *
from litex.soc.integration.builder import *

from litex.soc.cores.led import LedChaser
from litex.soc.cores.gpio import GPIOIn
from litex.soc.cores.gpio import GPIOOut
from litex.soc.cores.bitbang import I2CMaster

from litex.soc.interconnect import wishbone
from litex.soc.interconnect import csr

from litex.soc.cores.uart import UART
from litex.soc.cores.uart import RS232PHY

# possibly use octspi with a memory controller to send/rcv 32b/128b data with header and crc?
#from litespi.common import *
#from litespi.phy.generic_sdr import LiteSPISDRPHYCore
#from litespi.phy.generic_ddr import LiteSPIDDRPHYCore


# BaseSoC ------------------------------------------------------------------------------------------

from litex.soc.interconnect import wishbone

def _to_signal(obj):
return obj.raw_bits() if isinstance(obj, Record) else obj

class BaseSoC(SoCCore):

def __init__(self, sys_clk_freq=50e6, uart_baudrate=115200, **kwargs):

platform = caravel_user.Platform()

SoCCore.__init__(self, platform, 50e6, sys_clk_freq=50e6, cpu_type='a2p',
csr_data_width=32, with_uart=False, integrated_sram_size=0, integrated_rom_size=0,
ident='A2P Caravel Site Test', ident_version=True)

# no irq yet
self.add_constant('UART_POLLING')

self.mem_map = {
'csr': 0xFFF00000,
'sram': 0x00000000,
'mgmt': 0xE0000000
}


# I/O connections --------------------------------------------------------------------------
# clk is connected by platform
# make these exist even if unconnected so i/o are defined

# --- clk/rst
#self.sys_rst = Signal() #this creates sys_rst_1
#self.comb += self.int_rst.eq(platform.request('wb_rst_i')) no idea how to connect to top level sigs that are magically gen'd
# apprarently they give you a few things useful!
self.sys_rst = ResetSignal()
self.comb += self.sys_rst.eq(platform.request('wb_rst_i'))
# but gens some whack logic
# always @(*) begin
# sys_rst <= 1'd0;
# sys_rst <= wb_rst_i;
# sys_rst <= int_rst;
# end

self.user_clock2 = Signal()
self.comb += self.user_clock2.eq(platform.request('user_clock2'))

# --- wb
# options:
# * unused
# * user area is slave (config/test only)
# * user area is master/slave - not possible - NO MASTER SIGS!!!

# slave interface for mgmt macro (core controls, etc.); could hang csr off it and interface through them
# i suppose then you could let the csr be read/written by both sides, so you could do some polled mailbox messaging; probs could proxy i/o through pico
# they would have to be r/w by 2 different wb's
self.wb_mgmt = wishbone.Interface()
self.wb_io = Record([('cyc', 1), ('stb', 1), ('we', 1), ('sel', 4), ('adr', 32), ('ack', 1), ('dat_r', 32), ('dat_w', 32),
('cti', 1), ('bte', 32), ('err', 1)])
self.wb_io.cyc = platform.request('wbs_cyc_i')
self.wb_io.stb = platform.request('wbs_stb_i')
self.wb_io.we = platform.request('wbs_we_i')
self.wb_io.sel = platform.request('wbs_sel_i')
self.wb_io.adr = platform.request('wbs_adr_i')
self.wb_io.ack = platform.request('wbs_ack_o')
self.wb_io.dat_r = platform.request('wbs_dat_o')
self.wb_io.dat_w = platform.request('wbs_dat_i')
self.wb_io.cti = Signal()
self.wb_io.bte = Signal()
self.wb_io.err = Signal()
self.wb_mgmt.connect_to_pads(self.wb_io, mode='slave')

#somehow get this built and then connected to 2 wb
#self.wb_shared = wishbone.InterconnectShared(masters,slaves)
self.mailbox = csr.CSRStorage(size=16, name='mailbox')
self.add_csr('mailbox')

# --- gpio
self.in_in = Signal(19)
self.comb += self.in_in.eq(platform.request('in_in'))
self.in_out = Signal(19)
self.comb += self.in_out.eq(platform.request('in_out'))
self.in_oeb = Signal(19)
self.comb += self.in_oeb.eq(platform.request('in_oeb'))
# skip analog_in; too curvy

# allocate
uart_0_io = {
'rx': self.in_in[0],
'tx': self.in_out[0]
}
uart_1_io = {
'rx': self.in_in[1],
'tx': self.in_out[1]
}
i2c_io = {
'scl': self.in_out[2],
'sda': self.in_out[3]
}
dshot_io = self.in_out[3:6]
# toss
ram_io = {
'ce': Signal(1),
'oe': Signal(), # self.in_out[7],
'we': Signal(), # self.in_out[8],
'adr': Signal(19), # self.in_out[18:0],
'dat': Signal(8) # self.in_out[18:11]
}

# --- misc
self.user_irq = Signal(3)
self.comb += self.user_irq.eq(platform.request('user_irq'))

# --- la
self.la_data_in = Signal(128)
self.comb += self.la_data_in.eq(platform.request('la_data_in'))
self.la_data_out = Signal(128)
self.comb += self.la_data_out.eq(platform.request('la_data_out'))
self.la_oenb = Signal(128)
self.comb += self.la_oenb.eq(platform.request('la_oenb'))

# ON-BOARD MEM ------------------------------------------------------------------------------
# None, unless a small 'ROM'-like device
#self.add_rom('rom', origin=self.mem_map['rom'], size=rom_size, contents=romdata)

# MANAGER -----------------------------------------------------------------------------------
# service processor stuff controlled by the man

# External SRAM (512K) -----------------------------------------------------------------------
# GPIO-connected SRAM/FPGA

# *** doh, won't work - only half the i/o are outputs!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! ***
# will have to resurrect custom serial i/o with fpga on other end

from issiram import ISSIRam
platform.add_source('./momv modules/issiram.v')

sram_bus = wishbone.Interface()
sram = ISSIRam(self, ClockSignal(), ResetSignal(), sram_bus, ram_io)
self.submodules.sram = sram
# ERROR: Output port top.issiram.mem_adr (issiram) is connected to constants: { \basesoc_in_out [17:0] 1'x }
# Command exited with non-zero status 1
# Elapsed time: 0:12.27[h:]min:sec. CPU time: user 11.77 sys 0.48 (99%). Peak memory: 1468464KB.
# make: *** [Makefile:354: results/sky130hd/a2p_litex/output/20211125085224/base/1_1_yosys.v] Error 1
self.bus.add_slave('sram', sram_bus, SoCRegion(origin=self.mem_map['sram'], size=sram.size))
#self.logger.info('SRAM {} {} {}.'.format(
# colorer('sram'),
# colorer('added', color='green'),
# self.bus.regions['sram']))

# Leds n LaserBeams -----------------------------------------------------------------------
#self.submodules.leds = LedChaser(
# pads = platform.request_all('user_led'),
# sys_clk_freq = sys_clk_freq
#)
#self.add_csr('leds')

# Buttons n KillSwitches ------------------------------------------------------------------
#self.submodules.buttons = GPIOIn(
# pads = platform.request_all('user_btn')
#)
#self.add_csr('buttons')

# GPIO I2C
#wtf must be an elegant pythonic way to do this junk
pins = Record([('scl', 1), ('sda', 1)])
pins.scl = i2c_io['scl']
pins.sda = i2c_io['sda']
#wtf needs to be 'i2c' for bios for now
self.submodules.i2c = I2CMaster(pins)
self.add_csr('i2c')

# GPIO UARTs = 2 pins per -----------------------------------------------------------------
pins = Record([('rx', 1), ('tx', 1)])
pins.rx = uart_0_io['rx']
pins.tx = uart_0_io['tx']
self.submodules.uart_0_phy = RS232PHY(pins, sys_clk_freq, with_dynamic_baudrate=True)
self.add_csr('uart_0_phy')
self.submodules.uart_0 = UART(phy=self.uart_0_phy)
self.add_csr('uart_0')

pins = Record([('rx', 1), ('tx', 1)])
pins.rx = uart_1_io['tx']
pins.tx = uart_1_io['tx']
self.submodules.uart_1_phy = RS232PHY(pins, sys_clk_freq, with_dynamic_baudrate=True)
self.add_csr('uart_1_phy')
self.submodules.uart_1 = UART(phy=self.uart_1_phy)
self.add_csr('uart_1')

# DShot M0:M3 (no telemetry) = 4 pins -----------------------------------------------------
#self.submodules.dshot = DShot(dshot_io)
#self.add_csr('dshot')

# Build -------------------------------------------------------------------------------------------

def main():

parser = argparse.ArgumentParser(description='A2P Caravel Test Site')

builder_args(parser)
soc_sdram_args(parser)
args = parser.parse_args()

soc = BaseSoC(**soc_sdram_argdict(args))
builder = Builder(soc, **builder_argdict(args))

soc.build_name = 'wtf' #wtf dont work!
builder.build_name = 'wtf' #wtf dont work!
builder.compile_software = False
builder.csr_csv = 'csr.csv'
builder.build(run=False)

if __name__ == "__main__":
main()

@ -0,0 +1,79 @@

# Create Project

create_project -force -name caravel_user -part xc7a35t-CPG236-1
set_msg_config -id {Common 17-55} -new_severity {Warning}

# Add Sources

read_verilog {/home/wtf/projects/a2p-opf/build/openroad/litex/momv modules/issiram.v}
read_verilog {/home/wtf/projects/a2p-opf/build/openroad/litex/a2p/verilog/A2P_WB.v}
read_verilog {/home/wtf/projects/a2p-opf/build/openroad/litex/build/caravel_user/gateware/caravel_user.v}

# Add EDIFs


# Add IPs


# Add constraints

read_xdc caravel_user.xdc
set_property PROCESSING_ORDER EARLY [get_files caravel_user.xdc]

# Add pre-synthesis commands


# Synthesis

synth_design -directive default -top caravel_user -part xc7a35t-CPG236-1

# Synthesis report

report_timing_summary -file caravel_user_timing_synth.rpt
report_utilization -hierarchical -file caravel_user_utilization_hierarchical_synth.rpt
report_utilization -file caravel_user_utilization_synth.rpt

# Optimize design

opt_design -directive default

# Add pre-placement commands


# Placement

place_design -directive default

# Placement report

report_utilization -hierarchical -file caravel_user_utilization_hierarchical_place.rpt
report_utilization -file caravel_user_utilization_place.rpt
report_io -file caravel_user_io.rpt
report_control_sets -verbose -file caravel_user_control_sets.rpt
report_clock_utilization -file caravel_user_clock_utilization.rpt

# Add pre-routing commands


# Routing

route_design -directive default
phys_opt_design -directive default
write_checkpoint -force caravel_user_route.dcp

# Routing report

report_timing_summary -no_header -no_detailed_paths
report_route_status -file caravel_user_route_status.rpt
report_drc -file caravel_user_drc.rpt
report_timing_summary -datasheet -max_paths 10 -file caravel_user_timing.rpt
report_power -file caravel_user_power.rpt

# Bitstream generation

write_bitstream -force caravel_user.bit

# End

quit

@ -0,0 +1,42 @@
41
32
50
20
43
61
72
61
76
65
6c
20
53
69
74
65
20
54
65
73
74
20
32
30
32
31
2d
31
31
2d
32
35
20
31
33
3a
35
33
3a
33
32
00

@ -0,0 +1,591 @@
//--------------------------------------------------------------------------------
// Auto-generated by Migen (9a0be7a) & LiteX (85d6cb4b) on 2021-11-25 13:53:32
//--------------------------------------------------------------------------------
#include <generated/soc.h>
#ifndef __GENERATED_CSR_H
#define __GENERATED_CSR_H
#include <stdint.h>
#include <system.h>
#ifndef CSR_ACCESSORS_DEFINED
#include <hw/common.h>
#endif /* ! CSR_ACCESSORS_DEFINED */
#ifndef CSR_BASE
#define CSR_BASE 0xfff00000L
#endif

/* i2c */
#define CSR_I2C_BASE (CSR_BASE + 0x800L)
#define CSR_I2C_W_ADDR (CSR_BASE + 0x800L)
#define CSR_I2C_W_SIZE 1
static inline uint32_t i2c_w_read(void) {
return csr_read_simple(CSR_BASE + 0x800L);
}
static inline void i2c_w_write(uint32_t v) {
csr_write_simple(v, CSR_BASE + 0x800L);
}
#define CSR_I2C_W_SCL_OFFSET 0
#define CSR_I2C_W_SCL_SIZE 1
static inline uint32_t i2c_w_scl_extract(uint32_t oldword) {
uint32_t mask = ((1 << 1)-1);
return ( (oldword >> 0) & mask );
}
static inline uint32_t i2c_w_scl_read(void) {
uint32_t word = i2c_w_read();
return i2c_w_scl_extract(word);
}
static inline uint32_t i2c_w_scl_replace(uint32_t oldword, uint32_t plain_value) {
uint32_t mask = ((1 << 1)-1);
return (oldword & (~(mask << 0))) | (mask & plain_value)<< 0 ;
}
static inline void i2c_w_scl_write(uint32_t plain_value) {
uint32_t oldword = i2c_w_read();
uint32_t newword = i2c_w_scl_replace(oldword, plain_value);
i2c_w_write(newword);
}
#define CSR_I2C_W_OE_OFFSET 1
#define CSR_I2C_W_OE_SIZE 1
static inline uint32_t i2c_w_oe_extract(uint32_t oldword) {
uint32_t mask = ((1 << 1)-1);
return ( (oldword >> 1) & mask );
}
static inline uint32_t i2c_w_oe_read(void) {
uint32_t word = i2c_w_read();
return i2c_w_oe_extract(word);
}
static inline uint32_t i2c_w_oe_replace(uint32_t oldword, uint32_t plain_value) {
uint32_t mask = ((1 << 1)-1);
return (oldword & (~(mask << 1))) | (mask & plain_value)<< 1 ;
}
static inline void i2c_w_oe_write(uint32_t plain_value) {
uint32_t oldword = i2c_w_read();
uint32_t newword = i2c_w_oe_replace(oldword, plain_value);
i2c_w_write(newword);
}
#define CSR_I2C_W_SDA_OFFSET 2
#define CSR_I2C_W_SDA_SIZE 1
static inline uint32_t i2c_w_sda_extract(uint32_t oldword) {
uint32_t mask = ((1 << 1)-1);
return ( (oldword >> 2) & mask );
}
static inline uint32_t i2c_w_sda_read(void) {
uint32_t word = i2c_w_read();
return i2c_w_sda_extract(word);
}
static inline uint32_t i2c_w_sda_replace(uint32_t oldword, uint32_t plain_value) {
uint32_t mask = ((1 << 1)-1);
return (oldword & (~(mask << 2))) | (mask & plain_value)<< 2 ;
}
static inline void i2c_w_sda_write(uint32_t plain_value) {
uint32_t oldword = i2c_w_read();
uint32_t newword = i2c_w_sda_replace(oldword, plain_value);
i2c_w_write(newword);
}
#define CSR_I2C_R_ADDR (CSR_BASE + 0x804L)
#define CSR_I2C_R_SIZE 1
static inline uint32_t i2c_r_read(void) {
return csr_read_simple(CSR_BASE + 0x804L);
}
#define CSR_I2C_R_SDA_OFFSET 0
#define CSR_I2C_R_SDA_SIZE 1
static inline uint32_t i2c_r_sda_extract(uint32_t oldword) {
uint32_t mask = ((1 << 1)-1);
return ( (oldword >> 0) & mask );
}
static inline uint32_t i2c_r_sda_read(void) {
uint32_t word = i2c_r_read();
return i2c_r_sda_extract(word);
}

/* uart_0_phy */
#define CSR_UART_0_PHY_BASE (CSR_BASE + 0x1000L)
#define CSR_UART_0_PHY_TUNING_WORD_ADDR (CSR_BASE + 0x1000L)
#define CSR_UART_0_PHY_TUNING_WORD_SIZE 1
static inline uint32_t uart_0_phy_tuning_word_read(void) {
return csr_read_simple(CSR_BASE + 0x1000L);
}
static inline void uart_0_phy_tuning_word_write(uint32_t v) {
csr_write_simple(v, CSR_BASE + 0x1000L);
}

/* uart_0 */
#define CSR_UART_0_BASE (CSR_BASE + 0x1800L)
#define CSR_UART_0_RXTX_ADDR (CSR_BASE + 0x1800L)
#define CSR_UART_0_RXTX_SIZE 1
static inline uint32_t uart_0_rxtx_read(void) {
return csr_read_simple(CSR_BASE + 0x1800L);
}
static inline void uart_0_rxtx_write(uint32_t v) {
csr_write_simple(v, CSR_BASE + 0x1800L);
}
#define CSR_UART_0_TXFULL_ADDR (CSR_BASE + 0x1804L)
#define CSR_UART_0_TXFULL_SIZE 1
static inline uint32_t uart_0_txfull_read(void) {
return csr_read_simple(CSR_BASE + 0x1804L);
}
#define CSR_UART_0_RXEMPTY_ADDR (CSR_BASE + 0x1808L)
#define CSR_UART_0_RXEMPTY_SIZE 1
static inline uint32_t uart_0_rxempty_read(void) {
return csr_read_simple(CSR_BASE + 0x1808L);
}
#define CSR_UART_0_EV_STATUS_ADDR (CSR_BASE + 0x180cL)
#define CSR_UART_0_EV_STATUS_SIZE 1
static inline uint32_t uart_0_ev_status_read(void) {
return csr_read_simple(CSR_BASE + 0x180cL);
}
#define CSR_UART_0_EV_STATUS_TX_OFFSET 0
#define CSR_UART_0_EV_STATUS_TX_SIZE 1
static inline uint32_t uart_0_ev_status_tx_extract(uint32_t oldword) {
uint32_t mask = ((1 << 1)-1);
return ( (oldword >> 0) & mask );
}
static inline uint32_t uart_0_ev_status_tx_read(void) {
uint32_t word = uart_0_ev_status_read();
return uart_0_ev_status_tx_extract(word);
}
#define CSR_UART_0_EV_STATUS_RX_OFFSET 1
#define CSR_UART_0_EV_STATUS_RX_SIZE 1
static inline uint32_t uart_0_ev_status_rx_extract(uint32_t oldword) {
uint32_t mask = ((1 << 1)-1);
return ( (oldword >> 1) & mask );
}
static inline uint32_t uart_0_ev_status_rx_read(void) {
uint32_t word = uart_0_ev_status_read();
return uart_0_ev_status_rx_extract(word);
}
#define CSR_UART_0_EV_PENDING_ADDR (CSR_BASE + 0x1810L)
#define CSR_UART_0_EV_PENDING_SIZE 1
static inline uint32_t uart_0_ev_pending_read(void) {
return csr_read_simple(CSR_BASE + 0x1810L);
}
static inline void uart_0_ev_pending_write(uint32_t v) {
csr_write_simple(v, CSR_BASE + 0x1810L);
}
#define CSR_UART_0_EV_PENDING_TX_OFFSET 0
#define CSR_UART_0_EV_PENDING_TX_SIZE 1
static inline uint32_t uart_0_ev_pending_tx_extract(uint32_t oldword) {
uint32_t mask = ((1 << 1)-1);
return ( (oldword >> 0) & mask );
}
static inline uint32_t uart_0_ev_pending_tx_read(void) {
uint32_t word = uart_0_ev_pending_read();
return uart_0_ev_pending_tx_extract(word);
}
static inline uint32_t uart_0_ev_pending_tx_replace(uint32_t oldword, uint32_t plain_value) {
uint32_t mask = ((1 << 1)-1);
return (oldword & (~(mask << 0))) | (mask & plain_value)<< 0 ;
}
static inline void uart_0_ev_pending_tx_write(uint32_t plain_value) {
uint32_t oldword = uart_0_ev_pending_read();
uint32_t newword = uart_0_ev_pending_tx_replace(oldword, plain_value);
uart_0_ev_pending_write(newword);
}
#define CSR_UART_0_EV_PENDING_RX_OFFSET 1
#define CSR_UART_0_EV_PENDING_RX_SIZE 1
static inline uint32_t uart_0_ev_pending_rx_extract(uint32_t oldword) {
uint32_t mask = ((1 << 1)-1);
return ( (oldword >> 1) & mask );
}
static inline uint32_t uart_0_ev_pending_rx_read(void) {
uint32_t word = uart_0_ev_pending_read();
return uart_0_ev_pending_rx_extract(word);
}
static inline uint32_t uart_0_ev_pending_rx_replace(uint32_t oldword, uint32_t plain_value) {
uint32_t mask = ((1 << 1)-1);
return (oldword & (~(mask << 1))) | (mask & plain_value)<< 1 ;
}
static inline void uart_0_ev_pending_rx_write(uint32_t plain_value) {
uint32_t oldword = uart_0_ev_pending_read();
uint32_t newword = uart_0_ev_pending_rx_replace(oldword, plain_value);
uart_0_ev_pending_write(newword);
}
#define CSR_UART_0_EV_ENABLE_ADDR (CSR_BASE + 0x1814L)
#define CSR_UART_0_EV_ENABLE_SIZE 1
static inline uint32_t uart_0_ev_enable_read(void) {
return csr_read_simple(CSR_BASE + 0x1814L);
}
static inline void uart_0_ev_enable_write(uint32_t v) {
csr_write_simple(v, CSR_BASE + 0x1814L);
}
#define CSR_UART_0_EV_ENABLE_TX_OFFSET 0
#define CSR_UART_0_EV_ENABLE_TX_SIZE 1
static inline uint32_t uart_0_ev_enable_tx_extract(uint32_t oldword) {
uint32_t mask = ((1 << 1)-1);
return ( (oldword >> 0) & mask );
}
static inline uint32_t uart_0_ev_enable_tx_read(void) {
uint32_t word = uart_0_ev_enable_read();
return uart_0_ev_enable_tx_extract(word);
}
static inline uint32_t uart_0_ev_enable_tx_replace(uint32_t oldword, uint32_t plain_value) {
uint32_t mask = ((1 << 1)-1);
return (oldword & (~(mask << 0))) | (mask & plain_value)<< 0 ;
}
static inline void uart_0_ev_enable_tx_write(uint32_t plain_value) {
uint32_t oldword = uart_0_ev_enable_read();
uint32_t newword = uart_0_ev_enable_tx_replace(oldword, plain_value);
uart_0_ev_enable_write(newword);
}
#define CSR_UART_0_EV_ENABLE_RX_OFFSET 1
#define CSR_UART_0_EV_ENABLE_RX_SIZE 1
static inline uint32_t uart_0_ev_enable_rx_extract(uint32_t oldword) {
uint32_t mask = ((1 << 1)-1);
return ( (oldword >> 1) & mask );
}
static inline uint32_t uart_0_ev_enable_rx_read(void) {
uint32_t word = uart_0_ev_enable_read();
return uart_0_ev_enable_rx_extract(word);
}
static inline uint32_t uart_0_ev_enable_rx_replace(uint32_t oldword, uint32_t plain_value) {
uint32_t mask = ((1 << 1)-1);
return (oldword & (~(mask << 1))) | (mask & plain_value)<< 1 ;
}
static inline void uart_0_ev_enable_rx_write(uint32_t plain_value) {
uint32_t oldword = uart_0_ev_enable_read();
uint32_t newword = uart_0_ev_enable_rx_replace(oldword, plain_value);
uart_0_ev_enable_write(newword);
}
#define CSR_UART_0_TXEMPTY_ADDR (CSR_BASE + 0x1818L)
#define CSR_UART_0_TXEMPTY_SIZE 1
static inline uint32_t uart_0_txempty_read(void) {
return csr_read_simple(CSR_BASE + 0x1818L);
}
#define CSR_UART_0_RXFULL_ADDR (CSR_BASE + 0x181cL)
#define CSR_UART_0_RXFULL_SIZE 1
static inline uint32_t uart_0_rxfull_read(void) {
return csr_read_simple(CSR_BASE + 0x181cL);
}

/* uart_1_phy */
#define CSR_UART_1_PHY_BASE (CSR_BASE + 0x2000L)
#define CSR_UART_1_PHY_TUNING_WORD_ADDR (CSR_BASE + 0x2000L)
#define CSR_UART_1_PHY_TUNING_WORD_SIZE 1
static inline uint32_t uart_1_phy_tuning_word_read(void) {
return csr_read_simple(CSR_BASE + 0x2000L);
}
static inline void uart_1_phy_tuning_word_write(uint32_t v) {
csr_write_simple(v, CSR_BASE + 0x2000L);
}

/* uart_1 */
#define CSR_UART_1_BASE (CSR_BASE + 0x2800L)
#define CSR_UART_1_RXTX_ADDR (CSR_BASE + 0x2800L)
#define CSR_UART_1_RXTX_SIZE 1
static inline uint32_t uart_1_rxtx_read(void) {
return csr_read_simple(CSR_BASE + 0x2800L);
}
static inline void uart_1_rxtx_write(uint32_t v) {
csr_write_simple(v, CSR_BASE + 0x2800L);
}
#define CSR_UART_1_TXFULL_ADDR (CSR_BASE + 0x2804L)
#define CSR_UART_1_TXFULL_SIZE 1
static inline uint32_t uart_1_txfull_read(void) {
return csr_read_simple(CSR_BASE + 0x2804L);
}
#define CSR_UART_1_RXEMPTY_ADDR (CSR_BASE + 0x2808L)
#define CSR_UART_1_RXEMPTY_SIZE 1
static inline uint32_t uart_1_rxempty_read(void) {
return csr_read_simple(CSR_BASE + 0x2808L);
}
#define CSR_UART_1_EV_STATUS_ADDR (CSR_BASE + 0x280cL)
#define CSR_UART_1_EV_STATUS_SIZE 1
static inline uint32_t uart_1_ev_status_read(void) {
return csr_read_simple(CSR_BASE + 0x280cL);
}
#define CSR_UART_1_EV_STATUS_TX_OFFSET 0
#define CSR_UART_1_EV_STATUS_TX_SIZE 1
static inline uint32_t uart_1_ev_status_tx_extract(uint32_t oldword) {
uint32_t mask = ((1 << 1)-1);
return ( (oldword >> 0) & mask );
}
static inline uint32_t uart_1_ev_status_tx_read(void) {
uint32_t word = uart_1_ev_status_read();
return uart_1_ev_status_tx_extract(word);
}
#define CSR_UART_1_EV_STATUS_RX_OFFSET 1
#define CSR_UART_1_EV_STATUS_RX_SIZE 1
static inline uint32_t uart_1_ev_status_rx_extract(uint32_t oldword) {
uint32_t mask = ((1 << 1)-1);
return ( (oldword >> 1) & mask );
}
static inline uint32_t uart_1_ev_status_rx_read(void) {
uint32_t word = uart_1_ev_status_read();
return uart_1_ev_status_rx_extract(word);
}
#define CSR_UART_1_EV_PENDING_ADDR (CSR_BASE + 0x2810L)
#define CSR_UART_1_EV_PENDING_SIZE 1
static inline uint32_t uart_1_ev_pending_read(void) {
return csr_read_simple(CSR_BASE + 0x2810L);
}
static inline void uart_1_ev_pending_write(uint32_t v) {
csr_write_simple(v, CSR_BASE + 0x2810L);
}
#define CSR_UART_1_EV_PENDING_TX_OFFSET 0
#define CSR_UART_1_EV_PENDING_TX_SIZE 1
static inline uint32_t uart_1_ev_pending_tx_extract(uint32_t oldword) {
uint32_t mask = ((1 << 1)-1);
return ( (oldword >> 0) & mask );
}
static inline uint32_t uart_1_ev_pending_tx_read(void) {
uint32_t word = uart_1_ev_pending_read();
return uart_1_ev_pending_tx_extract(word);
}
static inline uint32_t uart_1_ev_pending_tx_replace(uint32_t oldword, uint32_t plain_value) {
uint32_t mask = ((1 << 1)-1);
return (oldword & (~(mask << 0))) | (mask & plain_value)<< 0 ;
}
static inline void uart_1_ev_pending_tx_write(uint32_t plain_value) {
uint32_t oldword = uart_1_ev_pending_read();
uint32_t newword = uart_1_ev_pending_tx_replace(oldword, plain_value);
uart_1_ev_pending_write(newword);
}
#define CSR_UART_1_EV_PENDING_RX_OFFSET 1
#define CSR_UART_1_EV_PENDING_RX_SIZE 1
static inline uint32_t uart_1_ev_pending_rx_extract(uint32_t oldword) {
uint32_t mask = ((1 << 1)-1);
return ( (oldword >> 1) & mask );
}
static inline uint32_t uart_1_ev_pending_rx_read(void) {
uint32_t word = uart_1_ev_pending_read();
return uart_1_ev_pending_rx_extract(word);
}
static inline uint32_t uart_1_ev_pending_rx_replace(uint32_t oldword, uint32_t plain_value) {
uint32_t mask = ((1 << 1)-1);
return (oldword & (~(mask << 1))) | (mask & plain_value)<< 1 ;
}
static inline void uart_1_ev_pending_rx_write(uint32_t plain_value) {
uint32_t oldword = uart_1_ev_pending_read();
uint32_t newword = uart_1_ev_pending_rx_replace(oldword, plain_value);
uart_1_ev_pending_write(newword);
}
#define CSR_UART_1_EV_ENABLE_ADDR (CSR_BASE + 0x2814L)
#define CSR_UART_1_EV_ENABLE_SIZE 1
static inline uint32_t uart_1_ev_enable_read(void) {
return csr_read_simple(CSR_BASE + 0x2814L);
}
static inline void uart_1_ev_enable_write(uint32_t v) {
csr_write_simple(v, CSR_BASE + 0x2814L);
}
#define CSR_UART_1_EV_ENABLE_TX_OFFSET 0
#define CSR_UART_1_EV_ENABLE_TX_SIZE 1
static inline uint32_t uart_1_ev_enable_tx_extract(uint32_t oldword) {
uint32_t mask = ((1 << 1)-1);
return ( (oldword >> 0) & mask );
}
static inline uint32_t uart_1_ev_enable_tx_read(void) {
uint32_t word = uart_1_ev_enable_read();
return uart_1_ev_enable_tx_extract(word);
}
static inline uint32_t uart_1_ev_enable_tx_replace(uint32_t oldword, uint32_t plain_value) {
uint32_t mask = ((1 << 1)-1);
return (oldword & (~(mask << 0))) | (mask & plain_value)<< 0 ;
}
static inline void uart_1_ev_enable_tx_write(uint32_t plain_value) {
uint32_t oldword = uart_1_ev_enable_read();
uint32_t newword = uart_1_ev_enable_tx_replace(oldword, plain_value);
uart_1_ev_enable_write(newword);
}
#define CSR_UART_1_EV_ENABLE_RX_OFFSET 1
#define CSR_UART_1_EV_ENABLE_RX_SIZE 1
static inline uint32_t uart_1_ev_enable_rx_extract(uint32_t oldword) {
uint32_t mask = ((1 << 1)-1);
return ( (oldword >> 1) & mask );
}
static inline uint32_t uart_1_ev_enable_rx_read(void) {
uint32_t word = uart_1_ev_enable_read();
return uart_1_ev_enable_rx_extract(word);
}
static inline uint32_t uart_1_ev_enable_rx_replace(uint32_t oldword, uint32_t plain_value) {
uint32_t mask = ((1 << 1)-1);
return (oldword & (~(mask << 1))) | (mask & plain_value)<< 1 ;
}
static inline void uart_1_ev_enable_rx_write(uint32_t plain_value) {
uint32_t oldword = uart_1_ev_enable_read();
uint32_t newword = uart_1_ev_enable_rx_replace(oldword, plain_value);
uart_1_ev_enable_write(newword);
}
#define CSR_UART_1_TXEMPTY_ADDR (CSR_BASE + 0x2818L)
#define CSR_UART_1_TXEMPTY_SIZE 1
static inline uint32_t uart_1_txempty_read(void) {
return csr_read_simple(CSR_BASE + 0x2818L);
}
#define CSR_UART_1_RXFULL_ADDR (CSR_BASE + 0x281cL)
#define CSR_UART_1_RXFULL_SIZE 1
static inline uint32_t uart_1_rxfull_read(void) {
return csr_read_simple(CSR_BASE + 0x281cL);
}

/* ctrl */
#define CSR_CTRL_BASE (CSR_BASE + 0x3000L)
#define CSR_CTRL_RESET_ADDR (CSR_BASE + 0x3000L)
#define CSR_CTRL_RESET_SIZE 1
static inline uint32_t ctrl_reset_read(void) {
return csr_read_simple(CSR_BASE + 0x3000L);
}
static inline void ctrl_reset_write(uint32_t v) {
csr_write_simple(v, CSR_BASE + 0x3000L);
}
#define CSR_CTRL_RESET_SOC_RST_OFFSET 0
#define CSR_CTRL_RESET_SOC_RST_SIZE 1
static inline uint32_t ctrl_reset_soc_rst_extract(uint32_t oldword) {
uint32_t mask = ((1 << 1)-1);
return ( (oldword >> 0) & mask );
}
static inline uint32_t ctrl_reset_soc_rst_read(void) {
uint32_t word = ctrl_reset_read();
return ctrl_reset_soc_rst_extract(word);
}
static inline uint32_t ctrl_reset_soc_rst_replace(uint32_t oldword, uint32_t plain_value) {
uint32_t mask = ((1 << 1)-1);
return (oldword & (~(mask << 0))) | (mask & plain_value)<< 0 ;
}
static inline void ctrl_reset_soc_rst_write(uint32_t plain_value) {
uint32_t oldword = ctrl_reset_read();
uint32_t newword = ctrl_reset_soc_rst_replace(oldword, plain_value);
ctrl_reset_write(newword);
}
#define CSR_CTRL_RESET_CPU_RST_OFFSET 1
#define CSR_CTRL_RESET_CPU_RST_SIZE 1
static inline uint32_t ctrl_reset_cpu_rst_extract(uint32_t oldword) {
uint32_t mask = ((1 << 1)-1);
return ( (oldword >> 1) & mask );
}
static inline uint32_t ctrl_reset_cpu_rst_read(void) {
uint32_t word = ctrl_reset_read();
return ctrl_reset_cpu_rst_extract(word);
}
static inline uint32_t ctrl_reset_cpu_rst_replace(uint32_t oldword, uint32_t plain_value) {
uint32_t mask = ((1 << 1)-1);
return (oldword & (~(mask << 1))) | (mask & plain_value)<< 1 ;
}
static inline void ctrl_reset_cpu_rst_write(uint32_t plain_value) {
uint32_t oldword = ctrl_reset_read();
uint32_t newword = ctrl_reset_cpu_rst_replace(oldword, plain_value);
ctrl_reset_write(newword);
}
#define CSR_CTRL_SCRATCH_ADDR (CSR_BASE + 0x3004L)
#define CSR_CTRL_SCRATCH_SIZE 1
static inline uint32_t ctrl_scratch_read(void) {
return csr_read_simple(CSR_BASE + 0x3004L);
}
static inline void ctrl_scratch_write(uint32_t v) {
csr_write_simple(v, CSR_BASE + 0x3004L);
}
#define CSR_CTRL_BUS_ERRORS_ADDR (CSR_BASE + 0x3008L)
#define CSR_CTRL_BUS_ERRORS_SIZE 1
static inline uint32_t ctrl_bus_errors_read(void) {
return csr_read_simple(CSR_BASE + 0x3008L);
}

/* identifier_mem */
#define CSR_IDENTIFIER_MEM_BASE (CSR_BASE + 0x3800L)

/* timer0 */
#define CSR_TIMER0_BASE (CSR_BASE + 0x4000L)
#define CSR_TIMER0_LOAD_ADDR (CSR_BASE + 0x4000L)
#define CSR_TIMER0_LOAD_SIZE 1
static inline uint32_t timer0_load_read(void) {
return csr_read_simple(CSR_BASE + 0x4000L);
}
static inline void timer0_load_write(uint32_t v) {
csr_write_simple(v, CSR_BASE + 0x4000L);
}
#define CSR_TIMER0_RELOAD_ADDR (CSR_BASE + 0x4004L)
#define CSR_TIMER0_RELOAD_SIZE 1
static inline uint32_t timer0_reload_read(void) {
return csr_read_simple(CSR_BASE + 0x4004L);
}
static inline void timer0_reload_write(uint32_t v) {
csr_write_simple(v, CSR_BASE + 0x4004L);
}
#define CSR_TIMER0_EN_ADDR (CSR_BASE + 0x4008L)
#define CSR_TIMER0_EN_SIZE 1
static inline uint32_t timer0_en_read(void) {
return csr_read_simple(CSR_BASE + 0x4008L);
}
static inline void timer0_en_write(uint32_t v) {
csr_write_simple(v, CSR_BASE + 0x4008L);
}
#define CSR_TIMER0_UPDATE_VALUE_ADDR (CSR_BASE + 0x400cL)
#define CSR_TIMER0_UPDATE_VALUE_SIZE 1
static inline uint32_t timer0_update_value_read(void) {
return csr_read_simple(CSR_BASE + 0x400cL);
}
static inline void timer0_update_value_write(uint32_t v) {
csr_write_simple(v, CSR_BASE + 0x400cL);
}
#define CSR_TIMER0_VALUE_ADDR (CSR_BASE + 0x4010L)
#define CSR_TIMER0_VALUE_SIZE 1
static inline uint32_t timer0_value_read(void) {
return csr_read_simple(CSR_BASE + 0x4010L);
}
#define CSR_TIMER0_EV_STATUS_ADDR (CSR_BASE + 0x4014L)
#define CSR_TIMER0_EV_STATUS_SIZE 1
static inline uint32_t timer0_ev_status_read(void) {
return csr_read_simple(CSR_BASE + 0x4014L);
}
#define CSR_TIMER0_EV_STATUS_ZERO_OFFSET 0
#define CSR_TIMER0_EV_STATUS_ZERO_SIZE 1
static inline uint32_t timer0_ev_status_zero_extract(uint32_t oldword) {
uint32_t mask = ((1 << 1)-1);
return ( (oldword >> 0) & mask );
}
static inline uint32_t timer0_ev_status_zero_read(void) {
uint32_t word = timer0_ev_status_read();
return timer0_ev_status_zero_extract(word);
}
#define CSR_TIMER0_EV_PENDING_ADDR (CSR_BASE + 0x4018L)
#define CSR_TIMER0_EV_PENDING_SIZE 1
static inline uint32_t timer0_ev_pending_read(void) {
return csr_read_simple(CSR_BASE + 0x4018L);
}
static inline void timer0_ev_pending_write(uint32_t v) {
csr_write_simple(v, CSR_BASE + 0x4018L);
}
#define CSR_TIMER0_EV_PENDING_ZERO_OFFSET 0
#define CSR_TIMER0_EV_PENDING_ZERO_SIZE 1
static inline uint32_t timer0_ev_pending_zero_extract(uint32_t oldword) {
uint32_t mask = ((1 << 1)-1);
return ( (oldword >> 0) & mask );
}
static inline uint32_t timer0_ev_pending_zero_read(void) {
uint32_t word = timer0_ev_pending_read();
return timer0_ev_pending_zero_extract(word);
}
static inline uint32_t timer0_ev_pending_zero_replace(uint32_t oldword, uint32_t plain_value) {
uint32_t mask = ((1 << 1)-1);
return (oldword & (~(mask << 0))) | (mask & plain_value)<< 0 ;
}
static inline void timer0_ev_pending_zero_write(uint32_t plain_value) {
uint32_t oldword = timer0_ev_pending_read();
uint32_t newword = timer0_ev_pending_zero_replace(oldword, plain_value);
timer0_ev_pending_write(newword);
}
#define CSR_TIMER0_EV_ENABLE_ADDR (CSR_BASE + 0x401cL)
#define CSR_TIMER0_EV_ENABLE_SIZE 1
static inline uint32_t timer0_ev_enable_read(void) {
return csr_read_simple(CSR_BASE + 0x401cL);
}
static inline void timer0_ev_enable_write(uint32_t v) {
csr_write_simple(v, CSR_BASE + 0x401cL);
}
#define CSR_TIMER0_EV_ENABLE_ZERO_OFFSET 0
#define CSR_TIMER0_EV_ENABLE_ZERO_SIZE 1
static inline uint32_t timer0_ev_enable_zero_extract(uint32_t oldword) {
uint32_t mask = ((1 << 1)-1);
return ( (oldword >> 0) & mask );
}
static inline uint32_t timer0_ev_enable_zero_read(void) {
uint32_t word = timer0_ev_enable_read();
return timer0_ev_enable_zero_extract(word);
}
static inline uint32_t timer0_ev_enable_zero_replace(uint32_t oldword, uint32_t plain_value) {
uint32_t mask = ((1 << 1)-1);
return (oldword & (~(mask << 0))) | (mask & plain_value)<< 0 ;
}
static inline void timer0_ev_enable_zero_write(uint32_t plain_value) {
uint32_t oldword = timer0_ev_enable_read();
uint32_t newword = timer0_ev_enable_zero_replace(oldword, plain_value);
timer0_ev_enable_write(newword);
}

#endif

@ -0,0 +1,9 @@
//--------------------------------------------------------------------------------
// Auto-generated by Migen (9a0be7a) & LiteX (85d6cb4b) on 2021-11-25 13:53:32
//--------------------------------------------------------------------------------
#ifndef __GENERATED_GIT_H
#define __GENERATED_GIT_H

#define MIGEN_GIT_SHA1 "9a0be7a"
#define LITEX_GIT_SHA1 "85d6cb4b"
#endif

@ -0,0 +1,20 @@
//--------------------------------------------------------------------------------
// Auto-generated by Migen (9a0be7a) & LiteX (85d6cb4b) on 2021-11-25 13:53:32
//--------------------------------------------------------------------------------
#ifndef __GENERATED_MEM_H
#define __GENERATED_MEM_H

#ifndef SRAM_BASE
#define SRAM_BASE 0x00000000L
#define SRAM_SIZE 0x00080000
#endif

#ifndef CSR_BASE
#define CSR_BASE 0xfff00000L
#define CSR_SIZE 0x00010000
#endif

#ifndef MEM_REGIONS
#define MEM_REGIONS "SRAM 0x00000000 0x80000 \nCSR 0xfff00000 0x10000 "
#endif
#endif

@ -0,0 +1,4 @@
MEMORY {
sram : ORIGIN = 0x00000000, LENGTH = 0x00080000
csr : ORIGIN = 0xfff00000, LENGTH = 0x00010000
}

@ -0,0 +1,55 @@
//--------------------------------------------------------------------------------
// Auto-generated by Migen (9a0be7a) & LiteX (85d6cb4b) on 2021-11-25 13:53:32
//--------------------------------------------------------------------------------
#ifndef __GENERATED_SOC_H
#define __GENERATED_SOC_H
#define CONFIG_CLOCK_FREQUENCY 50000000
#define CONFIG_CPU_HAS_INTERRUPT
#define CONFIG_CPU_RESET_ADDR 0
#define CONFIG_CPU_TYPE_A2P
#define CONFIG_CPU_VARIANT_STANDARD
#define CONFIG_CPU_HUMAN_NAME "A2P_WB"
#define CONFIG_CPU_NOP "nop"
#define CONFIG_WITH_BUILD_TIME
#define UART_POLLING
#define CONFIG_CSR_DATA_WIDTH 32
#define CONFIG_CSR_ALIGNMENT 32
#define CONFIG_BUS_STANDARD "WISHBONE"
#define CONFIG_BUS_DATA_WIDTH 32
#define CONFIG_BUS_ADDRESS_WIDTH 32
#define TIMER0_INTERRUPT 0

#ifndef __ASSEMBLER__
static inline int config_clock_frequency_read(void) {
return 50000000;
}
static inline int config_cpu_reset_addr_read(void) {
return 0;
}
static inline const char * config_cpu_human_name_read(void) {
return "A2P_WB";
}
static inline const char * config_cpu_nop_read(void) {
return "nop";
}
static inline int config_csr_data_width_read(void) {
return 32;
}
static inline int config_csr_alignment_read(void) {
return 32;
}
static inline const char * config_bus_standard_read(void) {
return "WISHBONE";
}
static inline int config_bus_data_width_read(void) {
return 32;
}
static inline int config_bus_address_width_read(void) {
return 32;
}
static inline int timer0_interrupt_read(void) {
return 0;
}
#endif // !__ASSEMBLER__

#endif

@ -0,0 +1,25 @@
PACKAGES=libc libcompiler_rt libbase libfatfs liblitespi liblitedram libliteeth liblitesdcard liblitesata bios
PACKAGE_DIRS=/home/wtf/projects/litex/litex/soc/software/libc /home/wtf/projects/litex/litex/soc/software/libcompiler_rt /home/wtf/projects/litex/litex/soc/software/libbase /home/wtf/projects/litex/litex/soc/software/libfatfs /home/wtf/projects/litex/litex/soc/software/liblitespi /home/wtf/projects/litex/litex/soc/software/liblitedram /home/wtf/projects/litex/litex/soc/software/libliteeth /home/wtf/projects/litex/litex/soc/software/liblitesdcard /home/wtf/projects/litex/litex/soc/software/liblitesata /home/wtf/projects/litex/litex/soc/software/bios
LIBS=libc libcompiler_rt libbase libfatfs liblitespi liblitedram libliteeth liblitesdcard liblitesata
TRIPLE=--not-found--
CPU=a2p
CPUFAMILY=ppc32
CPUFLAGS=-fomit-frame-pointer -Wall -fno-builtin -nostdinc -fno-stack-protector -fexceptions -Wstrict-prototypes -Wold-style-definition -Wmissing-prototypes -D__a2p__
CPUENDIANNESS=big
CLANG=0
CPU_DIRECTORY=/home/wtf/projects/a2p-opf/build/openroad/litex/a2p
SOC_DIRECTORY=/home/wtf/projects/litex/litex/soc
PICOLIBC_DIRECTORY=/home/wtf/projects/pythondata-software-picolibc/pythondata_software_picolibc/data
COMPILER_RT_DIRECTORY=/home/wtf/projects/pythondata-software-compiler_rt/pythondata_software_compiler_rt/data
export BUILDINC_DIRECTORY
BUILDINC_DIRECTORY=/home/wtf/projects/a2p-opf/build/openroad/litex/build/caravel_user/software/include
LIBC_DIRECTORY=/home/wtf/projects/litex/litex/soc/software/libc
LIBCOMPILER_RT_DIRECTORY=/home/wtf/projects/litex/litex/soc/software/libcompiler_rt
LIBBASE_DIRECTORY=/home/wtf/projects/litex/litex/soc/software/libbase
LIBFATFS_DIRECTORY=/home/wtf/projects/litex/litex/soc/software/libfatfs
LIBLITESPI_DIRECTORY=/home/wtf/projects/litex/litex/soc/software/liblitespi
LIBLITEDRAM_DIRECTORY=/home/wtf/projects/litex/litex/soc/software/liblitedram
LIBLITEETH_DIRECTORY=/home/wtf/projects/litex/litex/soc/software/libliteeth
LIBLITESDCARD_DIRECTORY=/home/wtf/projects/litex/litex/soc/software/liblitesdcard
LIBLITESATA_DIRECTORY=/home/wtf/projects/litex/litex/soc/software/liblitesata
BIOS_DIRECTORY=/home/wtf/projects/litex/litex/soc/software/bios

File diff suppressed because it is too large Load Diff

@ -0,0 +1,49 @@
# design and tech
export DESIGN_NICKNAME = a2p_litex
export DESIGN_NAME = top
export PLATFORM = sky130hd

export VERILOG_FILES := $(sort $(wildcard ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/src/*.v) \
./designs//$(PLATFORM)/$(DESIGN_NICKNAME)/litex/caravel_user.v \
./designs//$(PLATFORM)/$(DESIGN_NICKNAME)/litex/modules/issiram.v \
)
export SDC_FILE := ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc

$(info Source files:)
$(info $(VERILOG_FILES))
$(info ..................................................)

# design and tech
unit = a2p

export DIE_AREA = 0.0 0.0 5200 4609.14
export CORE_AREA = 210 210 4990 4389.14

export ABC_CLOCK_PERIOD_IN_PS = 10000
export ABC_DRIVER_CELL = sky130_fd_sc_hd__buf_1
export ABC_LOAD_IN_FF = 3

export SYNTH_MAX_FANOUT ?= 32
export SYNTH_MAX_TRAN ?= 100

export REPORT_SLACK_MAX_PATHS ?= 100

#HACK! uniquify logs, objects, reports, results
#wtf need to fix to all be in one timestamped dir
export DESIGN_NICKNAME := $(DESIGN_NICKNAME)/output/$(shell date "+%Y%m%d%H%M%S")
$(info [WTF] Output Dirs: $(DESIGN_NICKNAME))


# ----------------------------------------------------------------------------------
# ----------------------------------------------------------------------------------
# CTS

# forget about this for now - occurred when added dffram dir/caches. anton says hold misses are fake anyway :)
# do i need something else from dffram build?
# Repair hold violations...
# [INFO RSZ-0046] Found 60472 endpoints with hold violations.
# [WARNING RSZ-0066] Unable to repair all hold violations.
# [INFO RSZ-0032] Inserted 213923 hold buffers.
# [ERROR DPL-0019] detailed placement failed on hold33177
# continue if cts wants to barf...
export WTF_CTS_IGNORE_HOLD_MISSES = 1

@ -0,0 +1,32 @@
# A2P single-core with DFFRAM gpr, icdir, icdata, dcdir, dcdata gen'd by Litex

# ----------------------------------------------------------------------------------
# define clock

set clk_name wbs_clk_i
# set clk_period 50.0 ;# make it easy for or
#set clk_period 10.0 ;# 100Mhz
#set clk_period 25.0 ;# 40Mhz
set clk_period 40.0 ;# 25Mhz

puts "\[WTF\] clk_period=$clk_period"

set clkPort [get_ports $clk_name]
create_clock $clkPort -name clk -period $clk_period

# ----------------------------------------------------------------------------------
# apply clock to ins and outs

set input_delay_value 0.0
set output_delay_value 0.0

set clk_index [lsearch [all_inputs] $clkPort]
set all_inputs_wo_clk [lreplace [all_inputs] $clk_index $clk_index]
set_input_delay $input_delay_value -clock [get_clocks clk] $all_inputs_wo_clk
set_output_delay $output_delay_value -clock [get_clocks clk] [all_outputs]

# ----------------------------------------------------------------------------------
# false paths

set_false_path -from [get_ports {wbs_rst_i}] -to [get_clocks clk]
#set_false_path -from [get_ports {externalResetVector}] -to [get_clocks clk]

@ -0,0 +1,59 @@
#--------------------------------------------------------------------------------
# Auto-generated by Migen (9a0be7a) & LiteX (85d6cb4b) on 2021-11-25 13:53:32
#--------------------------------------------------------------------------------
csr_base,i2c,0xfff00800,,
csr_base,uart_0_phy,0xfff01000,,
csr_base,uart_0,0xfff01800,,
csr_base,uart_1_phy,0xfff02000,,
csr_base,uart_1,0xfff02800,,
csr_base,ctrl,0xfff03000,,
csr_base,identifier_mem,0xfff03800,,
csr_base,timer0,0xfff04000,,
csr_register,i2c_w,0xfff00800,1,rw
csr_register,i2c_r,0xfff00804,1,ro
csr_register,uart_0_phy_tuning_word,0xfff01000,1,rw
csr_register,uart_0_rxtx,0xfff01800,1,rw
csr_register,uart_0_txfull,0xfff01804,1,ro
csr_register,uart_0_rxempty,0xfff01808,1,ro
csr_register,uart_0_ev_status,0xfff0180c,1,ro
csr_register,uart_0_ev_pending,0xfff01810,1,rw
csr_register,uart_0_ev_enable,0xfff01814,1,rw
csr_register,uart_0_txempty,0xfff01818,1,ro
csr_register,uart_0_rxfull,0xfff0181c,1,ro
csr_register,uart_1_phy_tuning_word,0xfff02000,1,rw
csr_register,uart_1_rxtx,0xfff02800,1,rw
csr_register,uart_1_txfull,0xfff02804,1,ro
csr_register,uart_1_rxempty,0xfff02808,1,ro
csr_register,uart_1_ev_status,0xfff0280c,1,ro
csr_register,uart_1_ev_pending,0xfff02810,1,rw
csr_register,uart_1_ev_enable,0xfff02814,1,rw
csr_register,uart_1_txempty,0xfff02818,1,ro
csr_register,uart_1_rxfull,0xfff0281c,1,ro
csr_register,ctrl_reset,0xfff03000,1,rw
csr_register,ctrl_scratch,0xfff03004,1,rw
csr_register,ctrl_bus_errors,0xfff03008,1,ro
csr_register,timer0_load,0xfff04000,1,rw
csr_register,timer0_reload,0xfff04004,1,rw
csr_register,timer0_en,0xfff04008,1,rw
csr_register,timer0_update_value,0xfff0400c,1,rw
csr_register,timer0_value,0xfff04010,1,ro
csr_register,timer0_ev_status,0xfff04014,1,ro
csr_register,timer0_ev_pending,0xfff04018,1,rw
csr_register,timer0_ev_enable,0xfff0401c,1,rw
constant,config_clock_frequency,50000000,,
constant,config_cpu_has_interrupt,None,,
constant,config_cpu_reset_addr,0,,
constant,config_cpu_type_a2p,None,,
constant,config_cpu_variant_standard,None,,
constant,config_cpu_human_name,a2p_wb,,
constant,config_cpu_nop,nop,,
constant,config_with_build_time,None,,
constant,uart_polling,None,,
constant,config_csr_data_width,32,,
constant,config_csr_alignment,32,,
constant,config_bus_standard,wishbone,,
constant,config_bus_data_width,32,,
constant,config_bus_address_width,32,,
constant,timer0_interrupt,0,,
memory_region,sram,0x00000000,524288,cached
memory_region,csr,0xfff00000,65536,io
1 #--------------------------------------------------------------------------------
2 # Auto-generated by Migen (9a0be7a) & LiteX (85d6cb4b) on 2021-11-25 13:53:32
3 #--------------------------------------------------------------------------------
4 csr_base,i2c,0xfff00800,,
5 csr_base,uart_0_phy,0xfff01000,,
6 csr_base,uart_0,0xfff01800,,
7 csr_base,uart_1_phy,0xfff02000,,
8 csr_base,uart_1,0xfff02800,,
9 csr_base,ctrl,0xfff03000,,
10 csr_base,identifier_mem,0xfff03800,,
11 csr_base,timer0,0xfff04000,,
12 csr_register,i2c_w,0xfff00800,1,rw
13 csr_register,i2c_r,0xfff00804,1,ro
14 csr_register,uart_0_phy_tuning_word,0xfff01000,1,rw
15 csr_register,uart_0_rxtx,0xfff01800,1,rw
16 csr_register,uart_0_txfull,0xfff01804,1,ro
17 csr_register,uart_0_rxempty,0xfff01808,1,ro
18 csr_register,uart_0_ev_status,0xfff0180c,1,ro
19 csr_register,uart_0_ev_pending,0xfff01810,1,rw
20 csr_register,uart_0_ev_enable,0xfff01814,1,rw
21 csr_register,uart_0_txempty,0xfff01818,1,ro
22 csr_register,uart_0_rxfull,0xfff0181c,1,ro
23 csr_register,uart_1_phy_tuning_word,0xfff02000,1,rw
24 csr_register,uart_1_rxtx,0xfff02800,1,rw
25 csr_register,uart_1_txfull,0xfff02804,1,ro
26 csr_register,uart_1_rxempty,0xfff02808,1,ro
27 csr_register,uart_1_ev_status,0xfff0280c,1,ro
28 csr_register,uart_1_ev_pending,0xfff02810,1,rw
29 csr_register,uart_1_ev_enable,0xfff02814,1,rw
30 csr_register,uart_1_txempty,0xfff02818,1,ro
31 csr_register,uart_1_rxfull,0xfff0281c,1,ro
32 csr_register,ctrl_reset,0xfff03000,1,rw
33 csr_register,ctrl_scratch,0xfff03004,1,rw
34 csr_register,ctrl_bus_errors,0xfff03008,1,ro
35 csr_register,timer0_load,0xfff04000,1,rw
36 csr_register,timer0_reload,0xfff04004,1,rw
37 csr_register,timer0_en,0xfff04008,1,rw
38 csr_register,timer0_update_value,0xfff0400c,1,rw
39 csr_register,timer0_value,0xfff04010,1,ro
40 csr_register,timer0_ev_status,0xfff04014,1,ro
41 csr_register,timer0_ev_pending,0xfff04018,1,rw
42 csr_register,timer0_ev_enable,0xfff0401c,1,rw
43 constant,config_clock_frequency,50000000,,
44 constant,config_cpu_has_interrupt,None,,
45 constant,config_cpu_reset_addr,0,,
46 constant,config_cpu_type_a2p,None,,
47 constant,config_cpu_variant_standard,None,,
48 constant,config_cpu_human_name,a2p_wb,,
49 constant,config_cpu_nop,nop,,
50 constant,config_with_build_time,None,,
51 constant,uart_polling,None,,
52 constant,config_csr_data_width,32,,
53 constant,config_csr_alignment,32,,
54 constant,config_bus_standard,wishbone,,
55 constant,config_bus_data_width,32,,
56 constant,config_bus_address_width,32,,
57 constant,timer0_interrupt,0,,
58 memory_region,sram,0x00000000,524288,cached
59 memory_region,csr,0xfff00000,65536,io

@ -0,0 +1,42 @@
41
32
50
20
43
61
72
61
76
65
6c
20
53
69
74
65
20
54
65
73
74
20
32
30
32
31
2d
31
31
2d
32
35
20
30
39
3a
30
30
3a
35
33
00

@ -0,0 +1,102 @@
#!/usr/bin/python3

"""© IBM Corp. 2020
Licensed under the Apache License, Version 2.0 (the "License"), as modified by the terms below; you may not use the files in this
repository except in compliance with the License as modified.
You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0

Modified Terms:

1) For the purpose of the patent license granted to you in Section 3 of the License, the "Work" hereby includes implementations of
the work of authorship in physical form.

2) Notwithstanding any terms to the contrary in the License, any licenses necessary for implementation of the Work that are available
from OpenPOWER via the Power ISA End User License Agreement (EULA) are explicitly excluded hereunder, and may be obtained from OpenPOWER
under the terms and conditions of the EULA.

Unless required by applicable law or agreed to in writing, the reference design distributed under the License is distributed on an
"AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language
governing permissions and limitations under the License.

Additional rights, including the ability to physically implement a softcore that is compliant with the required sections of the Power
ISA Specification, are available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be obtained (along with the Power
ISA) here: https://openpowerfoundation.org.

Brief explanation of modifications:

Modification 1: This modification extends the patent license to an implementation of the Work in physical form i.e.,
it unambiguously permits a user to make and use the physical chip.

Modification 2: This modification clarifies that licenses for the Power ISA are provided via the (royalty-free) Power ISA EULA,
and not under this license. To prevent fragmentation of the Power ISA, the Power ISA EULA requires that Power ISA Cores be
licensed consistent with the terms of the Power ISA EULA. By ensuring that rights available via the Power ISA EULA are received
under (and subject to) the EULA, this consistency is maintained in accordance with the terms of the EULA. Any necessary additional
licenses for the specific Power ISA Core are granted under this modified Apache license.
"""

from migen import *
# if want AutoCSR
#from litex.soc.interconnect.csr import *
#class WB_ExtMem(Module, AutoCSR):
class ISSIRam(Module):

def __init__(self, module, clk, rst, wishbone, pins):

self.bus = wishbone
self.data_width = 32
self.size = 524288

module.specials += Instance("issiram",
i_clk = clk,
i_rst = rst,
i_wbs_stb_i = wishbone.stb,
i_wbs_cyc_i = wishbone.cyc,
i_wbs_adr_i = wishbone.adr,
i_wbs_we_i = wishbone.we,
i_wbs_sel_i = wishbone.sel,
i_wbs_dat_i = wishbone.dat_w,
o_wbs_ack_o = wishbone.ack,
o_wbs_dat_o = wishbone.dat_r,
o_mem_ce_n = pins['ce'],
o_mem_oe_n = pins['oe'],
o_mem_we_n = pins['we'],
o_mem_adr = pins['adr'],
io_mem_dat = pins['dat']
)

#def _to_signal(self, obj):
# return obj.raw_bits() if isinstance(obj, Record) else obj


if __name__ == '__main__':

from litex.build.generic_platform import *
from litex.soc.interconnect import wishbone

# need to use local; no oen here
# from litex_boards.platforms import cmod_a7
import sys
binPath = os.path.dirname(os.path.realpath(__file__))
sys.path.append(os.path.join(binPath, '../../build/litex'))
from platforms import cmod7

platform = cmod7.Platform()

platform.add_source("issiram.v")
clk = ClockSignal()
rst = ResetSignal()
bus = wishbone.Interface()

issiram = platform.request('issiram')
pins = {
'ce': issiram.cen,
'oe': issiram.oen,
'we': issiram.wen,
'adr': issiram.addr,
'dat': issiram.data
}
module = Module()
extmem = ISSIRam(module, clk, rst, bus, pins)

platform.build(module)

@ -0,0 +1,362 @@
/*
© IBM Corp. 2020
Licensed under the Apache License, Version 2.0 (the "License"), as modified by the terms below; you may not use the files in this
repository except in compliance with the License as modified.
You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0

Modified Terms:

1) For the purpose of the patent license granted to you in Section 3 of the License, the "Work" hereby includes implementations of
the work of authorship in physical form.

2) Notwithstanding any terms to the contrary in the License, any licenses necessary for implementation of the Work that are available
from OpenPOWER via the Power ISA End User License Agreement (EULA) are explicitly excluded hereunder, and may be obtained from OpenPOWER
under the terms and conditions of the EULA.

Unless required by applicable law or agreed to in writing, the reference design distributed under the License is distributed on an
"AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language
governing permissions and limitations under the License.

Additional rights, including the ability to physically implement a softcore that is compliant with the required sections of the Power
ISA Specification, are available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be obtained (along with the Power
ISA) here: https://openpowerfoundation.org.

Brief explanation of modifications:

Modification 1: This modification extends the patent license to an implementation of the Work in physical form i.e.,
it unambiguously permits a user to make and use the physical chip.

Modification 2: This modification clarifies that licenses for the Power ISA are provided via the (royalty-free) Power ISA EULA,
and not under this license. To prevent fragmentation of the Power ISA, the Power ISA EULA requires that Power ISA Cores be
licensed consistent with the terms of the Power ISA EULA. By ensuring that rights available via the Power ISA EULA are received
under (and subject to) the EULA, this consistency is maintained in accordance with the terms of the EULA. Any necessary additional
licenses for the specific Power ISA Core are granted under this modified Apache license.
*/

`timescale 1 ns / 1 ns

// Asynchronous SRAM Wishbone Slave (IS61WV5128)
// 32b non-pipelined, 3-cycle write, 512Kx8

module issiram #(
parameter WB_BITWIDTH = 32,
parameter RAM_BITWIDTH = 8
)(
input clk,
input rst,
input wbs_stb_i,
input wbs_cyc_i,
input [29:0] wbs_adr_i,
input wbs_we_i,
input [3:0] wbs_sel_i,
input [31:0] wbs_dat_i,
output wbs_ack_o,
output [31:0] wbs_dat_o,
output mem_ce_n,
output mem_oe_n,
output mem_we_n,
output [18:0] mem_adr,
inout [7:0] mem_dat
);

reg [18:0] cmd_adr_q;
wire [18:0] cmd_adr_d;
reg ack_q;
wire ack_d;
reg [31:0] rd_dat_q;
wire [31:0] rd_dat_d;
reg [3:0] wr_sel_q;
wire [3:0] wr_sel_d;
reg [31:0] wr_dat_q;
wire [31:0] wr_dat_d;
reg [5:0] seq_q;
wire [5:0] seq_d;

wire stall;
wire base_match;
wire cmd_val;
wire cmd_we;
wire idle;
wire read;
wire write;
wire oe;

// FF
always @(posedge clk) begin
if (rst) begin
cmd_adr_q <= 'h0;
ack_q <= 'b0;
rd_dat_q <= 'h0;
wr_sel_q <= 'b0;
wr_dat_q <= 'h0;
seq_q <= 'b111111;
end else begin
cmd_adr_q <= cmd_adr_d;
ack_q <= ack_d;
rd_dat_q <= rd_dat_d;
wr_sel_q <= wr_sel_d;
wr_dat_q <= wr_dat_d;
seq_q <= seq_d;
end
end

// WB Interface

assign stall = 0; // not supported
assign base_match = 1; // if need to check address range locally

assign cmd_val = idle & wbs_cyc_i & wbs_stb_i & ~stall & base_match & ~ack_q;
assign cmd_we = wbs_we_i;
assign cmd_adr_d = cmd_val ? {wbs_adr_i[16:0], 2'b00} : cmd_adr_q;
assign wr_sel_d = cmd_val ? wbs_sel_i : wr_sel_q;
assign wr_dat_d = cmd_val ? wbs_dat_i : wr_dat_q;

// R/W Sequencer

// R2,W3
// cmod-a7; runs 100

//tbl rwseq
//n seq_q seq_d
//n | cmd_val | read
//n | |cmd_we | |write
//n | ||wr_sel_q | ||oe
//n | ||| | |||ack_d
//n | ||| | ||||
//n | ||| | ||||
//n | ||| | ||||idle
//b 543210 ||3210 543210 |||||
//t iiiiii iiiiii oooooo ooooo
//*------------------------------------------------
//* Idle ******************************************
//s 111111 ------ ------ ----1
//s 111111 0----- 111111 0010- * ...zzz...
//s 111111 10---- 010000 0010- * read32
//s 111111 11---- 110000 0010- * write32
//* Read 0a****************************************
//s 010000 ------ 011000 00100
//* Read 0b****************************************
//s 011000 ------ 010001 10100
//* Read 1a****************************************
//s 010001 ------ 011001 00100
//* Read 1b****************************************
//s 011001 ------ 010010 10100
//* Read 2a ***************************************
//s 010010 ------ 011010 00100
//* Read 2b ***************************************
//s 011010 ------ 010011 10100
//* Read 3a ***************************************
//s 010011 ------ 011011 00100
//* Read 3b ***************************************
//s 011011 ------ 111111 10110 * done
//* Write 0a **************************************
//s 110000 -----1 110100 01100
//s 110000 -----0 110001 00100
//* Write 0b **************************************
//s 110100 ------ 111000 01000
//* Write 0c **************************************
//s 111000 ------ 110001 01100
//* Write 1a **************************************
//s 110001 ----1- 110101 01100
//s 110001 ----0- 110010 00100
//* Write 1b **************************************
//s 110101 ------ 111001 01000
//* Write 1c **************************************
//s 111001 ------ 110010 01100
//* Write 2a **************************************
//s 110010 ---1-- 110110 01100
//s 110010 ---0-- 110011 00100
//* Write 2b **************************************
//s 110110 ------ 111010 01000
//* Write 2c **************************************
//s 111010 ------ 110011 01100
//* Write 3a **************************************
//s 110011 --1--- 110111 01100
//s 110011 --0--- 111111 00110 * done
//* Write 3b **************************************
//s 110111 ------ 111011 01000
//* Write 3c **************************************
//s 111011 ------ 111111 01110 * done
//*------------------------------------------------
//tbl rwseq

// Tristate Data

assign rd_dat_d[7:0] = (read & (seq_q[1:0] == 2'b00)) ? mem_dat : rd_dat_q[7:0];
assign rd_dat_d[15:8] = (read & (seq_q[1:0] == 2'b01)) ? mem_dat : rd_dat_q[15:8];
assign rd_dat_d[23:16] = (read & (seq_q[1:0] == 2'b10)) ? mem_dat : rd_dat_q[23:16];
assign rd_dat_d[31:24] = (read & (seq_q[1:0] == 2'b11)) ? mem_dat : rd_dat_q[31:24];

assign mem_dat = write ? (seq_q[1:0] == 2'b00 ? wr_dat_q[7:0] :
seq_q[1:0] == 2'b01 ? wr_dat_q[15:8] :
seq_q[1:0] == 2'b10 ? wr_dat_q[23:16] :
wr_dat_q[31:24]) :
8'bz;

// Outputs

assign wbs_ack_o = ack_q & ~rst;
assign wbs_dat_o = rd_dat_q;

assign mem_ce_n = 'b0;
assign mem_oe_n = ~oe;
assign mem_we_n = ~write;
assign mem_adr = {cmd_adr_q[18:2], seq_q[1:0]};

// Generated
//vtable rwseq
assign seq_d[5] =
(seq_q[5] & seq_q[4] & seq_q[3] & seq_q[2] & seq_q[1] & seq_q[0] & ~cmd_val) +
(seq_q[5] & seq_q[4] & seq_q[3] & seq_q[2] & seq_q[1] & seq_q[0] & cmd_val & cmd_we) +
(~seq_q[5] & seq_q[4] & seq_q[3] & ~seq_q[2] & seq_q[1] & seq_q[0]) +
(seq_q[5] & seq_q[4] & ~seq_q[3] & ~seq_q[2] & ~seq_q[1] & ~seq_q[0] & wr_sel_q[0]) +
(seq_q[5] & seq_q[4] & ~seq_q[3] & ~seq_q[2] & ~seq_q[1] & ~seq_q[0] & ~wr_sel_q[0]) +
(seq_q[5] & seq_q[4] & ~seq_q[3] & seq_q[2] & ~seq_q[1] & ~seq_q[0]) +
(seq_q[5] & seq_q[4] & seq_q[3] & ~seq_q[2] & ~seq_q[1] & ~seq_q[0]) +
(seq_q[5] & seq_q[4] & ~seq_q[3] & ~seq_q[2] & ~seq_q[1] & seq_q[0] & wr_sel_q[1]) +
(seq_q[5] & seq_q[4] & ~seq_q[3] & ~seq_q[2] & ~seq_q[1] & seq_q[0] & ~wr_sel_q[1]) +
(seq_q[5] & seq_q[4] & ~seq_q[3] & seq_q[2] & ~seq_q[1] & seq_q[0]) +
(seq_q[5] & seq_q[4] & seq_q[3] & ~seq_q[2] & ~seq_q[1] & seq_q[0]) +
(seq_q[5] & seq_q[4] & ~seq_q[3] & ~seq_q[2] & seq_q[1] & ~seq_q[0] & wr_sel_q[2]) +
(seq_q[5] & seq_q[4] & ~seq_q[3] & ~seq_q[2] & seq_q[1] & ~seq_q[0] & ~wr_sel_q[2]) +
(seq_q[5] & seq_q[4] & ~seq_q[3] & seq_q[2] & seq_q[1] & ~seq_q[0]) +
(seq_q[5] & seq_q[4] & seq_q[3] & ~seq_q[2] & seq_q[1] & ~seq_q[0]) +
(seq_q[5] & seq_q[4] & ~seq_q[3] & ~seq_q[2] & seq_q[1] & seq_q[0] & wr_sel_q[3]) +
(seq_q[5] & seq_q[4] & ~seq_q[3] & ~seq_q[2] & seq_q[1] & seq_q[0] & ~wr_sel_q[3]) +
(seq_q[5] & seq_q[4] & ~seq_q[3] & seq_q[2] & seq_q[1] & seq_q[0]) +
(seq_q[5] & seq_q[4] & seq_q[3] & ~seq_q[2] & seq_q[1] & seq_q[0]);
assign seq_d[4] =
(seq_q[5] & seq_q[4] & seq_q[3] & seq_q[2] & seq_q[1] & seq_q[0] & ~cmd_val) +
(seq_q[5] & seq_q[4] & seq_q[3] & seq_q[2] & seq_q[1] & seq_q[0] & cmd_val & ~cmd_we) +
(seq_q[5] & seq_q[4] & seq_q[3] & seq_q[2] & seq_q[1] & seq_q[0] & cmd_val & cmd_we) +
(~seq_q[5] & seq_q[4] & ~seq_q[3] & ~seq_q[2] & ~seq_q[1] & ~seq_q[0]) +
(~seq_q[5] & seq_q[4] & seq_q[3] & ~seq_q[2] & ~seq_q[1] & ~seq_q[0]) +
(~seq_q[5] & seq_q[4] & ~seq_q[3] & ~seq_q[2] & ~seq_q[1] & seq_q[0]) +
(~seq_q[5] & seq_q[4] & seq_q[3] & ~seq_q[2] & ~seq_q[1] & seq_q[0]) +
(~seq_q[5] & seq_q[4] & ~seq_q[3] & ~seq_q[2] & seq_q[1] & ~seq_q[0]) +
(~seq_q[5] & seq_q[4] & seq_q[3] & ~seq_q[2] & seq_q[1] & ~seq_q[0]) +
(~seq_q[5] & seq_q[4] & ~seq_q[3] & ~seq_q[2] & seq_q[1] & seq_q[0]) +
(~seq_q[5] & seq_q[4] & seq_q[3] & ~seq_q[2] & seq_q[1] & seq_q[0]) +
(seq_q[5] & seq_q[4] & ~seq_q[3] & ~seq_q[2] & ~seq_q[1] & ~seq_q[0] & wr_sel_q[0]) +
(seq_q[5] & seq_q[4] & ~seq_q[3] & ~seq_q[2] & ~seq_q[1] & ~seq_q[0] & ~wr_sel_q[0]) +
(seq_q[5] & seq_q[4] & ~seq_q[3] & seq_q[2] & ~seq_q[1] & ~seq_q[0]) +
(seq_q[5] & seq_q[4] & seq_q[3] & ~seq_q[2] & ~seq_q[1] & ~seq_q[0]) +
(seq_q[5] & seq_q[4] & ~seq_q[3] & ~seq_q[2] & ~seq_q[1] & seq_q[0] & wr_sel_q[1]) +
(seq_q[5] & seq_q[4] & ~seq_q[3] & ~seq_q[2] & ~seq_q[1] & seq_q[0] & ~wr_sel_q[1]) +
(seq_q[5] & seq_q[4] & ~seq_q[3] & seq_q[2] & ~seq_q[1] & seq_q[0]) +
(seq_q[5] & seq_q[4] & seq_q[3] & ~seq_q[2] & ~seq_q[1] & seq_q[0]) +
(seq_q[5] & seq_q[4] & ~seq_q[3] & ~seq_q[2] & seq_q[1] & ~seq_q[0] & wr_sel_q[2]) +
(seq_q[5] & seq_q[4] & ~seq_q[3] & ~seq_q[2] & seq_q[1] & ~seq_q[0] & ~wr_sel_q[2]) +
(seq_q[5] & seq_q[4] & ~seq_q[3] & seq_q[2] & seq_q[1] & ~seq_q[0]) +
(seq_q[5] & seq_q[4] & seq_q[3] & ~seq_q[2] & seq_q[1] & ~seq_q[0]) +
(seq_q[5] & seq_q[4] & ~seq_q[3] & ~seq_q[2] & seq_q[1] & seq_q[0] & wr_sel_q[3]) +
(seq_q[5] & seq_q[4] & ~seq_q[3] & ~seq_q[2] & seq_q[1] & seq_q[0] & ~wr_sel_q[3]) +
(seq_q[5] & seq_q[4] & ~seq_q[3] & seq_q[2] & seq_q[1] & seq_q[0]) +
(seq_q[5] & seq_q[4] & seq_q[3] & ~seq_q[2] & seq_q[1] & seq_q[0]);
assign seq_d[3] =
(seq_q[5] & seq_q[4] & seq_q[3] & seq_q[2] & seq_q[1] & seq_q[0] & ~cmd_val) +
(~seq_q[5] & seq_q[4] & ~seq_q[3] & ~seq_q[2] & ~seq_q[1] & ~seq_q[0]) +
(~seq_q[5] & seq_q[4] & ~seq_q[3] & ~seq_q[2] & ~seq_q[1] & seq_q[0]) +
(~seq_q[5] & seq_q[4] & ~seq_q[3] & ~seq_q[2] & seq_q[1] & ~seq_q[0]) +
(~seq_q[5] & seq_q[4] & ~seq_q[3] & ~seq_q[2] & seq_q[1] & seq_q[0]) +
(~seq_q[5] & seq_q[4] & seq_q[3] & ~seq_q[2] & seq_q[1] & seq_q[0]) +
(seq_q[5] & seq_q[4] & ~seq_q[3] & seq_q[2] & ~seq_q[1] & ~seq_q[0]) +
(seq_q[5] & seq_q[4] & ~seq_q[3] & seq_q[2] & ~seq_q[1] & seq_q[0]) +
(seq_q[5] & seq_q[4] & ~seq_q[3] & seq_q[2] & seq_q[1] & ~seq_q[0]) +
(seq_q[5] & seq_q[4] & ~seq_q[3] & ~seq_q[2] & seq_q[1] & seq_q[0] & ~wr_sel_q[3]) +
(seq_q[5] & seq_q[4] & ~seq_q[3] & seq_q[2] & seq_q[1] & seq_q[0]) +
(seq_q[5] & seq_q[4] & seq_q[3] & ~seq_q[2] & seq_q[1] & seq_q[0]);
assign seq_d[2] =
(seq_q[5] & seq_q[4] & seq_q[3] & seq_q[2] & seq_q[1] & seq_q[0] & ~cmd_val) +
(~seq_q[5] & seq_q[4] & seq_q[3] & ~seq_q[2] & seq_q[1] & seq_q[0]) +
(seq_q[5] & seq_q[4] & ~seq_q[3] & ~seq_q[2] & ~seq_q[1] & ~seq_q[0] & wr_sel_q[0]) +
(seq_q[5] & seq_q[4] & ~seq_q[3] & ~seq_q[2] & ~seq_q[1] & seq_q[0] & wr_sel_q[1]) +
(seq_q[5] & seq_q[4] & ~seq_q[3] & ~seq_q[2] & seq_q[1] & ~seq_q[0] & wr_sel_q[2]) +
(seq_q[5] & seq_q[4] & ~seq_q[3] & ~seq_q[2] & seq_q[1] & seq_q[0] & wr_sel_q[3]) +
(seq_q[5] & seq_q[4] & ~seq_q[3] & ~seq_q[2] & seq_q[1] & seq_q[0] & ~wr_sel_q[3]) +
(seq_q[5] & seq_q[4] & seq_q[3] & ~seq_q[2] & seq_q[1] & seq_q[0]);
assign seq_d[1] =
(seq_q[5] & seq_q[4] & seq_q[3] & seq_q[2] & seq_q[1] & seq_q[0] & ~cmd_val) +
(~seq_q[5] & seq_q[4] & seq_q[3] & ~seq_q[2] & ~seq_q[1] & seq_q[0]) +
(~seq_q[5] & seq_q[4] & ~seq_q[3] & ~seq_q[2] & seq_q[1] & ~seq_q[0]) +
(~seq_q[5] & seq_q[4] & seq_q[3] & ~seq_q[2] & seq_q[1] & ~seq_q[0]) +
(~seq_q[5] & seq_q[4] & ~seq_q[3] & ~seq_q[2] & seq_q[1] & seq_q[0]) +
(~seq_q[5] & seq_q[4] & seq_q[3] & ~seq_q[2] & seq_q[1] & seq_q[0]) +
(seq_q[5] & seq_q[4] & ~seq_q[3] & ~seq_q[2] & ~seq_q[1] & seq_q[0] & ~wr_sel_q[1]) +
(seq_q[5] & seq_q[4] & seq_q[3] & ~seq_q[2] & ~seq_q[1] & seq_q[0]) +
(seq_q[5] & seq_q[4] & ~seq_q[3] & ~seq_q[2] & seq_q[1] & ~seq_q[0] & wr_sel_q[2]) +
(seq_q[5] & seq_q[4] & ~seq_q[3] & ~seq_q[2] & seq_q[1] & ~seq_q[0] & ~wr_sel_q[2]) +
(seq_q[5] & seq_q[4] & ~seq_q[3] & seq_q[2] & seq_q[1] & ~seq_q[0]) +
(seq_q[5] & seq_q[4] & seq_q[3] & ~seq_q[2] & seq_q[1] & ~seq_q[0]) +
(seq_q[5] & seq_q[4] & ~seq_q[3] & ~seq_q[2] & seq_q[1] & seq_q[0] & wr_sel_q[3]) +
(seq_q[5] & seq_q[4] & ~seq_q[3] & ~seq_q[2] & seq_q[1] & seq_q[0] & ~wr_sel_q[3]) +
(seq_q[5] & seq_q[4] & ~seq_q[3] & seq_q[2] & seq_q[1] & seq_q[0]) +
(seq_q[5] & seq_q[4] & seq_q[3] & ~seq_q[2] & seq_q[1] & seq_q[0]);
assign seq_d[0] =
(seq_q[5] & seq_q[4] & seq_q[3] & seq_q[2] & seq_q[1] & seq_q[0] & ~cmd_val) +
(~seq_q[5] & seq_q[4] & seq_q[3] & ~seq_q[2] & ~seq_q[1] & ~seq_q[0]) +
(~seq_q[5] & seq_q[4] & ~seq_q[3] & ~seq_q[2] & ~seq_q[1] & seq_q[0]) +
(~seq_q[5] & seq_q[4] & seq_q[3] & ~seq_q[2] & seq_q[1] & ~seq_q[0]) +
(~seq_q[5] & seq_q[4] & ~seq_q[3] & ~seq_q[2] & seq_q[1] & seq_q[0]) +
(~seq_q[5] & seq_q[4] & seq_q[3] & ~seq_q[2] & seq_q[1] & seq_q[0]) +
(seq_q[5] & seq_q[4] & ~seq_q[3] & ~seq_q[2] & ~seq_q[1] & ~seq_q[0] & ~wr_sel_q[0]) +
(seq_q[5] & seq_q[4] & seq_q[3] & ~seq_q[2] & ~seq_q[1] & ~seq_q[0]) +
(seq_q[5] & seq_q[4] & ~seq_q[3] & ~seq_q[2] & ~seq_q[1] & seq_q[0] & wr_sel_q[1]) +
(seq_q[5] & seq_q[4] & ~seq_q[3] & seq_q[2] & ~seq_q[1] & seq_q[0]) +
(seq_q[5] & seq_q[4] & ~seq_q[3] & ~seq_q[2] & seq_q[1] & ~seq_q[0] & ~wr_sel_q[2]) +
(seq_q[5] & seq_q[4] & seq_q[3] & ~seq_q[2] & seq_q[1] & ~seq_q[0]) +
(seq_q[5] & seq_q[4] & ~seq_q[3] & ~seq_q[2] & seq_q[1] & seq_q[0] & wr_sel_q[3]) +
(seq_q[5] & seq_q[4] & ~seq_q[3] & ~seq_q[2] & seq_q[1] & seq_q[0] & ~wr_sel_q[3]) +
(seq_q[5] & seq_q[4] & ~seq_q[3] & seq_q[2] & seq_q[1] & seq_q[0]) +
(seq_q[5] & seq_q[4] & seq_q[3] & ~seq_q[2] & seq_q[1] & seq_q[0]);
assign read =
(~seq_q[5] & seq_q[4] & seq_q[3] & ~seq_q[2] & ~seq_q[1] & ~seq_q[0]) +
(~seq_q[5] & seq_q[4] & seq_q[3] & ~seq_q[2] & ~seq_q[1] & seq_q[0]) +
(~seq_q[5] & seq_q[4] & seq_q[3] & ~seq_q[2] & seq_q[1] & ~seq_q[0]) +
(~seq_q[5] & seq_q[4] & seq_q[3] & ~seq_q[2] & seq_q[1] & seq_q[0]);
assign write =
(seq_q[5] & seq_q[4] & ~seq_q[3] & ~seq_q[2] & ~seq_q[1] & ~seq_q[0] & wr_sel_q[0]) +
(seq_q[5] & seq_q[4] & ~seq_q[3] & seq_q[2] & ~seq_q[1] & ~seq_q[0]) +
(seq_q[5] & seq_q[4] & seq_q[3] & ~seq_q[2] & ~seq_q[1] & ~seq_q[0]) +
(seq_q[5] & seq_q[4] & ~seq_q[3] & ~seq_q[2] & ~seq_q[1] & seq_q[0] & wr_sel_q[1]) +
(seq_q[5] & seq_q[4] & ~seq_q[3] & seq_q[2] & ~seq_q[1] & seq_q[0]) +
(seq_q[5] & seq_q[4] & seq_q[3] & ~seq_q[2] & ~seq_q[1] & seq_q[0]) +
(seq_q[5] & seq_q[4] & ~seq_q[3] & ~seq_q[2] & seq_q[1] & ~seq_q[0] & wr_sel_q[2]) +
(seq_q[5] & seq_q[4] & ~seq_q[3] & seq_q[2] & seq_q[1] & ~seq_q[0]) +
(seq_q[5] & seq_q[4] & seq_q[3] & ~seq_q[2] & seq_q[1] & ~seq_q[0]) +
(seq_q[5] & seq_q[4] & ~seq_q[3] & ~seq_q[2] & seq_q[1] & seq_q[0] & wr_sel_q[3]) +
(seq_q[5] & seq_q[4] & ~seq_q[3] & seq_q[2] & seq_q[1] & seq_q[0]) +
(seq_q[5] & seq_q[4] & seq_q[3] & ~seq_q[2] & seq_q[1] & seq_q[0]);
assign oe =
(seq_q[5] & seq_q[4] & seq_q[3] & seq_q[2] & seq_q[1] & seq_q[0] & ~cmd_val) +
(seq_q[5] & seq_q[4] & seq_q[3] & seq_q[2] & seq_q[1] & seq_q[0] & cmd_val & ~cmd_we) +
(seq_q[5] & seq_q[4] & seq_q[3] & seq_q[2] & seq_q[1] & seq_q[0] & cmd_val & cmd_we) +
(~seq_q[5] & seq_q[4] & ~seq_q[3] & ~seq_q[2] & ~seq_q[1] & ~seq_q[0]) +
(~seq_q[5] & seq_q[4] & seq_q[3] & ~seq_q[2] & ~seq_q[1] & ~seq_q[0]) +
(~seq_q[5] & seq_q[4] & ~seq_q[3] & ~seq_q[2] & ~seq_q[1] & seq_q[0]) +
(~seq_q[5] & seq_q[4] & seq_q[3] & ~seq_q[2] & ~seq_q[1] & seq_q[0]) +
(~seq_q[5] & seq_q[4] & ~seq_q[3] & ~seq_q[2] & seq_q[1] & ~seq_q[0]) +
(~seq_q[5] & seq_q[4] & seq_q[3] & ~seq_q[2] & seq_q[1] & ~seq_q[0]) +
(~seq_q[5] & seq_q[4] & ~seq_q[3] & ~seq_q[2] & seq_q[1] & seq_q[0]) +
(~seq_q[5] & seq_q[4] & seq_q[3] & ~seq_q[2] & seq_q[1] & seq_q[0]) +
(seq_q[5] & seq_q[4] & ~seq_q[3] & ~seq_q[2] & ~seq_q[1] & ~seq_q[0] & wr_sel_q[0]) +
(seq_q[5] & seq_q[4] & ~seq_q[3] & ~seq_q[2] & ~seq_q[1] & ~seq_q[0] & ~wr_sel_q[0]) +
(seq_q[5] & seq_q[4] & seq_q[3] & ~seq_q[2] & ~seq_q[1] & ~seq_q[0]) +
(seq_q[5] & seq_q[4] & ~seq_q[3] & ~seq_q[2] & ~seq_q[1] & seq_q[0] & wr_sel_q[1]) +
(seq_q[5] & seq_q[4] & ~seq_q[3] & ~seq_q[2] & ~seq_q[1] & seq_q[0] & ~wr_sel_q[1]) +
(seq_q[5] & seq_q[4] & seq_q[3] & ~seq_q[2] & ~seq_q[1] & seq_q[0]) +
(seq_q[5] & seq_q[4] & ~seq_q[3] & ~seq_q[2] & seq_q[1] & ~seq_q[0] & wr_sel_q[2]) +
(seq_q[5] & seq_q[4] & ~seq_q[3] & ~seq_q[2] & seq_q[1] & ~seq_q[0] & ~wr_sel_q[2]) +
(seq_q[5] & seq_q[4] & seq_q[3] & ~seq_q[2] & seq_q[1] & ~seq_q[0]) +
(seq_q[5] & seq_q[4] & ~seq_q[3] & ~seq_q[2] & seq_q[1] & seq_q[0] & wr_sel_q[3]) +
(seq_q[5] & seq_q[4] & ~seq_q[3] & ~seq_q[2] & seq_q[1] & seq_q[0] & ~wr_sel_q[3]) +
(seq_q[5] & seq_q[4] & seq_q[3] & ~seq_q[2] & seq_q[1] & seq_q[0]);
assign ack_d =
(~seq_q[5] & seq_q[4] & seq_q[3] & ~seq_q[2] & seq_q[1] & seq_q[0]) +
(seq_q[5] & seq_q[4] & ~seq_q[3] & ~seq_q[2] & seq_q[1] & seq_q[0] & ~wr_sel_q[3]) +
(seq_q[5] & seq_q[4] & seq_q[3] & ~seq_q[2] & seq_q[1] & seq_q[0]);
assign idle =
(seq_q[5] & seq_q[4] & seq_q[3] & seq_q[2] & seq_q[1] & seq_q[0]);
//vtable rwseq

endmodule

File diff suppressed because it is too large Load Diff

@ -0,0 +1,328 @@
OpenROAD v2.0-1901-g6157d4945
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
[INFO ODB-0222] Reading LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd.tlef
[INFO ODB-0223] Created 11 technology layers
[INFO ODB-0224] Created 25 technology vias
[INFO ODB-0226] Finished LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd.tlef
[INFO ODB-0222] Reading LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd_merged.lef
[INFO ODB-0225] Created 437 library cells
[INFO ODB-0226] Finished LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd_merged.lef
[WTF] clk_period=40.0
[WARNING STA-0337] port 'externalResetVector' not found.
[WARNING STA-0369] no valid objects specified for -from.
number instances in verilog is 452883
[INFO IFP-0001] Added 1535 rows of 10390 sites.
[INFO RSZ-0026] Removed 35343 buffers.
Default units for flow
time 1ns
capacitance 1pF
resistance 1kohm
voltage 1v
current 1mA
power 1nW
distance 1um

==========================================================================
floorplan final report_checks -path_delay min
--------------------------------------------------------------------------
Startpoint: _444084_ (rising edge-triggered flip-flop clocked by clk)
Endpoint: _443496_ (removal check against rising-edge clock clk)
Path Group: **async_default**
Path Type: min

Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 0.00 ^ _444084_/CLK (sky130_fd_sc_hd__dfxtp_1)
0.05 0.29 0.29 v _444084_/Q (sky130_fd_sc_hd__dfxtp_1)
3 0.01 basesoc_basesoc_reset_storage[0] (net)
0.05 0.00 0.30 v _385035_/A1 (sky130_fd_sc_hd__a211oi_1)
16.81 22.09 22.38 ^ _385035_/Y (sky130_fd_sc_hd__a211oi_1)
285 1.07 _000415_ (net)
16.81 0.00 22.39 ^ _443496_/RESET_B (sky130_fd_sc_hd__dfrtp_1)
22.39 data arrival time

0.00 0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 clock reconvergence pessimism
0.00 ^ _443496_/CLK (sky130_fd_sc_hd__dfrtp_1)
4.79 4.79 library removal time
4.79 data required time
-----------------------------------------------------------------------------
4.79 data required time
-22.39 data arrival time
-----------------------------------------------------------------------------
17.60 slack (MET)


Startpoint: in_in[0] (input port clocked by clk)
Endpoint: _387093_ (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: min

Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 ^ input external delay
0.00 0.00 0.00 ^ in_in[0] (in)
1 0.00 in_in[0] (net)
0.00 0.00 0.00 ^ _387093_/D (sky130_fd_sc_hd__dfxtp_1)
0.00 data arrival time

0.00 0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 clock reconvergence pessimism
0.00 ^ _387093_/CLK (sky130_fd_sc_hd__dfxtp_1)
-0.03 -0.03 library hold time
-0.03 data required time
-----------------------------------------------------------------------------
-0.03 data required time
-0.00 data arrival time
-----------------------------------------------------------------------------
0.03 slack (MET)



==========================================================================
floorplan final report_checks -path_delay max
--------------------------------------------------------------------------
Startpoint: _387097_ (rising edge-triggered flip-flop clocked by clk)
Endpoint: _443496_ (recovery check against rising-edge clock clk)
Path Group: **async_default**
Path Type: max

Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 0.00 ^ _387097_/CLK (sky130_fd_sc_hd__dfxtp_1)
3.99 3.26 3.26 v _387097_/Q (sky130_fd_sc_hd__dfxtp_1)
379 0.89 int_rst (net)
3.99 0.00 3.27 v _385035_/C1 (sky130_fd_sc_hd__a211oi_1)
30.61 23.23 26.50 ^ _385035_/Y (sky130_fd_sc_hd__a211oi_1)
285 1.07 _000415_ (net)
30.61 0.00 26.50 ^ _443496_/RESET_B (sky130_fd_sc_hd__dfrtp_1)
26.50 data arrival time

0.00 40.00 40.00 clock clk (rise edge)
0.00 40.00 clock network delay (ideal)
0.00 40.00 clock reconvergence pessimism
40.00 ^ _443496_/CLK (sky130_fd_sc_hd__dfrtp_1)
-8.06 31.94 library recovery time
31.94 data required time
-----------------------------------------------------------------------------
31.94 data required time
-26.50 data arrival time
-----------------------------------------------------------------------------
5.44 slack (MET)


Startpoint: _387097_ (rising edge-triggered flip-flop clocked by clk)
Endpoint: A2P_WB.IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[0].B.genblk1.CG
(rising clock gating-check end-point clocked by clk')
Path Group: clk
Path Type: max

Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 0.00 ^ _387097_/CLK (sky130_fd_sc_hd__dfxtp_1)
9.03 6.59 6.59 ^ _387097_/Q (sky130_fd_sc_hd__dfxtp_1)
379 0.98 int_rst (net)
9.03 0.00 6.60 ^ _196316_/A (sky130_fd_sc_hd__inv_1)
2.14 3.34 9.93 v _196316_/Y (sky130_fd_sc_hd__inv_1)
49 0.12 _058400_ (net)
2.14 0.00 9.94 v _196317_/A2 (sky130_fd_sc_hd__a21oi_1)
0.37 0.67 10.61 ^ _196317_/Y (sky130_fd_sc_hd__a21oi_1)
1 0.00 _058401_ (net)
0.37 0.01 10.61 ^ _196318_/B1 (sky130_fd_sc_hd__o41ai_2)
0.12 0.17 10.78 v _196318_/Y (sky130_fd_sc_hd__o41ai_2)
4 0.01 _058402_ (net)
0.12 0.00 10.79 v _196466_/A2 (sky130_fd_sc_hd__a311oi_1)
0.47 0.48 11.27 ^ _196466_/Y (sky130_fd_sc_hd__a311oi_1)
2 0.01 _058481_ (net)
0.47 0.00 11.28 ^ _196604_/A2 (sky130_fd_sc_hd__o31a_1)
9.06 6.54 17.82 ^ _196604_/X (sky130_fd_sc_hd__o31a_1)
359 0.91 _058558_ (net)
9.06 0.00 17.82 ^ _196767_/A (sky130_fd_sc_hd__nor3_1)
2.16 2.24 20.06 v _196767_/Y (sky130_fd_sc_hd__nor3_1)
22 0.05 _058712_ (net)
2.16 0.00 20.06 v _196770_/B1 (sky130_fd_sc_hd__a221o_1)
0.15 0.93 20.99 v _196770_/X (sky130_fd_sc_hd__a221o_1)
6 0.02 _058715_ (net)
0.15 0.00 21.00 v _196775_/A2 (sky130_fd_sc_hd__o21ai_2)
515.31 372.36 393.36 ^ _196775_/Y (sky130_fd_sc_hd__o21ai_2)
19863 50.50 _058720_ (net)
515.31 0.00 393.36 ^ _196785_/A2 (sky130_fd_sc_hd__o21ai_0)
20.90 3089.90 3483.26 v _196785_/Y (sky130_fd_sc_hd__o21ai_0)
1024 1.98 A2P_WB.IBusCachedPlugin_cache.ways_0_datas.adr[1] (net)
20.90 0.00 3483.26 v A2P_WB.IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.DEC0.AND2/C (sky130_fd_sc_hd__and4bb_2)
0.64 7.79 3491.06 v A2P_WB.IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.DEC0.AND2/X (sky130_fd_sc_hd__and4bb_2)
8 0.02 A2P_WB.IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.SEL0 (net)
0.64 0.00 3491.06 v A2P_WB.IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[0].B.CGAND/A (sky130_fd_sc_hd__and2_1)
0.20 0.35 3491.41 v A2P_WB.IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[0].B.CGAND/X (sky130_fd_sc_hd__and2_1)
1 0.00 A2P_WB.IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[0].B.WE0_WIRE (net)
0.20 0.00 3491.41 v A2P_WB.IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[0].B.genblk1.CG/GATE (sky130_fd_sc_hd__dlclkp_1)
3491.41 data arrival time

0.00 20.00 20.00 clock clk' (rise edge)
0.00 20.00 clock network delay (ideal)
0.00 20.00 clock reconvergence pessimism
20.00 ^ A2P_WB.IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[0].B.genblk1.CG/CLK (sky130_fd_sc_hd__dlclkp_1)
-0.19 19.81 library setup time
19.81 data required time
-----------------------------------------------------------------------------
19.81 data required time
-3491.41 data arrival time
-----------------------------------------------------------------------------
-3471.60 slack (VIOLATED)



==========================================================================
floorplan final report_checks -unconstrained
--------------------------------------------------------------------------
Startpoint: _387097_ (rising edge-triggered flip-flop clocked by clk)
Endpoint: _443496_ (recovery check against rising-edge clock clk)
Path Group: **async_default**
Path Type: max

Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 0.00 ^ _387097_/CLK (sky130_fd_sc_hd__dfxtp_1)
3.99 3.26 3.26 v _387097_/Q (sky130_fd_sc_hd__dfxtp_1)
379 0.89 int_rst (net)
3.99 0.00 3.27 v _385035_/C1 (sky130_fd_sc_hd__a211oi_1)
30.61 23.23 26.50 ^ _385035_/Y (sky130_fd_sc_hd__a211oi_1)
285 1.07 _000415_ (net)
30.61 0.00 26.50 ^ _443496_/RESET_B (sky130_fd_sc_hd__dfrtp_1)
26.50 data arrival time

0.00 40.00 40.00 clock clk (rise edge)
0.00 40.00 clock network delay (ideal)
0.00 40.00 clock reconvergence pessimism
40.00 ^ _443496_/CLK (sky130_fd_sc_hd__dfrtp_1)
-8.06 31.94 library recovery time
31.94 data required time
-----------------------------------------------------------------------------
31.94 data required time
-26.50 data arrival time
-----------------------------------------------------------------------------
5.44 slack (MET)


Startpoint: _387097_ (rising edge-triggered flip-flop clocked by clk)
Endpoint: A2P_WB.IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[0].B.genblk1.CG
(rising clock gating-check end-point clocked by clk')
Path Group: clk
Path Type: max

Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 0.00 ^ _387097_/CLK (sky130_fd_sc_hd__dfxtp_1)
9.03 6.59 6.59 ^ _387097_/Q (sky130_fd_sc_hd__dfxtp_1)
379 0.98 int_rst (net)
9.03 0.00 6.60 ^ _196316_/A (sky130_fd_sc_hd__inv_1)
2.14 3.34 9.93 v _196316_/Y (sky130_fd_sc_hd__inv_1)
49 0.12 _058400_ (net)
2.14 0.00 9.94 v _196317_/A2 (sky130_fd_sc_hd__a21oi_1)
0.37 0.67 10.61 ^ _196317_/Y (sky130_fd_sc_hd__a21oi_1)
1 0.00 _058401_ (net)
0.37 0.01 10.61 ^ _196318_/B1 (sky130_fd_sc_hd__o41ai_2)
0.12 0.17 10.78 v _196318_/Y (sky130_fd_sc_hd__o41ai_2)
4 0.01 _058402_ (net)
0.12 0.00 10.79 v _196466_/A2 (sky130_fd_sc_hd__a311oi_1)
0.47 0.48 11.27 ^ _196466_/Y (sky130_fd_sc_hd__a311oi_1)
2 0.01 _058481_ (net)
0.47 0.00 11.28 ^ _196604_/A2 (sky130_fd_sc_hd__o31a_1)
9.06 6.54 17.82 ^ _196604_/X (sky130_fd_sc_hd__o31a_1)
359 0.91 _058558_ (net)
9.06 0.00 17.82 ^ _196767_/A (sky130_fd_sc_hd__nor3_1)
2.16 2.24 20.06 v _196767_/Y (sky130_fd_sc_hd__nor3_1)
22 0.05 _058712_ (net)
2.16 0.00 20.06 v _196770_/B1 (sky130_fd_sc_hd__a221o_1)
0.15 0.93 20.99 v _196770_/X (sky130_fd_sc_hd__a221o_1)
6 0.02 _058715_ (net)
0.15 0.00 21.00 v _196775_/A2 (sky130_fd_sc_hd__o21ai_2)
515.31 372.36 393.36 ^ _196775_/Y (sky130_fd_sc_hd__o21ai_2)
19863 50.50 _058720_ (net)
515.31 0.00 393.36 ^ _196785_/A2 (sky130_fd_sc_hd__o21ai_0)
20.90 3089.90 3483.26 v _196785_/Y (sky130_fd_sc_hd__o21ai_0)
1024 1.98 A2P_WB.IBusCachedPlugin_cache.ways_0_datas.adr[1] (net)
20.90 0.00 3483.26 v A2P_WB.IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.DEC0.AND2/C (sky130_fd_sc_hd__and4bb_2)
0.64 7.79 3491.06 v A2P_WB.IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.DEC0.AND2/X (sky130_fd_sc_hd__and4bb_2)
8 0.02 A2P_WB.IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.SEL0 (net)
0.64 0.00 3491.06 v A2P_WB.IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[0].B.CGAND/A (sky130_fd_sc_hd__and2_1)
0.20 0.35 3491.41 v A2P_WB.IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[0].B.CGAND/X (sky130_fd_sc_hd__and2_1)
1 0.00 A2P_WB.IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[0].B.WE0_WIRE (net)
0.20 0.00 3491.41 v A2P_WB.IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[0].B.genblk1.CG/GATE (sky130_fd_sc_hd__dlclkp_1)
3491.41 data arrival time

0.00 20.00 20.00 clock clk' (rise edge)
0.00 20.00 clock network delay (ideal)
0.00 20.00 clock reconvergence pessimism
20.00 ^ A2P_WB.IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[2].W.BYTE[0].B.genblk1.CG/CLK (sky130_fd_sc_hd__dlclkp_1)
-0.19 19.81 library setup time
19.81 data required time
-----------------------------------------------------------------------------
19.81 data required time
-3491.41 data arrival time
-----------------------------------------------------------------------------
-3471.60 slack (VIOLATED)



==========================================================================
floorplan final report_tns
--------------------------------------------------------------------------
tns -7698805.00

==========================================================================
floorplan final report_wns
--------------------------------------------------------------------------
wns -3471.60

==========================================================================
floorplan final report_worst_slack
--------------------------------------------------------------------------
worst slack -3471.60

==========================================================================
floorplan final report_clock_skew
--------------------------------------------------------------------------
Clock clk
Latency CRPR Skew
A2P_WB.IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[0].RAM128.BLOCK[0].RAM32.SLICE[0].RAM8.WORD[0].W.BYTE[0].B.BIT[1].genblk1.STORAGE/GATE ^
0.26
A2P_WB.IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[0].RAM128.BLOCK[0].RAM32.Do0_FF[1]/CLK ^
0.00 0.00 0.26


==========================================================================
floorplan final report_power
--------------------------------------------------------------------------
Group Internal Switching Leakage Total
Power Power Power Power
----------------------------------------------------------------
Sequential 1.02e-01 2.57e-03 9.37e-07 1.05e-01 50.5%
Combinational 8.47e-02 1.78e-02 9.13e-07 1.02e-01 49.5%
Macro 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
Pad 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
----------------------------------------------------------------
Total 1.87e-01 2.03e-02 1.85e-06 2.07e-01 100.0%
90.2% 9.8% 0.0%

==========================================================================
floorplan final report_design_area
--------------------------------------------------------------------------
Design area 4680897 u^2 23% utilization.

Elapsed time: 2:55.02[h:]min:sec. CPU time: user 174.41 sys 0.58 (99%). Peak memory: 1336796KB.

@ -0,0 +1,28 @@
OpenROAD v2.0-1901-g6157d4945
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
[INFO ODB-0222] Reading LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd.tlef
[INFO ODB-0223] Created 11 technology layers
[INFO ODB-0224] Created 25 technology vias
[INFO ODB-0226] Finished LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd.tlef
[INFO ODB-0222] Reading LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd_merged.lef
[INFO ODB-0225] Created 437 library cells
[INFO ODB-0226] Finished LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd_merged.lef
[INFO ODB-0127] Reading DEF file: ./results/sky130hd/a2p_litex/output/20211125124450/base/2_1_floorplan.def
[INFO ODB-0128] Design: top
[INFO ODB-0094] Created 100000 Insts
[INFO ODB-0094] Created 200000 Insts
[INFO ODB-0094] Created 300000 Insts
[INFO ODB-0094] Created 400000 Insts
[INFO ODB-0097] Created 100000 Nets
[INFO ODB-0097] Created 200000 Nets
[INFO ODB-0097] Created 300000 Nets
[INFO ODB-0130] Created 533 pins.
[INFO ODB-0131] Created 417540 components and 2206334 component-terminals.
[INFO ODB-0133] Created 347346 nets and 1370964 connections.
[INFO ODB-0134] Finished DEF file: ./results/sky130hd/a2p_litex/output/20211125124450/base/2_1_floorplan.def
Found 0 macro blocks.
Using 1u default distance from corners.
Using 2 tracks default min distance between IO pins.
[INFO PPL-0007] Random pin placement.
Elapsed time: 0:06.03[h:]min:sec. CPU time: user 5.74 sys 0.25 (99%). Peak memory: 610948KB.

@ -0,0 +1,28 @@
OpenROAD v2.0-1901-g6157d4945
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
[INFO ODB-0222] Reading LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd.tlef
[INFO ODB-0223] Created 11 technology layers
[INFO ODB-0224] Created 25 technology vias
[INFO ODB-0226] Finished LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd.tlef
[INFO ODB-0222] Reading LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd_merged.lef
[INFO ODB-0225] Created 437 library cells
[INFO ODB-0226] Finished LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd_merged.lef
[INFO ODB-0127] Reading DEF file: ./results/sky130hd/a2p_litex/output/20211125124450/base/2_2_floorplan_io.def
[INFO ODB-0128] Design: top
[INFO ODB-0094] Created 100000 Insts
[INFO ODB-0094] Created 200000 Insts
[INFO ODB-0094] Created 300000 Insts
[INFO ODB-0094] Created 400000 Insts
[INFO ODB-0097] Created 100000 Nets
[INFO ODB-0097] Created 200000 Nets
[INFO ODB-0097] Created 300000 Nets
[INFO ODB-0130] Created 533 pins.
[INFO ODB-0131] Created 417540 components and 2206334 component-terminals.
[INFO ODB-0133] Created 347346 nets and 1370964 connections.
[INFO ODB-0134] Finished DEF file: ./results/sky130hd/a2p_litex/output/20211125124450/base/2_2_floorplan_io.def
[WTF] clk_period=40.0
[WARNING STA-0337] port 'externalResetVector' not found.
[WARNING STA-0369] no valid objects specified for -from.
No macros found: Skipping global_placement
Elapsed time: 0:06.38[h:]min:sec. CPU time: user 6.07 sys 0.27 (99%). Peak memory: 600852KB.

@ -0,0 +1,28 @@
OpenROAD v2.0-1901-g6157d4945
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
[INFO ODB-0222] Reading LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd.tlef
[INFO ODB-0223] Created 11 technology layers
[INFO ODB-0224] Created 25 technology vias
[INFO ODB-0226] Finished LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd.tlef
[INFO ODB-0222] Reading LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd_merged.lef
[INFO ODB-0225] Created 437 library cells
[INFO ODB-0226] Finished LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd_merged.lef
[INFO ODB-0127] Reading DEF file: ./results/sky130hd/a2p_litex/output/20211125124450/base/2_3_floorplan_tdms.def
[INFO ODB-0128] Design: top
[INFO ODB-0094] Created 100000 Insts
[INFO ODB-0094] Created 200000 Insts
[INFO ODB-0094] Created 300000 Insts
[INFO ODB-0094] Created 400000 Insts
[INFO ODB-0097] Created 100000 Nets
[INFO ODB-0097] Created 200000 Nets
[INFO ODB-0097] Created 300000 Nets
[INFO ODB-0130] Created 533 pins.
[INFO ODB-0131] Created 417540 components and 2206334 component-terminals.
[INFO ODB-0133] Created 347346 nets and 1370964 connections.
[INFO ODB-0134] Finished DEF file: ./results/sky130hd/a2p_litex/output/20211125124450/base/2_3_floorplan_tdms.def
[WTF] clk_period=40.0
[WARNING STA-0337] port 'externalResetVector' not found.
[WARNING STA-0369] no valid objects specified for -from.
No macros found: Skipping macro_placement
Elapsed time: 0:06.19[h:]min:sec. CPU time: user 5.89 sys 0.27 (99%). Peak memory: 600444KB.

@ -0,0 +1,29 @@
OpenROAD v2.0-1901-g6157d4945
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
[INFO ODB-0222] Reading LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd.tlef
[INFO ODB-0223] Created 11 technology layers
[INFO ODB-0224] Created 25 technology vias
[INFO ODB-0226] Finished LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd.tlef
[INFO ODB-0222] Reading LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd_merged.lef
[INFO ODB-0225] Created 437 library cells
[INFO ODB-0226] Finished LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd_merged.lef
[INFO ODB-0127] Reading DEF file: ./results/sky130hd/a2p_litex/output/20211125124450/base/2_4_floorplan_macro.def
[INFO ODB-0128] Design: top
[INFO ODB-0094] Created 100000 Insts
[INFO ODB-0094] Created 200000 Insts
[INFO ODB-0094] Created 300000 Insts
[INFO ODB-0094] Created 400000 Insts
[INFO ODB-0097] Created 100000 Nets
[INFO ODB-0097] Created 200000 Nets
[INFO ODB-0097] Created 300000 Nets
[INFO ODB-0130] Created 533 pins.
[INFO ODB-0131] Created 417540 components and 2206334 component-terminals.
[INFO ODB-0133] Created 347346 nets and 1370964 connections.
[INFO ODB-0134] Finished DEF file: ./results/sky130hd/a2p_litex/output/20211125124450/base/2_4_floorplan_macro.def
[WARNING TAP-0014] endcap_cpp option is deprecated.
[INFO TAP-0001] Found 0 macro blocks.
[INFO TAP-0002] Original rows: 1535
[INFO TAP-0003] Created 0 rows for a total of 1535 rows.
[INFO TAP-0005] Inserted 265901 tapcells.
Elapsed time: 0:06.53[h:]min:sec. CPU time: user 6.23 sys 0.27 (99%). Peak memory: 440540KB.

@ -0,0 +1,47 @@
OpenROAD v2.0-1901-g6157d4945
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
[INFO ODB-0222] Reading LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd.tlef
[INFO ODB-0223] Created 11 technology layers
[INFO ODB-0224] Created 25 technology vias
[INFO ODB-0226] Finished LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd.tlef
[INFO ODB-0222] Reading LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd_merged.lef
[INFO ODB-0225] Created 437 library cells
[INFO ODB-0226] Finished LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd_merged.lef
[INFO ODB-0127] Reading DEF file: ./results/sky130hd/a2p_litex/output/20211125124450/base/2_5_floorplan_tapcell.def
[INFO ODB-0128] Design: top
[INFO ODB-0094] Created 100000 Insts
[INFO ODB-0094] Created 200000 Insts
[INFO ODB-0094] Created 300000 Insts
[INFO ODB-0094] Created 400000 Insts
[INFO ODB-0094] Created 500000 Insts
[INFO ODB-0094] Created 600000 Insts
[INFO ODB-0097] Created 100000 Nets
[INFO ODB-0097] Created 200000 Nets
[INFO ODB-0097] Created 300000 Nets
[INFO ODB-0130] Created 533 pins.
[INFO ODB-0131] Created 683441 components and 2738136 component-terminals.
[INFO ODB-0133] Created 347346 nets and 1370964 connections.
[INFO ODB-0134] Finished DEF file: ./results/sky130hd/a2p_litex/output/20211125124450/base/2_5_floorplan_tapcell.def
[INFO PDN-0016] Power Delivery Network Generator: Generating PDN
config: ./platforms/sky130hd/pdn.cfg
[INFO PDN-0008] Design name is top.
[INFO PDN-0009] Reading technology data.
[INFO PDN-0011] ****** INFO ******
Type: stdcell, grid
Stdcell Rails
Layer: met1 - width: 0.480 pitch: 5.440 offset: 0.000
Straps
Layer: met4 - width: 1.600 pitch: 27.140 offset: 13.570
Layer: met5 - width: 1.600 pitch: 27.200 offset: 13.600
Connect: {met1 met4} {met4 met5}
Type: macro, CORE_macro_grid_1
Macro orientation: R0 R180 MX MY
Connect: {met4_PIN_ver met5}
Type: macro, CORE_macro_grid_2
Macro orientation: R90 R270 MXR90 MYR90
Connect: {met4_PIN_hor met5}
[INFO PDN-0012] **** END INFO ****
[INFO PDN-0013] Inserting stdcell grid - grid.
[INFO PDN-0015] Writing to database.
Elapsed time: 0:46.89[h:]min:sec. CPU time: user 45.44 sys 1.41 (99%). Peak memory: 3781116KB.

@ -0,0 +1,519 @@
OpenROAD v2.0-1901-g6157d4945
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
[INFO ODB-0222] Reading LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd.tlef
[INFO ODB-0223] Created 11 technology layers
[INFO ODB-0224] Created 25 technology vias
[INFO ODB-0226] Finished LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd.tlef
[INFO ODB-0222] Reading LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd_merged.lef
[INFO ODB-0225] Created 437 library cells
[INFO ODB-0226] Finished LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd_merged.lef
[INFO ODB-0127] Reading DEF file: ./results/sky130hd/a2p_litex/output/20211125124450/base/2_floorplan.def
[INFO ODB-0128] Design: top
[INFO ODB-0094] Created 100000 Insts
[INFO ODB-0094] Created 200000 Insts
[INFO ODB-0094] Created 300000 Insts
[INFO ODB-0094] Created 400000 Insts
[INFO ODB-0094] Created 500000 Insts
[INFO ODB-0094] Created 600000 Insts
[INFO ODB-0097] Created 100000 Nets
[INFO ODB-0097] Created 200000 Nets
[INFO ODB-0097] Created 300000 Nets
[INFO ODB-0130] Created 533 pins.
[INFO ODB-0131] Created 683441 components and 2738136 component-terminals.
[INFO ODB-0132] Created 2 special nets and 1366882 connections.
[INFO ODB-0133] Created 347346 nets and 1370964 connections.
[INFO ODB-0134] Finished DEF file: ./results/sky130hd/a2p_litex/output/20211125124450/base/2_floorplan.def
[INFO GPL-0002] DBU: 1000
[INFO GPL-0003] SiteSize: 460 2720
[INFO GPL-0004] CoreAreaLxLy: 210220 212160
[INFO GPL-0005] CoreAreaUxUy: 4989620 4387360
[INFO GPL-0006] NumInstances: 683441
[INFO GPL-0007] NumPlaceInstances: 417540
[INFO GPL-0008] NumFixedInstances: 265901
[INFO GPL-0009] NumDummyInstances: 0
[INFO GPL-0010] NumNets: 347346
[INFO GPL-0011] NumPins: 1371497
[INFO GPL-0012] DieAreaLxLy: 0 0
[INFO GPL-0013] DieAreaUxUy: 5200000 4609140
[INFO GPL-0014] CoreAreaLxLy: 210220 212160
[INFO GPL-0015] CoreAreaUxUy: 4989620 4387360
[INFO GPL-0016] CoreArea: 19954950880000
[INFO GPL-0017] NonPlaceInstsArea: 332695331200
[INFO GPL-0018] PlaceInstsArea: 8860305235200
[INFO GPL-0019] Util(%): 45.15
[INFO GPL-0020] StdInstsArea: 8860305235200
[INFO GPL-0021] MacroInstsArea: 0
[InitialPlace] Iter: 1 CG Error: 0.00476767 HPWL: 2881631440
[InitialPlace] Iter: 2 CG Error: 0.00028251 HPWL: 3220992706
[InitialPlace] Iter: 3 CG Error: 0.00004466 HPWL: 3263160336
[InitialPlace] Iter: 4 CG Error: 0.00001819 HPWL: 3277630523
[InitialPlace] Iter: 5 CG Error: 0.00001581 HPWL: 3277120263
[InitialPlace] Iter: 6 CG Error: 0.00001325 HPWL: 3279509625
[InitialPlace] Iter: 7 CG Error: 0.00001373 HPWL: 3277968503
[InitialPlace] Iter: 8 CG Error: 0.00001260 HPWL: 3279975990
[InitialPlace] Iter: 9 CG Error: 0.00001282 HPWL: 3278343485
[InitialPlace] Iter: 10 CG Error: 0.00001217 HPWL: 3280076139
[InitialPlace] Iter: 11 CG Error: 0.00001224 HPWL: 3278598677
[InitialPlace] Iter: 12 CG Error: 0.00001092 HPWL: 3280266645
[InitialPlace] Iter: 13 CG Error: 0.00001125 HPWL: 3278663198
[InitialPlace] Iter: 14 CG Error: 0.00001086 HPWL: 3280339816
[InitialPlace] Iter: 15 CG Error: 0.00000991 HPWL: 3278770210
[INFO GPL-0031] FillerInit: NumGCells: 555498
[INFO GPL-0032] FillerInit: NumGNets: 347346
[INFO GPL-0033] FillerInit: NumGPins: 1371497
[INFO GPL-0023] TargetDensity: 0.60
[INFO GPL-0024] AveragePlaceInstArea: 21220254
[INFO GPL-0025] IdealBinArea: 35367088
[INFO GPL-0026] IdealBinCnt: 564223
[INFO GPL-0027] TotalBinArea: 19954950880000
[INFO GPL-0028] BinCnt: 512 512
[INFO GPL-0029] BinSize: 9335 8155
[INFO GPL-0030] NumBins: 262144
[NesterovSolve] Iter: 1 overflow: 0.999655 HPWL: 372967566
[NesterovSolve] Iter: 10 overflow: 0.999577 HPWL: 415264128
[NesterovSolve] Iter: 20 overflow: 0.999471 HPWL: 419190294
[NesterovSolve] Iter: 30 overflow: 0.999391 HPWL: 420251720
[NesterovSolve] Iter: 40 overflow: 0.999333 HPWL: 421300440
[NesterovSolve] Iter: 50 overflow: 0.999285 HPWL: 421785921
[NesterovSolve] Iter: 60 overflow: 0.999287 HPWL: 422589683
[NesterovSolve] Iter: 70 overflow: 0.999274 HPWL: 423344509
[NesterovSolve] Iter: 80 overflow: 0.99925 HPWL: 424066190
[NesterovSolve] Iter: 90 overflow: 0.999235 HPWL: 424816803
[NesterovSolve] Iter: 100 overflow: 0.999209 HPWL: 425571110
[NesterovSolve] Iter: 110 overflow: 0.999197 HPWL: 426224143
[NesterovSolve] Iter: 120 overflow: 0.999192 HPWL: 426713358
[NesterovSolve] Iter: 130 overflow: 0.999178 HPWL: 427103833
[NesterovSolve] Iter: 140 overflow: 0.999173 HPWL: 427445648
[NesterovSolve] Iter: 150 overflow: 0.999173 HPWL: 427975950
[NesterovSolve] Iter: 160 overflow: 0.999171 HPWL: 429342885
[NesterovSolve] Iter: 170 overflow: 0.999138 HPWL: 432132467
[NesterovSolve] Iter: 180 overflow: 0.999123 HPWL: 437439840
[NesterovSolve] Iter: 190 overflow: 0.999105 HPWL: 448351242
[NesterovSolve] Iter: 200 overflow: 0.999013 HPWL: 473969960
[NesterovSolve] Iter: 210 overflow: 0.998887 HPWL: 531852686
[NesterovSolve] Iter: 220 overflow: 0.998665 HPWL: 643087341
[NesterovSolve] Iter: 230 overflow: 0.998354 HPWL: 788824127
[NesterovSolve] Iter: 240 overflow: 0.997734 HPWL: 950119955
[NesterovSolve] Iter: 250 overflow: 0.996773 HPWL: 1132475815
[NesterovSolve] Iter: 260 overflow: 0.995226 HPWL: 1345694931
[NesterovSolve] Iter: 270 overflow: 0.993153 HPWL: 1603814341
[NesterovSolve] Iter: 280 overflow: 0.990426 HPWL: 1915910217
[NesterovSolve] Iter: 290 overflow: 0.987118 HPWL: 2303638337
[NesterovSolve] Iter: 300 overflow: 0.982451 HPWL: 2790208685
[NesterovSolve] Iter: 310 overflow: 0.97594 HPWL: 3397694546
[NesterovSolve] Iter: 320 overflow: 0.966625 HPWL: 4156749120
[NesterovSolve] Iter: 330 overflow: 0.954496 HPWL: 5032126330
[NesterovSolve] Iter: 340 overflow: 0.938504 HPWL: 5969110457
[NesterovSolve] Iter: 350 overflow: 0.919921 HPWL: 6880890252
[NesterovSolve] Iter: 360 overflow: 0.901606 HPWL: 7658350930
[NesterovSolve] Iter: 370 overflow: 0.881927 HPWL: 8336323775
[NesterovSolve] Iter: 380 overflow: 0.856271 HPWL: 8911530348
[NesterovSolve] Iter: 390 overflow: 0.826507 HPWL: 9400911648
[NesterovSolve] Iter: 400 overflow: 0.795797 HPWL: 10007842059
[NesterovSolve] Iter: 410 overflow: 0.765046 HPWL: 10821975045
[NesterovSolve] Iter: 420 overflow: 0.734093 HPWL: 11831062284
[NesterovSolve] Iter: 430 overflow: 0.69918 HPWL: 13275806516
[NesterovSolve] Iter: 440 overflow: 0.668211 HPWL: 13735342544
[NesterovSolve] Iter: 450 overflow: 0.621002 HPWL: 14518816564
[NesterovSolve] Snapshot saved at iter = 454
[NesterovSolve] Iter: 460 overflow: 0.581219 HPWL: 14886905997
[NesterovSolve] Iter: 470 overflow: 0.540646 HPWL: 14441227682
[NesterovSolve] Iter: 480 overflow: 0.497012 HPWL: 13801169717
[NesterovSolve] Iter: 490 overflow: 0.464284 HPWL: 13144434178
[NesterovSolve] Iter: 500 overflow: 0.431626 HPWL: 13004007682
[NesterovSolve] Iter: 510 overflow: 0.407367 HPWL: 12250376611
[NesterovSolve] Iter: 520 overflow: 0.380475 HPWL: 11751305049
[NesterovSolve] Iter: 530 overflow: 0.353644 HPWL: 11313054527
[NesterovSolve] Iter: 540 overflow: 0.329116 HPWL: 10894623767
[NesterovSolve] Iter: 550 overflow: 0.307252 HPWL: 10521445573
[NesterovSolve] Iter: 560 overflow: 0.285406 HPWL: 10226850186
[NesterovSolve] Iter: 570 overflow: 0.256967 HPWL: 10013993049
[NesterovSolve] Iter: 580 overflow: 0.219324 HPWL: 9849795888
[INFO GPL-0075] Routability numCall: 1 inflationIterCnt: 1 bloatIterCnt: 0
[INFO GRT-0020] Min routing layer: met1
[INFO GRT-0021] Max routing layer: met5
[INFO GRT-0022] Global adjustment: 0%
[INFO GRT-0023] Grid origin: (0, 0)
[WARNING GRT-0043] No OR_DEFAULT vias defined.
[INFO GRT-0224] Chose via L1M1_PR as default.
[INFO GRT-0224] Chose via M1M2_PR as default.
[INFO GRT-0224] Chose via M2M3_PR as default.
[INFO GRT-0224] Chose via M3M4_PR as default.
[INFO GRT-0224] Chose via M4M5_PR as default.
[INFO GRT-0088] Layer li1 Track-Pitch = 0.4600 line-2-Via Pitch: 0.3400
[INFO GRT-0088] Layer met1 Track-Pitch = 0.3400 line-2-Via Pitch: 0.3400
[INFO GRT-0088] Layer met2 Track-Pitch = 0.4600 line-2-Via Pitch: 0.3500
[INFO GRT-0088] Layer met3 Track-Pitch = 0.6800 line-2-Via Pitch: 0.6150
[INFO GRT-0088] Layer met4 Track-Pitch = 0.9200 line-2-Via Pitch: 1.0400
[INFO GRT-0088] Layer met5 Track-Pitch = 3.4000 line-2-Via Pitch: 3.1100
[INFO GRT-0003] Macros: 0
[INFO GRT-0004] Blockages: 1994530
[INFO GRT-0019] Found 18045 clock nets.
[INFO GRT-0001] Minimum degree: 2
[INFO GRT-0002] Maximum degree: 69209
[INFO GRT-0017] Processing 3442454 blockages on layer met1.
[INFO GRT-0017] Processing 352 blockages on layer met4.
[INFO GRT-0017] Processing 306 blockages on layer met5.

[INFO GRT-0053] Routing resources analysis:
Routing Original Derated Resource
Layer Direction Resources Resources Reduction (%)
---------------------------------------------------------------
li1 Vertical 0 0 0.00%
met1 Horizontal 10045020 4929884 50.92%
met2 Vertical 7533765 4522140 39.98%
met3 Horizontal 5022510 3018528 39.90%
met4 Vertical 3013506 1510488 49.88%
met5 Horizontal 1004502 502336 49.99%
---------------------------------------------------------------

[INFO GRT-0104] Minimal overflow 2084 occurring at round 0.
[INFO GRT-0111] Final number of vias: 1938024
[INFO GRT-0112] Final usage 3D: 9057211
[WARNING GRT-0115] Global routing finished with overflow.

[INFO GRT-0096] Final congestion report:
Layer Resource Demand Usage (%) Max H / Max V / Total Overflow
---------------------------------------------------------------------------------------
li1 0 111 0.00% 0 / 3 / 111
met1 4929884 1372433 27.84% 4 / 0 / 86
met2 4522140 1384695 30.62% 0 / 7 / 1487
met3 3018528 314384 10.42% 5 / 0 / 30
met4 1510488 170311 11.28% 0 / 4 / 370
met5 502336 1205 0.24% 0 / 0 / 0
---------------------------------------------------------------------------------------
Total 14483376 3243139 22.39% 9 / 14 / 2084

[INFO GRT-0018] Total wirelength: 30627071 um
[INFO GPL-0036] TileLxLy: 0 0
[INFO GPL-0037] TileSize: 6900 6900
[INFO GPL-0038] TileCnt: 753 668
[INFO GPL-0039] numRoutingLayers: 6
[INFO GPL-0040] NumTiles: 503004
[INFO GPL-0063] TotalRouteOverflowH2: 3.450000047683716
[INFO GPL-0064] TotalRouteOverflowV2: 160.80002772808075
[INFO GPL-0065] OverflowTileCnt2: 1351
[INFO GPL-0066] 0.5%RC: 1.0321022215468318
[INFO GPL-0067] 1.0%RC: 1.0160527131604353
[INFO GPL-0068] 2.0%RC: 1.0080263565802177
[INFO GPL-0069] 5.0%RC: 0.9787463747722426
[INFO GPL-0070] 0.5rcK: 1.0
[INFO GPL-0071] 1.0rcK: 1.0
[INFO GPL-0072] 2.0rcK: 0.0
[INFO GPL-0073] 5.0rcK: 0.0
[INFO GPL-0074] FinalRC: 1.0240774
[NesterovSolve] Iter: 590 overflow: 0.18288 HPWL: 9725943662
[NesterovSolve] Iter: 600 overflow: 0.156602 HPWL: 9639925667
[NesterovSolve] Iter: 610 overflow: 0.13545 HPWL: 9594026892
[NesterovSolve] Iter: 620 overflow: 0.117229 HPWL: 9574078357
[NesterovSolve] Iter: 630 overflow: 0.104412 HPWL: 9374117730
[NesterovSolve] Finished with Overflow: 0.099583

==========================================================================
global place report_checks -path_delay min
--------------------------------------------------------------------------
Startpoint: _444084_ (rising edge-triggered flip-flop clocked by clk)
Endpoint: _443963_ (removal check against rising-edge clock clk)
Path Group: **async_default**
Path Type: min

Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 0.00 ^ _444084_/CLK (sky130_fd_sc_hd__dfxtp_1)
0.05 0.30 0.30 v _444084_/Q (sky130_fd_sc_hd__dfxtp_1)
3 0.01 basesoc_basesoc_reset_storage[0] (net)
0.05 0.00 0.30 v _385035_/A1 (sky130_fd_sc_hd__a211oi_1)
2.90 40.97 41.27 ^ _385035_/Y (sky130_fd_sc_hd__a211oi_1)
285 2.04 _000415_ (net)
2.90 0.90 42.17 ^ _443963_/RESET_B (sky130_fd_sc_hd__dfrtp_1)
42.17 data arrival time

0.00 0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 clock reconvergence pessimism
0.00 ^ _443963_/CLK (sky130_fd_sc_hd__dfrtp_1)
1.08 1.08 library removal time
1.08 data required time
-----------------------------------------------------------------------------
1.08 data required time
-42.17 data arrival time
-----------------------------------------------------------------------------
41.10 slack (MET)


Startpoint: _387095_ (rising edge-triggered flip-flop clocked by clk)
Endpoint: _387096_ (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: min

Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 0.00 ^ _387095_/CLK (sky130_fd_sc_hd__dfxtp_1)
0.04 0.28 0.28 ^ _387095_/Q (sky130_fd_sc_hd__dfxtp_1)
1 0.00 multiregimpl1_regs0 (net)
0.04 0.00 0.28 ^ _387096_/D (sky130_fd_sc_hd__dfxtp_1)
0.28 data arrival time

0.00 0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 clock reconvergence pessimism
0.00 ^ _387096_/CLK (sky130_fd_sc_hd__dfxtp_1)
-0.04 -0.04 library hold time
-0.04 data required time
-----------------------------------------------------------------------------
-0.04 data required time
-0.28 data arrival time
-----------------------------------------------------------------------------
0.32 slack (MET)



==========================================================================
global place report_checks -path_delay max
--------------------------------------------------------------------------
Startpoint: _387097_ (rising edge-triggered flip-flop clocked by clk)
Endpoint: _443908_ (recovery check against rising-edge clock clk)
Path Group: **async_default**
Path Type: max

Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 0.00 ^ _387097_/CLK (sky130_fd_sc_hd__dfxtp_1)
7.51 5.60 5.60 v _387097_/Q (sky130_fd_sc_hd__dfxtp_1)
379 1.65 int_rst (net)
7.53 0.31 5.91 v _385035_/C1 (sky130_fd_sc_hd__a211oi_1)
59.02 42.20 48.11 ^ _385035_/Y (sky130_fd_sc_hd__a211oi_1)
285 2.04 _000415_ (net)
59.07 1.51 49.62 ^ _443908_/RESET_B (sky130_fd_sc_hd__dfrtp_1)
49.62 data arrival time

0.00 40.00 40.00 clock clk (rise edge)
0.00 40.00 clock network delay (ideal)
0.00 40.00 clock reconvergence pessimism
40.00 ^ _443908_/CLK (sky130_fd_sc_hd__dfrtp_1)
-15.77 24.23 library recovery time
24.23 data required time
-----------------------------------------------------------------------------
24.23 data required time
-49.62 data arrival time
-----------------------------------------------------------------------------
-25.39 slack (VIOLATED)


Startpoint: _392218_ (rising edge-triggered flip-flop clocked by clk)
Endpoint: _394579_ (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max

Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 0.00 ^ _392218_/CLK (sky130_fd_sc_hd__dfxtp_1)
50.94 31.24 31.24 ^ _392218_/Q (sky130_fd_sc_hd__dfxtp_1)
1027 5.48 A2P_WB.BranchPlugin_branchExceptionPort_payload_badAddr[2] (net)
50.95 0.78 32.03 ^ _196666_/A1 (sky130_fd_sc_hd__mux2i_1)
5.20 1.11 33.14 v _196666_/Y (sky130_fd_sc_hd__mux2i_1)
1 0.00 _058612_ (net)
5.20 0.00 33.14 v _196667_/B (sky130_fd_sc_hd__nand2_1)
0.61 0.91 34.04 ^ _196667_/Y (sky130_fd_sc_hd__nand2_1)
1 0.00 _058613_ (net)
0.61 0.00 34.04 ^ _196668_/C (sky130_fd_sc_hd__nand3_1)
0.26 0.17 34.21 v _196668_/Y (sky130_fd_sc_hd__nand3_1)
2 0.00 _058614_ (net)
0.26 0.00 34.21 v _220800_/A2 (sky130_fd_sc_hd__a21oi_1)
969.85 690.25 724.46 ^ _220800_/Y (sky130_fd_sc_hd__a21oi_1)
8341 50.26 _073313_ (net)
970.06 12.04 736.50 ^ _221580_/A (sky130_fd_sc_hd__nor2_1)
4897.51 13556.93 14293.43 v _221580_/Y (sky130_fd_sc_hd__nor2_1)
420 5.55 _074093_ (net)
4897.51 2.18 14295.60 v _303251_/B2 (sky130_fd_sc_hd__a32oi_1)
761.67 1325.10 15620.71 ^ _303251_/Y (sky130_fd_sc_hd__a32oi_1)
1 0.01 _155718_ (net)
761.67 0.00 15620.71 ^ _303267_/A2 (sky130_fd_sc_hd__a31oi_1)
115.75 112.23 15732.94 v _303267_/Y (sky130_fd_sc_hd__a31oi_1)
1 0.02 _155734_ (net)
115.75 0.00 15732.94 v _303268_/B1 (sky130_fd_sc_hd__o311ai_0)
9.09 74.29 15807.23 ^ _303268_/Y (sky130_fd_sc_hd__o311ai_0)
1 0.06 _155735_ (net)
9.09 0.01 15807.24 ^ _303269_/C (sky130_fd_sc_hd__nand3_1)
10.25 1.68 15808.92 v _303269_/Y (sky130_fd_sc_hd__nand3_1)
1 0.03 _155736_ (net)
10.25 0.00 15808.93 v _303270_/C (sky130_fd_sc_hd__nand3_1)
2.43 4.74 15813.67 ^ _303270_/Y (sky130_fd_sc_hd__nand3_1)
1 0.05 _155737_ (net)
2.43 0.01 15813.67 ^ _303271_/A2 (sky130_fd_sc_hd__o21ai_1)
1.49 0.82 15814.49 v _303271_/Y (sky130_fd_sc_hd__o21ai_1)
1 0.05 _155738_ (net)
1.49 0.01 15814.50 v _304097_/B (sky130_fd_sc_hd__nand4_1)
0.25 0.43 15814.93 ^ _304097_/Y (sky130_fd_sc_hd__nand4_1)
1 0.00 _007891_ (net)
0.25 0.00 15814.93 ^ _394579_/D (sky130_fd_sc_hd__dfxtp_1)
15814.93 data arrival time

0.00 40.00 40.00 clock clk (rise edge)
0.00 40.00 clock network delay (ideal)
0.00 40.00 clock reconvergence pessimism
40.00 ^ _394579_/CLK (sky130_fd_sc_hd__dfxtp_1)
-0.11 39.89 library setup time
39.89 data required time
-----------------------------------------------------------------------------
39.89 data required time
-15814.93 data arrival time
-----------------------------------------------------------------------------
-15775.04 slack (VIOLATED)



==========================================================================
global place report_checks -unconstrained
--------------------------------------------------------------------------
Startpoint: _387097_ (rising edge-triggered flip-flop clocked by clk)
Endpoint: _443908_ (recovery check against rising-edge clock clk)
Path Group: **async_default**
Path Type: max

Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 0.00 ^ _387097_/CLK (sky130_fd_sc_hd__dfxtp_1)
7.51 5.60 5.60 v _387097_/Q (sky130_fd_sc_hd__dfxtp_1)
379 1.65 int_rst (net)
7.53 0.31 5.91 v _385035_/C1 (sky130_fd_sc_hd__a211oi_1)
59.02 42.20 48.11 ^ _385035_/Y (sky130_fd_sc_hd__a211oi_1)
285 2.04 _000415_ (net)
59.07 1.51 49.62 ^ _443908_/RESET_B (sky130_fd_sc_hd__dfrtp_1)
49.62 data arrival time

0.00 40.00 40.00 clock clk (rise edge)
0.00 40.00 clock network delay (ideal)
0.00 40.00 clock reconvergence pessimism
40.00 ^ _443908_/CLK (sky130_fd_sc_hd__dfrtp_1)
-15.77 24.23 library recovery time
24.23 data required time
-----------------------------------------------------------------------------
24.23 data required time
-49.62 data arrival time
-----------------------------------------------------------------------------
-25.39 slack (VIOLATED)


Startpoint: _392218_ (rising edge-triggered flip-flop clocked by clk)
Endpoint: _394579_ (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max

Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 0.00 clock clk (rise edge)
0.00 0.00 clock network delay (ideal)
0.00 0.00 0.00 ^ _392218_/CLK (sky130_fd_sc_hd__dfxtp_1)
50.94 31.24 31.24 ^ _392218_/Q (sky130_fd_sc_hd__dfxtp_1)
1027 5.48 A2P_WB.BranchPlugin_branchExceptionPort_payload_badAddr[2] (net)
50.95 0.78 32.03 ^ _196666_/A1 (sky130_fd_sc_hd__mux2i_1)
5.20 1.11 33.14 v _196666_/Y (sky130_fd_sc_hd__mux2i_1)
1 0.00 _058612_ (net)
5.20 0.00 33.14 v _196667_/B (sky130_fd_sc_hd__nand2_1)
0.61 0.91 34.04 ^ _196667_/Y (sky130_fd_sc_hd__nand2_1)
1 0.00 _058613_ (net)
0.61 0.00 34.04 ^ _196668_/C (sky130_fd_sc_hd__nand3_1)
0.26 0.17 34.21 v _196668_/Y (sky130_fd_sc_hd__nand3_1)
2 0.00 _058614_ (net)
0.26 0.00 34.21 v _220800_/A2 (sky130_fd_sc_hd__a21oi_1)
969.85 690.25 724.46 ^ _220800_/Y (sky130_fd_sc_hd__a21oi_1)
8341 50.26 _073313_ (net)
970.06 12.04 736.50 ^ _221580_/A (sky130_fd_sc_hd__nor2_1)
4897.51 13556.93 14293.43 v _221580_/Y (sky130_fd_sc_hd__nor2_1)
420 5.55 _074093_ (net)
4897.51 2.18 14295.60 v _303251_/B2 (sky130_fd_sc_hd__a32oi_1)
761.67 1325.10 15620.71 ^ _303251_/Y (sky130_fd_sc_hd__a32oi_1)
1 0.01 _155718_ (net)
761.67 0.00 15620.71 ^ _303267_/A2 (sky130_fd_sc_hd__a31oi_1)
115.75 112.23 15732.94 v _303267_/Y (sky130_fd_sc_hd__a31oi_1)
1 0.02 _155734_ (net)
115.75 0.00 15732.94 v _303268_/B1 (sky130_fd_sc_hd__o311ai_0)
9.09 74.29 15807.23 ^ _303268_/Y (sky130_fd_sc_hd__o311ai_0)
1 0.06 _155735_ (net)
9.09 0.01 15807.24 ^ _303269_/C (sky130_fd_sc_hd__nand3_1)
10.25 1.68 15808.92 v _303269_/Y (sky130_fd_sc_hd__nand3_1)
1 0.03 _155736_ (net)
10.25 0.00 15808.93 v _303270_/C (sky130_fd_sc_hd__nand3_1)
2.43 4.74 15813.67 ^ _303270_/Y (sky130_fd_sc_hd__nand3_1)
1 0.05 _155737_ (net)
2.43 0.01 15813.67 ^ _303271_/A2 (sky130_fd_sc_hd__o21ai_1)
1.49 0.82 15814.49 v _303271_/Y (sky130_fd_sc_hd__o21ai_1)
1 0.05 _155738_ (net)
1.49 0.01 15814.50 v _304097_/B (sky130_fd_sc_hd__nand4_1)
0.25 0.43 15814.93 ^ _304097_/Y (sky130_fd_sc_hd__nand4_1)
1 0.00 _007891_ (net)
0.25 0.00 15814.93 ^ _394579_/D (sky130_fd_sc_hd__dfxtp_1)
15814.93 data arrival time

0.00 40.00 40.00 clock clk (rise edge)
0.00 40.00 clock network delay (ideal)
0.00 40.00 clock reconvergence pessimism
40.00 ^ _394579_/CLK (sky130_fd_sc_hd__dfxtp_1)
-0.11 39.89 library setup time
39.89 data required time
-----------------------------------------------------------------------------
39.89 data required time
-15814.93 data arrival time
-----------------------------------------------------------------------------
-15775.04 slack (VIOLATED)



==========================================================================
global place report_tns
--------------------------------------------------------------------------
tns -37411468.00

==========================================================================
global place report_wns
--------------------------------------------------------------------------
wns -15775.04

==========================================================================
global place report_worst_slack
--------------------------------------------------------------------------
worst slack -15775.04

==========================================================================
global place report_clock_skew
--------------------------------------------------------------------------
Clock clk
Latency CRPR Skew
A2P_WB.IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[2].RAM128.BLOCK[3].RAM32.SLICE[1].RAM8.WORD[6].W.BYTE[0].B.BIT[6].genblk1.STORAGE/GATE ^
0.26
A2P_WB.IBusCachedPlugin_cache.ways_0_datas.dir.BANK512[0].RAM512.BANK128[2].RAM128.BLOCK[3].RAM32.Do0_FF[6]/CLK ^
0.00 0.00 0.26


==========================================================================
global place report_power
--------------------------------------------------------------------------
Group Internal Switching Leakage Total
Power Power Power Power
----------------------------------------------------------------
Sequential 1.10e-01 4.33e-03 9.37e-07 1.15e-01 30.1%
Combinational 1.60e-01 1.06e-01 9.13e-07 2.66e-01 69.9%
Macro 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
Pad 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
----------------------------------------------------------------
Total 2.70e-01 1.11e-01 1.85e-06 3.81e-01 100.0%
70.9% 29.1% 0.0%

==========================================================================
global place report_design_area
--------------------------------------------------------------------------
Design area 5013592 u^2 25% utilization.

Elapsed time: 15:55.51[h:]min:sec. CPU time: user 941.48 sys 13.84 (99%). Peak memory: 15866240KB.

@ -0,0 +1,39 @@
OpenROAD v2.0-1901-g6157d4945
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
[INFO ODB-0222] Reading LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd.tlef
[INFO ODB-0223] Created 11 technology layers
[INFO ODB-0224] Created 25 technology vias
[INFO ODB-0226] Finished LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd.tlef
[INFO ODB-0222] Reading LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd_merged.lef
[INFO ODB-0225] Created 437 library cells
[INFO ODB-0226] Finished LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd_merged.lef
[INFO ODB-0127] Reading DEF file: ./results/sky130hd/a2p_litex/output/20211125124450/base/3_1_place_gp.def
[INFO ODB-0128] Design: top
[INFO ODB-0094] Created 100000 Insts
[INFO ODB-0094] Created 200000 Insts
[INFO ODB-0094] Created 300000 Insts
[INFO ODB-0094] Created 400000 Insts
[INFO ODB-0094] Created 500000 Insts
[INFO ODB-0094] Created 600000 Insts
[INFO ODB-0097] Created 100000 Nets
[INFO ODB-0097] Created 200000 Nets
[INFO ODB-0097] Created 300000 Nets
[INFO ODB-0130] Created 533 pins.
[INFO ODB-0131] Created 683441 components and 2738136 component-terminals.
[INFO ODB-0132] Created 2 special nets and 1366882 connections.
[INFO ODB-0133] Created 347346 nets and 1370964 connections.
[INFO ODB-0134] Finished DEF file: ./results/sky130hd/a2p_litex/output/20211125124450/base/3_1_place_gp.def
Found 0 macro blocks.
Using 1u default distance from corners.
Using 2 tracks default min distance between IO pins.
[INFO PPL-0010] Tentative 0 to set up sections.
[INFO PPL-0001] Number of slots 18082
[INFO PPL-0002] Number of I/O 533
[INFO PPL-0003] Number of I/O w/sink 533
[INFO PPL-0004] Number of I/O w/o sink 513
[INFO PPL-0005] Slots per section 200
[INFO PPL-0006] Slots increase factor 0.01
[INFO PPL-0008] Successfully assigned pins to sections.
[INFO PPL-0012] I/O nets HPWL: 24572.07 um.
Elapsed time: 0:12.84[h:]min:sec. CPU time: user 12.28 sys 0.53 (99%). Peak memory: 1567496KB.

File diff suppressed because it is too large Load Diff

File diff suppressed because it is too large Load Diff

File diff suppressed because it is too large Load Diff

@ -0,0 +1,29 @@
OpenROAD v2.0-1901-g6157d4945
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
[INFO ODB-0222] Reading LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd.tlef
[INFO ODB-0223] Created 11 technology layers
[INFO ODB-0224] Created 25 technology vias
[INFO ODB-0226] Finished LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd.tlef
[INFO ODB-0222] Reading LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd_merged.lef
[INFO ODB-0225] Created 437 library cells
[INFO ODB-0226] Finished LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd_merged.lef
[INFO ODB-0127] Reading DEF file: ./results/sky130hd/a2p_litex/output/20211125124450/base/4_1_cts.def
[INFO ODB-0128] Design: top
[INFO ODB-0094] Created 100000 Insts
[INFO ODB-0094] Created 200000 Insts
[INFO ODB-0094] Created 300000 Insts
[INFO ODB-0094] Created 400000 Insts
[INFO ODB-0094] Created 500000 Insts
[INFO ODB-0094] Created 600000 Insts
[INFO ODB-0094] Created 700000 Insts
[INFO ODB-0097] Created 100000 Nets
[INFO ODB-0097] Created 200000 Nets
[INFO ODB-0097] Created 300000 Nets
[INFO ODB-0130] Created 533 pins.
[INFO ODB-0131] Created 731508 components and 2930404 component-terminals.
[INFO ODB-0132] Created 2 special nets and 1463016 connections.
[INFO ODB-0133] Created 395413 nets and 1465023 connections.
[INFO ODB-0134] Finished DEF file: ./results/sky130hd/a2p_litex/output/20211125124450/base/4_1_cts.def
[INFO DPL-0001] Placed 1985347 filler instances.
Elapsed time: 0:23.33[h:]min:sec. CPU time: user 22.44 sys 0.86 (99%). Peak memory: 2452676KB.

File diff suppressed because it is too large Load Diff

@ -0,0 +1,4 @@
{
"drt::wire length::total" : 24581941
, "drt::vias::total" : 3382120
}

File diff suppressed because it is too large Load Diff

@ -0,0 +1,42 @@
[INFO] Reporting cells prior to loading DEF ...
[INFO] Reading DEF ...
[INFO] Clearing cells...
[INFO] ... preserving 'VIA_L1M1_PR'
[INFO] ... preserving 'VIA_L1M1_PR_R'
[INFO] ... preserving 'VIA_L1M1_PR_M'
[INFO] ... preserving 'VIA_L1M1_PR_MR'
[INFO] ... preserving 'VIA_L1M1_PR_C'
[INFO] ... preserving 'VIA_M1M2_PR'
[INFO] ... preserving 'VIA_M1M2_PR_R'
[INFO] ... preserving 'VIA_M1M2_PR_M'
[INFO] ... preserving 'VIA_M1M2_PR_MR'
[INFO] ... preserving 'VIA_M1M2_PR_C'
[INFO] ... preserving 'VIA_M2M3_PR'
[INFO] ... preserving 'VIA_M2M3_PR_R'
[INFO] ... preserving 'VIA_M2M3_PR_M'
[INFO] ... preserving 'VIA_M2M3_PR_MR'
[INFO] ... preserving 'VIA_M2M3_PR_C'
[INFO] ... preserving 'VIA_M3M4_PR'
[INFO] ... preserving 'VIA_M3M4_PR_R'
[INFO] ... preserving 'VIA_M3M4_PR_M'
[INFO] ... preserving 'VIA_M3M4_PR_MR'
[INFO] ... preserving 'VIA_M3M4_PR_C'
[INFO] ... preserving 'VIA_M4M5_PR'
[INFO] ... preserving 'VIA_M4M5_PR_R'
[INFO] ... preserving 'VIA_M4M5_PR_M'
[INFO] ... preserving 'VIA_M4M5_PR_MR'
[INFO] ... preserving 'VIA_M4M5_PR_C'
[INFO] ... preserving 'VIA_via_1600x480'
[INFO] ... preserving 'VIA_via2_1600x480'
[INFO] ... preserving 'VIA_via3_1600x480'
[INFO] ... preserving 'VIA_via4_1600x1600'
[INFO] Merging GDS/OAS files...
./platforms/sky130hd/gds/sky130_fd_sc_hd.gds
[INFO] Copying toplevel cell 'top'
INFO: Reading config file: ./platforms/sky130hd/fill.json
[INFO] Checking for missing cell from GDS/OAS...
[INFO] All LEF cells have matching GDS/OAS cells
[INFO] Checking for orphan cell in the final layout...
[INFO] No orphan cells
[INFO] Writing out GDS/OAS 'results/sky130hd/a2p_litex/output/20211125124450/base/6_1_merged.gds'
Elapsed time: 0:55.35[h:]min:sec. CPU time: user 52.34 sys 2.42 (98%). Peak memory: 6709152KB.

File diff suppressed because it is too large Load Diff

@ -0,0 +1,4 @@
Warning - class CORE ANTENNACELL is not found. This message can be ignored if not in the antenna-avoid flow
Number of pins violated: 0
Number of nets violated: 0
Total number of unspecial nets: 395413

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After

Width:  |  Height:  |  Size: 2.4 MiB

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After

Width:  |  Height:  |  Size: 2.1 MiB

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After

Width:  |  Height:  |  Size: 1.8 MiB

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After

Width:  |  Height:  |  Size: 1.9 MiB

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@ -0,0 +1,154 @@

33. Printing statistics.

=== top ===

Number of wires: 382174
Number of wire bits: 382689
Number of public wires: 186548
Number of public wire bits: 187063
Number of memories: 0
Number of memory bits: 0
Number of processes: 0
Number of cells: 452883
sky130_fd_sc_hd__a2111o_1 10
sky130_fd_sc_hd__a2111oi_0 845
sky130_fd_sc_hd__a2111oi_2 1
sky130_fd_sc_hd__a211o_1 100
sky130_fd_sc_hd__a211oi_1 303
sky130_fd_sc_hd__a21boi_0 32
sky130_fd_sc_hd__a21o_1 177
sky130_fd_sc_hd__a21oi_1 6816
sky130_fd_sc_hd__a21oi_2 2
sky130_fd_sc_hd__a221o_1 56
sky130_fd_sc_hd__a221o_2 2
sky130_fd_sc_hd__a221oi_1 350
sky130_fd_sc_hd__a221oi_2 1
sky130_fd_sc_hd__a222oi_1 40
sky130_fd_sc_hd__a22o_1 102
sky130_fd_sc_hd__a22oi_1 563
sky130_fd_sc_hd__a2bb2oi_1 2
sky130_fd_sc_hd__a311o_1 55
sky130_fd_sc_hd__a311oi_1 3602
sky130_fd_sc_hd__a311oi_2 1
sky130_fd_sc_hd__a31o_1 1
sky130_fd_sc_hd__a31o_2 21
sky130_fd_sc_hd__a31oi_1 2962
sky130_fd_sc_hd__a31oi_2 1
sky130_fd_sc_hd__a32o_1 77
sky130_fd_sc_hd__a32oi_1 421
sky130_fd_sc_hd__a41o_1 17
sky130_fd_sc_hd__a41oi_1 35
sky130_fd_sc_hd__and2_0 3
sky130_fd_sc_hd__and2_1 9253
sky130_fd_sc_hd__and2_2 2
sky130_fd_sc_hd__and2b_2 2
sky130_fd_sc_hd__and3_1 2419
sky130_fd_sc_hd__and3_2 94
sky130_fd_sc_hd__and3_4 3
sky130_fd_sc_hd__and3b_1 5
sky130_fd_sc_hd__and3b_2 188
sky130_fd_sc_hd__and3b_4 6
sky130_fd_sc_hd__and4_1 12
sky130_fd_sc_hd__and4_2 300
sky130_fd_sc_hd__and4b_1 1
sky130_fd_sc_hd__and4b_2 900
sky130_fd_sc_hd__and4bb_2 900
sky130_fd_sc_hd__buf_1 2626
sky130_fd_sc_hd__buf_2 5445
sky130_fd_sc_hd__buf_4 314
sky130_fd_sc_hd__buf_6 46
sky130_fd_sc_hd__clkbuf_1 17663
sky130_fd_sc_hd__clkbuf_16 2844
sky130_fd_sc_hd__clkbuf_2 6401
sky130_fd_sc_hd__clkbuf_4 20
sky130_fd_sc_hd__clkinv_1 19
sky130_fd_sc_hd__conb_1 290
sky130_fd_sc_hd__dfrtp_1 282
sky130_fd_sc_hd__dfstp_2 3
sky130_fd_sc_hd__dfxtp_1 60831
sky130_fd_sc_hd__dlclkp_1 9084
sky130_fd_sc_hd__dlxtp_1 71168
sky130_fd_sc_hd__ebufn_2 75440
sky130_fd_sc_hd__fa_1 1187
sky130_fd_sc_hd__ha_1 1256
sky130_fd_sc_hd__inv_1 19614
sky130_fd_sc_hd__inv_2 11
sky130_fd_sc_hd__inv_4 256
sky130_fd_sc_hd__maj3_1 16
sky130_fd_sc_hd__mux2_1 71
sky130_fd_sc_hd__mux2_2 48969
sky130_fd_sc_hd__mux2_4 4
sky130_fd_sc_hd__mux2i_1 3820
sky130_fd_sc_hd__mux2i_2 1
sky130_fd_sc_hd__mux2i_4 1
sky130_fd_sc_hd__mux4_1 684
sky130_fd_sc_hd__mux4_2 1911
sky130_fd_sc_hd__nand2_1 58581
sky130_fd_sc_hd__nand2_2 4
sky130_fd_sc_hd__nand2_4 1
sky130_fd_sc_hd__nand2b_1 92
sky130_fd_sc_hd__nand3_1 16776
sky130_fd_sc_hd__nand3b_1 50
sky130_fd_sc_hd__nand4_1 427
sky130_fd_sc_hd__nand4b_1 9
sky130_fd_sc_hd__nor2_1 5655
sky130_fd_sc_hd__nor2_2 1
sky130_fd_sc_hd__nor2b_1 103
sky130_fd_sc_hd__nor3_1 1587
sky130_fd_sc_hd__nor3_2 1
sky130_fd_sc_hd__nor3_4 2
sky130_fd_sc_hd__nor3b_1 50
sky130_fd_sc_hd__nor3b_2 97
sky130_fd_sc_hd__nor3b_4 3
sky130_fd_sc_hd__nor4_1 719
sky130_fd_sc_hd__nor4b_1 25
sky130_fd_sc_hd__nor4b_2 303
sky130_fd_sc_hd__nor4bb_1 7
sky130_fd_sc_hd__o2111a_1 5
sky130_fd_sc_hd__o2111ai_1 172
sky130_fd_sc_hd__o211a_1 22
sky130_fd_sc_hd__o211ai_1 353
sky130_fd_sc_hd__o211ai_2 2
sky130_fd_sc_hd__o21a_1 73
sky130_fd_sc_hd__o21ai_0 2925
sky130_fd_sc_hd__o21ai_1 75
sky130_fd_sc_hd__o21ai_2 1
sky130_fd_sc_hd__o21ba_2 1
sky130_fd_sc_hd__o21bai_1 35
sky130_fd_sc_hd__o221a_1 1
sky130_fd_sc_hd__o221a_2 11
sky130_fd_sc_hd__o221ai_1 1054
sky130_fd_sc_hd__o22a_1 23
sky130_fd_sc_hd__o22ai_1 816
sky130_fd_sc_hd__o2bb2ai_1 5
sky130_fd_sc_hd__o311a_1 20
sky130_fd_sc_hd__o311ai_0 129
sky130_fd_sc_hd__o311ai_1 8
sky130_fd_sc_hd__o31a_1 24
sky130_fd_sc_hd__o31ai_1 205
sky130_fd_sc_hd__o31ai_4 1
sky130_fd_sc_hd__o32a_1 17
sky130_fd_sc_hd__o32ai_1 158
sky130_fd_sc_hd__o41a_1 4
sky130_fd_sc_hd__o41ai_1 114
sky130_fd_sc_hd__o41ai_2 1
sky130_fd_sc_hd__or2_0 1
sky130_fd_sc_hd__or2_1 1
sky130_fd_sc_hd__or2_2 40
sky130_fd_sc_hd__or3_1 147
sky130_fd_sc_hd__or3b_2 7
sky130_fd_sc_hd__or4_1 90
sky130_fd_sc_hd__or4b_1 3
sky130_fd_sc_hd__or4b_2 5
sky130_fd_sc_hd__xnor2_1 587
sky130_fd_sc_hd__xnor2_2 10
sky130_fd_sc_hd__xnor2_4 4
sky130_fd_sc_hd__xnor3_1 8
sky130_fd_sc_hd__xnor3_2 6
sky130_fd_sc_hd__xor2_1 262
sky130_fd_sc_hd__xor2_2 2
sky130_fd_sc_hd__xor3_1 2

Chip area for module '\top': 4890414.044807

@ -0,0 +1,124 @@

# virtual platform for efabless caravel user area
# tots general-purpose (no defined i/o for specific site being built)


from litex.build.generic_platform import *

'''
defines.v:`define MPRJ_IO_PADS_1 19 /* number of user GPIO pads on user1 side */
defines.v:`define MPRJ_IO_PADS_2 19 /* number of user GPIO pads on user2 side */

module user_project_wrapper #(
parameter BITS = 32
`ifdef USE_POWER_PINS
inout vdda1, // User area 1 3.3V supply
inout vdda2, // User area 2 3.3V supply
inout vssa1, // User area 1 analog ground
inout vssa2, // User area 2 analog ground
inout vccd1, // User area 1 1.8V supply
inout vccd2, // User area 2 1.8v supply
inout vssd1, // User area 1 digital ground
inout vssd2, // User area 2 digital ground
`endif

// Wishbone Slave ports (WB MI A)
input wb_clk_i,
input wb_rst_i,
input wbs_stb_i,
input wbs_cyc_i,
input wbs_we_i,
input [3:0] wbs_sel_i,
input [31:0] wbs_dat_i,
input [31:0] wbs_adr_i,
output wbs_ack_o,
output [31:0] wbs_dat_o,

// Logic Analyzer Signals
input [127:0] la_data_in,
output [127:0] la_data_out,
input [127:0] la_oenb,

// IOs
input [`MPRJ_IO_PADS-1:0] io_in,
output [`MPRJ_IO_PADS-1:0] io_out,
output [`MPRJ_IO_PADS-1:0] io_oeb,

// Analog (direct connection to GPIO pad---use with caution)
// Note that analog I/O is not available on the 7 lowest-numbered
// GPIO pads, and so the analog_io indexing is offset from the
// GPIO indexing by 7 (also upper 2 GPIOs do not have analog_io).
inout [`MPRJ_IO_PADS-10:0] analog_io,

// Independent clock (on independent integer divider)
input user_clock2,

// User maskable interrupt signals
output [2:0] user_irq
);
'''

# IOs ----------------------------------------------------------------------------------------------

_io = [
# Clk / Rst
('wb_clk_i', 0, Pins(1)),
('user_clock2', 0, Pins(1)),
("wb_rst_i", 0, Pins(1)),

# WB Slave
('wbs_stb_i', 0, Pins(1)),
('wbs_cyc_i', 0, Pins(1)),
('wbs_we_i', 0, Pins(1)),
('wbs_sel_i', 0, Pins(4)),
('wbs_adr_i', 0, Pins(32)),
('wbs_dat_i', 0, Pins(32)),
('wbs_ack_o', 0, Pins(1)),
('wbs_dat_o', 0, Pins(32)),

# GPIO
('in_in', 0, Pins(19)),
('in_out', 0, Pins(19)),
('in_oeb', 0, Pins(1)),
('analog_in', 0, Pins(1)),

# Misc
('user_irq', 0, Pins(3)),

# LA
('la_data_in', 0, Pins(128)),
('la_data_out', 0, Pins(128)),
('la_oenb', 0, Pins(128))
]

# Platform -----------------------------------------------------------------------------------------


# Platform -----------------------------------------------------------------------------------------

# this somehow appears to work
from platforms.virtual import VirtualPlatform

class Platform(VirtualPlatform):
default_clk_name = 'wb_clk_i'
default_clk_period = 1e9/50e6

def __init__(self):
VirtualPlatform.__init__(self, 'caravel_user', _io)

def do_finalize(self, fragment):
VirtualPlatform.do_finalize(self, fragment)

'''
from litex.build.xilinx import XilinxPlatform, VivadoProgrammer

class Platform(XilinxPlatform):
default_clk_name = 'wb_clk_i'
default_clk_period = 1e9/50e6

def __init__(self):
XilinxPlatform.__init__(self, "xc7a35t-CPG236-1", _io, toolchain="vivado")

def do_finalize(self, fragment):
XilinxPlatform.do_finalize(self, fragment)
'''

@ -0,0 +1,80 @@
import os

from litex.build.generic_platform import GenericPlatform
from litex.build.xilinx import common, vivado, ise, symbiflow

from migen.fhdl.structure import _Fragment

class VirtualPlatform(GenericPlatform):

def __init__(self, *args, toolchain='ise', **kwargs):
GenericPlatform.__init__(self, *args, **kwargs)
#self.edifs = set()
#self.ips = {}
#if toolchain == "ise":
# self.toolchain = ise.XilinxISEToolchain()
#elif toolchain == "vivado":
# self.toolchain = vivado.XilinxVivadoToolchain()
#elif toolchain == "symbiflow":
# self.toolchain = symbiflow.SymbiflowToolchain()
#else:
# raise ValueError("Unknown toolchain")

#def add_edif(self, filename):
# pass
#self.edifs.add((os.path.abspath(filename)))

#def add_ip(self, filename, disable_constraints=False):
# pass
#self.ips.update({os.path.abspath(filename): disable_constraints})

def get_verilog(self, *args, special_overrides=dict(), **kwargs):
return GenericPlatform.get_verilog(self, *args)

#def get_edif(self, fragment, **kwargs):
# pass
#return GenericPlatform.get_edif(self, fragment, "UNISIMS", "Xilinx", self.device, **kwargs)

def build(self, *args, **kwargs):
return self.toolchain_build(self, *args, **kwargs)

def add_period_constraint(self, clk, period):
pass
#if clk is None: return
#if hasattr(clk, "p"):
# clk = clk.p
#self.toolchain.add_period_constraint(self, clk, period)

#def add_false_path_constraint(self, from_, to):
# pass
#if hasattr(from_, "p"):
# from_ = from_.p
#if hasattr(to, "p"):
# to = to.p
#self.toolchain.add_false_path_constraint(self, from_, to)

def toolchain_build(self, platform, fragment,
build_dir = 'build',
build_name = 'virtual', #doesnt do anything!!!
**kwargs):

# Create build directory
os.makedirs(build_dir, exist_ok=True)
cwd = os.getcwd()
os.chdir(build_dir)

# Finalize design
if not isinstance(fragment, _Fragment):
fragment = fragment.get_fragment()
platform.finalize(fragment)

# Generate verilog
v_output = platform.get_verilog(fragment, name=build_name, **kwargs)
named_sc, named_pc = platform.resolve_signals(v_output.ns)
v_file = build_name + ".v"
v_output.write(v_file)
platform.add_source(v_file)

os.chdir(cwd)

return v_output.ns

@ -0,0 +1,33 @@
# Using Litex to build a Caravel User Project Area

Create a module usable for FPGA and tech mapping, containing various Litex structures like CSR, WB, UART, I2C, etc. and
custom verilog modules (core, async RAM, GPIO, etc.).

* create a virtual platform corresponding to the I/O on the Caravel User module

* create virtual 'soc' design using that platform

* module can be used for OL synthesis (expand_type set for tech)

* module can be included in FPGA SOC for testing and development (expand_type set for inferred)

* create real soc incorporating above, plus clocks, real GPIO connections, etc.


### Virtual Platform

* create user area

```
a2p_site.py
cp build/caravel_user/gateware/mem.init .
cp build/caravel_user/gateware/caravel_user.v .
```

* OL didn't die

```
make DESIGN_CONFIG=./designs/sky130hd/a2p_litex/config.mk
```


@ -0,0 +1,123 @@
// SPDX-FileCopyrightText: 2020 Efabless Corporation
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
// SPDX-License-Identifier: Apache-2.0

`default_nettype none
/*
*-------------------------------------------------------------
*
* user_project_wrapper
*
* This wrapper enumerates all of the pins available to the
* user for the user project.
*
* An example user project is provided in this wrapper. The
* example should be removed and replaced with the actual
* user project.
*
*-------------------------------------------------------------
*/

module user_project_wrapper #(
parameter BITS = 32
) (
`ifdef USE_POWER_PINS
inout vdda1, // User area 1 3.3V supply
inout vdda2, // User area 2 3.3V supply
inout vssa1, // User area 1 analog ground
inout vssa2, // User area 2 analog ground
inout vccd1, // User area 1 1.8V supply
inout vccd2, // User area 2 1.8v supply
inout vssd1, // User area 1 digital ground
inout vssd2, // User area 2 digital ground
`endif

// Wishbone Slave ports (WB MI A)
input wb_clk_i,
input wb_rst_i,
input wbs_stb_i,
input wbs_cyc_i,
input wbs_we_i,
input [3:0] wbs_sel_i,
input [31:0] wbs_dat_i,
input [31:0] wbs_adr_i,
output wbs_ack_o,
output [31:0] wbs_dat_o,

// Logic Analyzer Signals
input [127:0] la_data_in,
output [127:0] la_data_out,
input [127:0] la_oenb,

// IOs
input [`MPRJ_IO_PADS-1:0] io_in,
output [`MPRJ_IO_PADS-1:0] io_out,
output [`MPRJ_IO_PADS-1:0] io_oeb,

// Analog (direct connection to GPIO pad---use with caution)
// Note that analog I/O is not available on the 7 lowest-numbered
// GPIO pads, and so the analog_io indexing is offset from the
// GPIO indexing by 7 (also upper 2 GPIOs do not have analog_io).
inout [`MPRJ_IO_PADS-10:0] analog_io,

// Independent clock (on independent integer divider)
input user_clock2,

// User maskable interrupt signals
output [2:0] user_irq
);

/*--------------------------------------*/
/* User project is instantiated here */
/*--------------------------------------*/

user_proj_example mprj (
`ifdef USE_POWER_PINS
.vccd1(vccd1), // User area 1 1.8V power
.vssd1(vssd1), // User area 1 digital ground
`endif

.wb_clk_i(wb_clk_i),
.wb_rst_i(wb_rst_i),

// MGMT SoC Wishbone Slave

.wbs_cyc_i(wbs_cyc_i),
.wbs_stb_i(wbs_stb_i),
.wbs_we_i(wbs_we_i),
.wbs_sel_i(wbs_sel_i),
.wbs_adr_i(wbs_adr_i),
.wbs_dat_i(wbs_dat_i),
.wbs_ack_o(wbs_ack_o),
.wbs_dat_o(wbs_dat_o),

// Logic Analyzer

.la_data_in(la_data_in),
.la_data_out(la_data_out),
.la_oenb (la_oenb),

// IO Pads

.io_in (io_in),
.io_out(io_out),
.io_oeb(io_oeb),

// IRQ
.irq(user_irq)
);

endmodule // user_project_wrapper

`default_nettype wire

@ -2,6 +2,14 @@

* manually replace inferred mem with array macros; eventually make all arrays components (inferred for FPGA, phys for tech)

* how do you integrate with OpenLane?

1. use built .v from dffram.py? and run a fixup after to place?
2. reference dffram.py module but don't include .v?
3. totally place/route dffram and then include it?
4. include/copy stuff from build dir to openlane somewhere?


## Arrays to convert to DFFRAM

* IC (4K)
@ -51,8 +59,7 @@

```
# clone DFFRam
export PDK_ROOT=/home/wtf/projects2/OpenLane/pdks

```export PDK_ROOT``` if not set up already
# optionally set design name for any builds; **doesn't set the output name**
# export FORCE_DESIGN_NAME=ram_32_32
```

@ -11,6 +11,20 @@

* Misc: UARTs, I2C, toysram, ...

* To Do

* pre-place i/o's before synth

* synth experiments (LSOracle and/or opt refinement)

* get packed DFFRAMs incorporated

* modify code to do a 3R1W reg

* modify code to do non-power-of-2 words

* should 1Kx32 be built from smaller blocks?

<br clear="all" />

## OpenROAD-flow-scripts
@ -40,6 +54,8 @@ https://github.com/The-OpenROAD-Project/OpenSTA/blob/35a3f1e4e3f148b30678f9455e6

https://github.com/ayush-saran/Openlane_Workshop_VSD

https://docs.google.com/document/d/13J1AY1zhzxur8vaFs3rRW9ZWX113rSDs63LezOOoXZ8/edit#heading=h.9y68197ebff7


### steps


@ -0,0 +1,62 @@
// SPDX-FileCopyrightText: 2020 Efabless Corporation
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
// SPDX-License-Identifier: Apache-2.0

`default_nettype none

`ifndef __GLOBAL_DEFINE_H
// Global parameters
`define __GLOBAL_DEFINE_H

`define MPRJ_IO_PADS_1 19 /* number of user GPIO pads on user1 side */
`define MPRJ_IO_PADS_2 19 /* number of user GPIO pads on user2 side */
`define MPRJ_IO_PADS (`MPRJ_IO_PADS_1 + `MPRJ_IO_PADS_2)

`define MPRJ_PWR_PADS_1 2 /* vdda1, vccd1 enable/disable control */
`define MPRJ_PWR_PADS_2 2 /* vdda2, vccd2 enable/disable control */
`define MPRJ_PWR_PADS (`MPRJ_PWR_PADS_1 + `MPRJ_PWR_PADS_2)

// Analog pads are only used by the "caravan" module and associated
// modules such as user_analog_project_wrapper and chip_io_alt.

`define ANALOG_PADS_1 5
`define ANALOG_PADS_2 6

`define ANALOG_PADS (`ANALOG_PADS_1 + `ANALOG_PADS_2)

// Size of soc_mem_synth

// Type and size of soc_mem
// `define USE_OPENRAM
`define USE_CUSTOM_DFFRAM
// don't change the following without double checking addr widths
`define MEM_WORDS 256

// Number of columns in the custom memory; takes one of three values:
// 1 column : 1 KB, 2 column: 2 KB, 4 column: 4KB
`define DFFRAM_WSIZE 4
`define DFFRAM_USE_LATCH 0

// not really parameterized but just to easily keep track of the number
// of ram_block across different modules
`define RAM_BLOCKS 2

// Clock divisor default value
`define CLK_DIV 3'b010

// GPIO conrol default mode and enable
`define DM_INIT 3'b110
`define OENB_INIT 1'b1

`endif // __GLOBAL_DEFINE_H
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