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@ -12,7 +12,7 @@ A2P is a mashup of OpenPOWER architecture and VexRiscv, creating a new 32b Power
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<img align="right" width="50%" src="media/sim.png">
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* Ops (100+) not thoroughly tested, but running a minimal kernel and partial Litex BIOS in Verilator and on FPGAs. Likely still
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* Ops (100+) not thoroughly tested, but running a minimal kernel and Litex BIOS in Verilator and on FPGAs. Likely still
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some bugs in CR/XER handling for div/mul(?).
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* Need to define supported translation modes.
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@ -23,11 +23,15 @@ some bugs in CR/XER handling for div/mul(?).
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* Core and SOC run in Verilator/pyverilator. SOC uses emulated host UART.
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### OpenROAD Implementation
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* experimenting with DFFRAM for GPR, dirs, caches for efabless site
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### FPGA Implementation
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* Currently using Cmod A7-35T board.
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* Needs SOC code update to access external SRAM. I2C works.
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* ~~Needs SOC code update to access external SRAM.~~ I2C, async RAM, multiple UARTS, custom GPIO work.
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<img width="50%" src="media/fpga.png">
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