From 2ede551084b82b411ec4267476cc77801db9eb6c Mon Sep 17 00:00:00 2001
From: William Flynn <wtf@noreply.openpower.foundation>
Date: Mon, 29 Nov 2021 01:08:53 +0100
Subject: [PATCH] Update 'readme.md'

---
 readme.md | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/readme.md b/readme.md
index eef4240..f1bdf89 100644
--- a/readme.md
+++ b/readme.md
@@ -12,7 +12,7 @@ A2P is a mashup of OpenPOWER architecture and VexRiscv, creating a new 32b Power
 
 <img align="right" width="50%" src="media/sim.png">
 
-* Ops (100+) not thoroughly tested, but running a minimal kernel and partial Litex BIOS in Verilator and on FPGAs.  Likely still
+* Ops (100+) not thoroughly tested, but running a minimal kernel and Litex BIOS in Verilator and on FPGAs.  Likely still
 some bugs in CR/XER handling for div/mul(?).
 
 * Need to define supported translation modes.
@@ -23,11 +23,15 @@ some bugs in CR/XER handling for div/mul(?).
 
 * Core and SOC run in Verilator/pyverilator.  SOC uses emulated host UART.
 
+### OpenROAD Implementation
+
+* experimenting with DFFRAM for GPR, dirs, caches for efabless site
+
 ### FPGA Implementation
 
 * Currently using Cmod A7-35T board. 
 
-* Needs SOC code update to access external SRAM.  I2C works.
+* ~~Needs SOC code update to access external SRAM.~~  I2C, async RAM, multiple UARTS, custom GPIO work.
 
 <img width="50%" src="media/fpga.png">