openroad
wtf
3 years ago
parent
4948e96692
commit
2576396abb
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dffram/
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# A2P for OpenLane/Carousel
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* manually replace inferred mem with array macros; eventually make all arrays components (inferred for FPGA, phys for tech)
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## Arrays to convert to DFFRAM
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* IC (4K)
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```
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reg [21:0] ways_0_tags [0:127];
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reg [31:0] ways_0_datas [0:1023];
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```
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* tag: 128x22b
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* data: 1024x32b
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* DC (4K)
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```
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reg [21:0] DC_DIR_tags [0:127];
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reg [7:0] DC_DIR_data_symbol0 [0:1023];
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reg [7:0] DC_DIR_data_symbol1 [0:1023];
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reg [7:0] DC_DIR_data_symbol2 [0:1023];
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reg [7:0] DC_DIR_data_symbol3 [0:1023];
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```
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* tag: 128x22b
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* data(4): 1024x8b
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* GPR
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```
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reg [31:0] RegFilePlugin_regFile [0:31] /* verilator public */ ;
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```
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* 32x32b, 3 read, 1 write
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## Creating DFFRAM arrays
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* ***REQUIRES DOCKER***
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* github.com/efabless/openlane/blob/master/README.md
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```
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# clone OpenLane
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# make full-pdk
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```
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* github.com/Cloud-V/DFFRAM
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```
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# clone DFFRam
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export PDK_ROOT=/home/wtf/projects2/OpenLane/pdks
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# optionally set design name for any builds; **doesn't set the output name**
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# export FORCE_DESIGN_NAME=ram_32_32
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```
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### GPR
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* need 3r1w and DFFRam creates 2r1w reg; so need 2 regs, or 3 32x32 RAM, or custom 3r script
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* -v 1R1W not supported; is this basically the same as ram_32_32??
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* multiple arrays will be instantiated in single gpr module; use parameter to select gen style
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#### RAM
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```
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#export FORCE_DESIGN_NAME=ram_32x32
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dffram.py -s 32x32 -p $PDK_ROOT
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```
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#### REG
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* building block <pdk>:<scl>:<name> corresponds to platforms/<pdk>/<scl>/_building_blocks/<name>/model.v
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```
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#export FORCE_DESIGN_NAME=reg_32x32
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dffram.py -s 32x32 -v 2R1W -p $PDK_ROOT -b sky130A:sky130_fd_sc_hd:rf
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```
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#### Tag Arrays, 4K
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* need to make **decellerator** script to whack the extra 10 bits/word after place and then run rest of stuff
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```
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#export FORCE_DESIGN_NAME=ram_128x32
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dffram.py -s 128x32 -p $PDK_ROOT
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```
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* OR try...
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```
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export FORCE_ACCEPT_SIZE=wtf
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#export FORCE_DESIGN_NAME=ram_128x22
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dffram.py -s 128x22 -p $PDK_ROOT
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unset FORCE_ACCEPT_SIZE
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```
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#### Data Array, IC
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```
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#export FORCE_DESIGN_NAME=ram_1024x32
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dffram.py -s 1024x32 -p $PDK_ROOT
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```
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#### Data Array, DC (4)
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* DFFRam handles byte writes, so this is same as IC
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```
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#export FORCE_DESIGN_NAME=ram_1024x8
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#dffram.py -s 1024x8 -p $PDK_ROOT
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```
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IC/DC arrays could be built using different subunits if better for layout/timing; 4KB = 128 lines x 32B.
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## Updating core manually
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* this is compiling components on non-generated paths...
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```verilator --lint-only -Wno-fatal A2P_WB_RAM.v```
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* add gpr.v and module to top; can use this to test on FPGA with ```EXPAND_TYPE=`INFERRED```
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@ -1 +0,0 @@
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/home/wtf/projects/a2p/core/A2P_WB.v
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File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,54 @@
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`include "defs.v"
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module dcdata #(
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parameter EXPAND_TYPE=`INFERRED,
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parameter LINES=1024
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) (
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input clk,
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input [9:0] rd_adr,
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output [31:0] rd_dat,
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input [3:0] wr_en,
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input [9:0] wr_adr,
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input [31:0] wr_dat
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);
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generate case (EXPAND_TYPE)
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`INFERRED: begin
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reg [7:0] dir0 [0:LINES-1];
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reg [7:0] dir1 [0:LINES-1];
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reg [7:0] dir2 [0:LINES-1];
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reg [7:0] dir3 [0:LINES-1];
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assign rd_dat = {dir3[rd_adr],dir2[rd_adr],dir1[rd_adr],dir0[rd_adr]};
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always @ (posedge clk) begin
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if(wr_en[0]) begin
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dir0[wr_adr] <= wr_dat[7:0];
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end
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if(wr_en[1]) begin
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dir1[wr_adr] <= wr_dat[15:8];
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end
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if(wr_en[2]) begin
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dir2[wr_adr] <= wr_dat[23:16];
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end
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if(wr_en[3]) begin
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dir3[wr_adr] <= wr_dat[31:24];
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end
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end
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end
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`DIR_RAM: begin
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wire [9:0] adr;
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assign adr = |wr_en ? wr_adr : rd_adr;
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RAM1024 #() dir (
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.CLK(clk),
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.EN0('b1),
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.A0(adr),
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.Do0(rd_dat),
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.WE0(wr_en),
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.Di0(wr_dat)
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);
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end
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endcase
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endgenerate
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endmodule
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@ -0,0 +1,44 @@
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`include "defs.v"
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module dcdir #(
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parameter EXPAND_TYPE=`INFERRED,
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parameter LINES=128
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) (
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input clk,
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input [6:0] rd_adr,
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output [21:0] rd_dat,
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input [3:0] wr_en,
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input [6:0] wr_adr,
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input [21:0] wr_dat
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);
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generate case (EXPAND_TYPE)
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`INFERRED: begin
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reg [21:0] dir [0:LINES-1];
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assign rd_dat = dir[rd_adr];
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always @ (posedge clk) begin
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if(wr_en[0]) begin
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dir[wr_adr] <= wr_dat;
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end
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end
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end
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`DIR_RAM: begin
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wire [6:0] adr;
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wire [31:0] dat;
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assign adr = wr_en ? wr_adr : rd_adr;
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assign rd_dat = dat[21:0];
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RAM128 #() dir (
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.CLK(clk),
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.EN0('b1),
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.A0(adr),
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.Do0(dat),
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.WE0(wr_en),
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.Di0({'b0000000000, wr_dat})
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);
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end
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endcase
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endgenerate
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endmodule
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// A2P defines
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// Generation controls
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`define INFERRED 0
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`define GPR_2R1W 1
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`define GPR_RAM 2
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`define GPR_3R1W 3
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`define DIR_RAM 1
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@ -0,0 +1,75 @@
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`include "defs.v"
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module gpr #(
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parameter EXPAND_TYPE=`INFERRED
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) (
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input clk,
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input [4:0] rd_adr_0,
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output [31:0] rd_dat_0,
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input [4:0] rd_adr_1,
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output [31:0] rd_dat_1,
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input [4:0] rd_adr_2,
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output [31:0] rd_dat_2,
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input wr_en_0,
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input [4:0] wr_adr_0,
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input [31:0] wr_dat_0
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);
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generate case (EXPAND_TYPE)
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`INFERRED: begin
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reg [31:0] regFile [0:31] /* verilator public */ ;
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assign rd_dat_0 = regFile[rd_adr_0];
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assign rd_dat_1 = regFile[rd_adr_1];
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assign rd_dat_2 = regFile[rd_adr_2];
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always @ (posedge clk) begin
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if(wr_en_0) begin
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regFile[wr_adr_0] <= wr_dat_0;
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end
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end
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end
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`GPR_2R1W: begin
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/* veeerilator is parsing this when not gen'd */
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DFFRF_2R1W #() regFile01 (
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.CLK(clk),
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.RA(rd_adr_0),
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.DA(rd_dat_0),
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.RB(rd_adr_1),
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.DB(rd_dat_1),
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.RW(wr_adr_0),
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.WE(wr_en_0),
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.DW(wr_dat_0)
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);
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// should this be a ram_32x32? any other diffs between reg/ram besides multiple we vs extra port?
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DFFRF_2R1W #() regFile23 (
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.CLK(clk),
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.RA(rd_adr_2),
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.DA(rd_dat_2),
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.RB('h0),
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.DB(),
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.RW(wr_adr_0),
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.WE(wr_en_0),
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.DW(wr_dat_0)
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);
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end
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`GPR_3R1W: begin
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reg_3r1w #() regFile (
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);
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end
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`GPR_RAM: begin
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ram_32x32 #() regFile0 (
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);
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ram_32x32 #() regFile1 (
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);
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ram_32x32 #() regFile2 (
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);
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end
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endcase
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endgenerate
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endmodule
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@ -0,0 +1,54 @@
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`include "defs.v"
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module icdata #(
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parameter EXPAND_TYPE=`INFERRED,
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parameter LINES=1024
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) (
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input clk,
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input [9:0] rd_adr,
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output [31:0] rd_dat,
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input [3:0] wr_en,
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input [9:0] wr_adr,
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input [31:0] wr_dat
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);
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generate case (EXPAND_TYPE)
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`INFERRED: begin
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reg [7:0] dir0 [0:LINES-1];
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reg [7:0] dir1 [0:LINES-1];
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reg [7:0] dir2 [0:LINES-1];
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reg [7:0] dir3 [0:LINES-1];
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assign rd_dat = {dir3[rd_adr],dir2[rd_adr],dir1[rd_adr],dir0[rd_adr]};
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always @ (posedge clk) begin
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if(wr_en[0]) begin
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dir0[wr_adr] <= wr_dat[7:0];
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end
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if(wr_en[1]) begin
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dir1[wr_adr] <= wr_dat[15:8];
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end
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if(wr_en[2]) begin
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dir2[wr_adr] <= wr_dat[23:16];
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end
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if(wr_en[3]) begin
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dir3[wr_adr] <= wr_dat[31:24];
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end
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end
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end
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`DIR_RAM: begin
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wire [9:0] adr;
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assign adr = wr_en[0] ? wr_adr : rd_adr;
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RAM1024 #() dir (
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.CLK(clk),
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.EN0('b1),
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.A0(adr),
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.Do0(rd_dat),
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.WE0(wr_en),
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.Di0(wr_dat)
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);
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end
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endcase
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endgenerate
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endmodule
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@ -0,0 +1,44 @@
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`include "defs.v"
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module icdir #(
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parameter EXPAND_TYPE=`INFERRED,
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parameter LINES=128
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) (
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input clk,
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input [6:0] rd_adr,
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output [21:0] rd_dat,
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input [3:0] wr_en,
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input [6:0] wr_adr,
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input [21:0] wr_dat
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);
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generate case (EXPAND_TYPE)
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`INFERRED: begin
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reg [21:0] dir [0:LINES-1];
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assign rd_dat = dir[rd_adr];
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always @ (posedge clk) begin
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if(wr_en[0]) begin
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dir[wr_adr] <= wr_dat;
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end
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end
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end
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`DIR_RAM: begin
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wire [6:0] adr;
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wire [31:0] dat;
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assign adr = wr_en ? wr_adr : rd_adr;
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assign rd_dat = dat[21:0];
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RAM128 #() dir (
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.CLK(clk),
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.EN0('b1),
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.A0(adr),
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.Do0(dat),
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.WE0(wr_en),
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.Di0({'b0000000000, wr_dat})
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);
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end
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endcase
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endgenerate
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endmodule
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