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75 lines
1.5 KiB
Verilog
75 lines
1.5 KiB
Verilog
`include "defs.v"
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module gpr #(
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parameter EXPAND_TYPE=`INFERRED
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) (
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input clk,
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input [4:0] rd_adr_0,
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output [31:0] rd_dat_0,
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input [4:0] rd_adr_1,
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output [31:0] rd_dat_1,
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input [4:0] rd_adr_2,
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output [31:0] rd_dat_2,
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input wr_en_0,
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input [4:0] wr_adr_0,
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input [31:0] wr_dat_0
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);
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generate case (EXPAND_TYPE)
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`INFERRED: begin
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reg [31:0] regFile [0:31] /* verilator public */ ;
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assign rd_dat_0 = regFile[rd_adr_0];
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assign rd_dat_1 = regFile[rd_adr_1];
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assign rd_dat_2 = regFile[rd_adr_2];
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always @ (posedge clk) begin
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if(wr_en_0) begin
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regFile[wr_adr_0] <= wr_dat_0;
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end
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end
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end
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`GPR_2R1W: begin
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/* veeerilator is parsing this when not gen'd */
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DFFRF_2R1W #() regFile01 (
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.CLK(clk),
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.RA(rd_adr_0),
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.DA(rd_dat_0),
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.RB(rd_adr_1),
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.DB(rd_dat_1),
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.RW(wr_adr_0),
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.WE(wr_en_0),
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.DW(wr_dat_0)
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);
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// should this be a ram_32x32? any other diffs between reg/ram besides multiple we vs extra port?
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DFFRF_2R1W #() regFile23 (
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.CLK(clk),
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.RA(rd_adr_2),
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.DA(rd_dat_2),
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.RB('h0),
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.DB(),
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.RW(wr_adr_0),
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.WE(wr_en_0),
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.DW(wr_dat_0)
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);
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end
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`GPR_3R1W: begin
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reg_3r1w #() regFile (
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);
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end
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`GPR_RAM: begin
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ram_32x32 #() regFile0 (
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);
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ram_32x32 #() regFile1 (
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);
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ram_32x32 #() regFile2 (
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);
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end
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endcase
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endgenerate
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endmodule |