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54 lines
1.1 KiB
Coq
54 lines
1.1 KiB
Coq
3 years ago
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`include "defs.v"
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module icdata #(
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parameter EXPAND_TYPE=`INFERRED,
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parameter LINES=1024
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) (
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input clk,
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input [9:0] rd_adr,
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output [31:0] rd_dat,
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input [3:0] wr_en,
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input [9:0] wr_adr,
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input [31:0] wr_dat
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);
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generate case (EXPAND_TYPE)
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`INFERRED: begin
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reg [7:0] dir0 [0:LINES-1];
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reg [7:0] dir1 [0:LINES-1];
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reg [7:0] dir2 [0:LINES-1];
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reg [7:0] dir3 [0:LINES-1];
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assign rd_dat = {dir3[rd_adr],dir2[rd_adr],dir1[rd_adr],dir0[rd_adr]};
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always @ (posedge clk) begin
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if(wr_en[0]) begin
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dir0[wr_adr] <= wr_dat[7:0];
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end
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if(wr_en[1]) begin
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dir1[wr_adr] <= wr_dat[15:8];
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end
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if(wr_en[2]) begin
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dir2[wr_adr] <= wr_dat[23:16];
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end
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if(wr_en[3]) begin
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dir3[wr_adr] <= wr_dat[31:24];
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end
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end
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end
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`DIR_RAM: begin
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wire [9:0] adr;
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assign adr = wr_en[0] ? wr_adr : rd_adr;
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RAM1024 #() dir (
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.CLK(clk),
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.EN0('b1),
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.A0(adr),
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.Do0(rd_dat),
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.WE0(wr_en),
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.Di0(wr_dat)
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);
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end
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endcase
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endgenerate
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endmodule
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