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# Test Site
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* Litex platform for efabless caravel
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* Core, I2C, UARTs, SPI, GPIO
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#### https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts/tree/master/flow
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create dir and add sources
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```
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cd ../../..
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make DESIGN_CONFIG=./designs/sky130hd/a2p/config.mk
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```
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## docs
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https://openroad.readthedocs.io/en/latest/user/UserGuide.html#option-1-rtl-to-gds-flow
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http://www.clifford.at/yosys/files/yosys_manual.pdf
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https://people.eecs.berkeley.edu/~alanmi/abc/
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https://github.com/The-OpenROAD-Project/OpenSTA/blob/35a3f1e4e3f148b30678f9455e64d220c6758462/doc/OpenSTA.pdf
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## links
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https://github.com/ayush-saran/Openlane_Workshop_VSD
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### steps
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1. initial synth/timing
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* initialize floorplan (initialize_floorplan)
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* gate_resizer (multiple commands)
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* can set estimated wire rc per layer
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* can add buffers on I/O
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* repairs fanouts/caps/etc.
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* STA can run before and/or after this
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* OpenSTA (sta)
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2. full PD
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* macro place (macro_placement)
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* tapcell/endcap (tapcell)
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* global placement (global_placement)
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* detailed placement (legalize_placement)
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* CTS (clock_tree_synthesis)
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* global routing (fast_route)
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* detailed routing (detailed_route)
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### replace inferred mems with DFFRAM components
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(readme-dffram.md)
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1. test with gpr using DFFRAMs and ic/dc dir/dat using small inferred mems (1 location)
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* completed flow
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