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79 lines
1.5 KiB
Markdown
79 lines
1.5 KiB
Markdown
3 years ago
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# Litex SOC
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```a2p_cmod7.py``` is a sample SOC for Digilent Cmod A7: https://digilent.com/reference/programmable-logic/cmod-a7/start
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* 64K ROM (BRAM)
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* 512K RAM (Async SRAM on board)
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* UART for console
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```rom.init``` is an asm test nanokernel plus Litex BIOS.
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Generate SOC verilog and create bitstream...
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```
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make -c # copy rom.init, build, program
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make # build, program
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make -p # program
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```
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Start terminal...
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```
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lxterm /dev/ttyUSB1 # or whatever
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```
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```
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A2P POWAflight
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SRAM OK.
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Copying ROM to RAM...
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Jumping to main()...
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__ _ __ _ __
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/ / (_) /____ | |/_/
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/ /__/ / __/ -_)> <
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/____/_/\__/\__/_/|_|
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Build your hardware, easily!
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(c) Copyright 2012-2021 Enjoy-Digital
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(c) Copyright 2007-2015 M-Labs
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BIOS built on Oct 30 2021 08:02:58
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BIOS CRC failed (expected 00000000, got 3f6a3f1d)
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The system will continue, but expect problems.
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Migen git sha1: 27dbf03
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LiteX git sha1: 78c1751c
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--=============== SoC ==================--
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CPU: A2P_WB @ 100MHz
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BUS: WISHBONE 32-bit @ 4GiB
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CSR: 32-bit data
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ROM: 64KiB
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SRAM: 512KiB
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--============== Boot ==================--
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Booting from serial...
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Press Q or ESC to abort boot completely.
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sL5DdSMmkekro
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Timeout
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No boot medium found
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--============= Console ================--
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litex> mem_list
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Available memory regions:
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ROM 0x00000000 0x10000
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SRAM 0x00100000 0x80000
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CSR 0xfff00000 0x10000
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litex> mem_test 0x120000 0x50000
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Memtest at 0x120000 (320.0KiB)...
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Write: 0x120000-0x170000 320.0KiB
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Read: 0x120000-0x170000 320.0KiB
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Memtest OK
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litex>
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```
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