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a2p
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wtf 3 years ago
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11
.gitignore vendored
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__pycache__
*.pyc

vivado*jou
vivado*log

*.o
*.d

1
build/litex/a2p/__init__.py
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from .core import A2P

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build/litex/a2p/boot-helper.S
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.section .text, "ax", @progbits

.global boot_helper
boot_helper:
blr

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build/litex/a2p/core.py
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import os

from migen import *

from litex import get_data_mod
from litex.soc.interconnect import wishbone
from litex.soc.interconnect.csr import *
from litex.soc.cores.cpu import CPU

dir = os.path.dirname(os.path.realpath(__file__))

# these select the top RTL file for each variant name
CPU_VARIANTS = {
'AXI': 'A2P_AXI',
'WB': 'A2P_WB',
'standard': 'A2P_WB' #wtf litex does this as default
}

GCC_FLAGS = {
'WB' : '-fomit-frame-pointer -Wall -fno-builtin -nostdinc -fno-stack-protector -fexceptions -Wstrict-prototypes -Wold-style-definition -Wmissing-prototypes'
}

class A2P(CPU, AutoCSR):
name = "a2p"
human_name = "a2p"
variants = CPU_VARIANTS
data_width = 32
endianness = "big"
gcc_triple = "powerpc-linux-gnu"
linker_output_format = "elf32-powerpc"
nop = "nop"
io_regions = {0x80000000: 0x80000000} # origin, length

@property
def mem_map(self):
return {
"rom": 0x00000000,
"sram": 0x00004000,
"main_ram": 0x40000000,
"csr": 0xf0000000,
}

@property
def gcc_flags(self):
flags = GCC_FLAGS[self.variant]
flags += " -D__a2p__"
return flags

def __init__(self, platform, variant='WB'):

if variant == 'standard':
variant = 'WB'

self.platform = platform
self.variant = variant
self.human_name = CPU_VARIANTS.get(variant, "A2P")
self.external_variant = None
self.reset = Signal()
self.interrupt = Signal(32)
self.interruptS = Signal()
self.ibus = ibus = wishbone.Interface()
self.dbus = dbus = wishbone.Interface()
self.periph_buses = [ibus, dbus]
self.memory_buses = []
self.enableDebug = False
self.enableJTAG = False
self.externalResetVector = 0

# # #

self.cpu_params = dict(
i_clk = ClockSignal(),
i_reset = ResetSignal() | self.reset,

i_externalInterrupt = self.interrupt[0],
i_externalInterruptS = self.interruptS,
i_timerInterrupt = 0,
i_softwareInterrupt = 0,

o_iBusWB_ADR = ibus.adr,
o_iBusWB_DAT_MOSI = ibus.dat_w,
o_iBusWB_SEL = ibus.sel,
o_iBusWB_CYC = ibus.cyc,
o_iBusWB_STB = ibus.stb,
o_iBusWB_WE = ibus.we,
o_iBusWB_CTI = ibus.cti,
o_iBusWB_BTE = ibus.bte,
i_iBusWB_DAT_MISO = ibus.dat_r,
i_iBusWB_ACK = ibus.ack,
i_iBusWB_ERR = ibus.err,

o_dBusWB_ADR = dbus.adr,
o_dBusWB_DAT_MOSI = dbus.dat_w,
o_dBusWB_SEL = dbus.sel,
o_dBusWB_CYC = dbus.cyc,
o_dBusWB_STB = dbus.stb,
o_dBusWB_WE = dbus.we,
o_dBusWB_CTI = dbus.cti,
o_dBusWB_BTE = dbus.bte,
i_dBusWB_DAT_MISO = dbus.dat_r,
i_dBusWB_ACK = dbus.ack,
i_dBusWB_ERR = dbus.err
)

self.cpu_params['i_externalResetVector'] = self.externalResetVector

# these need to connect to top nets
if self.enableDebug:
self.cpu_params['i_debugReset'] = 0
self.cpu_params['o_debug_resetOut'] = 0
self.cpu_params['i_debug_bus_cmd_valid'] = 0
self.cpu_params['i_debug_bus_cmd_ready'] = 0
self.cpu_params['i_debug_bus_cmd_payload_wr'] = 0
self.cpu_params['i_debug_bus_cmd_payload_address'] = 0
self.cpu_params['i_debug_bus_cmd_payload_data'] = 0
self.cpu_params['o_debug_bus_rsp_data'] = 0

if self.enableJTAG:
self.cpu_params['i_jtag_tms'] = 0
self.cpu_params['i_jtag_tck'] = 0
self.cpu_params['i_jtag_tdi'] = 0
self.cpu_params['o_jtag_tdo'] = 0

def set_reset_address(self, reset_address):
assert not hasattr(self, "reset_address")
self.reset_address = reset_address
self.cpu_params.update(i_externalResetVector=Signal(32, reset=reset_address))

@staticmethod
def add_sources(platform, variant="WB"):
cpu_filename = CPU_VARIANTS[variant] + ".v"
vdir = os.path.join(dir, 'verilog')
platform.add_source(os.path.join(vdir, cpu_filename))

def use_external_variant(self, variant_filename):
self.external_variant = True
self.platform.add_source(variant_filename)

def do_finalize(self):
assert hasattr(self, "reset_address")
if not self.external_variant:
self.add_sources(self.platform, self.variant)
self.specials += Instance("A2P_WB", **self.cpu_params)

0
build/litex/a2p/csr-defs.h
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build/litex/a2p/irq.h
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#ifndef __IRQ_H
#define __IRQ_H

static inline void irq_setmask(unsigned int mask) {
}

static inline unsigned int irq_getmask(void) {
return 0;
}

static inline unsigned int irq_pending(void) {
return 0;
}

static inline void irq_setie(unsigned int mask) {
}

#endif

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build/litex/a2p/system.h
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// swizzlin

#ifndef __SYSTEM_H
#define __SYSTEM_H

#include <stdint.h>

/*
void flush_l2_cache(void) {
}
*/
static void flush_cpu_icache(void);
static void flush_cpu_dcache(void);

static void flush_cpu_icache(void) {
}
static void flush_cpu_dcache(void) {
}

#define CSR_ACCESSORS_DEFINED

#ifdef __ASSEMBLER__
#define MMPTR(x) x
#else /* ! __ASSEMBLER__ */

#include <generated/soc.h>
#if !defined(CONFIG_CSR_DATA_WIDTH)
#error CSR_DATA_WIDTH MUST be set before including this file!
#endif

#define MMPTR(a) (*((volatile uint32_t *)(a)))

static inline unsigned long swizzle(unsigned long v);

static inline unsigned long swizzle(unsigned long v) {
return ((v & 0x000000FF) << 24) | ((v & 0x0000FF00) << 8) | ((v & 0x00FF0000) >> 8) | ((v & 0xFF000000) >> 24);
//return v;
}

static inline void csr_write_simple(unsigned long v, unsigned long a)
{
//MMPTR(a) = v;
MMPTR(a) = swizzle(v);
}

static inline unsigned long csr_read_simple(unsigned long a)
{
//return MMPTR(a);
return swizzle(MMPTR(a));
}

#endif /* ! __ASSEMBLER__ */

#endif /* __SYSTEM_H */

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build/litex/a2p/verilog/A2P_WB_no_byps.v
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build/litex/a2p/verilog/A2P_WB_no_cr_byp.v
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build/litex/a2p_cmod7.py
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#!/usr/bin/env python3

# A2P Test
# python3 a2p_cmod7.py --csr-csv csr.csv --no-compile-software --build
#

import os
import argparse

from migen import *

# local platform
from platforms import cmod7

# local core
import sys
binPath = os.path.dirname(os.path.realpath(__file__))
sys.path.append(os.path.join(binPath, 'a2p'))
from a2p import A2P
from litex.soc.cores import cpu
cpu.CPUS['a2p'] = A2P # add to litex dict

# local modules
sys.path.append(os.path.join(binPath, 'modules'))

from litex.soc.cores.clock import *
from litex.soc.integration.soc import colorer
from litex.soc.integration.soc import SoCRegion
from litex.soc.integration.soc_core import *
from litex.soc.integration.soc_sdram import *
from litex.soc.integration.builder import *

from litex.soc.cores.led import LedChaser
from litex.soc.cores import dna, xadc
from litex.soc.cores.gpio import GPIOIn
from litex.soc.cores.gpio import GPIOOut
from litex.soc.cores.bitbang import I2CMaster

from litex.soc.interconnect import wishbone

from litex.soc.cores import uart
from litex.soc.cores.uart import UART
from litex.soc.cores.uart import UARTPHY
from litex.soc.cores.uart import UARTWishboneBridge
from litescope import LiteScopeAnalyzer

# CRG ----------------------------------------------------------------------------------------------

class _CRG(Module):
def __init__(self, platform, sys_clk_freq):
self.rst = Signal()
self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_sys2x = ClockDomain(reset_less=True)
self.clock_domains.cd_idelay = ClockDomain()

self.submodules.pll = pll = S7MMCM(speedgrade=-1)
#wtf no idea how to modify the reset signal later (add btn0)
self.comb += pll.reset.eq(self.rst)
pll.register_clkin(platform.request("clk12"), 12e6)
pll.create_clkout(self.cd_sys, sys_clk_freq)
pll.create_clkout(self.cd_sys2x, 2*sys_clk_freq)
pll.create_clkout(self.cd_idelay, 200e6)
platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin)
self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_idelay)


# BaseSoC ------------------------------------------------------------------------------------------

from litex.soc.interconnect import wishbone

def _to_signal(obj):
return obj.raw_bits() if isinstance(obj, Record) else obj

class BaseSoC(SoCCore):

def __init__(self, sys_clk_freq=int(50e6),
with_analyzer=False,
uart_baudrate=115200,
**kwargs):

coreUART = True
platform = cmod7.Platform()

SoCCore.__init__(self, platform, sys_clk_freq, csr_data_width=32,
with_uart=coreUART, integrated_sram_size=0, integrated_rom_size=0,
ident="A2P", ident_version=True, uart_baudrate=uart_baudrate,
cpu_type='a2p')

#wtf no irq yet
self.add_constant("UART_POLLING")

#wtf this appears to be how to set up fixed csr order but not sure it works this way.
#SoCCore.csr_map
#self.csr_map = {**SoCCore.csr_map, **{
#self.csr_map = {
# "ctrl": 0,
# "dna" : 1,
# "uart": 2,
# "i2c": 3,
# "leds": 4
#}}

#interrupt_map = {**soc_cls.interrupt_map, **{
# "uart": 0,
# "timer0": 1,
#}}

# rom, sram are referenced by code linker so names must match!!!
self.mem_map = {
"csr": 0xFFF00000,
"sram": 0x00100000,
"rom": 0x00000000
}

# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)

# UART -------------------------------------------------------------------------------------
if not coreUART:
self.submodules.serial_bridge = UARTWishboneBridge(platform.request("serial"), sys_clk_freq)
self.add_wb_master(self.serial_bridge.wishbone)
#self.add_uartbone('serial', sys_clk_freq, baudrate=115200)

# ON-BOARD MEM ------------------------------------------------------------------------------

rom_size = 0x10000
with open('rom.init', 'r') as file:
hexdata = file.read().replace('\n', '')

outFile = open('mem_1.init', 'w') # write data immediately so available even if not building (sim)
bytedata = []
for i in range(0, len(hexdata), 8):
data = int(hexdata[i+6:i+8] + hexdata[i+4:i+6] + hexdata[i+2:i+4] + hexdata[i:i+2], 16) # BE->LE
bytedata.append(data)
outFile.write(hexdata[i+6:i+8] + hexdata[i+4:i+6] + hexdata[i+2:i+4] + hexdata[i:i+2] + '\n')
romdata = bytedata
outFile.close()
if len(romdata)*4 > rom_size:
self.logger.info('ROM {} {} {}.'.format(
colorer('Read', color='red'),
colorer(len(romdata)*4, color='red'),
colorer('bytes for preload. Too big!', color='red')))
quit(-100)
else:
self.logger.info('ROM {} {} {}.'.format(
colorer('Read', color='bright'),
colorer(len(romdata)*4, color='cyan'),
colorer('bytes for preload. Wrote mem_1.init.', color='bright')))

self.add_rom("rom", origin=self.mem_map["rom"], size=rom_size, contents=romdata)

# Internal SRAM (64K) -----------------------------------------------------------------------
#self.add_ram("sram", origin=self.mem_map["sram"], size=0x10000)

# External SRAM (512K) -----------------------------------------------------------------------

from issiram import ISSIRam
platform.add_source("./modules/issiram.v")

sram_bus = wishbone.Interface()
pins = platform.request('issiram')
mem = {
'ce': pins.cen,
'oe': pins.oen,
'we': pins.wen,
'adr': pins.addr,
'dat': pins.data
}
sram = ISSIRam(self, ClockSignal(), ResetSignal(), sram_bus, mem)
self.submodules.sram = sram
self.bus.add_slave('sram', sram_bus,
SoCRegion(origin=self.mem_map['sram'], size=sram.size))
self.logger.info("SRAM {} {} {}.".format(
colorer('sram'),
colorer("added", color="green"),
self.bus.regions['sram']))

# FPGA identification ------------------------------------------------------------------------
self.submodules.dna = dna.DNA()
self.add_csr("dna")

# FPGA temperature/voltage -------------------------------------------------------------------
self.submodules.xadc = xadc.XADC()
self.add_csr("xadc")

# Leds ---------------------------------------------------------------------------------------
self.submodules.leds = LedChaser(
pads = platform.request_all("user_led"),
sys_clk_freq = sys_clk_freq
)
self.add_csr("leds")

# Buttons ------------------------------------------------------------------------------------
self.submodules.buttons = GPIOIn(
pads = platform.request_all("user_btn")
)
self.add_csr("buttons")

# GPIO I2C -----------------------------------------------------------------------------------
i2c_0 = Record([("scl", 1), ("sda", 1)])
i2c_0.scl = platform.request('pmod', 0) # P1
i2c_0.sda = platform.request('pmod', 1) # P2
#wtf needs to be 'i2c' for bios for now
self.submodules.i2c = I2CMaster(i2c_0)
self.add_csr('i2c')

# GPIO UARTs ---------------------------------------------------------------------------------
#wtf someday

# GPIO Custom Serial -------------------------------------------------------------------------
#wtf attach to
self.submodules.dshot_0 = GPIOOut(
pads = platform.request("digital", 43) # P48
)
self.add_csr("dshot_0")

#wtf need to try...
# Analyzer -----------------------------------------------------------------------------------
if with_analyzer:
analyzer_signals = [
# IBus
self.cpu.ibus.stb,
self.cpu.ibus.cyc,
self.cpu.ibus.adr,
self.cpu.ibus.we,
self.cpu.ibus.ack,
self.cpu.ibus.sel,
self.cpu.ibus.dat_w,
self.cpu.ibus.dat_r,
# DBus
self.cpu.dbus.stb,
self.cpu.dbus.cyc,
self.cpu.dbus.adr,
self.cpu.dbus.we,
self.cpu.dbus.ack,
self.cpu.dbus.sel,
self.cpu.dbus.dat_w,
self.cpu.dbus.dat_r,
]
self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals,
depth = 512,
clock_domain = "sys",
csr_csv = "analyzer.csv")
self.add_csr("analyzer")

# Build --------------------------------------------------------------------------------------------

def main():

parser = argparse.ArgumentParser(description="A2P/cmod7")
parser.add_argument("--build", action="store_true", help="Build bitstream")
parser.add_argument("--load", action="store_true", help="Load bitstream")
parser.add_argument("--sys-clk-freq", default=100e6, help="System clock frequency (default: 100MHz)")
parser.add_argument("--with-analyzer", action="store_true", help="Include analyzer")

builder_args(parser)
soc_sdram_args(parser)
args = parser.parse_args()

print(args)

soc = BaseSoC(
sys_clk_freq = int(float(args.sys_clk_freq)),
with_analyzer = args.with_analyzer,
**soc_sdram_argdict(args)
)

builder = Builder(soc, **builder_argdict(args))
builder.build(run=args.build)

#wtf needs openocd!!!
if args.load:
prog = soc.platform.create_programmer()
prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".bit"))

if __name__ == "__main__":
main()

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build/litex/make
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#!/usr/bin/bash

code=../../software/a2p-bios/rom.init
soc=a2p_cmod7.py
top=build/cmod7/gateware/cmod7

vivado=vivado

program() {
$vivado -mode tcl -source pgmfpga.tcl
rm vivado*jou
rm vivado*log
rm -r .Xil
echo ""
echo ""
echo "Done."
}

if [ "$1" == "-c" ]; then
cp $code .
echo "Updated code ($code)."
echo ""
echo ""
elif [ "$1" == "-p" ]; then
program
exit
elif [ "$1" != "" ]; then
echo "make [-c|-p] (-c=also copy code, -p=just program"
exit
fi

# build and program
python3 $soc --csr-csv csr.csv --no-compile-software --build
if [ $? -ne 0 ]; then
exit
fi

echo "Copying .v and .bit, and programming..."
echo ""
echo ""
cp ${top}.v .
cp ${top}.bit .

program

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build/litex/modules/issiram.py
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../../../rtl/issiram/issiram.py

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build/litex/modules/issiram.v
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../../../rtl/issiram/issiram.v

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build/litex/pgmfpga.tcl
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# vivado -mode tcl -source pgmfpga.tcl

open_hw_manager

connect_hw_server
current_hw_target [get_hw_targets */xilinx_tcf/Digilent/*]
open_hw_target

set dev [lindex [get_hw_devices] 0]
current_hw_device $dev
refresh_hw_device -update_hw_probes false $dev
set_property PROGRAM.FILE {./cmod7.bit} $dev
#set_property PROBES.FILE {./cmod7.ltx} $dev

program_hw_devices $dev
refresh_hw_device $dev

puts "Device programmed."

quit

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build/litex/platforms/cmod7.py
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from litex.build.generic_platform import *
from litex.build.xilinx import XilinxPlatform, VivadoProgrammer
from litex.build.openocd import OpenOCD

# IOs ----------------------------------------------------------------------------------------------

_io = [
# Clk / Rst
("clk12", 0, Pins("L17"), IOStandard("LVCMOS33")),

# Leds
("user_led", 0, Pins("A17"), IOStandard("LVCMOS33")), # LD1
("user_led", 1, Pins("C16"), IOStandard("LVCMOS33")), # LD2

# RGB
("user_rgb_led", 0,
Subsignal("r", Pins("C17")),
Subsignal("g", Pins("B16")),
Subsignal("b", Pins("B17")),
IOStandard("LVCMOS33"),
),

# Buttons
("user_btn", 0, Pins("A18"), IOStandard("LVCMOS33")), # B0
("user_btn", 1, Pins("B18"), IOStandard("LVCMOS33")), # B1

("uart_0", 0,
Subsignal("tx", Pins("J3")), # 10
Subsignal("rx", Pins("J1")), # 11
IOStandard("LVCMOS33"),
),

# GPIO
("digital", 0, Pins("M3"), IOStandard("LVCMOS33")), # 1
("digital", 1, Pins("L3"), IOStandard("LVCMOS33")), # 2
("digital", 2, Pins("A16"), IOStandard("LVCMOS33")), # 3
("digital", 3, Pins("K3"), IOStandard("LVCMOS33")), # 4
("digital", 4, Pins("C15"), IOStandard("LVCMOS33")), # 5
("digital", 5, Pins("H1"), IOStandard("LVCMOS33")), # 6
("digital", 6, Pins("A15"), IOStandard("LVCMOS33")), # 7
("digital", 7, Pins("B15"), IOStandard("LVCMOS33")), # 8
("digital", 8, Pins("A14"), IOStandard("LVCMOS33")), # 9
("digital", 9, Pins("J3"), IOStandard("LVCMOS33")), # 10
("digital", 10, Pins("J1"), IOStandard("LVCMOS33")), # 11
("digital", 11, Pins("K2"), IOStandard("LVCMOS33")), # 12
("digital", 12, Pins("L1"), IOStandard("LVCMOS33")), # 13
("digital", 13, Pins("L2"), IOStandard("LVCMOS33")), # 14
("digital", 14, Pins("M1"), IOStandard("LVCMOS33")), # 17
("digital", 15, Pins("N3"), IOStandard("LVCMOS33")), # 18
("digital", 16, Pins("P3"), IOStandard("LVCMOS33")), # 19
("digital", 17, Pins("M2"), IOStandard("LVCMOS33")), # 20
("digital", 18, Pins("N1"), IOStandard("LVCMOS33")), # 21
("digital", 19, Pins("N2"), IOStandard("LVCMOS33")), # 22
("digital", 20, Pins("P1"), IOStandard("LVCMOS33")), # 23
("digital", 21, Pins("R3"), IOStandard("LVCMOS33")), # 26
("digital", 22, Pins("T3"), IOStandard("LVCMOS33")), # 27
("digital", 23, Pins("R2"), IOStandard("LVCMOS33")), # 28
("digital", 24, Pins("T1"), IOStandard("LVCMOS33")), # 29
("digital", 25, Pins("T2"), IOStandard("LVCMOS33")), # 30
("digital", 26, Pins("U1"), IOStandard("LVCMOS33")), # 31
("digital", 27, Pins("W2"), IOStandard("LVCMOS33")), # 32
("digital", 28, Pins("V2"), IOStandard("LVCMOS33")), # 33
("digital", 29, Pins("W3"), IOStandard("LVCMOS33")), # 34
("digital", 30, Pins("V3"), IOStandard("LVCMOS33")), # 35
("digital", 31, Pins("W5"), IOStandard("LVCMOS33")), # 36
("digital", 32, Pins("V4"), IOStandard("LVCMOS33")), # 37
("digital", 33, Pins("U4"), IOStandard("LVCMOS33")), # 38
("digital", 34, Pins("V5"), IOStandard("LVCMOS33")), # 39
("digital", 35, Pins("W4"), IOStandard("LVCMOS33")), # 40
("digital", 36, Pins("U5"), IOStandard("LVCMOS33")), # 41
("digital", 37, Pins("U2"), IOStandard("LVCMOS33")), # 42
("digital", 38, Pins("W6"), IOStandard("LVCMOS33")), # 43
("digital", 39, Pins("U3"), IOStandard("LVCMOS33")), # 44
("digital", 40, Pins("U7"), IOStandard("LVCMOS33")), # 45
("digital", 41, Pins("W7"), IOStandard("LVCMOS33")), # 46
("digital", 42, Pins("U8"), IOStandard("LVCMOS33")), # 47
("digital", 43, Pins("V8"), IOStandard("LVCMOS33")), # 48

("analog", 0,
Subsignal("n"), Pins("G2"),
Subsignal("p"), Pins("G3"),
IOStandard("LVCMOS33")
),

("analog", 1,
Subsignal("n"), Pins("J2"),
Subsignal("p"), Pins("H2"),
IOStandard("LVCMOS33")
),

# PMOD
("pmod", 0, Pins("G17"), IOStandard("LVCMOS33")), # 1
("pmod", 1, Pins("G19"), IOStandard("LVCMOS33")), # 2
("pmod", 2, Pins("N18"), IOStandard("LVCMOS33")), # 3
("pmod", 3, Pins("L18"), IOStandard("LVCMOS33")), # 4
("pmod", 4, Pins("H17"), IOStandard("LVCMOS33")), # 7
("pmod", 5, Pins("H19"), IOStandard("LVCMOS33")), # 8
("pmod", 6, Pins("J19"), IOStandard("LVCMOS33")), # 9
("pmod", 7, Pins("K18"), IOStandard("LVCMOS33")), # 10

# Serial
("serial", 0,
Subsignal("tx", Pins("J18")),
Subsignal("rx", Pins("J17")),
IOStandard("LVCMOS33"),
),

# JTAG: TMS(W9),TCK(C8),TDI(W10),TDO(W8)

# Crypto 1-Wire (?) - goes to ATSHA204A-MAHCZ-T
("crypto_sda", 0, Pins("D17"), IOStandard("LVCMOS33")),

# QSPI
("mx25l3233_spi", 0,
Subsignal("cs", Pins("K19")),
Subsignal("mosi", Pins("D18")), # DQ0
Subsignal("miso", Pins("D19")), # DQ1
#Subsignal("clk", Pins("E19")), # ref says E19; doesn't show in xdc; C11 in schematic
Subsignal("wp", Pins("G18")), # DQ2
Subsignal("hld", Pins("F18")), # DQ3
IOStandard("LVCMOS33")
),

# SRAM
("issiram", 0,
Subsignal("addr", Pins("M18 M19 K17 N17 P17 P18 R18 W19 U19 V19 W18 T17 T18 U17 U18 V16 W16 W17 V15"),
IOStandard("LVCMOS33")
),
Subsignal("data", Pins("W15 W13 W14 U15 U16 V13 V14 U14"),
IOStandard("LVCMOS33")
),
Subsignal("oen", Pins("P19"), IOStandard("LVCMOS33")),
Subsignal("wen", Pins("R19"), IOStandard("LVCMOS33")),
Subsignal("cen", Pins("N19"), IOStandard("LVCMOS33")),
Misc('SLEW=FAST')
),

]

# Platform -----------------------------------------------------------------------------------------

class Platform(XilinxPlatform):
default_clk_name = "clk12"
default_clk_period = 1e9/12e6

def __init__(self):
XilinxPlatform.__init__(self, "xc7a35t-CPG236-1", _io, toolchain="vivado")

#def create_programmer(self):
# return OpenOCD("openocd_xc7_ft2232.cfg", "bscan_spi_xc7a100t.bit")

def do_finalize(self, fragment):
XilinxPlatform.do_finalize(self, fragment)
self.add_period_constraint(self.lookup_request("clk12", loose=True), self.default_clk_period)

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# Litex SOC

```a2p_cmod7.py``` is a sample SOC for Digilent Cmod A7: https://digilent.com/reference/programmable-logic/cmod-a7/start

* 64K ROM (BRAM)
* 512K RAM (Async SRAM on board)
* UART for console

```rom.init``` is an asm test nanokernel plus Litex BIOS.

Generate SOC verilog and create bitstream...

```
make -c # copy rom.init, build, program
make # build, program
make -p # program
```

Start terminal...

```
lxterm /dev/ttyUSB1 # or whatever
```

```
A2P POWAflight

SRAM OK.
Copying ROM to RAM...
Jumping to main()...

__ _ __ _ __
/ / (_) /____ | |/_/
/ /__/ / __/ -_)> <
/____/_/\__/\__/_/|_|
Build your hardware, easily!

(c) Copyright 2012-2021 Enjoy-Digital
(c) Copyright 2007-2015 M-Labs

BIOS built on Oct 30 2021 08:02:58
BIOS CRC failed (expected 00000000, got 3f6a3f1d)
The system will continue, but expect problems.

Migen git sha1: 27dbf03
LiteX git sha1: 78c1751c

--=============== SoC ==================--
CPU: A2P_WB @ 100MHz
BUS: WISHBONE 32-bit @ 4GiB
CSR: 32-bit data
ROM: 64KiB
SRAM: 512KiB


--============== Boot ==================--
Booting from serial...
Press Q or ESC to abort boot completely.
sL5DdSMmkekro
Timeout
No boot medium found

--============= Console ================--

litex> mem_list
Available memory regions:
ROM 0x00000000 0x10000
SRAM 0x00100000 0x80000
CSR 0xfff00000 0x10000

litex> mem_test 0x120000 0x50000
Memtest at 0x120000 (320.0KiB)...
Write: 0x120000-0x170000 320.0KiB
Read: 0x120000-0x170000 320.0KiB
Memtest OK

litex>

```

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#!/bin/bash

sbt "runMain a2p.demo.A2P_WB_Verilog"

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# Performance

* tools, core analysis, competitive analysis

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# arci

* achitectural and compliancy tests for verifying cores (static bugs, compliancy aberrations)

* test generation/build/run

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* Simple test

* Initialization

R R1 00000001

* Test

I 00001000 38210001 addi r1,r1,1

* Results

R R1 00000002 * do you has opulence or are you worthless and weak?

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# dufi

* DUT kernel for verifying single-/multi-core, pipeline, memory, and system (dynamic bugs)

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# LLVM

* modify backend and add switches for A2 architectural experiments

* modify backend to add new accelerator/sandbox ops

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# Micropython

* build it

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# puki

* DUT kernel serving [emetic rat poison](https://hitman.fandom.com/wiki/Emetic_Rat_Poison) to the core

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# Tools

* stuff to do stuff
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