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299 lines
9.3 KiB
Markdown
299 lines
9.3 KiB
Markdown
# Verilator
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* verilator now successfully runs, once the nclk[] changes were completed to separate clk and rst, and
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remove lcb's driving lclk's
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## a2o w/WB wrapper
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```
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verilator -cc --exe --trace --Mdir obj_dir --language 1364-2001 -Wno-fatal -Wno-LITENDIAN --error-limit 1 -Iverilog/a2o_litex -Iverilog/work -Iverilog/trilib -Iverilog/unisims a2owb.v tb_litex.cpp |& tee verilator.txt
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make -C obj_dir -f Va2owb.mk Va2owb
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obj_dir/Va2owb
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```
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* about 5 non-scan UNOPTFLATs
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## Litex SOC
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* full SOC also runs; now need to add uart to tb and more code to get to litex terminal
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```
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top=cmod7_kintex
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build=../../build/litex/build/$top/gateware
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# keep consistent naming
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mod=soc
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cp $build/$top.v $mod.v
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sed -i "s/module $top/module $mod/" $mod.v
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# don't absolutely need this? soc will reset itself; also, csr can reset
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# make public - would be nice to do these with a --publics <file>
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sed -i 's#reg soc_rst =.*;#reg soc_rst /*verilator public*/ = 0;#' $mod.v
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# verilog loads a rom init file; gen'd during soc build or externally
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# test3 copies tst to @10000; ALSO! the tst wrapper has to be loaded into ram space since it has save/restore areas.
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#cp $build/${top}_rom.init . #LE
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cp ../mem/test3/rom_soc.init ${top}_rom.init #BE
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touch ${top}_mem.init # csr
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touch ${top}_sram.init # on-board
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touch ${top}_main_ram.init # ext
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verilator -cc --exe --trace --Mdir obj_dir_$mod --language 1364-2001 -Wno-fatal -Wno-LITENDIAN --error-limit 1 -I$. -Iverilog/a2o_litex -Iverilog/work -Iverilog/trilib -Iverilog/unisims -Iverilog/unisims_soc $mod tb_litex_$mod.cpp |& tee verilator_$mod.txt
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make -C obj_dir_$mod -f V$mod.mk V$mod
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obj_dir_$mod/V$mod | tee sim_soc.txt
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vcd2fst a2olitex.vcd soc.fst
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rm a2olitex.vcd
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gtkwave soc.fst soc.gtkw
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time obj_dir_$mod/V$mod > sim_soc_notrace.txt
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real 1m3.318s
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user 0m58.941s
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sys 0m3.368s
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```
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* notrace - faster execution?
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```
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dir=obj_dir_${mod}_notrace
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verilator -cc --exe -CFLAGS -DNO_TRACE=1 --Mdir $dir --language 1364-2001 -Wno-fatal -Wno-LITENDIAN --error-limit 1 -I$. -Iverilog/a2o_litex -Iverilog/work -Iverilog/trilib -Iverilog/unisims -Iverilog/unisims_soc $mod tb_litex_$mod.cpp |& tee verilator_$mod.txt
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make -j6 -C $dir -f V$mod.mk V$mod
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time $dir/V$mod > sim_soc_notrace.txt
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real 0m19.814s
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user 0m19.577s
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sys 0m0.188s
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```
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that is ~1.25KHz clk (25K cycs/20s).
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* -O3 + notrace
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```
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dir=obj_dir_${mod}_notrace_o3
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verilator -cc --exe -O3 -CFLAGS -DNO_TRACE=1 --Mdir $dir --language 1364-2001 -Wno-fatal -Wno-LITENDIAN --error-limit 1 -I$. -Iverilog/a2o_litex -Iverilog/work -Iverilog/trilib -Iverilog/unisims -Iverilog/unisims_soc $mod tb_litex_$mod.cpp |& tee verilator_$mod.txt
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make -j6 -C $dir -f V$mod.mk V$mod
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$dir/V$mod | tee sim_soc_o3.txt
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time $dir/V$mod > sim_soc_notrace_o3.txt
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real 0m23.279s
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user 0m22.916s
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sys 0m0.260s
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```
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* -O3 -O3 + notrace
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```
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dir=obj_dir_${mod}_notrace_o3_o3
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verilator -cc --exe -O3 -CFLAGS -O3 -CFLAGS -DNO_TRACE=1 --Mdir $dir --language 1364-2001 -Wno-fatal -Wno-LITENDIAN --error-limit 1 -I$. -Iverilog/a2o_litex -Iverilog/work -Iverilog/trilib -Iverilog/unisims -Iverilog/unisims_soc $mod tb_litex_$mod.cpp |& tee verilator_$mod.txt
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make -j6 -C $dir -f V$mod.mk V$mod
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$dir/V$mod | tee sim_soc_o3_o3.txt
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time $dir/V$mod > sim_soc_notrace_o3_o3.txt
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real 0m23.244s
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user 0m22.963s
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sys 0m0.192s
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```
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##### first try
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* runs until last completion of 134C???
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```
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00001338 <tst_cleanup>:
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1338: 3c 60 00 00 lis r3,0
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133c: 60 63 10 60 ori r3,r3,4192
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1340: 80 23 00 9c lwz r1,156(r3)
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1344: 3c 60 08 67 lis r3,2151
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1348: 60 63 53 09 ori r3,r3,21257
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134c: 48 00 0e 0f bla e0c <tst_done>
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00000e0c <tst_done>:
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e0c: 94 21 ff e0 stwu r1,-32(r1)
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```
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* bumped stopOnHang to 500 cycles and it does complete 1C0 after 134C. dsi on stwu. dear=FFFFFFE0. that is suspiciously identical to 0-32. what is trying to be read from @1060 to set r1??? that is in rom space. the tst wrapper is being linked into rom and not relocated! it should probably use a linker-gen'd pointer to use for its r/w data space. but wouldn't generally be building a tst into rom.
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##### second try
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* changed linker.ld to put tst in .data so it's copied by bios to ram...
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```
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00024966 C0: CP 0:000FD8 0000000000000FD8
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00024983 C0: CP 0:000FDC 1:000FE0 0000000000000FDC
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00024985 C0: CP 0:000FE4 1:000FF4 0000000000000FE4
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00024986 C0: CP 0:000FF8 1:000FFC 0000000000000FF8
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00025000 ...tick...
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00025005 C0: CP 0:001000 0000000000001000
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00025006 C0: CP 0:001004 0000000000001004
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00025008 C0: CP 0:001008 0000000000001008
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00025022 C0: CP 0:00100C 000000000000100C
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00025071 C0: CP 0:0007F0 00000000000007F0
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*** Passing IAR detected ***
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tb_litex_soc
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Cycles run=25074
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You has opulence.
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```
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## Experiments
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### core-only initial experiment
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```
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verilator -cc --exe --trace --Mdir obj_dir --language 1364-2001 -Wno-fatal -Wno-LITENDIAN --error-limit 1 -Iverilog/work -Iverilog/trilib_clk1x -Iverilog/trilib -Iverilog/unisims c.v tb.cpp
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make -C obj_dir -f Vc.mk Vc
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obj_dir/Vc
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```
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### core + node (extmem version)
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```
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verilator -cc --exe --trace --Mdir obj_dir --language 1364-2001 -Wno-fatal -Wno-LITENDIAN --error-limit 1 -Iverilog/work -Iverilog/trilib_clk1x -Iverilog/trilib -Iverilog/unisims -Iverilog/a2node a2owb.v tb_node.cpp
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make -C obj_dir -f Va2owb.mk Va2owb
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obj_dir/Va2owb
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```
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* doesn't work (test3/mem.init), which does work for coccotb/icarus
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* tid compare at start looks like it's using wrong value (imm from following bc?) and erat code is skipped
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### core + node wb (litex)
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* verilog/a2onode_litex
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```
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verilator -cc --exe --trace --Mdir obj_dir --language 1364-2001 -Wno-fatal -Wno-LITENDIAN --error-limit 1 -Iverilog/a2o_litex -Iverilog/work -Iverilog/trilib_clk1x -Iverilog/trilib -Iverilog/unisims a2owb.v tb_litex.cpp
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make -C obj_dir -f Va2owb.mk Va2owb
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obj_dir/Va2owb
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```
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* debugged several fails near start of test (in issues) - first few are cases of ff behaving incorrectly; syntax changes in trilib got to reaching i=1 ifetches
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* added CP signals to track completions (/*verilator public*/) and now first isync fails (flushes to @04)
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# Verilator Debug
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##### Old Stuff
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* install multiple versions concurrently
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```
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git pull
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git checkout master
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#..or...
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#git checkout stable
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#git checkout vxxx
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unset VERILATOR_ROOT
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export VERILATOR_VERSION=`git describe | sed "s/verilator_//"`
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./configure --prefix /tools/verilator/$VERILATOR_VERSION
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make -j <n>
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make install
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cp -r include /tools/verilator/$VERILATOR_VERSION # had to do this too
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# symlink
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ln -sf /tools/verilator/$VERILATOR_VERSION /tools/verilator/latest
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```
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* pick and run...
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```
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export VERILATOR_ROOT=/tools/verilator/latest
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# rm -r obj_dir # to be safe?
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verilator -cc --exe --trace --Mdir obj_dir --language 1364-2001 -Wno-fatal -Wno-LITENDIAN --error-limit 1 -Iverilog/a2o_litex -Iverilog/work -Iverilog/trilib_clk1x -Iverilog/trilib -Iverilog/unisims a2owb.v tb_litex.cpp
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make -C obj_dir -f Va2owb.mk Va2owb
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obj_dir/Va2owb
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```
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#### Try different versions with same RTL
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* rtl and tb_litex.cpp
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```
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git log | head -1
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commit 7cbbf9f3844a9287c5fac88867bcbcd5739914cf
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```
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* export VERILATOR_ROOT=/tools/verilator/v4.106
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* #define OLD_PUBLIC in tb_litex.cpp
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* the ifetch is bad, but so are the completes a little before it; @42C=```eratwe r8,r0,0```
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```
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...
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00000250 Completed: I0:1 000000000000042C
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00000262 WB RD RA=00000460
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00000263 WB RD ACK RA=00000460 DATA=7D4011A6
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00000264 WB RD RA=00000464
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00000265 WB RD ACK RA=00000464 DATA=7C8009A6
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00000266 WB RD RA=00000468
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00000267 WB RD ACK RA=00000468 DATA=7D0001A6
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00000268 WB RD RA=0000046C
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00000269 WB RD ACK RA=0000046C DATA=4C00012C
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00000272 Completed: I0:1 0000000000000000 I1:1 0000000000000000
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00000286 WB RD RA=00000000
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*** Fetch to boot address (00000000) after initial boot! ***
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```
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* export VERILATOR_ROOT=/tools/verilator/v4.204
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```
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00000250 Completed: I0:1 000000000000042C
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00000262 WB RD RA=00000460
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00000263 WB RD ACK RA=00000460 DATA=7D4011A6
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00000264 WB RD RA=00000464
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00000265 WB RD ACK RA=00000464 DATA=7C8009A6
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00000266 WB RD RA=00000468
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00000267 WB RD ACK RA=00000468 DATA=7D0001A6
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00000268 WB RD RA=0000046C
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00000269 WB RD ACK RA=0000046C DATA=4C00012C
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00000272 Completed: I0:1 0000000000000000 I1:1 0000000000000000
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00000286 WB RD RA=00000000
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*** Fetch to boot address (00000000) after initial boot! ***
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```
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* export VERILATOR_ROOT=/tools/verilator/stable (v4.224-26-g8b7480806)
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```
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00000250 Completed: I0:1 000000000000042C
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00000262 WB RD RA=00000460
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00000263 WB RD ACK RA=00000460 DATA=7D4011A6
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00000264 WB RD RA=00000464
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00000265 WB RD ACK RA=00000464 DATA=7C8009A6
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00000266 WB RD RA=00000468
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00000267 WB RD ACK RA=00000468 DATA=7D0001A6
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00000268 WB RD RA=0000046C
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00000269 WB RD ACK RA=0000046C DATA=4C00012C
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00000272 Completed: I0:1 0000000000000000 I1:1 0000000000000000
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00000286 WB RD RA=00000000
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*** Fetch to boot address (00000000) after initial boot! ***
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```
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* export VERILATOR_ROOT=/tools/verilator/latest (v4.224-82-gcbe1b8e26)
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```
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%Error: Verilator internal fault, sorry. Suggest trying --debug --gdbbt
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%Error: Command Failed /tools/verilator/latest/bin/verilator_bin -cc --exe --trace --Mdir obj_dir --language 1364-2001 -Wno-fatal -Wno-LITENDIAN --error-limit 1 -Iverilog/a2o_litex -Iverilog/work -I
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verilator -cc --debug --gddbt--exe --trace --Mdir obj_dir --language 1364-2001 -Wno-fatal -Wno-LITENDIAN --error-limit 1 -Iverilog/a2o_litex -Iverilog/work -Iverilog/trilib_clk1x -Iverilog/trilib -Iverilog/unisims a2owb.v tb_litex.cpp |& tee verilator-v224-82-debug.txt
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```
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