add wishbone interface

dev/bin/vtable

@@ -222,7 +222,7 @@ else:
    openBracket = '['
    closeBracket = ']'
    opAnd = '&'
-   opOr = '+'
+   opOr = '|'
    opNot = '~'
    zero = "'b0"
    tablePattern = re.compile(r'^\s*?\/\/tbl(?:\s+([^\s]+).*$|\s*$)')

dev/readme.md

@@ -25,8 +25,21 @@
 ## Next To Do
 
 * create A2L2 cpp model that can be used by Verilator and cocotb (Cython wrapper)
+   * eventually; don't need right now if can skip to RTL for A2L2
+
 * create simple A2L2-WB RTL for easily connecting to Litex, etc.
+   * version 1 is pre-WB; uses RAM interface which could be sim driver or BRAM
+
 * create Litex core wrapper
 * OpenLane experiments with blackbox arrays and yosys/abc/sta
-* create FPGA version of GPR/FPR (4R4W) using (4)4R1W banks and valid table
+* create FPGA version of GPR/FPR (4R4W) using (4)4R1W banks and *valid* table
 * parse vcd/fst and serve browser code for custom trace screens (handle spec/arch mapped facilities, arrays, etc.)
+
+
+#### node
+
+* test BE/LE versions; kernel can stay BE until jump to BIOS; any problem with BIOS to initial ROM copy/zero or is it always words?
+* eventually node should handle reset vector fetch; or make the reset vector tied to inputs so always configurable?
+* add config pins
+* add L2 internally (before WB)
+

dev/sim/coco/A2L2.py

@@ -504,10 +504,59 @@ async def A2L2Monitor(dut, sim, watchTrans=False):
             sim.msg(f'RELD tag={tag:02X} {data:32X}')  #wtf need qw,crit
             dataValidCyc = dataValidCyc[1:]
 
-class A2L2:
+# added wb stuff to try to use cocoext_wishbone
+class A2L2():
    driver = A2L2Driver
    checker = A2L2Checker
    monitor = A2L2Monitor
 
    def __init__(self):
       pass
+
+   @classmethod
+   def addWBSlave(cls, dut, sim, signals):
+      cls.dut = dut
+      cls.sim = sim
+      cls.wbSignals = signals
+
+   @classmethod
+   def wbSlave(cls, trans):
+      for t in trans:
+         adr = t.adr.integer
+         if t.datwr is not None:
+            be = t.sel.integer
+            dat = t.datwr.value
+            cls.sim.msg(f'WB Slave: WR @{adr:08X} sel={be:X} dat={dat:08X}')
+            cls.sim.mem.write(adr, dat, be)
+         else: # reads either no wait or waitIdle?
+            #cls.sim.msg(f'WB Slave: RD @{adr:08X} {t.datrd:08X}')
+            pass # datgen msg only
+         if t.waitAck or t.waitStall or t.waitIdle:
+            #cls.sim.msg(f'WB Slave: stall={t.waitStall} ack={t.waitAck} idle={t.waitIdle}')
+            #cls.sim.msg(f'WB Slave: got wait!')
+            pass
+
+   @classmethod
+   # no adr from slave!
+   def wbDatgen(cls):
+      sigAdr = getattr(cls.dut, cls.wbSignals['adr'])
+      try:
+         adr = sigAdr.value.integer
+      except:
+         adr = 0
+      dat = cls.sim.mem.read(adr)
+      cls.sim.msg(f'WB Slave: RD @{adr:08X}={dat:08X}')
+      return dat #yield dat
+
+class A2L2Iterable:
+   def __init__(self):
+      self.a2l2 = A2L2
+
+   def __iter__(self):
+      return self
+
+   def __next__(self):
+      return A2L2.wbDatgen()
+
+
+

dev/sim/coco/Makefile.node

@@ -20,6 +20,7 @@ TOPLEVEL = cocotb_icarus_node
 
 # python test
 MODULE = tb_node
+TESTCASE = tb_node
 
 # cocotb make rules
 include $(shell cocotb-config --makefiles)/Makefile.sim

dev/sim/coco/Makefile.wb

@@ -0,0 +1,36 @@
+# a2o tb-node
+
+SIM_BUILD ?= build_node
+SIM ?= icarus
+
+# icarus
+VERILOG_ROOT = ../../verilog
+
+# a2node_verilator has some test, etc. inputs tied in rtl
+# also has l/s credits set to 1 in defines
+COMPILE_ARGS = -I$(VERILOG_ROOT)/a2node_wb -I$(VERILOG_ROOT)/trilib -I$(VERILOG_ROOT)/work -y$(VERILOG_ROOT)/a2node_wb -y$(VERILOG_ROOT)/unisims -y$(VERILOG_ROOT)/trilib_clk1x -y$(VERILOG_ROOT)/trilib -y$(VERILOG_ROOT)/work
+
+# other options
+
+# rtl
+TOPLEVEL_LANG = verilog
+# top-level to enable trace, etc.
+VERILOG_SOURCES = ./cocotb_icarus_node.v
+TOPLEVEL = cocotb_icarus_node
+
+# python test
+MODULE = tb_node
+TESTCASE = tb_node_wb
+
+# cocotb make rules
+include $(shell cocotb-config --makefiles)/Makefile.sim
+
+build: clean sim fst
+
+run: sim fst
+
+vcd: sim
+
+fst:
+	vcd2fst a2onode.vcd a2onode.fst
+	rm a2onode.vcd

dev/sim/coco/OPEnv.py

@@ -89,12 +89,13 @@ class TransQ(DotMap):
 # could allow registering callback for loads and/or stores in range
 class Memory(DotMap):
 
-   def __init__(self, sim, default=0, logStores=True):
+   def __init__(self, sim, default=0, logReads=False, logStores=True):
       super().__init__()
       self.sim = sim
       self.data = {}
       self.le = False
       self.default = default  # default word data for unloaded
+      self.logReads = logReads
       self.logStores = logStores
 
    def loadFile(self, filename, format='ascii', addr=0, le=0):
@@ -121,6 +122,11 @@ class Memory(DotMap):
          addr = addr + 0
       except:
          addr = int(addr, 16)
+      if self.logReads:
+         if addr not in self.data:
+            self.sim.msg(f'Mem Read: @{addr:08X} XXXXXXXX')
+         else:
+            self.sim.msg(f'Mem Read: @{addr:08X} {self.data[addr]:08X}')
       if addr in self.data:
          return self.data[addr]
       else:

dev/sim/coco/readme.md

@@ -8,7 +8,7 @@
 make -f Makefile.st build |& grep -v Anac
 ```
 
-## Core+wrapper version with partial implementation of A2Node
+## Core+wrapper version with partial implementation of A2Node (direct memory)
 
 * testbench provides memory using simple RAM interface
 
@@ -18,8 +18,15 @@ make -f Makefile.node build |& grep -v Anac
 
 ## Core+wrapper version with implementation of A2Node (Wishbone system bus)
 
-* testbench provides Wishbone interface
+* testbench provides 4B Wishbone memory interface (using cocoext-wishbone for now)
-* can be easily dropped into Litex, etc. for Verilator and FPGA
+
+```
+make -f Makefile.wb build |& grep -v Anac
+``
+
+* update wrapper to include normal Litex, etc. I/O (WB plus ints, config, etc.)
+* add Litex core definition (migen)
+
 * can add L2 mem
 * can add multiple core intefaces (SMP)
 * can add multicore+heterogeneous cores (mixed A2L2, WB-1, WB-2)

dev/sim/coco/tb.py

@@ -231,8 +231,7 @@ async def tb(dut):
 
    sim = Sim(dut)
    sim.mem = Memory(sim)
-   #sim.maxCycles = 2000000
+   sim.maxCycles = 20000
-   sim.maxCycles = 300
    # original fpga design needed 4 cred, no fwd (set in logic currently)
    #sim.config.core.creditsSt = 32
    #sim.config.core.lsDataForward = 0   # disable=1
@@ -269,7 +268,6 @@ async def tb(dut):
    ]
    '''
 
-   '''
    # rom+bios+arcitst
    sim.memFiles = [
       {
@@ -277,8 +275,8 @@ async def tb(dut):
       'file' : '../mem/test3/rom.init'
       }
    ]
-   '''
 
+   '''
    # rom+bios+dhrystone
    sim.memFiles = [
       {
@@ -286,6 +284,7 @@ async def tb(dut):
       'file' : '../mem/dhrystone/rom.init'
       }
    ]
+   '''
 
    for i in range(len(sim.memFiles)):  #wtf el should be object with name, format, etc.
       sim.mem.loadFile(sim.memFiles[i]['file'], addr=sim.memFiles[i]['addr'])

dev/sim/coco/tb_node.py

@@ -81,6 +81,8 @@ async def init(dut, sim):
          dut.an_ac_hang_pulse[i].value = 0
          dut.an_ac_uncond_dbg_event[i].value = 0
 
+   dut.wb_datr = 0x08675309
+
    await Timer(9, units='ns')
 
 async def config(dut, sim):
@@ -329,3 +331,106 @@ async def tb_node(dut):
       dut._log.info(f'[{sim.cycle:08d}] You are worthless and weak!')
       dut._log.info(f'[{sim.cycle:08d}] {sim.fail}')
       assert False
+
+@cocotb.test()
+async def tb_node_wb(dut):
+   """A2O with WB and cocoext slave"""
+
+   sim = Sim(dut)
+   sim.mem = Memory(sim)
+   sim.maxCycles = 20000
+
+   # rom+bios+arcitst
+   sim.memFiles = [
+      {
+      'addr': 0x00000000,
+      'file' : '../mem/test3/rom.init'
+      }
+   ]
+
+   for i in range(len(sim.memFiles)):  #wtf el should be object with name, format, etc.
+      sim.mem.loadFile(sim.memFiles[i]['file'], addr=sim.memFiles[i]['addr'])
+
+   if sim.resetAddr is not None and sim.mem.read(sim.resetAddr) == sim.mem.default:
+      sim.mem.write(sim.resetAddr, sim.resetOp)
+      sim.msg(f'Set reset fetch @{sim.resetAddr:08X} to {sim.resetOp:08X}.')
+
+   # init stuff
+   await init(dut, sim)
+
+   # start clocks,reset
+   await cocotb.start(genClocks(dut, sim))
+   await cocotb.start(genReset(dut, sim))
+
+   # start interfaces
+   await cocotb.start(scom(dut, sim))
+
+   sim.a2o = A2OCore(sim, dut.c0.c0)
+   sim.a2o.traceFacUpdates =  True
+   sim.a2o.stopOnHang = 200
+   sim.a2o.stopOnLoop = 50
+   sim.a2o.iarPass = 0x7F0
+   sim.a2o.iarFail = 0x7F4
+
+   await cocotb.start(A2O.driver(dut, sim))
+
+   # sim memory
+   #await cocotb.start(memory(dut, sim))
+   # wishbone memory
+   from cocotbext.wishbone.monitor import WishboneSlave
+   # slave should take non-iterator for datgen and call it with f(self.bus) if next(f) fails
+   wbSignals = {"cyc": "wb_cyc",
+                "stb": "wb_stb",
+                "adr": "wb_adr",
+                "we":  "wb_we",
+                "sel": "wb_sel",
+                "datwr": "wb_datw",
+                "ack":  "wb_ack",
+                "datrd": "wb_datr"
+               }
+   a2l2Iterable = A2L2Iterable()
+   wbs = WishboneSlave(dut, None, dut.clk_1x, width=32, signals_dict=wbSignals, datgen=iter(a2l2Iterable))
+   A2L2.addWBSlave(dut, sim, wbSignals)
+   wbs.add_callback(A2L2.wbSlave)
+
+   #await cocotb.start(A2L2.driver(dut, sim))
+   await cocotb.start(A2L2.checker(dut, sim))
+   await cocotb.start(A2L2.monitor(dut, sim, watchTrans=True))
+
+   await Timer((sim.resetCycle + 5)*8, units='ns')
+   if dut.nclk[1].value != 0:
+      sim.ok = False
+      sim.fail = 'Reset active too long!'
+
+   # config stuff
+
+   # config for a2onode w/1 req buffer
+   # a2node_verilator defines have these set already
+   #sim.a2o.config.creditsLd = 1
+   #sim.a2o.config.creditsSt = 1
+   #sim.a2o.config.creditsLdStSingle = True
+
+   # original fpga design needed 4 cred, no fwd (set in logic currently)
+   #sim.a2o.lsDataForward = 0   # disable=1
+
+   await A2O.config(dut, sim)
+
+   await cocotb.start(A2O.checker(dut, sim))
+   await cocotb.start(A2O.monitor(dut, sim))
+
+   await cocotb.start(checker(dut, sim))
+
+   # release thread(s)
+   dut.an_ac_pm_thread_stop.value = 0
+   await RisingEdge(dut.clk_1x)
+   dut._log.info(f'[{sim.cycle:08d}] Threads enabled.')
+
+   # should await sim.done
+   await Timer((sim.maxCycles+100)*8, units='ns')
+
+   if sim.ok:
+      dut._log.info(f'[{sim.cycle:08d}] You has opulence.')
+   else:
+      dut._log.info(f'[{sim.cycle:08d}] You are worthless and weak!')
+      dut._log.info(f'[{sim.cycle:08d}] {sim.fail}')
+      assert False

dev/verilog/a2node_verilator/vtable

@@ -222,7 +222,7 @@ else:
    openBracket = '['
    closeBracket = ']'
    opAnd = '&'
-   opOr = '+'
+   opOr = '|'
    opNot = '~'
    zero = "'b0"
    tablePattern = re.compile(r'^\s*?\/\/tbl(?:\s+([^\s]+).*$|\s*$)')

dev/verilog/a2node_wb/a2l2wb.v

@@ -0,0 +1,800 @@
+// © IBM Corp. 2022
+// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+// the terms below; you may not use the files in this repository except in
+// compliance with the License as modified.
+// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+//
+// Modified Terms:
+//
+//    1) For the purpose of the patent license granted to you in Section 3 of the
+//    License, the "Work" hereby includes implementations of the work of authorship
+//    in physical form.
+//
+//    2) Notwithstanding any terms to the contrary in the License, any licenses
+//    necessary for implementation of the Work that are available from OpenPOWER
+//    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+//    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+//    of the EULA.
+//
+// Unless required by applicable law or agreed to in writing, the reference design
+// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+// for the specific language governing permissions and limitations under the License.
+//
+// Additional rights, including the ability to physically implement a softcore that
+// is compliant with the required sections of the Power ISA Specification, are
+// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+// obtained (along with the Power ISA) here: https://openpowerfoundation.org.
+
+// A2L2 bridge
+//  single req (shared L/S credit)
+//  interface to wb32
+
+`include "tri_a2o.vh"
+
+`timescale 1ns/1ps
+
+module a2l2wb #(
+   parameter                        MEM_MODE = 2,           // 0:ext 1:int 2:wb
+   parameter                        MEM_QW = 16384
+)
+(
+   input                            clk,
+   input                            rst,
+
+   input                            ac_an_req_pwr_token,
+   input                            ac_an_req,
+	input  [64-`REAL_IFAR_WIDTH:63]  ac_an_req_ra,
+	input  [0:5]                     ac_an_req_ttype,
+	input  [0:2]                     ac_an_req_thread,
+	input  [0:4]                     ac_an_req_ld_core_tag,
+	input  [0:2]                     ac_an_req_ld_xfr_len,
+	input                            ac_an_req_wimg_w,
+	input                            ac_an_req_wimg_i,
+	input                            ac_an_req_wimg_m,
+	input                            ac_an_req_wimg_g,
+	input                            ac_an_req_endian,
+	input  [0:3]                     ac_an_req_user_defined,
+	input  [0:3]                     ac_an_req_spare_ctrl_a0,
+	input                            ac_an_st_data_pwr_token,
+	input  [0:31]                    ac_an_st_byte_enbl,
+	input  [0:255]                   ac_an_st_data,
+
+	output                           an_ac_reld_data_vld,
+	output [0:4]                     an_ac_reld_core_tag,
+	output [0:127]                   an_ac_reld_data,
+	output [58:59]                   an_ac_reld_qw,
+	output                           an_ac_reld_ecc_err,
+	output                           an_ac_reld_ecc_err_ue,
+	output                           an_ac_reld_data_coming,
+	output                           an_ac_reld_ditc,
+	output                           an_ac_reld_crit_qw,
+	output                           an_ac_reld_l1_dump,
+	output [0:3]                     an_ac_req_spare_ctrl_a1,
+	output [0:`THREADS-1]            an_ac_sync_ack,
+
+	output                           an_ac_req_ld_pop,
+	output                           an_ac_req_st_pop,
+	output                           an_ac_req_st_gather,
+
+	output [0:`THREADS-1]            an_ac_stcx_complete,
+	output [0:`THREADS-1]            an_ac_stcx_pass,
+   output [0:`THREADS-1]            an_ac_reservation_vld,
+
+	output                           an_ac_icbi_ack,
+	output [0:1]                     an_ac_icbi_ack_thread,
+   output                           an_ac_back_inv,
+	output [64-`REAL_IFAR_WIDTH:63]  an_ac_back_inv_addr,
+	output [0:4]                     an_ac_back_inv_target,
+	output                           an_ac_back_inv_local,
+	output                           an_ac_back_inv_lbit,
+	output                           an_ac_back_inv_gs,
+	output                           an_ac_back_inv_ind,
+	output [0:7]                     an_ac_back_inv_lpar_id,
+	input                            ac_an_back_inv_reject,
+	input  [0:7]                     ac_an_lpar_id,
+   output                           an_ac_checkstop,
+
+    // direct-attach mem
+   output [0:31]                    mem_adr,
+   input  [0:127]                   mem_dat,
+   output                           mem_wr_val,
+   output [0:15]                    mem_wr_be,
+   output [0:127]                   mem_wr_dat,
+
+    // wishbone
+   output                           wb_stb,
+   output                           wb_cyc,
+   output [31:0]                    wb_adr,
+   output                           wb_we,
+   output [3:0]                     wb_sel,
+   output [31:0]                    wb_datw,
+   input                            wb_ack,
+   input  [31:0]                    wb_datr
+);
+
+   // unsupported right now
+
+   assign an_ac_sync_ack = 0;
+   assign an_ac_stcx_complete = 0;
+   assign an_ac_stcx_pass = 0;
+   assign an_ac_reservation_vld = 0;
+
+   assign an_ac_icbi_ack = 0;
+   assign an_ac_icbi_ack_thread = 0;
+   assign an_ac_back_inv = 0;
+   assign an_ac_back_inv_addr = 0;
+   assign an_ac_back_inv_target = 0;
+   assign an_ac_back_inv_local = 0;
+   assign an_ac_back_inv_lbit = 0;
+   assign an_ac_back_inv_gs = 0;
+   assign an_ac_back_inv_ind = 0;
+   assign an_ac_back_inv_lpar_id = 0;
+
+   assign an_ac_req_st_gather = 0;
+   assign an_ac_req_spare_ctrl_a1 = 0;
+   assign an_ac_reld_l1_dump = 0;
+
+   wire   [0:4]                  cmdseq_d;
+   reg    [0:4]                  cmdseq_q /*verilator public */;
+   wire   [0:30+`REAL_IFAR_WIDTH] req_d;
+   reg    [0:30+`REAL_IFAR_WIDTH] req_q;
+   wire   [0:31+256]             std_d;
+   reg    [0:31+256]             std_q;
+   reg                           req_tkn_q;
+   reg                           std_tkn_q;
+   wire   [0:255]                rld_d;
+   reg    [0:255]                rld_q;
+   wire   [0:1]                  qw_d;
+   reg    [0:1]                  qw_q;
+   wire   [0:1]                  mem_qw_d;
+   reg    [0:1]                  mem_qw_q;
+   wire   [0:1]                  wb_qw_d;
+   reg    [0:1]                  wb_qw_q;
+   wire   [0:7]                  err_d;
+   reg    [0:7]                  err_q /*verilator public */;
+
+   // depend on MEM_MODE
+   reg    [0:127]                mem[MEM_QW];
+   wire   [0:127]                mem_dat_int;
+   reg    [0:3]                  wbseq_q;
+   wire   [0:3]                  wbseq_d;
+   reg    [0:127]                wb_datr_q[0:3];
+   wire   [0:127]                wb_datr_d[0:3];
+
+   wire                          new_req;
+   wire                          req_ld_val;
+   wire                          req_st_val;
+   wire                          req_ieq1;
+   wire                          req_le;
+   wire 	 [64-`REAL_IFAR_WIDTH:63] req_adr;
+   wire   [0:4]                  req_tag;
+   wire   [0:2]                  req_len;
+   wire   [0:255]                req_st_dat;
+   wire   [0:31]                 req_st_be;
+   wire   [0:7]                  req_st_we;
+
+   wire                          rld_coming;
+   wire                          rld_valid;
+   wire                          rld_done;
+   wire   [0:1]                  rld_qw;
+   wire                          cmdseq_idle;
+   wire                          ld_ready;
+   wire                          st_ready;
+   wire                          do_store;
+   wire                          wb_inc_qw;
+   wire                          inc_qw;
+   wire   [0:1]                  dat_sel;
+   wire                          qw_sel_0;
+   wire                          qw_sel_1;
+   wire                          qw_sel_2;
+   wire                          qw_sel_3;
+
+   // FF
+   always @(posedge clk) begin
+
+      if (rst) begin
+
+         cmdseq_q = 'b11111;
+         req_q = 0;
+         std_q = 0;
+         req_tkn_q = 0;
+         std_tkn_q = 0;
+         qw_q = 0;
+         mem_qw_q = 0;
+         err_q = 0;
+
+      end else begin
+
+         cmdseq_q = cmdseq_d;
+         req_q = req_d;
+         std_q = std_d;
+         req_tkn_q = ac_an_req_pwr_token;
+         std_tkn_q = ac_an_st_data_pwr_token;
+         qw_q = qw_d;
+         mem_qw_q = mem_qw_d;
+         err_q = err_d;
+
+      end
+   end
+
+// adr needs to be created for cacheable!
+
+// ext/int mem
+// mem_adr ---          (qw-aligned byte address)
+// mem_dat     ---
+
+// external memory
+generate if (MEM_MODE == 0) begin
+   assign mem_dat_int = mem_dat;
+end
+endgenerate
+
+// internal memory
+generate if (MEM_MODE == 1) begin
+   always @(posedge clk) begin
+      if (!rst & mem_wr_val) begin
+         mem[mem_adr] = mem_wr_dat;
+      end
+   end
+   assign mem_dat_int = mem[req_adr];
+end
+endgenerate
+
+// wishbone
+generate if (MEM_MODE == 2) begin
+   always @(posedge clk) begin
+      if (rst) begin
+         wbseq_q = 4'b1111;
+         wb_qw_q = 0;
+      end else begin
+         wbseq_q = wbseq_d;
+         wb_datr_q[0] = wb_datr_d[0];
+         wb_datr_q[1] = wb_datr_d[1];
+         wb_datr_q[2] = wb_datr_d[2];
+         wb_datr_q[3] = wb_datr_d[3];
+         wb_qw_q = wb_qw_d;
+      end
+   end
+   assign mem_dat_int = wb_qw_q == 2'b00 ? wb_datr_q[0] :
+                        wb_qw_q == 2'b01 ? wb_datr_q[1] :
+                        wb_qw_q == 2'b10 ? wb_datr_q[2] :
+                                           wb_datr_q[3];
+end
+endgenerate
+
+generate if (MEM_MODE == 2) begin
+   assign mem_adr = req_st_val ? {req_adr[32:59], dat_sel, 2'b00} :
+                    req_ieq1 ?   {req_adr[32:59], dat_sel, 2'b00} :
+                                 {req_adr[32:57], qw_q, dat_sel, 2'b00};
+end else begin
+   assign mem_adr = req_st_val ? {req_adr[32:59], 4'b0000} :
+                    req_ieq1 ?   req_adr[32:63] :
+                                 {req_adr[32:57], mem_qw_q, 4'b0000};
+end
+endgenerate
+
+   // clkgate
+   // oflow if req_q[0]==1!
+   assign new_req = req_tkn_q & ac_an_req;
+   assign req_d = new_req ?
+                              {1'b1,                     // 0
+                               ac_an_req_thread,         // 1:3
+                               ac_an_req_ttype,          // 4:9
+                               ac_an_req_ld_core_tag,    // 10:14
+                               ac_an_req_ra,             // 15:56
+                               ac_an_req_ld_xfr_len,     // 57:59
+                               ac_an_req_wimg_w,         // 60
+                               ac_an_req_wimg_i,         // 61
+                               ac_an_req_wimg_m,         // 62
+                               ac_an_req_wimg_g,         // 63
+                               ac_an_req_endian,         // 64
+                               ac_an_req_user_defined,   // 65:68
+                               ac_an_req_spare_ctrl_a0   // 69:72
+                              } :
+                   (rld_done | do_store) ? 0 : req_q;
+
+   assign std_d = std_tkn_q ? {ac_an_st_byte_enbl,       // 0:31
+                               ac_an_st_data             // 32:287
+                              } : do_store ? 0 : std_q;
+
+   // request
+   assign req_ld_val = req_q[0] & (
+                       (req_q[4:9] == 6'b000000) |  // if
+                       (req_q[4:9] == 6'b001000) |  // ld
+                       (req_q[4:9] == 6'b100010) |  // ditc
+                       (req_q[4:9] == 6'b001001) |  // larx
+                       (req_q[4:9] == 6'b001011)    // larx hint
+   );
+   assign req_ieq1 = req_q[61];
+   assign req_le = req_q[64];
+
+   assign req_st_val = req_q[0] & (
+                       (req_q[4:9] == 6'b100000) |  // st
+                       (req_q[4:9] == 6'b101001)    // stcx
+   );
+
+   assign req_tag = req_q[10:14];
+   assign req_adr = req_q[15:15+`REAL_IFAR_WIDTH-1];
+   assign req_len = req_q[57:59];
+
+   assign req_st_be = std_q[0:31];
+   assign req_st_we[0] = |std_q[0:3];
+   assign req_st_we[1] = |std_q[4:7];
+   assign req_st_we[2] = |std_q[8:11];
+   assign req_st_we[3] = |std_q[12:15];
+   assign req_st_dat = std_q[32:287];
+
+// random delay, or wb trans complete
+generate if (MEM_MODE != 2) begin
+   assign ld_ready = 1;
+   assign st_ready = 1;
+end
+endgenerate
+
+   // A2L2 Interface
+
+   // b2b
+   // coming  ---    ---
+   // valid      --- --- --- ---           (and qualifiers)
+   // data               --- --- --- ---   (only 1 beat for ieq1)
+
+   // vtable -V -b 0 a2l2wb.v
+   //tbl cmdseq
+   //n cmdseq_q                            cmdseq_d
+   //n |                                   |     rld_coming
+   //n |     req_ld_val                    |     |rld_valid
+   //n |     |req_st_val                   |     ||do_store
+   //n |     ||ld_ready                    |     |||rld_done
+   //n |     |||st_ready                   |     ||||inc_qw
+   //n |     ||||req_ieq1                  |     |||||  cmdseq_idle
+   //n |     |||||                         |     |||||  |
+   //n |     |||||                         |     |||||  |
+   //b 01234 |||||                         01234 |||||  |
+   //t iiiii iiiii                         ooooo ooooo  o
+   //*----------------------------------------------------------------------
+   //* Idle ****************************************************************
+   //s 11111 -----                         ----- 00000  1
+   //s 11111 00---                         11111 00000  -                              * ...zzz...
+   //s 11111 1----                         00001 00000  -
+   //s 11111 -1---                         10000 00000  -
+   //* Load ****************************************************************
+   //s 00001 --0--                         00001 00000  0
+   //s 00001 --1--                         00010 10000  0
+   //* Reload V0 ***********************************************************           * val 0
+   //s 00010 -----                         00011 01001  0
+   //* Reload Nop ***********************************************************          * val 1 (not ieq1)
+   //s 00011 ----1                         00100 00000  0
+   //s 00011 ----0                         01000 11001  0
+   //* Reload D0 (I=1) ******************************************************          * dat 0 (ieq1)
+   //s 00100 -----                         11111 00010  0
+   //* Reload D0 ************************************************************          * val 2, dat 0
+   //s 01000 -----                         01001 01001  0
+   //* Reload D1 ************************************************************          * val 3, dat 1
+   //s 01001 -----                         01010 01001  0
+   //* Reload D2 ************************************************************          * dat 2
+   //s 01010 -----                         01011 00000  0
+   //* Reload D3 ************************************************************          * dat 3
+   //s 01011 -----                         11111 00010  0
+   //* Store ***************************************************************
+   //s 10000 ---0-                         10000 00000  0
+   //s 10000 ---1-                         11111 00100  0
+   //*----------------------------------------------------------------------
+   //tbl cmdseq
+
+   // Wishbone Interface
+   // 4B data
+   // req_ld_val: 4 or 16 wb reqs based on ieq1
+   // set ldready when all data rcvd
+   // req_st_val: 0-4 wb reqs based on be
+   // set stready when last data ack'd
+
+   //tbl wbseq
+   //n wbseq_q                               wbseq_d
+   //n |    cmdseq_idle                      |
+   //n |    | req_ld_val                     |
+   //n |    | |req_ieq1                      |    wb_stb
+   //n |    | ||req_st_val                   |    |wb_cyc
+   //n |    | |||req_st_we                   |    ||wb_we
+   //n |    | ||||                           |    ||| dat_sel
+   //n |    | ||||                           |    ||| |  ld_ready
+   //n |    | ||||    qw_q                   |    ||| |  |st_ready
+   //n |    | ||||    |  wb_ack              |    ||| |  ||wb_inc_qw
+   //n |    | ||||    |  |                   |    ||| |  |||
+   //n |    | ||||    |  |                   |    ||| |  |||
+   //b 0123 | |||0123 01 |                   0123 ||| 01 |||
+   //t iiii i iiiiiii ii i                   oooo ooo oo ooo
+   //*------------------------------------------------------
+   //* Idle ************************************************
+   //s 1111 - 0-0---- -- -                   1111 000 00 000          * ...zzz...
+   //s 1111 - 1-0---- -- -                   0100 000 00 000
+   //s 1111 - 0-11--- -- -                   1000 000 00 000
+   //s 1111 - 0-101-- -- -                   1001 000 00 000
+   //s 1111 - 0-1001- -- -                   1010 000 00 000
+   //s 1111 - 0-10001 -- -                   1011 000 00 000
+   //s 1111 - 0-10000 -- -                   1111 000 00 010
+   //* Load W0 *********************************************
+   //s 0100 - ------- -- 0                   0100 110 00 000
+   //s 0100 - ------- -- 1                   0101 110 00 000
+   //* Load W1 *********************************************
+   //s 0101 - ------- -- 0                   0101 110 01 000
+   //s 0101 - ------- -- 1                   0110 110 01 000
+   //* Load W2 *********************************************
+   //s 0110 - ------- -- 0                   0110 110 10 000
+   //s 0110 - ------- -- 1                   0111 110 10 000
+   //* Load W3 *********************************************
+   //s 0111 - ------- -- 0                   0111 110 11 000
+   //s 0111 - -0----- 0- 1                   0100 110 11 001
+   //s 0111 - -0----- -0 1                   0100 110 11 001
+   //s 0111 - -1----- -- 1                   1110 110 11 100
+   //s 0111 - -0----- 11 1                   1110 110 11 100
+   //* Store W0 ********************************************
+   //s 1000 - ------- -- 0                   1000 111 00 000
+   //s 1000 - ----1-- -- 1                   1001 111 00 000
+   //s 1000 - ----01- -- 1                   1010 111 00 000
+   //s 1000 - ----001 -- 1                   1011 111 00 000
+   //s 1000 - ----000 -- 1                   1110 111 00 010
+   //* Store W1 ********************************************
+   //s 1001 - ------- -- 0                   1001 111 01 000
+   //s 1001 - -----1- -- 1                   1010 111 01 000
+   //s 1001 - -----01 -- 1                   1011 111 01 000
+   //s 1001 - -----00 -- 1                   1110 111 01 010
+   //* Store W2 ********************************************
+   //s 1010 - ------- -- 0                   1010 111 10 000
+   //s 1010 - ------1 -- 1                   1011 111 10 000
+   //s 1010 - ------0 -- 1                   1110 111 10 010
+   //* Store W3 ********************************************
+   //s 1011 - ------- -- 0                   1011 111 11 000
+   //s 1011 - ------- -- 1                   1110 111 11 010
+   //* Wait for op complete ********************************
+   //s 1110 0 ------- -- -                   1110 000 00 000
+   //s 1110 1 ------- -- -                   1111 000 00 000
+   //*------------------------------------------------------
+   //tbl wbseq
+
+generate if (MEM_MODE == 2) begin
+   assign wb_adr = mem_adr;
+
+   assign qw_sel_0 = qw_q == 2'b00;
+   assign qw_sel_1 = qw_q == 2'b01;
+   assign qw_sel_2 = qw_q == 2'b10;
+   assign qw_sel_3 = qw_q == 2'b11;
+
+   assign wb_datr_d[0][0:31]   = (req_ld_val & wb_ack & qw_sel_0 & dat_sel == 2'b00) ? wb_datr : wb_datr_q[0][0:31];
+   assign wb_datr_d[0][32:63]  = (req_ld_val & wb_ack & qw_sel_0 & dat_sel == 2'b01) ? wb_datr : wb_datr_q[0][32:63];
+   assign wb_datr_d[0][64:95]  = (req_ld_val & wb_ack & qw_sel_0 & dat_sel == 2'b10) ? wb_datr : wb_datr_q[0][63:95];
+   assign wb_datr_d[0][96:127] = (req_ld_val & wb_ack & qw_sel_0 & dat_sel == 2'b11) ? wb_datr : wb_datr_q[0][96:127];
+
+   assign wb_datr_d[1][0:31]   = (req_ld_val & wb_ack & qw_sel_1 & dat_sel == 2'b00) ? wb_datr : wb_datr_q[1][0:31];
+   assign wb_datr_d[1][32:63]  = (req_ld_val & wb_ack & qw_sel_1 & dat_sel == 2'b01) ? wb_datr : wb_datr_q[1][32:63];
+   assign wb_datr_d[1][64:95]  = (req_ld_val & wb_ack & qw_sel_1 & dat_sel == 2'b10) ? wb_datr : wb_datr_q[1][63:95];
+   assign wb_datr_d[1][96:127] = (req_ld_val & wb_ack & qw_sel_1 & dat_sel == 2'b11) ? wb_datr : wb_datr_q[1][96:127];
+
+   assign wb_datr_d[2][0:31]   = (req_ld_val & wb_ack & qw_sel_2 & dat_sel == 2'b00) ? wb_datr : wb_datr_q[2][0:31];
+   assign wb_datr_d[2][32:63]  = (req_ld_val & wb_ack & qw_sel_2 & dat_sel == 2'b01) ? wb_datr : wb_datr_q[2][32:63];
+   assign wb_datr_d[2][64:95]  = (req_ld_val & wb_ack & qw_sel_2 & dat_sel == 2'b10) ? wb_datr : wb_datr_q[2][63:95];
+   assign wb_datr_d[2][96:127] = (req_ld_val & wb_ack & qw_sel_2 & dat_sel == 2'b11) ? wb_datr : wb_datr_q[2][96:127];
+
+   assign wb_datr_d[3][0:31]   = (req_ld_val & wb_ack & qw_sel_3 & dat_sel == 2'b00) ? wb_datr : wb_datr_q[3][0:31];
+   assign wb_datr_d[3][32:63]  = (req_ld_val & wb_ack & qw_sel_3 & dat_sel == 2'b01) ? wb_datr : wb_datr_q[3][32:63];
+   assign wb_datr_d[3][64:95]  = (req_ld_val & wb_ack & qw_sel_3 & dat_sel == 2'b10) ? wb_datr : wb_datr_q[3][63:95];
+   assign wb_datr_d[3][96:127] = (req_ld_val & wb_ack & qw_sel_3 & dat_sel == 2'b11) ? wb_datr : wb_datr_q[3][96:127];
+
+   assign wb_sel = dat_sel == 2'b00 ? req_st_be[0:3]  :
+                   dat_sel == 2'b01 ? req_st_be[4:7]  :
+                   dat_sel == 2'b10 ? req_st_be[8:11] :
+                                      req_st_be[12:15];
+
+   assign wb_datw = dat_sel == 2'b00 ? req_st_dat[0:31]  :
+                    dat_sel == 2'b01 ? req_st_dat[32:63] :
+                    dat_sel == 2'b10 ? req_st_dat[64:95] :
+                                       req_st_dat[96:127];
+end
+endgenerate
+
+   // qw for wb loads, or a2l2 rld
+   // crit first uses qw pattern instead of +1
+   // valid (d-2)
+   assign qw_d = (new_req | ld_ready) ? 0 :
+                 (inc_qw | wb_inc_qw) ? qw_q + 1 :
+                 qw_q;
+
+   assign rld_qw = req_ieq1 ? 2'b00 : qw_q;
+
+   // mem address (d-1) non-wb
+   assign mem_qw_d = rld_qw;
+
+   // dat sel (d-0) wb
+   //assign wb_qw_d = mem_qw_q;  wb_qw_q is not always following wb_qw_d!!! iverilog e7b700f48ed07c2e272c436079da057394642443
+   assign wb_qw_d[0] = mem_qw_q[0];
+   assign wb_qw_d[1] = mem_qw_q[1];
+
+   // response
+   assign an_ac_reld_ecc_err = 0;
+   assign an_ac_reld_ecc_err_ue = 0;
+   assign an_ac_reld_ditc = 0;
+
+   // loads
+   assign an_ac_reld_data_coming = rld_coming;
+   assign an_ac_reld_data_vld = rld_valid;
+   assign an_ac_reld_core_tag = req_tag;
+   assign an_ac_reld_qw = rld_qw;
+   assign an_ac_reld_crit_qw = req_ieq1 | (req_adr[58:59] == rld_qw);
+   assign an_ac_reld_data = mem_dat_int;
+   assign an_ac_req_ld_pop = rld_done;
+
+   // stores
+   assign an_ac_req_st_pop = do_store;
+
+   // BE, 16B max store
+   assign mem_wr_val = do_store;
+   assign mem_wr_be = std_q[0:15];
+   assign mem_wr_dat = std_q[32:32+127];
+
+   // misc
+   assign err_d = {(new_req & ~cmdseq_idle), 7'b0};
+   assign an_ac_checkstop = err_q != 0;
+
+//vtable cmdseq
+assign cmdseq_d[0] =
+  (cmdseq_q[0] & cmdseq_q[1] & cmdseq_q[2] & cmdseq_q[3] & cmdseq_q[4] & ~req_ld_val & ~req_st_val) |
+  (cmdseq_q[0] & cmdseq_q[1] & cmdseq_q[2] & cmdseq_q[3] & cmdseq_q[4] & req_st_val) |
+  (~cmdseq_q[0] & ~cmdseq_q[1] & cmdseq_q[2] & ~cmdseq_q[3] & ~cmdseq_q[4]) |
+  (~cmdseq_q[0] & cmdseq_q[1] & ~cmdseq_q[2] & cmdseq_q[3] & cmdseq_q[4]) |
+  (cmdseq_q[0] & ~cmdseq_q[1] & ~cmdseq_q[2] & ~cmdseq_q[3] & ~cmdseq_q[4] & ~st_ready) |
+  (cmdseq_q[0] & ~cmdseq_q[1] & ~cmdseq_q[2] & ~cmdseq_q[3] & ~cmdseq_q[4] & st_ready);
+assign cmdseq_d[1] =
+  (cmdseq_q[0] & cmdseq_q[1] & cmdseq_q[2] & cmdseq_q[3] & cmdseq_q[4] & ~req_ld_val & ~req_st_val) |
+  (~cmdseq_q[0] & ~cmdseq_q[1] & ~cmdseq_q[2] & cmdseq_q[3] & cmdseq_q[4] & ~req_ieq1) |
+  (~cmdseq_q[0] & ~cmdseq_q[1] & cmdseq_q[2] & ~cmdseq_q[3] & ~cmdseq_q[4]) |
+  (~cmdseq_q[0] & cmdseq_q[1] & ~cmdseq_q[2] & ~cmdseq_q[3] & ~cmdseq_q[4]) |
+  (~cmdseq_q[0] & cmdseq_q[1] & ~cmdseq_q[2] & ~cmdseq_q[3] & cmdseq_q[4]) |
+  (~cmdseq_q[0] & cmdseq_q[1] & ~cmdseq_q[2] & cmdseq_q[3] & ~cmdseq_q[4]) |
+  (~cmdseq_q[0] & cmdseq_q[1] & ~cmdseq_q[2] & cmdseq_q[3] & cmdseq_q[4]) |
+  (cmdseq_q[0] & ~cmdseq_q[1] & ~cmdseq_q[2] & ~cmdseq_q[3] & ~cmdseq_q[4] & st_ready);
+assign cmdseq_d[2] =
+  (cmdseq_q[0] & cmdseq_q[1] & cmdseq_q[2] & cmdseq_q[3] & cmdseq_q[4] & ~req_ld_val & ~req_st_val) |
+  (~cmdseq_q[0] & ~cmdseq_q[1] & ~cmdseq_q[2] & cmdseq_q[3] & cmdseq_q[4] & req_ieq1) |
+  (~cmdseq_q[0] & ~cmdseq_q[1] & cmdseq_q[2] & ~cmdseq_q[3] & ~cmdseq_q[4]) |
+  (~cmdseq_q[0] & cmdseq_q[1] & ~cmdseq_q[2] & cmdseq_q[3] & cmdseq_q[4]) |
+  (cmdseq_q[0] & ~cmdseq_q[1] & ~cmdseq_q[2] & ~cmdseq_q[3] & ~cmdseq_q[4] & st_ready);
+assign cmdseq_d[3] =
+  (cmdseq_q[0] & cmdseq_q[1] & cmdseq_q[2] & cmdseq_q[3] & cmdseq_q[4] & ~req_ld_val & ~req_st_val) |
+  (~cmdseq_q[0] & ~cmdseq_q[1] & ~cmdseq_q[2] & ~cmdseq_q[3] & cmdseq_q[4] & ld_ready) |
+  (~cmdseq_q[0] & ~cmdseq_q[1] & ~cmdseq_q[2] & cmdseq_q[3] & ~cmdseq_q[4]) |
+  (~cmdseq_q[0] & ~cmdseq_q[1] & cmdseq_q[2] & ~cmdseq_q[3] & ~cmdseq_q[4]) |
+  (~cmdseq_q[0] & cmdseq_q[1] & ~cmdseq_q[2] & ~cmdseq_q[3] & cmdseq_q[4]) |
+  (~cmdseq_q[0] & cmdseq_q[1] & ~cmdseq_q[2] & cmdseq_q[3] & ~cmdseq_q[4]) |
+  (~cmdseq_q[0] & cmdseq_q[1] & ~cmdseq_q[2] & cmdseq_q[3] & cmdseq_q[4]) |
+  (cmdseq_q[0] & ~cmdseq_q[1] & ~cmdseq_q[2] & ~cmdseq_q[3] & ~cmdseq_q[4] & st_ready);
+assign cmdseq_d[4] =
+  (cmdseq_q[0] & cmdseq_q[1] & cmdseq_q[2] & cmdseq_q[3] & cmdseq_q[4] & ~req_ld_val & ~req_st_val) |
+  (cmdseq_q[0] & cmdseq_q[1] & cmdseq_q[2] & cmdseq_q[3] & cmdseq_q[4] & req_ld_val) |
+  (~cmdseq_q[0] & ~cmdseq_q[1] & ~cmdseq_q[2] & ~cmdseq_q[3] & cmdseq_q[4] & ~ld_ready) |
+  (~cmdseq_q[0] & ~cmdseq_q[1] & ~cmdseq_q[2] & cmdseq_q[3] & ~cmdseq_q[4]) |
+  (~cmdseq_q[0] & ~cmdseq_q[1] & cmdseq_q[2] & ~cmdseq_q[3] & ~cmdseq_q[4]) |
+  (~cmdseq_q[0] & cmdseq_q[1] & ~cmdseq_q[2] & ~cmdseq_q[3] & ~cmdseq_q[4]) |
+  (~cmdseq_q[0] & cmdseq_q[1] & ~cmdseq_q[2] & cmdseq_q[3] & ~cmdseq_q[4]) |
+  (~cmdseq_q[0] & cmdseq_q[1] & ~cmdseq_q[2] & cmdseq_q[3] & cmdseq_q[4]) |
+  (cmdseq_q[0] & ~cmdseq_q[1] & ~cmdseq_q[2] & ~cmdseq_q[3] & ~cmdseq_q[4] & st_ready);
+assign rld_coming =
+  (~cmdseq_q[0] & ~cmdseq_q[1] & ~cmdseq_q[2] & ~cmdseq_q[3] & cmdseq_q[4] & ld_ready) |
+  (~cmdseq_q[0] & ~cmdseq_q[1] & ~cmdseq_q[2] & cmdseq_q[3] & cmdseq_q[4] & ~req_ieq1);
+assign rld_valid =
+  (~cmdseq_q[0] & ~cmdseq_q[1] & ~cmdseq_q[2] & cmdseq_q[3] & ~cmdseq_q[4]) |
+  (~cmdseq_q[0] & ~cmdseq_q[1] & ~cmdseq_q[2] & cmdseq_q[3] & cmdseq_q[4] & ~req_ieq1) |
+  (~cmdseq_q[0] & cmdseq_q[1] & ~cmdseq_q[2] & ~cmdseq_q[3] & ~cmdseq_q[4]) |
+  (~cmdseq_q[0] & cmdseq_q[1] & ~cmdseq_q[2] & ~cmdseq_q[3] & cmdseq_q[4]);
+assign do_store =
+  (cmdseq_q[0] & ~cmdseq_q[1] & ~cmdseq_q[2] & ~cmdseq_q[3] & ~cmdseq_q[4] & st_ready);
+assign rld_done =
+  (~cmdseq_q[0] & ~cmdseq_q[1] & cmdseq_q[2] & ~cmdseq_q[3] & ~cmdseq_q[4]) |
+  (~cmdseq_q[0] & cmdseq_q[1] & ~cmdseq_q[2] & cmdseq_q[3] & cmdseq_q[4]);
+assign inc_qw =
+  (~cmdseq_q[0] & ~cmdseq_q[1] & ~cmdseq_q[2] & cmdseq_q[3] & ~cmdseq_q[4]) |
+  (~cmdseq_q[0] & ~cmdseq_q[1] & ~cmdseq_q[2] & cmdseq_q[3] & cmdseq_q[4] & ~req_ieq1) |
+  (~cmdseq_q[0] & cmdseq_q[1] & ~cmdseq_q[2] & ~cmdseq_q[3] & ~cmdseq_q[4]) |
+  (~cmdseq_q[0] & cmdseq_q[1] & ~cmdseq_q[2] & ~cmdseq_q[3] & cmdseq_q[4]);
+assign cmdseq_idle =
+  (cmdseq_q[0] & cmdseq_q[1] & cmdseq_q[2] & cmdseq_q[3] & cmdseq_q[4]);
+//vtable cmdseq
+
+generate if (MEM_MODE == 2) begin
+//vtable wbseq
+assign wbseq_d[0] =
+  (wbseq_q[0] & wbseq_q[1] & wbseq_q[2] & wbseq_q[3] & ~req_ld_val & ~req_st_val) |
+  (wbseq_q[0] & wbseq_q[1] & wbseq_q[2] & wbseq_q[3] & ~req_ld_val & req_st_val & req_st_we[0]) |
+  (wbseq_q[0] & wbseq_q[1] & wbseq_q[2] & wbseq_q[3] & ~req_ld_val & req_st_val & ~req_st_we[0] & req_st_we[1]) |
+  (wbseq_q[0] & wbseq_q[1] & wbseq_q[2] & wbseq_q[3] & ~req_ld_val & req_st_val & ~req_st_we[0] & ~req_st_we[1] & req_st_we[2]) |
+  (wbseq_q[0] & wbseq_q[1] & wbseq_q[2] & wbseq_q[3] & ~req_ld_val & req_st_val & ~req_st_we[0] & ~req_st_we[1] & ~req_st_we[2] & req_st_we[3]) |
+  (wbseq_q[0] & wbseq_q[1] & wbseq_q[2] & wbseq_q[3] & ~req_ld_val & req_st_val & ~req_st_we[0] & ~req_st_we[1] & ~req_st_we[2] & ~req_st_we[3]) |
+  (~wbseq_q[0] & wbseq_q[1] & wbseq_q[2] & wbseq_q[3] & req_ieq1 & wb_ack) |
+  (~wbseq_q[0] & wbseq_q[1] & wbseq_q[2] & wbseq_q[3] & ~req_ieq1 & qw_q[0] & qw_q[1] & wb_ack) |
+  (wbseq_q[0] & ~wbseq_q[1] & ~wbseq_q[2] & ~wbseq_q[3] & ~wb_ack) |
+  (wbseq_q[0] & ~wbseq_q[1] & ~wbseq_q[2] & ~wbseq_q[3] & req_st_we[1] & wb_ack) |
+  (wbseq_q[0] & ~wbseq_q[1] & ~wbseq_q[2] & ~wbseq_q[3] & ~req_st_we[1] & req_st_we[2] & wb_ack) |
+  (wbseq_q[0] & ~wbseq_q[1] & ~wbseq_q[2] & ~wbseq_q[3] & ~req_st_we[1] & ~req_st_we[2] & req_st_we[3] & wb_ack) |
+  (wbseq_q[0] & ~wbseq_q[1] & ~wbseq_q[2] & ~wbseq_q[3] & ~req_st_we[1] & ~req_st_we[2] & ~req_st_we[3] & wb_ack) |
+  (wbseq_q[0] & ~wbseq_q[1] & ~wbseq_q[2] & wbseq_q[3] & ~wb_ack) |
+  (wbseq_q[0] & ~wbseq_q[1] & ~wbseq_q[2] & wbseq_q[3] & req_st_we[2] & wb_ack) |
+  (wbseq_q[0] & ~wbseq_q[1] & ~wbseq_q[2] & wbseq_q[3] & ~req_st_we[2] & req_st_we[3] & wb_ack) |
+  (wbseq_q[0] & ~wbseq_q[1] & ~wbseq_q[2] & wbseq_q[3] & ~req_st_we[2] & ~req_st_we[3] & wb_ack) |
+  (wbseq_q[0] & ~wbseq_q[1] & wbseq_q[2] & ~wbseq_q[3] & ~wb_ack) |
+  (wbseq_q[0] & ~wbseq_q[1] & wbseq_q[2] & ~wbseq_q[3] & req_st_we[3] & wb_ack) |
+  (wbseq_q[0] & ~wbseq_q[1] & wbseq_q[2] & ~wbseq_q[3] & ~req_st_we[3] & wb_ack) |
+  (wbseq_q[0] & ~wbseq_q[1] & wbseq_q[2] & wbseq_q[3] & ~wb_ack) |
+  (wbseq_q[0] & ~wbseq_q[1] & wbseq_q[2] & wbseq_q[3] & wb_ack) |
+  (wbseq_q[0] & wbseq_q[1] & wbseq_q[2] & ~wbseq_q[3] & ~cmdseq_idle) |
+  (wbseq_q[0] & wbseq_q[1] & wbseq_q[2] & ~wbseq_q[3] & cmdseq_idle);
+assign wbseq_d[1] =
+  (wbseq_q[0] & wbseq_q[1] & wbseq_q[2] & wbseq_q[3] & ~req_ld_val & ~req_st_val) |
+  (wbseq_q[0] & wbseq_q[1] & wbseq_q[2] & wbseq_q[3] & req_ld_val & ~req_st_val) |
+  (wbseq_q[0] & wbseq_q[1] & wbseq_q[2] & wbseq_q[3] & ~req_ld_val & req_st_val & ~req_st_we[0] & ~req_st_we[1] & ~req_st_we[2] & ~req_st_we[3]) |
+  (~wbseq_q[0] & wbseq_q[1] & ~wbseq_q[2] & ~wbseq_q[3] & ~wb_ack) |
+  (~wbseq_q[0] & wbseq_q[1] & ~wbseq_q[2] & ~wbseq_q[3] & wb_ack) |
+  (~wbseq_q[0] & wbseq_q[1] & ~wbseq_q[2] & wbseq_q[3] & ~wb_ack) |
+  (~wbseq_q[0] & wbseq_q[1] & ~wbseq_q[2] & wbseq_q[3] & wb_ack) |
+  (~wbseq_q[0] & wbseq_q[1] & wbseq_q[2] & ~wbseq_q[3] & ~wb_ack) |
+  (~wbseq_q[0] & wbseq_q[1] & wbseq_q[2] & ~wbseq_q[3] & wb_ack) |
+  (~wbseq_q[0] & wbseq_q[1] & wbseq_q[2] & wbseq_q[3] & ~wb_ack) |
+  (~wbseq_q[0] & wbseq_q[1] & wbseq_q[2] & wbseq_q[3] & ~req_ieq1 & ~qw_q[0] & wb_ack) |
+  (~wbseq_q[0] & wbseq_q[1] & wbseq_q[2] & wbseq_q[3] & ~req_ieq1 & ~qw_q[1] & wb_ack) |
+  (~wbseq_q[0] & wbseq_q[1] & wbseq_q[2] & wbseq_q[3] & req_ieq1 & wb_ack) |
+  (~wbseq_q[0] & wbseq_q[1] & wbseq_q[2] & wbseq_q[3] & ~req_ieq1 & qw_q[0] & qw_q[1] & wb_ack) |
+  (wbseq_q[0] & ~wbseq_q[1] & ~wbseq_q[2] & ~wbseq_q[3] & ~req_st_we[1] & ~req_st_we[2] & ~req_st_we[3] & wb_ack) |
+  (wbseq_q[0] & ~wbseq_q[1] & ~wbseq_q[2] & wbseq_q[3] & ~req_st_we[2] & ~req_st_we[3] & wb_ack) |
+  (wbseq_q[0] & ~wbseq_q[1] & wbseq_q[2] & ~wbseq_q[3] & ~req_st_we[3] & wb_ack) |
+  (wbseq_q[0] & ~wbseq_q[1] & wbseq_q[2] & wbseq_q[3] & wb_ack) |
+  (wbseq_q[0] & wbseq_q[1] & wbseq_q[2] & ~wbseq_q[3] & ~cmdseq_idle) |
+  (wbseq_q[0] & wbseq_q[1] & wbseq_q[2] & ~wbseq_q[3] & cmdseq_idle);
+assign wbseq_d[2] =
+  (wbseq_q[0] & wbseq_q[1] & wbseq_q[2] & wbseq_q[3] & ~req_ld_val & ~req_st_val) |
+  (wbseq_q[0] & wbseq_q[1] & wbseq_q[2] & wbseq_q[3] & ~req_ld_val & req_st_val & ~req_st_we[0] & ~req_st_we[1] & req_st_we[2]) |
+  (wbseq_q[0] & wbseq_q[1] & wbseq_q[2] & wbseq_q[3] & ~req_ld_val & req_st_val & ~req_st_we[0] & ~req_st_we[1] & ~req_st_we[2] & req_st_we[3]) |
+  (wbseq_q[0] & wbseq_q[1] & wbseq_q[2] & wbseq_q[3] & ~req_ld_val & req_st_val & ~req_st_we[0] & ~req_st_we[1] & ~req_st_we[2] & ~req_st_we[3]) |
+  (~wbseq_q[0] & wbseq_q[1] & ~wbseq_q[2] & wbseq_q[3] & wb_ack) |
+  (~wbseq_q[0] & wbseq_q[1] & wbseq_q[2] & ~wbseq_q[3] & ~wb_ack) |
+  (~wbseq_q[0] & wbseq_q[1] & wbseq_q[2] & ~wbseq_q[3] & wb_ack) |
+  (~wbseq_q[0] & wbseq_q[1] & wbseq_q[2] & wbseq_q[3] & ~wb_ack) |
+  (~wbseq_q[0] & wbseq_q[1] & wbseq_q[2] & wbseq_q[3] & req_ieq1 & wb_ack) |
+  (~wbseq_q[0] & wbseq_q[1] & wbseq_q[2] & wbseq_q[3] & ~req_ieq1 & qw_q[0] & qw_q[1] & wb_ack) |
+  (wbseq_q[0] & ~wbseq_q[1] & ~wbseq_q[2] & ~wbseq_q[3] & ~req_st_we[1] & req_st_we[2] & wb_ack) |
+  (wbseq_q[0] & ~wbseq_q[1] & ~wbseq_q[2] & ~wbseq_q[3] & ~req_st_we[1] & ~req_st_we[2] & req_st_we[3] & wb_ack) |
+  (wbseq_q[0] & ~wbseq_q[1] & ~wbseq_q[2] & ~wbseq_q[3] & ~req_st_we[1] & ~req_st_we[2] & ~req_st_we[3] & wb_ack) |
+  (wbseq_q[0] & ~wbseq_q[1] & ~wbseq_q[2] & wbseq_q[3] & req_st_we[2] & wb_ack) |
+  (wbseq_q[0] & ~wbseq_q[1] & ~wbseq_q[2] & wbseq_q[3] & ~req_st_we[2] & req_st_we[3] & wb_ack) |
+  (wbseq_q[0] & ~wbseq_q[1] & ~wbseq_q[2] & wbseq_q[3] & ~req_st_we[2] & ~req_st_we[3] & wb_ack) |
+  (wbseq_q[0] & ~wbseq_q[1] & wbseq_q[2] & ~wbseq_q[3] & ~wb_ack) |
+  (wbseq_q[0] & ~wbseq_q[1] & wbseq_q[2] & ~wbseq_q[3] & req_st_we[3] & wb_ack) |
+  (wbseq_q[0] & ~wbseq_q[1] & wbseq_q[2] & ~wbseq_q[3] & ~req_st_we[3] & wb_ack) |
+  (wbseq_q[0] & ~wbseq_q[1] & wbseq_q[2] & wbseq_q[3] & ~wb_ack) |
+  (wbseq_q[0] & ~wbseq_q[1] & wbseq_q[2] & wbseq_q[3] & wb_ack) |
+  (wbseq_q[0] & wbseq_q[1] & wbseq_q[2] & ~wbseq_q[3] & ~cmdseq_idle) |
+  (wbseq_q[0] & wbseq_q[1] & wbseq_q[2] & ~wbseq_q[3] & cmdseq_idle);
+assign wbseq_d[3] =
+  (wbseq_q[0] & wbseq_q[1] & wbseq_q[2] & wbseq_q[3] & ~req_ld_val & ~req_st_val) |
+  (wbseq_q[0] & wbseq_q[1] & wbseq_q[2] & wbseq_q[3] & ~req_ld_val & req_st_val & ~req_st_we[0] & req_st_we[1]) |
+  (wbseq_q[0] & wbseq_q[1] & wbseq_q[2] & wbseq_q[3] & ~req_ld_val & req_st_val & ~req_st_we[0] & ~req_st_we[1] & ~req_st_we[2] & req_st_we[3]) |
+  (wbseq_q[0] & wbseq_q[1] & wbseq_q[2] & wbseq_q[3] & ~req_ld_val & req_st_val & ~req_st_we[0] & ~req_st_we[1] & ~req_st_we[2] & ~req_st_we[3]) |
+  (~wbseq_q[0] & wbseq_q[1] & ~wbseq_q[2] & ~wbseq_q[3] & wb_ack) |
+  (~wbseq_q[0] & wbseq_q[1] & ~wbseq_q[2] & wbseq_q[3] & ~wb_ack) |
+  (~wbseq_q[0] & wbseq_q[1] & wbseq_q[2] & ~wbseq_q[3] & wb_ack) |
+  (~wbseq_q[0] & wbseq_q[1] & wbseq_q[2] & wbseq_q[3] & ~wb_ack) |
+  (wbseq_q[0] & ~wbseq_q[1] & ~wbseq_q[2] & ~wbseq_q[3] & req_st_we[1] & wb_ack) |
+  (wbseq_q[0] & ~wbseq_q[1] & ~wbseq_q[2] & ~wbseq_q[3] & ~req_st_we[1] & ~req_st_we[2] & req_st_we[3] & wb_ack) |
+  (wbseq_q[0] & ~wbseq_q[1] & ~wbseq_q[2] & wbseq_q[3] & ~wb_ack) |
+  (wbseq_q[0] & ~wbseq_q[1] & ~wbseq_q[2] & wbseq_q[3] & ~req_st_we[2] & req_st_we[3] & wb_ack) |
+  (wbseq_q[0] & ~wbseq_q[1] & wbseq_q[2] & ~wbseq_q[3] & req_st_we[3] & wb_ack) |
+  (wbseq_q[0] & ~wbseq_q[1] & wbseq_q[2] & wbseq_q[3] & ~wb_ack) |
+  (wbseq_q[0] & wbseq_q[1] & wbseq_q[2] & ~wbseq_q[3] & cmdseq_idle);
+assign wb_stb =
+  (~wbseq_q[0] & wbseq_q[1] & ~wbseq_q[2] & ~wbseq_q[3] & ~wb_ack) |
+  (~wbseq_q[0] & wbseq_q[1] & ~wbseq_q[2] & ~wbseq_q[3] & wb_ack) |
+  (~wbseq_q[0] & wbseq_q[1] & ~wbseq_q[2] & wbseq_q[3] & ~wb_ack) |
+  (~wbseq_q[0] & wbseq_q[1] & ~wbseq_q[2] & wbseq_q[3] & wb_ack) |
+  (~wbseq_q[0] & wbseq_q[1] & wbseq_q[2] & ~wbseq_q[3] & ~wb_ack) |
+  (~wbseq_q[0] & wbseq_q[1] & wbseq_q[2] & ~wbseq_q[3] & wb_ack) |
+  (~wbseq_q[0] & wbseq_q[1] & wbseq_q[2] & wbseq_q[3] & ~wb_ack) |
+  (~wbseq_q[0] & wbseq_q[1] & wbseq_q[2] & wbseq_q[3] & ~req_ieq1 & ~qw_q[0] & wb_ack) |
+  (~wbseq_q[0] & wbseq_q[1] & wbseq_q[2] & wbseq_q[3] & ~req_ieq1 & ~qw_q[1] & wb_ack) |
+  (~wbseq_q[0] & wbseq_q[1] & wbseq_q[2] & wbseq_q[3] & req_ieq1 & wb_ack) |
+  (~wbseq_q[0] & wbseq_q[1] & wbseq_q[2] & wbseq_q[3] & ~req_ieq1 & qw_q[0] & qw_q[1] & wb_ack) |
+  (wbseq_q[0] & ~wbseq_q[1] & ~wbseq_q[2] & ~wbseq_q[3] & ~wb_ack) |
+  (wbseq_q[0] & ~wbseq_q[1] & ~wbseq_q[2] & ~wbseq_q[3] & req_st_we[1] & wb_ack) |
+  (wbseq_q[0] & ~wbseq_q[1] & ~wbseq_q[2] & ~wbseq_q[3] & ~req_st_we[1] & req_st_we[2] & wb_ack) |
+  (wbseq_q[0] & ~wbseq_q[1] & ~wbseq_q[2] & ~wbseq_q[3] & ~req_st_we[1] & ~req_st_we[2] & req_st_we[3] & wb_ack) |
+  (wbseq_q[0] & ~wbseq_q[1] & ~wbseq_q[2] & ~wbseq_q[3] & ~req_st_we[1] & ~req_st_we[2] & ~req_st_we[3] & wb_ack) |
+  (wbseq_q[0] & ~wbseq_q[1] & ~wbseq_q[2] & wbseq_q[3] & ~wb_ack) |
+  (wbseq_q[0] & ~wbseq_q[1] & ~wbseq_q[2] & wbseq_q[3] & req_st_we[2] & wb_ack) |
+  (wbseq_q[0] & ~wbseq_q[1] & ~wbseq_q[2] & wbseq_q[3] & ~req_st_we[2] & req_st_we[3] & wb_ack) |
+  (wbseq_q[0] & ~wbseq_q[1] & ~wbseq_q[2] & wbseq_q[3] & ~req_st_we[2] & ~req_st_we[3] & wb_ack) |
+  (wbseq_q[0] & ~wbseq_q[1] & wbseq_q[2] & ~wbseq_q[3] & ~wb_ack) |
+  (wbseq_q[0] & ~wbseq_q[1] & wbseq_q[2] & ~wbseq_q[3] & req_st_we[3] & wb_ack) |
+  (wbseq_q[0] & ~wbseq_q[1] & wbseq_q[2] & ~wbseq_q[3] & ~req_st_we[3] & wb_ack) |
+  (wbseq_q[0] & ~wbseq_q[1] & wbseq_q[2] & wbseq_q[3] & ~wb_ack) |
+  (wbseq_q[0] & ~wbseq_q[1] & wbseq_q[2] & wbseq_q[3] & wb_ack);
+assign wb_cyc =
+  (~wbseq_q[0] & wbseq_q[1] & ~wbseq_q[2] & ~wbseq_q[3] & ~wb_ack) |
+  (~wbseq_q[0] & wbseq_q[1] & ~wbseq_q[2] & ~wbseq_q[3] & wb_ack) |
+  (~wbseq_q[0] & wbseq_q[1] & ~wbseq_q[2] & wbseq_q[3] & ~wb_ack) |
+  (~wbseq_q[0] & wbseq_q[1] & ~wbseq_q[2] & wbseq_q[3] & wb_ack) |
+  (~wbseq_q[0] & wbseq_q[1] & wbseq_q[2] & ~wbseq_q[3] & ~wb_ack) |
+  (~wbseq_q[0] & wbseq_q[1] & wbseq_q[2] & ~wbseq_q[3] & wb_ack) |
+  (~wbseq_q[0] & wbseq_q[1] & wbseq_q[2] & wbseq_q[3] & ~wb_ack) |
+  (~wbseq_q[0] & wbseq_q[1] & wbseq_q[2] & wbseq_q[3] & ~req_ieq1 & ~qw_q[0] & wb_ack) |
+  (~wbseq_q[0] & wbseq_q[1] & wbseq_q[2] & wbseq_q[3] & ~req_ieq1 & ~qw_q[1] & wb_ack) |
+  (~wbseq_q[0] & wbseq_q[1] & wbseq_q[2] & wbseq_q[3] & req_ieq1 & wb_ack) |
+  (~wbseq_q[0] & wbseq_q[1] & wbseq_q[2] & wbseq_q[3] & ~req_ieq1 & qw_q[0] & qw_q[1] & wb_ack) |
+  (wbseq_q[0] & ~wbseq_q[1] & ~wbseq_q[2] & ~wbseq_q[3] & ~wb_ack) |
+  (wbseq_q[0] & ~wbseq_q[1] & ~wbseq_q[2] & ~wbseq_q[3] & req_st_we[1] & wb_ack) |
+  (wbseq_q[0] & ~wbseq_q[1] & ~wbseq_q[2] & ~wbseq_q[3] & ~req_st_we[1] & req_st_we[2] & wb_ack) |
+  (wbseq_q[0] & ~wbseq_q[1] & ~wbseq_q[2] & ~wbseq_q[3] & ~req_st_we[1] & ~req_st_we[2] & req_st_we[3] & wb_ack) |
+  (wbseq_q[0] & ~wbseq_q[1] & ~wbseq_q[2] & ~wbseq_q[3] & ~req_st_we[1] & ~req_st_we[2] & ~req_st_we[3] & wb_ack) |
+  (wbseq_q[0] & ~wbseq_q[1] & ~wbseq_q[2] & wbseq_q[3] & ~wb_ack) |
+  (wbseq_q[0] & ~wbseq_q[1] & ~wbseq_q[2] & wbseq_q[3] & req_st_we[2] & wb_ack) |
+  (wbseq_q[0] & ~wbseq_q[1] & ~wbseq_q[2] & wbseq_q[3] & ~req_st_we[2] & req_st_we[3] & wb_ack) |
+  (wbseq_q[0] & ~wbseq_q[1] & ~wbseq_q[2] & wbseq_q[3] & ~req_st_we[2] & ~req_st_we[3] & wb_ack) |
+  (wbseq_q[0] & ~wbseq_q[1] & wbseq_q[2] & ~wbseq_q[3] & ~wb_ack) |
+  (wbseq_q[0] & ~wbseq_q[1] & wbseq_q[2] & ~wbseq_q[3] & req_st_we[3] & wb_ack) |
+  (wbseq_q[0] & ~wbseq_q[1] & wbseq_q[2] & ~wbseq_q[3] & ~req_st_we[3] & wb_ack) |
+  (wbseq_q[0] & ~wbseq_q[1] & wbseq_q[2] & wbseq_q[3] & ~wb_ack) |
+  (wbseq_q[0] & ~wbseq_q[1] & wbseq_q[2] & wbseq_q[3] & wb_ack);
+assign wb_we =
+  (wbseq_q[0] & ~wbseq_q[1] & ~wbseq_q[2] & ~wbseq_q[3] & ~wb_ack) |
+  (wbseq_q[0] & ~wbseq_q[1] & ~wbseq_q[2] & ~wbseq_q[3] & req_st_we[1] & wb_ack) |
+  (wbseq_q[0] & ~wbseq_q[1] & ~wbseq_q[2] & ~wbseq_q[3] & ~req_st_we[1] & req_st_we[2] & wb_ack) |
+  (wbseq_q[0] & ~wbseq_q[1] & ~wbseq_q[2] & ~wbseq_q[3] & ~req_st_we[1] & ~req_st_we[2] & req_st_we[3] & wb_ack) |
+  (wbseq_q[0] & ~wbseq_q[1] & ~wbseq_q[2] & ~wbseq_q[3] & ~req_st_we[1] & ~req_st_we[2] & ~req_st_we[3] & wb_ack) |
+  (wbseq_q[0] & ~wbseq_q[1] & ~wbseq_q[2] & wbseq_q[3] & ~wb_ack) |
+  (wbseq_q[0] & ~wbseq_q[1] & ~wbseq_q[2] & wbseq_q[3] & req_st_we[2] & wb_ack) |
+  (wbseq_q[0] & ~wbseq_q[1] & ~wbseq_q[2] & wbseq_q[3] & ~req_st_we[2] & req_st_we[3] & wb_ack) |
+  (wbseq_q[0] & ~wbseq_q[1] & ~wbseq_q[2] & wbseq_q[3] & ~req_st_we[2] & ~req_st_we[3] & wb_ack) |
+  (wbseq_q[0] & ~wbseq_q[1] & wbseq_q[2] & ~wbseq_q[3] & ~wb_ack) |
+  (wbseq_q[0] & ~wbseq_q[1] & wbseq_q[2] & ~wbseq_q[3] & req_st_we[3] & wb_ack) |
+  (wbseq_q[0] & ~wbseq_q[1] & wbseq_q[2] & ~wbseq_q[3] & ~req_st_we[3] & wb_ack) |
+  (wbseq_q[0] & ~wbseq_q[1] & wbseq_q[2] & wbseq_q[3] & ~wb_ack) |
+  (wbseq_q[0] & ~wbseq_q[1] & wbseq_q[2] & wbseq_q[3] & wb_ack);
+assign dat_sel[0] =
+  (~wbseq_q[0] & wbseq_q[1] & wbseq_q[2] & ~wbseq_q[3] & ~wb_ack) |
+  (~wbseq_q[0] & wbseq_q[1] & wbseq_q[2] & ~wbseq_q[3] & wb_ack) |
+  (~wbseq_q[0] & wbseq_q[1] & wbseq_q[2] & wbseq_q[3] & ~wb_ack) |
+  (~wbseq_q[0] & wbseq_q[1] & wbseq_q[2] & wbseq_q[3] & ~req_ieq1 & ~qw_q[0] & wb_ack) |
+  (~wbseq_q[0] & wbseq_q[1] & wbseq_q[2] & wbseq_q[3] & ~req_ieq1 & ~qw_q[1] & wb_ack) |
+  (~wbseq_q[0] & wbseq_q[1] & wbseq_q[2] & wbseq_q[3] & req_ieq1 & wb_ack) |
+  (~wbseq_q[0] & wbseq_q[1] & wbseq_q[2] & wbseq_q[3] & ~req_ieq1 & qw_q[0] & qw_q[1] & wb_ack) |
+  (wbseq_q[0] & ~wbseq_q[1] & wbseq_q[2] & ~wbseq_q[3] & ~wb_ack) |
+  (wbseq_q[0] & ~wbseq_q[1] & wbseq_q[2] & ~wbseq_q[3] & req_st_we[3] & wb_ack) |
+  (wbseq_q[0] & ~wbseq_q[1] & wbseq_q[2] & ~wbseq_q[3] & ~req_st_we[3] & wb_ack) |
+  (wbseq_q[0] & ~wbseq_q[1] & wbseq_q[2] & wbseq_q[3] & ~wb_ack) |
+  (wbseq_q[0] & ~wbseq_q[1] & wbseq_q[2] & wbseq_q[3] & wb_ack);
+assign dat_sel[1] =
+  (~wbseq_q[0] & wbseq_q[1] & ~wbseq_q[2] & wbseq_q[3] & ~wb_ack) |
+  (~wbseq_q[0] & wbseq_q[1] & ~wbseq_q[2] & wbseq_q[3] & wb_ack) |
+  (~wbseq_q[0] & wbseq_q[1] & wbseq_q[2] & wbseq_q[3] & ~wb_ack) |
+  (~wbseq_q[0] & wbseq_q[1] & wbseq_q[2] & wbseq_q[3] & ~req_ieq1 & ~qw_q[0] & wb_ack) |
+  (~wbseq_q[0] & wbseq_q[1] & wbseq_q[2] & wbseq_q[3] & ~req_ieq1 & ~qw_q[1] & wb_ack) |
+  (~wbseq_q[0] & wbseq_q[1] & wbseq_q[2] & wbseq_q[3] & req_ieq1 & wb_ack) |
+  (~wbseq_q[0] & wbseq_q[1] & wbseq_q[2] & wbseq_q[3] & ~req_ieq1 & qw_q[0] & qw_q[1] & wb_ack) |
+  (wbseq_q[0] & ~wbseq_q[1] & ~wbseq_q[2] & wbseq_q[3] & ~wb_ack) |
+  (wbseq_q[0] & ~wbseq_q[1] & ~wbseq_q[2] & wbseq_q[3] & req_st_we[2] & wb_ack) |
+  (wbseq_q[0] & ~wbseq_q[1] & ~wbseq_q[2] & wbseq_q[3] & ~req_st_we[2] & req_st_we[3] & wb_ack) |
+  (wbseq_q[0] & ~wbseq_q[1] & ~wbseq_q[2] & wbseq_q[3] & ~req_st_we[2] & ~req_st_we[3] & wb_ack) |
+  (wbseq_q[0] & ~wbseq_q[1] & wbseq_q[2] & wbseq_q[3] & ~wb_ack) |
+  (wbseq_q[0] & ~wbseq_q[1] & wbseq_q[2] & wbseq_q[3] & wb_ack);
+assign ld_ready =
+  (~wbseq_q[0] & wbseq_q[1] & wbseq_q[2] & wbseq_q[3] & req_ieq1 & wb_ack) |
+  (~wbseq_q[0] & wbseq_q[1] & wbseq_q[2] & wbseq_q[3] & ~req_ieq1 & qw_q[0] & qw_q[1] & wb_ack);
+assign st_ready =
+  (wbseq_q[0] & wbseq_q[1] & wbseq_q[2] & wbseq_q[3] & ~req_ld_val & req_st_val & ~req_st_we[0] & ~req_st_we[1] & ~req_st_we[2] & ~req_st_we[3]) |
+  (wbseq_q[0] & ~wbseq_q[1] & ~wbseq_q[2] & ~wbseq_q[3] & ~req_st_we[1] & ~req_st_we[2] & ~req_st_we[3] & wb_ack) |
+  (wbseq_q[0] & ~wbseq_q[1] & ~wbseq_q[2] & wbseq_q[3] & ~req_st_we[2] & ~req_st_we[3] & wb_ack) |
+  (wbseq_q[0] & ~wbseq_q[1] & wbseq_q[2] & ~wbseq_q[3] & ~req_st_we[3] & wb_ack) |
+  (wbseq_q[0] & ~wbseq_q[1] & wbseq_q[2] & wbseq_q[3] & wb_ack);
+assign wb_inc_qw =
+  (~wbseq_q[0] & wbseq_q[1] & wbseq_q[2] & wbseq_q[3] & ~req_ieq1 & ~qw_q[0] & wb_ack) |
+  (~wbseq_q[0] & wbseq_q[1] & wbseq_q[2] & wbseq_q[3] & ~req_ieq1 & ~qw_q[1] & wb_ack);
+//vtable wbseq
+end
+endgenerate
+
+endmodule

dev/verilog/a2node_wb/a2owb.v

@@ -0,0 +1,515 @@
+// add ties for all the test junk, etc. so they can be optimized out of model
+
+// © IBM Corp. 2022
+// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+// the terms below; you may not use the files in this repository except in
+// compliance with the License as modified.
+// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+//
+// Modified Terms:
+//
+//    1) For the purpose of the patent license granted to you in Section 3 of the
+//    License, the "Work" hereby includes implementations of the work of authorship
+//    in physical form.
+//
+//    2) Notwithstanding any terms to the contrary in the License, any licenses
+//    necessary for implementation of the Work that are available from OpenPOWER
+//    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+//    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+//    of the EULA.
+//
+// Unless required by applicable law or agreed to in writing, the reference design
+// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+// for the specific language governing permissions and limitations under the License.
+//
+// Additional rights, including the ability to physically implement a softcore that
+// is compliant with the required sections of the Power ISA Specification, are
+// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+// obtained (along with the Power ISA) here: https://openpowerfoundation.org.
+
+`include "tri_a2o.vh"
+
+`timescale 1ns/1ps
+
+module a2owb (
+
+	 input  [0:`NCLK_WIDTH-1]                               nclk,
+	 input                                                  scan_in,
+	 output                                                 scan_out,
+
+/*
+	 // Pervasive clock control
+	 input                                                  an_ac_rtim_sl_thold_8,
+	 input                                                  an_ac_func_sl_thold_8,
+	 input                                                  an_ac_func_nsl_thold_8,
+	 input                                                  an_ac_ary_nsl_thold_8,
+	 input                                                  an_ac_sg_8,
+	 input                                                  an_ac_fce_8,
+	 input  [0:7]                                           an_ac_abst_scan_in,
+
+
+	 //SCOM Satellite
+	 input  [0:3]                                           an_ac_scom_sat_id,
+	 input                                                  an_ac_scom_dch,
+	 input                                                  an_ac_scom_cch,
+*/
+	 output                                                 ac_an_scom_dch,
+	 output                                                 ac_an_scom_cch,
+
+	 // FIR and Error Signals
+	 output [0:`THREADS-1]                                  ac_an_special_attn,
+	 output [0:2]                                           ac_an_checkstop,
+	 output [0:2]                                           ac_an_local_checkstop,
+	 output [0:2]                                           ac_an_recov_err,
+	 output                                                 ac_an_trace_error,
+    output                                                 ac_an_livelock_active,
+
+	 // Perfmon Event Bus
+	 output [0:4*`THREADS-1]                                ac_an_event_bus0,
+	 output [0:4*`THREADS-1]                                ac_an_event_bus1,
+
+	 // Power Management
+	 output [0:`THREADS-1]                                  ac_an_pm_thread_running,
+	 input  [0:`THREADS-1]                                  an_ac_pm_thread_stop,
+	 input  [0:`THREADS-1]                                  an_ac_pm_fetch_halt,
+
+/*
+	 // Clock, Test, and LCB Controls
+	 input                                                  an_ac_gsd_test_enable_dc,
+	 input                                                  an_ac_gsd_test_acmode_dc,
+	 input                                                  an_ac_ccflush_dc,
+	 input                                                  an_ac_ccenable_dc,
+	 input                                                  an_ac_lbist_en_dc,
+	 input                                                  an_ac_lbist_ip_dc,
+	 input                                                  an_ac_lbist_ac_mode_dc,
+	 input                                                  an_ac_scan_diag_dc,
+	 input                                                  an_ac_scan_dis_dc_b,
+
+	 //Thold input to clock control macro
+	 input  [0:8]                                           an_ac_scan_type_dc,
+*/
+
+	 // Pervasive
+	 output                                                 ac_an_reset_1_request,
+	 output                                                 ac_an_reset_2_request,
+	 output                                                 ac_an_reset_3_request,
+	 output                                                 ac_an_reset_wd_request,
+/*
+	 input                                                  an_ac_lbist_ary_wrt_thru_dc,
+*/
+	 input  [0:`THREADS-1]                                  an_ac_sleep_en,
+	 input  [0:`THREADS-1]                                  an_ac_ext_interrupt,
+	 input  [0:`THREADS-1]                                  an_ac_crit_interrupt,
+	 input  [0:`THREADS-1]                                  an_ac_perf_interrupt,
+	 input  [0:`THREADS-1]                                  an_ac_hang_pulse,
+	 input                                                  an_ac_tb_update_enable,
+	 input                                                  an_ac_tb_update_pulse,
+/*
+	 input  [0:3]                                           an_ac_chipid_dc,
+	 input  [0:7]                                           an_ac_coreid,
+*/
+	 output [0:`THREADS-1]                                  ac_an_machine_check,
+	 input                                                  an_ac_debug_stop,
+	 output [0:`THREADS-1]                                  ac_an_debug_trigger,
+	 input  [0:`THREADS-1]                                  an_ac_uncond_dbg_event,
+	 output [0:31]                                          ac_an_debug_bus,
+	 output                                                 ac_an_coretrace_first_valid,
+	 output							                             ac_an_coretrace_valid,
+	 output [0:1]						                          ac_an_coretrace_type,
+    input                                                  an_ac_flh2l2_gate,
+    input                                                  an_ac_reset_1_complete,
+    input                                                  an_ac_reset_2_complete,
+    input                                                  an_ac_reset_3_complete,
+    input                                                  an_ac_reset_wd_complete,
+    output                                                 an_ac_checkstop,
+    input  [0:`THREADS-1]                                  an_ac_external_mchk,
+    output                                                 ac_an_power_managed,
+    output                                                 ac_an_rvwinkle_mode,
+
+    // direct-attach mem
+    output [0:31]                                          mem_adr,
+    input  [0:127]                                         mem_dat,
+    output                                                 mem_wr_val,
+    output [0:15]                                          mem_wr_be,
+    output [0:127]                                         mem_wr_dat,
+
+    // wishbone
+    output                                                 wb_stb,
+    output                                                 wb_cyc,
+    output [31:0]                                          wb_adr,
+    output                                                 wb_we,
+    output [3:0]                                           wb_sel,
+    output [31:0]                                          wb_datw,
+    input                                                  wb_ack,
+    input  [31:0]                                          wb_datr
+);
+
+wire   [0:`THREADS-1]            an_ac_stcx_complete /*verilator public */;
+wire   [0:`THREADS-1]            an_ac_stcx_pass;
+wire                             an_ac_icbi_ack;
+wire   [0:1]                     an_ac_icbi_ack_thread;
+wire                             an_ac_back_inv_lbit;
+wire                             an_ac_back_inv_gs;
+wire                             an_ac_back_inv_ind;
+wire                             ac_an_back_inv_reject;
+wire                             an_ac_reld_data_vld;
+wire                             an_ac_reld_ecc_err;
+wire                             an_ac_reld_ecc_err_ue;
+wire                             an_ac_reld_data_coming;
+wire                             an_ac_reld_ditc;
+wire                             an_ac_reld_crit_qw;
+wire                             an_ac_reld_l1_dump;
+wire                             an_ac_req_ld_pop;
+wire                             an_ac_req_st_pop;
+wire                             an_ac_req_st_gather;
+wire                             ac_an_req_pwr_token;
+wire                             ac_an_req /*verilator public */;
+wire                             ac_an_req_wimg_w;
+wire                             ac_an_req_wimg_i;
+wire                             ac_an_req_wimg_m;
+wire                             ac_an_req_wimg_g;
+wire                             ac_an_req_endian;
+wire                             ac_an_st_data_pwr_token;
+wire   [64-`REAL_IFAR_WIDTH:63]  ac_an_req_ra /*verilator public */;
+wire                             an_ac_back_inv;
+wire                             an_ac_back_inv_local;
+wire   [0:4]                     an_ac_back_inv_target;
+wire   [0:7]                     an_ac_back_inv_lpar_id;
+wire   [0:7]                     ac_an_lpar_id;
+wire   [0:4]                     an_ac_reld_core_tag;
+wire   [0:127]                   an_ac_reld_data;
+wire   [0:1]                     an_ac_reld_qw;
+wire   [64-`REAL_IFAR_WIDTH:63]  an_ac_back_inv_addr;
+wire   [0:5]                     ac_an_req_ttype;
+wire   [0:2]                     ac_an_req_thread;
+wire   [0:3]                     ac_an_req_user_defined;
+wire   [0:3]                     ac_an_req_spare_ctrl_a0;
+wire   [0:4]                     ac_an_req_ld_core_tag;
+wire   [0:2]                     ac_an_req_ld_xfr_len;
+wire   [0:31]                    ac_an_st_byte_enbl;
+wire   [0:255]                   ac_an_st_data;
+wire   [0:3]                     an_ac_req_spare_ctrl_a1;
+wire   [0:`THREADS-1]            an_ac_sync_ack;
+wire   [0:`THREADS-1]            an_ac_reservation_vld;
+
+// ties
+wire                             an_ac_rtim_sl_thold_8;
+wire                             an_ac_func_sl_thold_8;
+wire                             an_ac_func_nsl_thold_8;
+wire                             an_ac_ary_nsl_thold_8;
+wire                             an_ac_sg_8;
+wire                             an_ac_fce_8;
+wire  [0:7]                      an_ac_abst_scan_in;
+wire  [0:3]                      an_ac_scom_sat_id;
+wire                             an_ac_scom_dch;
+wire                             an_ac_scom_cch;
+wire                             an_ac_gsd_test_enable_dc;
+wire                             an_ac_gsd_test_acmode_dc;
+wire                             an_ac_ccflush_dc;
+wire                             an_ac_ccenable_dc;
+wire                             an_ac_lbist_en_dc;
+wire                             an_ac_lbist_ip_dc;
+wire                             an_ac_lbist_ac_mode_dc;
+wire                             an_ac_scan_diag_dc;
+wire                             an_ac_scan_dis_dc_b;
+wire  [0:8]                      an_ac_scan_type_dc;
+wire                             an_ac_lbist_ary_wrt_thru_dc;
+wire  [0:3]                      an_ac_chipid_dc;
+wire  [0:7]                      an_ac_coreid;
+
+assign an_ac_chipid_dc = 4'h0;
+assign an_ac_coreid = 8'h0;
+
+// Pervasive clock control
+assign an_ac_rtim_sl_thold_8 = 0;
+assign an_ac_func_sl_thold_8 = 0;
+assign an_ac_func_nsl_thold_8 = 0;
+assign an_ac_ary_nsl_thold_8 = 0;
+assign an_ac_sg_8 = 0;
+assign an_ac_fce_8 = 0;
+assign an_ac_abst_scan_in = 8'h00;
+
+// SCOM
+assign an_ac_scom_sat_id = 4'h0;
+assign an_ac_scom_dch = 0;
+assign an_ac_scom_cch = 0;
+
+// Clock, Test, and LCB Controls
+assign an_ac_gsd_test_enable_dc = 0;
+assign an_ac_gsd_test_acmode_dc = 0;
+assign an_ac_ccflush_dc = 0;
+assign an_ac_ccenable_dc = 0;
+assign an_ac_lbist_en_dc = 0;
+assign an_ac_lbist_ip_dc = 0;
+assign an_ac_lbist_ac_mode_dc = 0;
+assign an_ac_scan_diag_dc = 0;
+assign an_ac_scan_dis_dc_b = 0;
+
+assign an_ac_scan_type_dc = 9'h000;
+assign an_ac_lbist_ary_wrt_thru_dc = 0;
+
+
+c c0(
+      .nclk(nclk),
+      .scan_in(scan_in),
+      .scan_out(scan_out),
+
+      .an_ac_rtim_sl_thold_8(an_ac_rtim_sl_thold_8),
+      .an_ac_func_sl_thold_8(an_ac_func_sl_thold_8),
+      .an_ac_func_nsl_thold_8(an_ac_func_nsl_thold_8),
+      .an_ac_ary_nsl_thold_8(an_ac_ary_nsl_thold_8),
+      .an_ac_sg_8(an_ac_sg_8),
+      .an_ac_fce_8(an_ac_fce_8),
+      .an_ac_abst_scan_in(an_ac_abst_scan_in),
+
+      .an_ac_stcx_complete(an_ac_stcx_complete[0]),
+      .an_ac_stcx_pass(an_ac_stcx_pass[0]),
+      .an_ac_reservation_vld(an_ac_reservation_vld[0]),
+
+      .an_ac_icbi_ack(an_ac_icbi_ack),
+      .an_ac_icbi_ack_thread(an_ac_icbi_ack_thread),
+      .an_ac_sync_ack(an_ac_sync_ack[0]),
+
+      .an_ac_back_inv(an_ac_back_inv),
+      .an_ac_back_inv_addr(an_ac_back_inv_addr),
+      .an_ac_back_inv_target(an_ac_back_inv_target),
+      .an_ac_back_inv_local(an_ac_back_inv_local),
+      .an_ac_back_inv_lbit(an_ac_back_inv_lbit),
+      .an_ac_back_inv_gs(an_ac_back_inv_gs),
+      .an_ac_back_inv_ind(an_ac_back_inv_ind),
+      .an_ac_back_inv_lpar_id(an_ac_back_inv_lpar_id),
+      .ac_an_back_inv_reject(ac_an_back_inv_reject),
+      .ac_an_lpar_id(ac_an_lpar_id),
+
+      .an_ac_reld_data_vld(an_ac_reld_data_vld),
+      .an_ac_reld_core_tag(an_ac_reld_core_tag),
+      .an_ac_reld_data(an_ac_reld_data),
+      .an_ac_reld_qw(an_ac_reld_qw),
+      .an_ac_reld_ecc_err(an_ac_reld_ecc_err),
+      .an_ac_reld_ecc_err_ue(an_ac_reld_ecc_err_ue),
+      .an_ac_reld_data_coming(an_ac_reld_data_coming),
+      .an_ac_reld_ditc(an_ac_reld_ditc),
+      .an_ac_reld_crit_qw(an_ac_reld_crit_qw),
+      .an_ac_reld_l1_dump(an_ac_reld_l1_dump),
+      .an_ac_req_spare_ctrl_a1(an_ac_req_spare_ctrl_a1),
+
+      .an_ac_flh2l2_gate(an_ac_flh2l2_gate),
+      .an_ac_req_ld_pop(an_ac_req_ld_pop),
+      .an_ac_req_st_pop(an_ac_req_st_pop),
+      .an_ac_req_st_gather(an_ac_req_st_gather),
+      .an_ac_pm_fetch_halt(an_ac_pm_fetch_halt),
+
+      .an_ac_scom_sat_id(an_ac_scom_sat_id),
+      .an_ac_scom_dch(an_ac_scom_dch),
+      .an_ac_scom_cch(an_ac_scom_cch),
+      .ac_an_scom_dch(ac_an_scom_dch),
+      .ac_an_scom_cch(ac_an_scom_cch),
+
+      .ac_an_special_attn(ac_an_special_attn),
+      .ac_an_checkstop(ac_an_checkstop),
+      .ac_an_local_checkstop(ac_an_local_checkstop),
+      .ac_an_recov_err(ac_an_recov_err),
+      .ac_an_trace_error(ac_an_trace_error),
+      .ac_an_livelock_active(ac_an_livelock_active),
+      .an_ac_checkstop(an_ac_checkstop),
+      .an_ac_external_mchk(an_ac_external_mchk),
+
+      .ac_an_event_bus0(ac_an_event_bus0),
+
+      .an_ac_reset_1_complete(an_ac_reset_1_complete),
+      .an_ac_reset_2_complete(an_ac_reset_2_complete),
+      .an_ac_reset_3_complete(an_ac_reset_3_complete),
+      .an_ac_reset_wd_complete(an_ac_reset_wd_complete),
+
+      .ac_an_pm_thread_running(ac_an_pm_thread_running),
+      .an_ac_pm_thread_stop(an_ac_pm_thread_stop),
+      .ac_an_power_managed(ac_an_power_managed),
+      .ac_an_rvwinkle_mode(ac_an_rvwinkle_mode),
+
+      .an_ac_gsd_test_enable_dc(an_ac_gsd_test_enable_dc),
+      .an_ac_gsd_test_acmode_dc(an_ac_gsd_test_acmode_dc),
+      .an_ac_ccflush_dc(an_ac_ccflush_dc),
+      .an_ac_ccenable_dc(an_ac_ccenable_dc),
+      .an_ac_lbist_en_dc(an_ac_lbist_en_dc),
+      .an_ac_lbist_ip_dc(an_ac_lbist_ip_dc),
+      .an_ac_lbist_ac_mode_dc(an_ac_lbist_ac_mode_dc),
+      .an_ac_scan_diag_dc(an_ac_scan_diag_dc),
+      .an_ac_scan_dis_dc_b(an_ac_scan_dis_dc_b),
+      .an_ac_scan_type_dc(an_ac_scan_type_dc),
+      .ac_an_reset_1_request(ac_an_reset_1_request),
+      .ac_an_reset_2_request(ac_an_reset_2_request),
+      .ac_an_reset_3_request(ac_an_reset_3_request),
+      .ac_an_reset_wd_request(ac_an_reset_wd_request),
+      .an_ac_lbist_ary_wrt_thru_dc(an_ac_lbist_ary_wrt_thru_dc),
+      .an_ac_sleep_en(an_ac_sleep_en),
+      .an_ac_ext_interrupt(an_ac_ext_interrupt),
+      .an_ac_crit_interrupt(an_ac_crit_interrupt),
+      .an_ac_perf_interrupt(an_ac_perf_interrupt),
+      .an_ac_hang_pulse(an_ac_hang_pulse),
+      .an_ac_tb_update_enable(an_ac_tb_update_enable),
+      .an_ac_tb_update_pulse(an_ac_tb_update_pulse),
+      .an_ac_chipid_dc(an_ac_chipid_dc),
+      .an_ac_coreid(an_ac_coreid),
+      .ac_an_machine_check(ac_an_machine_check),
+      .an_ac_debug_stop(an_ac_debug_stop),
+      .ac_an_debug_trigger(ac_an_debug_trigger),
+      .an_ac_uncond_dbg_event(an_ac_uncond_dbg_event),
+
+      .ac_an_req_pwr_token(ac_an_req_pwr_token),
+      .ac_an_req(ac_an_req),
+      .ac_an_req_ra(ac_an_req_ra),
+      .ac_an_req_ttype(ac_an_req_ttype),
+      .ac_an_req_thread(ac_an_req_thread),
+      .ac_an_req_wimg_w(ac_an_req_wimg_w),
+      .ac_an_req_wimg_i(ac_an_req_wimg_i),
+      .ac_an_req_wimg_m(ac_an_req_wimg_m),
+      .ac_an_req_wimg_g(ac_an_req_wimg_g),
+      .ac_an_req_user_defined(ac_an_req_user_defined),
+      .ac_an_req_spare_ctrl_a0(ac_an_req_spare_ctrl_a0),
+      .ac_an_req_ld_core_tag(ac_an_req_ld_core_tag),
+      .ac_an_req_ld_xfr_len(ac_an_req_ld_xfr_len),
+      .ac_an_st_byte_enbl(ac_an_st_byte_enbl),
+      .ac_an_st_data(ac_an_st_data),
+      .ac_an_req_endian(ac_an_req_endian),
+      .ac_an_st_data_pwr_token(ac_an_st_data_pwr_token)
+   );
+
+a2l2wb n0(
+      .clk(clk_1x),
+      .rst(rst),
+
+      // request
+      .ac_an_req_pwr_token(ac_an_req_pwr_token),
+      .ac_an_req(ac_an_req),
+      .ac_an_req_ra(ac_an_req_ra),
+      .ac_an_req_ttype(ac_an_req_ttype),
+      .ac_an_req_thread(ac_an_req_thread),
+      .ac_an_req_ld_core_tag(ac_an_req_ld_core_tag),
+      .ac_an_req_ld_xfr_len(ac_an_req_ld_xfr_len),
+      .ac_an_st_data_pwr_token(ac_an_st_data_pwr_token),
+      .ac_an_st_byte_enbl(ac_an_st_byte_enbl),
+      .ac_an_st_data(ac_an_st_data),
+      .ac_an_req_wimg_w(ac_an_req_wimg_w),
+      .ac_an_req_wimg_i(ac_an_req_wimg_i),
+      .ac_an_req_wimg_m(ac_an_req_wimg_m),
+      .ac_an_req_wimg_g(ac_an_req_wimg_g),
+      .ac_an_req_endian(ac_an_req_endian),
+      .ac_an_req_user_defined(ac_an_req_user_defined),
+      .ac_an_req_spare_ctrl_a0(ac_an_req_spare_ctrl_a0),
+
+      // reload
+      .an_ac_reld_data_vld(an_ac_reld_data_vld),
+      .an_ac_reld_core_tag(an_ac_reld_core_tag),
+      .an_ac_reld_data(an_ac_reld_data),
+      .an_ac_reld_qw(an_ac_reld_qw),
+      .an_ac_reld_ecc_err(an_ac_reld_ecc_err),
+      .an_ac_reld_ecc_err_ue(an_ac_reld_ecc_err_ue),
+      .an_ac_reld_data_coming(an_ac_reld_data_coming),
+      .an_ac_reld_ditc(an_ac_reld_ditc),
+      .an_ac_reld_crit_qw(an_ac_reld_crit_qw),
+      .an_ac_reld_l1_dump(an_ac_reld_l1_dump),
+      .an_ac_req_spare_ctrl_a1(an_ac_req_spare_ctrl_a1),
+
+      // larx/stcx
+      .an_ac_stcx_complete(an_ac_stcx_complete),
+      .an_ac_stcx_pass(an_ac_stcx_pass),
+      .an_ac_reservation_vld(an_ac_reservation_vld),
+
+      // icbi
+      .an_ac_icbi_ack(an_ac_icbi_ack),
+      .an_ac_icbi_ack_thread(an_ac_icbi_ack_thread),
+
+      // back invalidate
+      .an_ac_back_inv(an_ac_back_inv),
+      .an_ac_back_inv_addr(an_ac_back_inv_addr),
+      .an_ac_back_inv_target(an_ac_back_inv_target),
+      .an_ac_back_inv_local(an_ac_back_inv_local),
+      .an_ac_back_inv_lbit(an_ac_back_inv_lbit),
+      .an_ac_back_inv_gs(an_ac_back_inv_gs),
+      .an_ac_back_inv_ind(an_ac_back_inv_ind),
+      .an_ac_back_inv_lpar_id(an_ac_back_inv_lpar_id),
+      .ac_an_back_inv_reject(ac_an_back_inv_reject),
+      .ac_an_lpar_id(ac_an_lpar_id),
+
+      // credits
+      .an_ac_req_ld_pop(an_ac_req_ld_pop),
+      .an_ac_req_st_pop(an_ac_req_st_pop),
+      .an_ac_req_st_gather(an_ac_req_st_gather),
+      .an_ac_sync_ack(an_ac_sync_ack),
+      //.an_ac_pm_fetch_halt(an_ac_pm_fetch_halt),
+
+      // misc
+      //.an_ac_flh2l2_gate(an_ac_flh2l2_gate),
+      //.an_ac_reset_1_complete(an_ac_reset_1_complete),
+      //.an_ac_reset_2_complete(an_ac_reset_2_complete),
+      //.an_ac_reset_3_complete(an_ac_reset_3_complete),
+      //.an_ac_reset_wd_complete(an_ac_reset_wd_complete),
+      //.an_ac_sleep_en(an_ac_sleep_en),
+      //.an_ac_ext_interrupt(an_ac_ext_interrupt),
+      //.an_ac_crit_interrupt(an_ac_crit_interrupt),
+      //.an_ac_perf_interrupt(an_ac_perf_interrupt),
+      //.an_ac_hang_pulse(an_ac_hang_pulse),
+      //.an_ac_tb_update_enable(an_ac_tb_update_enable),
+      //.an_ac_tb_update_pulse(an_ac_tb_update_pulse),
+      //.an_ac_chipid_dc(an_ac_chipid_dc),
+      //.an_ac_coreid(an_ac_coreid),
+      //.an_ac_debug_stop(an_ac_debug_stop),
+      //.ac_an_debug_trigger(ac_an_debug_trigger),
+      //.an_ac_uncond_dbg_event(an_ac_uncond_dbg_event),
+
+      // scom
+      //.an_ac_scom_sat_id(an_ac_scom_sat_id),
+      //.an_ac_scom_dch(an_ac_scom_dch),
+      //.an_ac_scom_cch(an_ac_scom_cch),
+      //.ac_an_scom_dch(ac_an_scom_dch),
+      //.ac_an_scom_cch(ac_an_scom_cch),
+
+      // errors
+      //.ac_an_special_attn(ac_an_special_attn),
+      //.ac_an_checkstop(ac_an_checkstop),
+      //.ac_an_local_checkstop(ac_an_local_checkstop),
+      //.ac_an_recov_err(ac_an_recov_err),
+      //.ac_an_trace_error(ac_an_trace_error),
+      //.ac_an_livelock_active(ac_an_livelock_active),
+      .an_ac_checkstop(an_ac_checkstop),
+      //.an_ac_external_mchk(an_ac_external_mchk),
+      //.ac_an_machine_check(ac_an_machine_check),
+
+      // perfmon
+      //.ac_an_event_bus0(ac_an_event_bus0),
+      //.ac_an_event_bus1(ac_an_event_bus1),
+
+      // power
+      //.ac_an_pm_thread_running(ac_an_pm_thread_running),
+      //.an_ac_pm_thread_stop(an_ac_pm_thread_stop),
+      //.ac_an_power_managed(ac_an_power_managed),
+      //.ac_an_rvwinkle_mode(ac_an_rvwinkle_mode)
+      // direct-attach mem
+      .mem_adr(mem_adr),
+      .mem_dat(mem_dat),
+      .mem_wr_be(mem_wr_be),
+      .mem_wr_val(mem_wr_val),
+
+      .mem_wr_dat(mem_wr_dat),
+
+      // wishbone
+      .wb_stb(wb_stb),
+      .wb_cyc(wb_cyc),
+      .wb_adr(wb_adr),
+      .wb_we(wb_we),
+      .wb_ack(wb_ack),
+      .wb_sel(wb_sel),
+      .wb_datr(wb_datr),
+      .wb_datw(wb_datw)
+
+   );
+
+wire clk_1x, clk_2x, clk_4x, rst;
+
+assign clk_1x = nclk[0];
+assign clk_2x = nclk[2];
+assign clk_4x = nclk[3];
+assign rst = nclk[1];
+
+endmodule

dev/verilog/a2node_wb/tri_a2o.vh

@@ -0,0 +1,194 @@
+// © IBM Corp. 2020
+// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
+// the terms below; you may not use the files in this repository except in
+// compliance with the License as modified.
+// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
+//
+// Modified Terms:
+//
+//    1) For the purpose of the patent license granted to you in Section 3 of the
+//    License, the "Work" hereby includes implementations of the work of authorship
+//    in physical form.
+//
+//    2) Notwithstanding any terms to the contrary in the License, any licenses
+//    necessary for implementation of the Work that are available from OpenPOWER
+//    via the Power ISA End User License Agreement (EULA) are explicitly excluded
+//    hereunder, and may be obtained from OpenPOWER under the terms and conditions
+//    of the EULA.
+//
+// Unless required by applicable law or agreed to in writing, the reference design
+// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
+// for the specific language governing permissions and limitations under the License.
+//
+// Additional rights, including the ability to physically implement a softcore that
+// is compliant with the required sections of the Power ISA Specification, are
+// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
+// obtained (along with the Power ISA) here: https://openpowerfoundation.org.
+
+// Transaction limiting
+// LOAD_CREDITS=1, STORE_CREDITS=1, XUCR0[52]=1
+
+`ifndef _tri_a2o_vh_
+`define _tri_a2o_vh_
+
+`include "tri.vh"
+
+// Use this line for 1 thread.  Comment out for 2 thread design.
+`define THREADS1
+
+`define  gpr_t  3'b000
+`define  cr_t  3'b001
+`define  lr_t  3'b010
+`define  ctr_t  3'b011
+`define  xer_t  3'b100
+`define  spr_t  3'b101
+`define  axu0_t  3'b110
+`define  axu1_t  3'b111
+
+`ifdef THREADS1
+    `define  THREADS  1
+    `define  THREAD_POOL_ENC  0
+    `define  THREADS_POOL_ENC  0
+`else
+    `define  THREADS  2
+    `define  THREAD_POOL_ENC  1
+    `define  THREADS_POOL_ENC  1
+`endif
+`define  EFF_IFAR_ARCH  62
+`define  EFF_IFAR_WIDTH  20
+`define  EFF_IFAR   20
+`define  FPR_POOL_ENC 6
+`define  REGMODE 6
+`define  FPR_POOL 64
+`define  REAL_IFAR_WIDTH  42
+`define  EMQ_ENTRIES  4
+`define  GPR_WIDTH  64
+`define  ITAG_SIZE_ENC  7
+`define  CPL_Q_DEPTH  32
+`define  CPL_Q_DEPTH_ENC  6
+`define  GPR_WIDTH_ENC 6
+`define  GPR_POOL_ENC  6
+`define  GPR_POOL  64
+`define  GPR_UCODE_POOL  4
+`define  CR_POOL_ENC  5
+`define  CR_POOL  24
+`define  CR_UCODE_POOL  1
+`define  BR_POOL_ENC  3
+`define  BR_POOL      8
+`define  LR_POOL_ENC  3
+`define  LR_POOL  8
+`define  LR_UCODE_POOL  0
+`define  CTR_POOL_ENC  3
+`define  CTR_POOL  8
+`define  CTR_UCODE_POOL  0
+`define  XER_POOL_ENC  4
+`define  XER_POOL  12
+`define  XER_UCODE_POOL  0
+`define  LDSTQ_ENTRIES  16
+`define  LDSTQ_ENTRIES_ENC  4
+`define  STQ_ENTRIES  12
+`define  STQ_ENTRIES_ENC  4
+`define  STQ_FWD_ENTRIES  4		// number of stq entries that can be forwarded from
+`define  STQ_DATA_SIZE  64		// 64 or 128 Bit store data sizes supported
+`define  DC_SIZE  15			// 14 => 16K L1D$, 15 => 32K L1D$
+`define  CL_SIZE  6			// 6 => 64B CLINE, 7 => 128B CLINE
+`define  LMQ_ENTRIES  8
+`define  LMQ_ENTRIES_ENC  3
+`define  LGQ_ENTRIES  8
+`define  AXU_SPARE_ENC  3
+`define  RV_FX0_ENTRIES  12
+`define  RV_FX1_ENTRIES  12
+`define  RV_LQ_ENTRIES  16
+`define  RV_AXU0_ENTRIES  12
+`define  RV_AXU1_ENTRIES  0
+`define  RV_FX0_ENTRIES_ENC  4
+`define  RV_FX1_ENTRIES_ENC  4
+`define  RV_LQ_ENTRIES_ENC  4
+`define  RV_AXU0_ENTRIES_ENC  4
+`define  RV_AXU1_ENTRIES_ENC  1
+`define  UCODE_ENTRIES  8
+`define  UCODE_ENTRIES_ENC  3
+`define  FXU1_ENABLE  1
+`define  TYPE_WIDTH 3
+`define  IBUFF_INSTR_WIDTH  70
+`define  IBUFF_IFAR_WIDTH  20
+`define  IBUFF_DEPTH  16
+`define  PF_IAR_BITS  12		// number of IAR bits used by prefetch
+`define  FXU0_PIPE_START 1
+`define  FXU0_PIPE_END 8
+`define  FXU1_PIPE_START 1
+`define  FXU1_PIPE_END 5
+`define  LQ_LOAD_PIPE_START 4
+`define  LQ_LOAD_PIPE_END 8
+`define  LQ_REL_PIPE_START 2
+`define  LQ_REL_PIPE_END 4
+`define  LOAD_CREDITS   1
+`define  STORE_CREDITS 1
+`define  IUQ_ENTRIES   4 		   // Instruction Fetch Queue Size
+`define  MMQ_ENTRIES   2 		   // MMU Queue Size
+`define  CR_WIDTH 4
+`define  BUILD_PFETCH  1		   // 1=> include pfetch in the build, 0=> build without pfetch
+`define  PF_IFAR_WIDTH  12
+`define  PFETCH_INITIAL_DEPTH  0	// the initial value for the SPR that determines how many lines to prefetch
+`define  PFETCH_Q_SIZE_ENC  3		// number of bits to address queue size (3 => 8 entries, 4 => 16 entries)
+`define  PFETCH_Q_SIZE  8		   // number of entries
+`define  INCLUDE_IERAT_BYPASS  1	// 0 => Removes IERAT Bypass logic, 1=> includes (power savings)
+`define  XER_WIDTH  10
+
+//wtf: change for verilatorsim - didnt help
+//`define  INIT_BHT  1			      // 0=> array init time set to 16 clocks, 1=> increased to 512 to init BHT
+`define  INIT_BHT  0			      // 0=> array init time set to 16 clocks, 1=> increased to 512 to init BHT
+//`define  INIT_IUCR0  16'h0000	   // BP disabled
+`define  INIT_IUCR0  16'h00FA	   // BP enabled
+
+
+`define  INIT_MASK  2'b10
+`define  RELQ_INCLUDE  0		   // Reload Queue Included
+
+`define  G_BRANCH_LEN  `EFF_IFAR_WIDTH + 1 + 1 + `EFF_IFAR_WIDTH + 3 + 18 + 1
+
+//wtf: add completion stuff
+/*
+   assign spr_cpcr0_fx0_cnt = cpcr0_l2[35:39];
+   assign spr_cpcr0_fx1_cnt = cpcr0_l2[43:47];
+   assign spr_cpcr0_lq_cnt = cpcr0_l2[51:55];
+   assign spr_cpcr0_sq_cnt = cpcr0_l2[59:63];
+*/
+`define INIT_CPCR0                  32'h0C0C100C   // 000a aaaa 000b bbbb 000c cccc 000d dddd   watermarks: a=fx0 b=fx1 c=ls d=sq ---- um p.543 wrong!; was this in vlog: hex 0C0C100C = 202117132
+//`define INIT_CPCR0                  32'h01010201     // 1/1/2/1
+/*
+   assign spr_cpcr1_fu0_cnt = cpcr1_l2[43:47];
+   assign spr_cpcr1_fu1_cnt = cpcr1_l2[51:55];
+*/
+`define INIT_CPCR1                  32'h000C0C00     // 0000 0000 000a aaaa 000b bbbb 0000 0000   credits: a=fx0 b=fx1 c=ls d=sq ---- um p.544 wrong!; was this in vlog: hex 000C0C00 = 789504
+//`define INIT_CPCR1                  32'h00010100      // 1/1
+
+`define  INIT_XUCR0   32'h00000C60  // 52:single-credit LS
+
+// IERAT boot config entry values
+`define  IERAT_BCFG_EPN_0TO15      0
+`define  IERAT_BCFG_EPN_16TO31     0
+`define  IERAT_BCFG_EPN_32TO47     (2 ** 16) - 1   // 1 for 64K, 65535 for 4G
+`define  IERAT_BCFG_EPN_48TO51     (2 ** 4) - 1    // 15 for 64K or 4G
+`define  IERAT_BCFG_RPN_22TO31     0               // (2 ** 10) - 1  for x3ff
+`define  IERAT_BCFG_RPN_32TO47     (2 ** 16) - 1   // 1 for 64K, 8181 for 512M, 65535 for 4G
+`define  IERAT_BCFG_RPN_48TO51     (2 ** 4) - 1    // 15 for 64K or 4G
+`define  IERAT_BCFG_RPN2_32TO47    0               // 0 to match dd1 hardwired value; (2**16)-1 for same 64K page
+`define  IERAT_BCFG_RPN2_48TO51    0               // 0 to match dd1 hardwired value;  (2**4)-2 for adjacent 4K page
+`define  IERAT_BCFG_ATTR    0                      // u0-u3, endian
+
+// DERAT boot config entry values
+`define  DERAT_BCFG_EPN_0TO15      0
+`define  DERAT_BCFG_EPN_16TO31     0
+`define  DERAT_BCFG_EPN_32TO47     (2 ** 16) - 1   // 1 for 64K, 65535 for 4G
+`define  DERAT_BCFG_EPN_48TO51     (2 ** 4) - 1    // 15 for 64K or 4G
+`define  DERAT_BCFG_RPN_22TO31     0               // (2 ** 10) - 1  for x3ff
+`define  DERAT_BCFG_RPN_32TO47     (2 ** 16) - 1   // 1 for 64K, 8191 for 512M, 65535 for 4G
+`define  DERAT_BCFG_RPN_48TO51     (2 ** 4) - 1    // 15 for 64K or 4G
+`define  DERAT_BCFG_RPN2_32TO47    0               // 0 to match dd1 hardwired value; (2**16)-1 for same 64K page
+`define  DERAT_BCFG_RPN2_48TO51    0               // 0 to match dd1 hardwired value;  (2**4)-2 for adjacent 4K page
+`define  DERAT_BCFG_ATTR    0                      // u0-u3, endian
+
+// Do NOT add any defines below this line
+`endif  //_tri_a2o_vh_